1 /** 2 * Driver for Zarlink zl10036 DVB-S silicon tuner 3 * 4 * Copyright (C) 2006 Tino Reichardt 5 * Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License Version 2, as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 * 20 ** 21 * The data sheet for this tuner can be found at: 22 * http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf 23 * 24 * This one is working: (at my Avermedia DVB-S Pro) 25 * - zl10036 (40pin, FTA) 26 * 27 * A driver for zl10038 should be very similar. 28 */ 29 30 #include <linux/module.h> 31 #include <linux/dvb/frontend.h> 32 #include <linux/slab.h> 33 #include <linux/types.h> 34 35 #include "zl10036.h" 36 37 static int zl10036_debug; 38 #define dprintk(level, args...) \ 39 do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \ 40 } while (0) 41 42 #define deb_info(args...) dprintk(0x01, args) 43 #define deb_i2c(args...) dprintk(0x02, args) 44 45 struct zl10036_state { 46 struct i2c_adapter *i2c; 47 const struct zl10036_config *config; 48 u32 frequency; 49 u8 br, bf; 50 }; 51 52 53 /* This driver assumes the tuner is driven by a 10.111MHz Cristal */ 54 #define _XTAL 10111 55 56 /* Some of the possible dividers: 57 * 64, (write 0x05 to reg), freq step size 158kHz 58 * 10, (write 0x0a to reg), freq step size 1.011kHz (used here) 59 * 5, (write 0x09 to reg), freq step size 2.022kHz 60 */ 61 62 #define _RDIV 10 63 #define _RDIV_REG 0x0a 64 #define _FR (_XTAL/_RDIV) 65 66 #define STATUS_POR 0x80 /* Power on Reset */ 67 #define STATUS_FL 0x40 /* Frequency & Phase Lock */ 68 69 /* read/write for zl10036 and zl10038 */ 70 71 static int zl10036_read_status_reg(struct zl10036_state *state) 72 { 73 u8 status; 74 struct i2c_msg msg[1] = { 75 { .addr = state->config->tuner_address, .flags = I2C_M_RD, 76 .buf = &status, .len = sizeof(status) }, 77 }; 78 79 if (i2c_transfer(state->i2c, msg, 1) != 1) { 80 printk(KERN_ERR "%s: i2c read failed at addr=%02x\n", 81 __func__, state->config->tuner_address); 82 return -EIO; 83 } 84 85 deb_i2c("R(status): %02x [FL=%d]\n", status, 86 (status & STATUS_FL) ? 1 : 0); 87 if (status & STATUS_POR) 88 deb_info("%s: Power-On-Reset bit enabled - need to initialize the tuner\n", 89 __func__); 90 91 return status; 92 } 93 94 static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count) 95 { 96 struct i2c_msg msg[1] = { 97 { .addr = state->config->tuner_address, .flags = 0, 98 .buf = buf, .len = count }, 99 }; 100 u8 reg = 0; 101 int ret; 102 103 if (zl10036_debug & 0x02) { 104 /* every 8bit-value satisifes this! 105 * so only check for debug log */ 106 if ((buf[0] & 0x80) == 0x00) 107 reg = 2; 108 else if ((buf[0] & 0xc0) == 0x80) 109 reg = 4; 110 else if ((buf[0] & 0xf0) == 0xc0) 111 reg = 6; 112 else if ((buf[0] & 0xf0) == 0xd0) 113 reg = 8; 114 else if ((buf[0] & 0xf0) == 0xe0) 115 reg = 10; 116 else if ((buf[0] & 0xf0) == 0xf0) 117 reg = 12; 118 119 deb_i2c("W(%d):", reg); 120 { 121 int i; 122 for (i = 0; i < count; i++) 123 printk(KERN_CONT " %02x", buf[i]); 124 printk(KERN_CONT "\n"); 125 } 126 } 127 128 ret = i2c_transfer(state->i2c, msg, 1); 129 if (ret != 1) { 130 printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret); 131 return -EIO; 132 } 133 134 return 0; 135 } 136 137 static void zl10036_release(struct dvb_frontend *fe) 138 { 139 struct zl10036_state *state = fe->tuner_priv; 140 141 fe->tuner_priv = NULL; 142 kfree(state); 143 } 144 145 static int zl10036_sleep(struct dvb_frontend *fe) 146 { 147 struct zl10036_state *state = fe->tuner_priv; 148 u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */ 149 int ret; 150 151 deb_info("%s\n", __func__); 152 153 if (fe->ops.i2c_gate_ctrl) 154 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ 155 156 ret = zl10036_write(state, buf, sizeof(buf)); 157 158 if (fe->ops.i2c_gate_ctrl) 159 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ 160 161 return ret; 162 } 163 164 /** 165 * register map of the ZL10036/ZL10038 166 * 167 * reg[default] content 168 * 2[0x00]: 0 | N14 | N13 | N12 | N11 | N10 | N9 | N8 169 * 3[0x00]: N7 | N6 | N5 | N4 | N3 | N2 | N1 | N0 170 * 4[0x80]: 1 | 0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN 171 * 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0 172 * 6[0xc0]: 1 | 1 | 0 | 0 | RSD | 0 | 0 | 0 173 * 7[0x20]: P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 | 0 174 * 8[0xdb]: 1 | 1 | 0 | 1 | 0 | CC | 1 | 1 175 * 9[0x30]: VSD | V2 | V1 | V0 | S3 | S2 | S1 | S0 176 * 10[0xe1]: 1 | 1 | 1 | 0 | 0 | LS2 | LS1 | LS0 177 * 11[0xf5]: WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE 178 * 12[0xf0]: 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 179 * 13[0x28]: PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR | TL 180 */ 181 182 static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency) 183 { 184 u8 buf[2]; 185 u32 div, foffset; 186 187 div = (frequency + _FR/2) / _FR; 188 state->frequency = div * _FR; 189 190 foffset = frequency - state->frequency; 191 192 buf[0] = (div >> 8) & 0x7f; 193 buf[1] = (div >> 0) & 0xff; 194 195 deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__, 196 frequency, state->frequency, foffset, div); 197 198 return zl10036_write(state, buf, sizeof(buf)); 199 } 200 201 static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw) 202 { 203 /* fbw is measured in kHz */ 204 u8 br, bf; 205 int ret; 206 u8 buf_bf[] = { 207 0xc0, 0x00, /* 6/7: rsd=0 bf=0 */ 208 }; 209 u8 buf_br[] = { 210 0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/ 211 }; 212 u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */ 213 214 /* ensure correct values */ 215 if (fbw > 35000) 216 fbw = 35000; 217 if (fbw < 8000) 218 fbw = 8000; 219 220 #define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */ 221 222 /* <= 28,82 MHz */ 223 if (fbw <= 28820) { 224 br = _BR_MAXIMUM; 225 } else { 226 /** 227 * f(bw)=34,6MHz f(xtal)=10.111MHz 228 * br = (10111/34600) * 63 * 1/K = 14; 229 */ 230 br = ((_XTAL * 21 * 1000) / (fbw * 419)); 231 } 232 233 /* ensure correct values */ 234 if (br < 4) 235 br = 4; 236 if (br > _BR_MAXIMUM) 237 br = _BR_MAXIMUM; 238 239 /* 240 * k = 1.257 241 * bf = fbw/_XTAL * br * k - 1 */ 242 243 bf = (fbw * br * 1257) / (_XTAL * 1000) - 1; 244 245 /* ensure correct values */ 246 if (bf > 62) 247 bf = 62; 248 249 buf_bf[1] = (bf << 1) & 0x7e; 250 buf_br[1] = (br << 2) & 0x7c; 251 deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf); 252 253 if (br != state->br) { 254 ret = zl10036_write(state, buf_br, sizeof(buf_br)); 255 if (ret < 0) 256 return ret; 257 } 258 259 if (bf != state->bf) { 260 ret = zl10036_write(state, buf_bf, sizeof(buf_bf)); 261 if (ret < 0) 262 return ret; 263 264 /* time = br/(32* fxtal) */ 265 /* minimal sleep time to be calculated 266 * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */ 267 msleep(1); 268 269 ret = zl10036_write(state, zl10036_rsd_off, 270 sizeof(zl10036_rsd_off)); 271 if (ret < 0) 272 return ret; 273 } 274 275 state->br = br; 276 state->bf = bf; 277 278 return 0; 279 } 280 281 static int zl10036_set_gain_params(struct zl10036_state *state, 282 int c) 283 { 284 u8 buf[2]; 285 u8 rfg, ba, bg; 286 287 /* default values */ 288 rfg = 0; /* enable when using an lna */ 289 ba = 1; 290 bg = 1; 291 292 /* reg 4 */ 293 buf[0] = 0x80 | ((rfg << 5) & 0x20) 294 | ((ba << 3) & 0x18) | ((bg << 1) & 0x06); 295 296 if (!state->config->rf_loop_enable) 297 buf[0] |= 0x01; 298 299 /* P0=0 */ 300 buf[1] = _RDIV_REG | ((c << 5) & 0x60); 301 302 deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg); 303 return zl10036_write(state, buf, sizeof(buf)); 304 } 305 306 static int zl10036_set_params(struct dvb_frontend *fe) 307 { 308 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 309 struct zl10036_state *state = fe->tuner_priv; 310 int ret = 0; 311 u32 frequency = p->frequency; 312 u32 fbw; 313 int i; 314 u8 c; 315 316 /* ensure correct values 317 * maybe redundant as core already checks this */ 318 if ((frequency < fe->ops.info.frequency_min) 319 || (frequency > fe->ops.info.frequency_max)) 320 return -EINVAL; 321 322 /** 323 * alpha = 1.35 for dvb-s 324 * fBW = (alpha*symbolrate)/(2*0.8) 325 * 1.35 / (2*0.8) = 27 / 32 326 */ 327 fbw = (27 * p->symbol_rate) / 32; 328 329 /* scale to kHz */ 330 fbw /= 1000; 331 332 /* Add safe margin of 3MHz */ 333 fbw += 3000; 334 335 /* setting the charge pump - guessed values */ 336 if (frequency < 950000) 337 return -EINVAL; 338 else if (frequency < 1250000) 339 c = 0; 340 else if (frequency < 1750000) 341 c = 1; 342 else if (frequency < 2175000) 343 c = 2; 344 else 345 return -EINVAL; 346 347 if (fe->ops.i2c_gate_ctrl) 348 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ 349 350 ret = zl10036_set_gain_params(state, c); 351 if (ret < 0) 352 goto error; 353 354 ret = zl10036_set_frequency(state, p->frequency); 355 if (ret < 0) 356 goto error; 357 358 ret = zl10036_set_bandwidth(state, fbw); 359 if (ret < 0) 360 goto error; 361 362 /* wait for tuner lock - no idea if this is really needed */ 363 for (i = 0; i < 20; i++) { 364 ret = zl10036_read_status_reg(state); 365 if (ret < 0) 366 goto error; 367 368 /* check Frequency & Phase Lock Bit */ 369 if (ret & STATUS_FL) 370 break; 371 372 msleep(10); 373 } 374 375 error: 376 if (fe->ops.i2c_gate_ctrl) 377 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ 378 379 return ret; 380 } 381 382 static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency) 383 { 384 struct zl10036_state *state = fe->tuner_priv; 385 386 *frequency = state->frequency; 387 388 return 0; 389 } 390 391 static int zl10036_init_regs(struct zl10036_state *state) 392 { 393 int ret; 394 int i; 395 396 /* could also be one block from reg 2 to 13 and additional 10/11 */ 397 u8 zl10036_init_tab[][2] = { 398 { 0x04, 0x00 }, /* 2/3: div=0x400 - arbitrary value */ 399 { 0x8b, _RDIV_REG }, /* 4/5: rfg=0 ba=1 bg=1 len=? */ 400 /* p0=0 c=0 r=_RDIV_REG */ 401 { 0xc0, 0x20 }, /* 6/7: rsd=0 bf=0x10 */ 402 { 0xd3, 0x40 }, /* 8/9: from datasheet */ 403 { 0xe3, 0x5b }, /* 10/11: lock window level */ 404 { 0xf0, 0x28 }, /* 12/13: br=0xa clr=0 tl=0*/ 405 { 0xe3, 0xf9 }, /* 10/11: unlock window level */ 406 }; 407 408 /* invalid values to trigger writing */ 409 state->br = 0xff; 410 state->bf = 0xff; 411 412 if (!state->config->rf_loop_enable) 413 zl10036_init_tab[1][0] |= 0x01; 414 415 deb_info("%s\n", __func__); 416 417 for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) { 418 ret = zl10036_write(state, zl10036_init_tab[i], 2); 419 if (ret < 0) 420 return ret; 421 } 422 423 return 0; 424 } 425 426 static int zl10036_init(struct dvb_frontend *fe) 427 { 428 struct zl10036_state *state = fe->tuner_priv; 429 int ret = 0; 430 431 if (fe->ops.i2c_gate_ctrl) 432 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ 433 434 ret = zl10036_read_status_reg(state); 435 if (ret < 0) 436 return ret; 437 438 /* Only init if Power-on-Reset bit is set? */ 439 ret = zl10036_init_regs(state); 440 441 if (fe->ops.i2c_gate_ctrl) 442 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ 443 444 return ret; 445 } 446 447 static const struct dvb_tuner_ops zl10036_tuner_ops = { 448 .info = { 449 .name = "Zarlink ZL10036", 450 .frequency_min = 950000, 451 .frequency_max = 2175000 452 }, 453 .init = zl10036_init, 454 .release = zl10036_release, 455 .sleep = zl10036_sleep, 456 .set_params = zl10036_set_params, 457 .get_frequency = zl10036_get_frequency, 458 }; 459 460 struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe, 461 const struct zl10036_config *config, 462 struct i2c_adapter *i2c) 463 { 464 struct zl10036_state *state; 465 int ret; 466 467 if (!config) { 468 printk(KERN_ERR "%s: no config specified", __func__); 469 return NULL; 470 } 471 472 state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL); 473 if (!state) 474 return NULL; 475 476 state->config = config; 477 state->i2c = i2c; 478 479 if (fe->ops.i2c_gate_ctrl) 480 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ 481 482 ret = zl10036_read_status_reg(state); 483 if (ret < 0) { 484 printk(KERN_ERR "%s: No zl10036 found\n", __func__); 485 goto error; 486 } 487 488 ret = zl10036_init_regs(state); 489 if (ret < 0) { 490 printk(KERN_ERR "%s: tuner initialization failed\n", 491 __func__); 492 goto error; 493 } 494 495 if (fe->ops.i2c_gate_ctrl) 496 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ 497 498 fe->tuner_priv = state; 499 500 memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops, 501 sizeof(struct dvb_tuner_ops)); 502 printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n", 503 __func__, fe->ops.tuner_ops.info.name, config->tuner_address); 504 505 return fe; 506 507 error: 508 kfree(state); 509 return NULL; 510 } 511 EXPORT_SYMBOL(zl10036_attach); 512 513 module_param_named(debug, zl10036_debug, int, 0644); 514 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 515 MODULE_DESCRIPTION("DVB ZL10036 driver"); 516 MODULE_AUTHOR("Tino Reichardt"); 517 MODULE_AUTHOR("Matthias Schwarzott"); 518 MODULE_LICENSE("GPL"); 519