1 /*
2  * Driver for Zarlink zl10036 DVB-S silicon tuner
3  *
4  * Copyright (C) 2006 Tino Reichardt
5  * Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License Version 2, as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  **
17  * The data sheet for this tuner can be found at:
18  *    http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf
19  *
20  * This one is working: (at my Avermedia DVB-S Pro)
21  * - zl10036 (40pin, FTA)
22  *
23  * A driver for zl10038 should be very similar.
24  */
25 
26 #include <linux/module.h>
27 #include <linux/dvb/frontend.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
30 
31 #include "zl10036.h"
32 
33 static int zl10036_debug;
34 #define dprintk(level, args...) \
35 	do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \
36 	} while (0)
37 
38 #define deb_info(args...)  dprintk(0x01, args)
39 #define deb_i2c(args...)  dprintk(0x02, args)
40 
41 struct zl10036_state {
42 	struct i2c_adapter *i2c;
43 	const struct zl10036_config *config;
44 	u32 frequency;
45 	u8 br, bf;
46 };
47 
48 
49 /* This driver assumes the tuner is driven by a 10.111MHz Cristal */
50 #define _XTAL 10111
51 
52 /* Some of the possible dividers:
53  *   64, (write 0x05 to reg), freq step size   158kHz
54  *   10, (write 0x0a to reg), freq step size 1.011kHz (used here)
55  *    5, (write 0x09 to reg), freq step size 2.022kHz
56  */
57 
58 #define _RDIV 10
59 #define _RDIV_REG 0x0a
60 #define _FR   (_XTAL/_RDIV)
61 
62 #define STATUS_POR 0x80 /* Power on Reset */
63 #define STATUS_FL  0x40 /* Frequency & Phase Lock */
64 
65 /* read/write for zl10036 and zl10038 */
66 
67 static int zl10036_read_status_reg(struct zl10036_state *state)
68 {
69 	u8 status;
70 	struct i2c_msg msg[1] = {
71 		{ .addr = state->config->tuner_address, .flags = I2C_M_RD,
72 		  .buf = &status, .len = sizeof(status) },
73 	};
74 
75 	if (i2c_transfer(state->i2c, msg, 1) != 1) {
76 		printk(KERN_ERR "%s: i2c read failed at addr=%02x\n",
77 			__func__, state->config->tuner_address);
78 		return -EIO;
79 	}
80 
81 	deb_i2c("R(status): %02x  [FL=%d]\n", status,
82 		(status & STATUS_FL) ? 1 : 0);
83 	if (status & STATUS_POR)
84 		deb_info("%s: Power-On-Reset bit enabled - need to initialize the tuner\n",
85 			 __func__);
86 
87 	return status;
88 }
89 
90 static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count)
91 {
92 	struct i2c_msg msg[1] = {
93 		{ .addr = state->config->tuner_address, .flags = 0,
94 		  .buf = buf, .len = count },
95 	};
96 	u8 reg = 0;
97 	int ret;
98 
99 	if (zl10036_debug & 0x02) {
100 		/* every 8bit-value satisifes this!
101 		 * so only check for debug log */
102 		if ((buf[0] & 0x80) == 0x00)
103 			reg = 2;
104 		else if ((buf[0] & 0xc0) == 0x80)
105 			reg = 4;
106 		else if ((buf[0] & 0xf0) == 0xc0)
107 			reg = 6;
108 		else if ((buf[0] & 0xf0) == 0xd0)
109 			reg = 8;
110 		else if ((buf[0] & 0xf0) == 0xe0)
111 			reg = 10;
112 		else if ((buf[0] & 0xf0) == 0xf0)
113 			reg = 12;
114 
115 		deb_i2c("W(%d):", reg);
116 		{
117 			int i;
118 			for (i = 0; i < count; i++)
119 				printk(KERN_CONT " %02x", buf[i]);
120 			printk(KERN_CONT "\n");
121 		}
122 	}
123 
124 	ret = i2c_transfer(state->i2c, msg, 1);
125 	if (ret != 1) {
126 		printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret);
127 		return -EIO;
128 	}
129 
130 	return 0;
131 }
132 
133 static void zl10036_release(struct dvb_frontend *fe)
134 {
135 	struct zl10036_state *state = fe->tuner_priv;
136 
137 	fe->tuner_priv = NULL;
138 	kfree(state);
139 }
140 
141 static int zl10036_sleep(struct dvb_frontend *fe)
142 {
143 	struct zl10036_state *state = fe->tuner_priv;
144 	u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */
145 	int ret;
146 
147 	deb_info("%s\n", __func__);
148 
149 	if (fe->ops.i2c_gate_ctrl)
150 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
151 
152 	ret = zl10036_write(state, buf, sizeof(buf));
153 
154 	if (fe->ops.i2c_gate_ctrl)
155 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
156 
157 	return ret;
158 }
159 
160 /*
161  * register map of the ZL10036/ZL10038
162  *
163  * reg[default] content
164  *  2[0x00]:   0 | N14 | N13 | N12 | N11 | N10 |  N9 |  N8
165  *  3[0x00]:  N7 |  N6 |  N5 |  N4 |  N3 |  N2 |  N1 |  N0
166  *  4[0x80]:   1 |   0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN
167  *  5[0x00]:  P0 |  C1 |  C0 |  R4 |  R3 |  R2 |  R1 |  R0
168  *  6[0xc0]:   1 |   1 |   0 |   0 | RSD |   0 |   0 |   0
169  *  7[0x20]:  P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 |   0
170  *  8[0xdb]:   1 |   1 |   0 |   1 |   0 |  CC |   1 |   1
171  *  9[0x30]: VSD |  V2 |  V1 |  V0 |  S3 |  S2 |  S1 |  S0
172  * 10[0xe1]:   1 |   1 |   1 |   0 |   0 | LS2 | LS1 | LS0
173  * 11[0xf5]:  WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE
174  * 12[0xf0]:   1 |   1 |   1 |   1 |   0 |   0 |   0 |   0
175  * 13[0x28]:  PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR |  TL
176  */
177 
178 static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency)
179 {
180 	u8 buf[2];
181 	u32 div, foffset;
182 
183 	div = (frequency + _FR/2) / _FR;
184 	state->frequency = div * _FR;
185 
186 	foffset = frequency - state->frequency;
187 
188 	buf[0] = (div >> 8) & 0x7f;
189 	buf[1] = (div >> 0) & 0xff;
190 
191 	deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__,
192 		frequency, state->frequency, foffset, div);
193 
194 	return zl10036_write(state, buf, sizeof(buf));
195 }
196 
197 static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
198 {
199 	/* fbw is measured in kHz */
200 	u8 br, bf;
201 	int ret;
202 	u8 buf_bf[] = {
203 		0xc0, 0x00, /*   6/7: rsd=0 bf=0 */
204 	};
205 	u8 buf_br[] = {
206 		0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/
207 	};
208 	u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */
209 
210 	/* ensure correct values */
211 	if (fbw > 35000)
212 		fbw = 35000;
213 	if (fbw <  8000)
214 		fbw =  8000;
215 
216 #define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */
217 
218 	/* <= 28,82 MHz */
219 	if (fbw <= 28820) {
220 		br = _BR_MAXIMUM;
221 	} else {
222 		/*
223 		 *  f(bw)=34,6MHz f(xtal)=10.111MHz
224 		 *  br = (10111/34600) * 63 * 1/K = 14;
225 		 */
226 		br = ((_XTAL * 21 * 1000) / (fbw * 419));
227 	}
228 
229 	/* ensure correct values */
230 	if (br < 4)
231 		br = 4;
232 	if (br > _BR_MAXIMUM)
233 		br = _BR_MAXIMUM;
234 
235 	/*
236 	 * k = 1.257
237 	 * bf = fbw/_XTAL * br * k - 1 */
238 
239 	bf = (fbw * br * 1257) / (_XTAL * 1000) - 1;
240 
241 	/* ensure correct values */
242 	if (bf > 62)
243 		bf = 62;
244 
245 	buf_bf[1] = (bf << 1) & 0x7e;
246 	buf_br[1] = (br << 2) & 0x7c;
247 	deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf);
248 
249 	if (br != state->br) {
250 		ret = zl10036_write(state, buf_br, sizeof(buf_br));
251 		if (ret < 0)
252 			return ret;
253 	}
254 
255 	if (bf != state->bf) {
256 		ret = zl10036_write(state, buf_bf, sizeof(buf_bf));
257 		if (ret < 0)
258 			return ret;
259 
260 		/* time = br/(32* fxtal) */
261 		/* minimal sleep time to be calculated
262 		 * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */
263 		msleep(1);
264 
265 		ret = zl10036_write(state, zl10036_rsd_off,
266 			sizeof(zl10036_rsd_off));
267 		if (ret < 0)
268 			return ret;
269 	}
270 
271 	state->br = br;
272 	state->bf = bf;
273 
274 	return 0;
275 }
276 
277 static int zl10036_set_gain_params(struct zl10036_state *state,
278 	int c)
279 {
280 	u8 buf[2];
281 	u8 rfg, ba, bg;
282 
283 	/* default values */
284 	rfg = 0; /* enable when using an lna */
285 	ba = 1;
286 	bg = 1;
287 
288 	/* reg 4 */
289 	buf[0] = 0x80 | ((rfg << 5) & 0x20)
290 		| ((ba  << 3) & 0x18) | ((bg  << 1) & 0x06);
291 
292 	if (!state->config->rf_loop_enable)
293 		buf[0] |= 0x01;
294 
295 	/* P0=0 */
296 	buf[1] = _RDIV_REG | ((c << 5) & 0x60);
297 
298 	deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg);
299 	return zl10036_write(state, buf, sizeof(buf));
300 }
301 
302 static int zl10036_set_params(struct dvb_frontend *fe)
303 {
304 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
305 	struct zl10036_state *state = fe->tuner_priv;
306 	int ret = 0;
307 	u32 frequency = p->frequency;
308 	u32 fbw;
309 	int i;
310 	u8 c;
311 
312 	/* ensure correct values
313 	 * maybe redundant as core already checks this */
314 	if ((frequency < fe->ops.info.frequency_min_hz / kHz)
315 	||  (frequency > fe->ops.info.frequency_max_hz / kHz))
316 		return -EINVAL;
317 
318 	/*
319 	 * alpha = 1.35 for dvb-s
320 	 * fBW = (alpha*symbolrate)/(2*0.8)
321 	 * 1.35 / (2*0.8) = 27 / 32
322 	 */
323 	fbw = (27 * p->symbol_rate) / 32;
324 
325 	/* scale to kHz */
326 	fbw /= 1000;
327 
328 	/* Add safe margin of 3MHz */
329 	fbw += 3000;
330 
331 	/* setting the charge pump - guessed values */
332 	if (frequency < 950000)
333 		return -EINVAL;
334 	else if (frequency < 1250000)
335 		c = 0;
336 	else if (frequency < 1750000)
337 		c = 1;
338 	else if (frequency < 2175000)
339 		c = 2;
340 	else
341 		return -EINVAL;
342 
343 	if (fe->ops.i2c_gate_ctrl)
344 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
345 
346 	ret = zl10036_set_gain_params(state, c);
347 	if (ret < 0)
348 		goto error;
349 
350 	ret = zl10036_set_frequency(state, p->frequency);
351 	if (ret < 0)
352 		goto error;
353 
354 	ret = zl10036_set_bandwidth(state, fbw);
355 	if (ret < 0)
356 		goto error;
357 
358 	/* wait for tuner lock - no idea if this is really needed */
359 	for (i = 0; i < 20; i++) {
360 		ret = zl10036_read_status_reg(state);
361 		if (ret < 0)
362 			goto error;
363 
364 		/* check Frequency & Phase Lock Bit */
365 		if (ret & STATUS_FL)
366 			break;
367 
368 		msleep(10);
369 	}
370 
371 error:
372 	if (fe->ops.i2c_gate_ctrl)
373 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
374 
375 	return ret;
376 }
377 
378 static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency)
379 {
380 	struct zl10036_state *state = fe->tuner_priv;
381 
382 	*frequency = state->frequency;
383 
384 	return 0;
385 }
386 
387 static int zl10036_init_regs(struct zl10036_state *state)
388 {
389 	int ret;
390 	int i;
391 
392 	/* could also be one block from reg 2 to 13 and additional 10/11 */
393 	u8 zl10036_init_tab[][2] = {
394 		{ 0x04, 0x00 },		/*   2/3: div=0x400 - arbitrary value */
395 		{ 0x8b, _RDIV_REG },	/*   4/5: rfg=0 ba=1 bg=1 len=? */
396 					/*        p0=0 c=0 r=_RDIV_REG */
397 		{ 0xc0, 0x20 },		/*   6/7: rsd=0 bf=0x10 */
398 		{ 0xd3, 0x40 },		/*   8/9: from datasheet */
399 		{ 0xe3, 0x5b },		/* 10/11: lock window level */
400 		{ 0xf0, 0x28 },		/* 12/13: br=0xa clr=0 tl=0*/
401 		{ 0xe3, 0xf9 },		/* 10/11: unlock window level */
402 	};
403 
404 	/* invalid values to trigger writing */
405 	state->br = 0xff;
406 	state->bf = 0xff;
407 
408 	if (!state->config->rf_loop_enable)
409 		zl10036_init_tab[1][0] |= 0x01;
410 
411 	deb_info("%s\n", __func__);
412 
413 	for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) {
414 		ret = zl10036_write(state, zl10036_init_tab[i], 2);
415 		if (ret < 0)
416 			return ret;
417 	}
418 
419 	return 0;
420 }
421 
422 static int zl10036_init(struct dvb_frontend *fe)
423 {
424 	struct zl10036_state *state = fe->tuner_priv;
425 	int ret = 0;
426 
427 	if (fe->ops.i2c_gate_ctrl)
428 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
429 
430 	ret = zl10036_read_status_reg(state);
431 	if (ret < 0)
432 		return ret;
433 
434 	/* Only init if Power-on-Reset bit is set? */
435 	ret = zl10036_init_regs(state);
436 
437 	if (fe->ops.i2c_gate_ctrl)
438 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
439 
440 	return ret;
441 }
442 
443 static const struct dvb_tuner_ops zl10036_tuner_ops = {
444 	.info = {
445 		.name = "Zarlink ZL10036",
446 		.frequency_min_hz =  950 * MHz,
447 		.frequency_max_hz = 2175 * MHz
448 	},
449 	.init = zl10036_init,
450 	.release = zl10036_release,
451 	.sleep = zl10036_sleep,
452 	.set_params = zl10036_set_params,
453 	.get_frequency = zl10036_get_frequency,
454 };
455 
456 struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
457 				    const struct zl10036_config *config,
458 				    struct i2c_adapter *i2c)
459 {
460 	struct zl10036_state *state;
461 	int ret;
462 
463 	if (!config) {
464 		printk(KERN_ERR "%s: no config specified", __func__);
465 		return NULL;
466 	}
467 
468 	state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
469 	if (!state)
470 		return NULL;
471 
472 	state->config = config;
473 	state->i2c = i2c;
474 
475 	if (fe->ops.i2c_gate_ctrl)
476 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
477 
478 	ret = zl10036_read_status_reg(state);
479 	if (ret < 0) {
480 		printk(KERN_ERR "%s: No zl10036 found\n", __func__);
481 		goto error;
482 	}
483 
484 	ret = zl10036_init_regs(state);
485 	if (ret < 0) {
486 		printk(KERN_ERR "%s: tuner initialization failed\n",
487 			__func__);
488 		goto error;
489 	}
490 
491 	if (fe->ops.i2c_gate_ctrl)
492 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
493 
494 	fe->tuner_priv = state;
495 
496 	memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops,
497 		sizeof(struct dvb_tuner_ops));
498 	printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n",
499 		__func__, fe->ops.tuner_ops.info.name, config->tuner_address);
500 
501 	return fe;
502 
503 error:
504 	kfree(state);
505 	return NULL;
506 }
507 EXPORT_SYMBOL(zl10036_attach);
508 
509 module_param_named(debug, zl10036_debug, int, 0644);
510 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
511 MODULE_DESCRIPTION("DVB ZL10036 driver");
512 MODULE_AUTHOR("Tino Reichardt");
513 MODULE_AUTHOR("Matthias Schwarzott");
514 MODULE_LICENSE("GPL");
515