11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2cba862dcSMauro Carvalho Chehab /*
39a0bf528SMauro Carvalho Chehab * Driver for Zarlink zl10036 DVB-S silicon tuner
49a0bf528SMauro Carvalho Chehab *
59a0bf528SMauro Carvalho Chehab * Copyright (C) 2006 Tino Reichardt
69a0bf528SMauro Carvalho Chehab * Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de>
79a0bf528SMauro Carvalho Chehab *
89a0bf528SMauro Carvalho Chehab **
99a0bf528SMauro Carvalho Chehab * The data sheet for this tuner can be found at:
109a0bf528SMauro Carvalho Chehab * http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf
119a0bf528SMauro Carvalho Chehab *
129a0bf528SMauro Carvalho Chehab * This one is working: (at my Avermedia DVB-S Pro)
139a0bf528SMauro Carvalho Chehab * - zl10036 (40pin, FTA)
149a0bf528SMauro Carvalho Chehab *
159a0bf528SMauro Carvalho Chehab * A driver for zl10038 should be very similar.
169a0bf528SMauro Carvalho Chehab */
179a0bf528SMauro Carvalho Chehab
189a0bf528SMauro Carvalho Chehab #include <linux/module.h>
199a0bf528SMauro Carvalho Chehab #include <linux/dvb/frontend.h>
209a0bf528SMauro Carvalho Chehab #include <linux/slab.h>
219a0bf528SMauro Carvalho Chehab #include <linux/types.h>
229a0bf528SMauro Carvalho Chehab
239a0bf528SMauro Carvalho Chehab #include "zl10036.h"
249a0bf528SMauro Carvalho Chehab
259a0bf528SMauro Carvalho Chehab static int zl10036_debug;
269a0bf528SMauro Carvalho Chehab #define dprintk(level, args...) \
279a0bf528SMauro Carvalho Chehab do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \
289a0bf528SMauro Carvalho Chehab } while (0)
299a0bf528SMauro Carvalho Chehab
309a0bf528SMauro Carvalho Chehab #define deb_info(args...) dprintk(0x01, args)
319a0bf528SMauro Carvalho Chehab #define deb_i2c(args...) dprintk(0x02, args)
329a0bf528SMauro Carvalho Chehab
339a0bf528SMauro Carvalho Chehab struct zl10036_state {
349a0bf528SMauro Carvalho Chehab struct i2c_adapter *i2c;
359a0bf528SMauro Carvalho Chehab const struct zl10036_config *config;
369a0bf528SMauro Carvalho Chehab u32 frequency;
379a0bf528SMauro Carvalho Chehab u8 br, bf;
389a0bf528SMauro Carvalho Chehab };
399a0bf528SMauro Carvalho Chehab
409a0bf528SMauro Carvalho Chehab
419a0bf528SMauro Carvalho Chehab /* This driver assumes the tuner is driven by a 10.111MHz Cristal */
429a0bf528SMauro Carvalho Chehab #define _XTAL 10111
439a0bf528SMauro Carvalho Chehab
449a0bf528SMauro Carvalho Chehab /* Some of the possible dividers:
459a0bf528SMauro Carvalho Chehab * 64, (write 0x05 to reg), freq step size 158kHz
469a0bf528SMauro Carvalho Chehab * 10, (write 0x0a to reg), freq step size 1.011kHz (used here)
479a0bf528SMauro Carvalho Chehab * 5, (write 0x09 to reg), freq step size 2.022kHz
489a0bf528SMauro Carvalho Chehab */
499a0bf528SMauro Carvalho Chehab
509a0bf528SMauro Carvalho Chehab #define _RDIV 10
519a0bf528SMauro Carvalho Chehab #define _RDIV_REG 0x0a
529a0bf528SMauro Carvalho Chehab #define _FR (_XTAL/_RDIV)
539a0bf528SMauro Carvalho Chehab
549a0bf528SMauro Carvalho Chehab #define STATUS_POR 0x80 /* Power on Reset */
559a0bf528SMauro Carvalho Chehab #define STATUS_FL 0x40 /* Frequency & Phase Lock */
569a0bf528SMauro Carvalho Chehab
579a0bf528SMauro Carvalho Chehab /* read/write for zl10036 and zl10038 */
589a0bf528SMauro Carvalho Chehab
zl10036_read_status_reg(struct zl10036_state * state)599a0bf528SMauro Carvalho Chehab static int zl10036_read_status_reg(struct zl10036_state *state)
609a0bf528SMauro Carvalho Chehab {
619a0bf528SMauro Carvalho Chehab u8 status;
629a0bf528SMauro Carvalho Chehab struct i2c_msg msg[1] = {
639a0bf528SMauro Carvalho Chehab { .addr = state->config->tuner_address, .flags = I2C_M_RD,
649a0bf528SMauro Carvalho Chehab .buf = &status, .len = sizeof(status) },
659a0bf528SMauro Carvalho Chehab };
669a0bf528SMauro Carvalho Chehab
679a0bf528SMauro Carvalho Chehab if (i2c_transfer(state->i2c, msg, 1) != 1) {
689a0bf528SMauro Carvalho Chehab printk(KERN_ERR "%s: i2c read failed at addr=%02x\n",
699a0bf528SMauro Carvalho Chehab __func__, state->config->tuner_address);
709a0bf528SMauro Carvalho Chehab return -EIO;
719a0bf528SMauro Carvalho Chehab }
729a0bf528SMauro Carvalho Chehab
739a0bf528SMauro Carvalho Chehab deb_i2c("R(status): %02x [FL=%d]\n", status,
749a0bf528SMauro Carvalho Chehab (status & STATUS_FL) ? 1 : 0);
759a0bf528SMauro Carvalho Chehab if (status & STATUS_POR)
764bd69e7bSMauro Carvalho Chehab deb_info("%s: Power-On-Reset bit enabled - need to initialize the tuner\n",
774bd69e7bSMauro Carvalho Chehab __func__);
789a0bf528SMauro Carvalho Chehab
799a0bf528SMauro Carvalho Chehab return status;
809a0bf528SMauro Carvalho Chehab }
819a0bf528SMauro Carvalho Chehab
zl10036_write(struct zl10036_state * state,u8 buf[],u8 count)829a0bf528SMauro Carvalho Chehab static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count)
839a0bf528SMauro Carvalho Chehab {
849a0bf528SMauro Carvalho Chehab struct i2c_msg msg[1] = {
859a0bf528SMauro Carvalho Chehab { .addr = state->config->tuner_address, .flags = 0,
869a0bf528SMauro Carvalho Chehab .buf = buf, .len = count },
879a0bf528SMauro Carvalho Chehab };
889a0bf528SMauro Carvalho Chehab u8 reg = 0;
899a0bf528SMauro Carvalho Chehab int ret;
909a0bf528SMauro Carvalho Chehab
919a0bf528SMauro Carvalho Chehab if (zl10036_debug & 0x02) {
929a0bf528SMauro Carvalho Chehab /* every 8bit-value satisifes this!
939a0bf528SMauro Carvalho Chehab * so only check for debug log */
949a0bf528SMauro Carvalho Chehab if ((buf[0] & 0x80) == 0x00)
959a0bf528SMauro Carvalho Chehab reg = 2;
969a0bf528SMauro Carvalho Chehab else if ((buf[0] & 0xc0) == 0x80)
979a0bf528SMauro Carvalho Chehab reg = 4;
989a0bf528SMauro Carvalho Chehab else if ((buf[0] & 0xf0) == 0xc0)
999a0bf528SMauro Carvalho Chehab reg = 6;
1009a0bf528SMauro Carvalho Chehab else if ((buf[0] & 0xf0) == 0xd0)
1019a0bf528SMauro Carvalho Chehab reg = 8;
1029a0bf528SMauro Carvalho Chehab else if ((buf[0] & 0xf0) == 0xe0)
1039a0bf528SMauro Carvalho Chehab reg = 10;
1049a0bf528SMauro Carvalho Chehab else if ((buf[0] & 0xf0) == 0xf0)
1059a0bf528SMauro Carvalho Chehab reg = 12;
1069a0bf528SMauro Carvalho Chehab
1079a0bf528SMauro Carvalho Chehab deb_i2c("W(%d):", reg);
1089a0bf528SMauro Carvalho Chehab {
1099a0bf528SMauro Carvalho Chehab int i;
1109a0bf528SMauro Carvalho Chehab for (i = 0; i < count; i++)
1119a0bf528SMauro Carvalho Chehab printk(KERN_CONT " %02x", buf[i]);
1129a0bf528SMauro Carvalho Chehab printk(KERN_CONT "\n");
1139a0bf528SMauro Carvalho Chehab }
1149a0bf528SMauro Carvalho Chehab }
1159a0bf528SMauro Carvalho Chehab
1169a0bf528SMauro Carvalho Chehab ret = i2c_transfer(state->i2c, msg, 1);
1179a0bf528SMauro Carvalho Chehab if (ret != 1) {
1189a0bf528SMauro Carvalho Chehab printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret);
1199a0bf528SMauro Carvalho Chehab return -EIO;
1209a0bf528SMauro Carvalho Chehab }
1219a0bf528SMauro Carvalho Chehab
1229a0bf528SMauro Carvalho Chehab return 0;
1239a0bf528SMauro Carvalho Chehab }
1249a0bf528SMauro Carvalho Chehab
zl10036_release(struct dvb_frontend * fe)125f2709c20SMauro Carvalho Chehab static void zl10036_release(struct dvb_frontend *fe)
126f2709c20SMauro Carvalho Chehab {
127f2709c20SMauro Carvalho Chehab struct zl10036_state *state = fe->tuner_priv;
128f2709c20SMauro Carvalho Chehab
129f2709c20SMauro Carvalho Chehab fe->tuner_priv = NULL;
130f2709c20SMauro Carvalho Chehab kfree(state);
131f2709c20SMauro Carvalho Chehab }
132f2709c20SMauro Carvalho Chehab
zl10036_sleep(struct dvb_frontend * fe)1339a0bf528SMauro Carvalho Chehab static int zl10036_sleep(struct dvb_frontend *fe)
1349a0bf528SMauro Carvalho Chehab {
1359a0bf528SMauro Carvalho Chehab struct zl10036_state *state = fe->tuner_priv;
1369a0bf528SMauro Carvalho Chehab u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */
1379a0bf528SMauro Carvalho Chehab int ret;
1389a0bf528SMauro Carvalho Chehab
1399a0bf528SMauro Carvalho Chehab deb_info("%s\n", __func__);
1409a0bf528SMauro Carvalho Chehab
1419a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
1429a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
1439a0bf528SMauro Carvalho Chehab
1449a0bf528SMauro Carvalho Chehab ret = zl10036_write(state, buf, sizeof(buf));
1459a0bf528SMauro Carvalho Chehab
1469a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
1479a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
1489a0bf528SMauro Carvalho Chehab
1499a0bf528SMauro Carvalho Chehab return ret;
1509a0bf528SMauro Carvalho Chehab }
1519a0bf528SMauro Carvalho Chehab
152cba862dcSMauro Carvalho Chehab /*
1539a0bf528SMauro Carvalho Chehab * register map of the ZL10036/ZL10038
1549a0bf528SMauro Carvalho Chehab *
1559a0bf528SMauro Carvalho Chehab * reg[default] content
1569a0bf528SMauro Carvalho Chehab * 2[0x00]: 0 | N14 | N13 | N12 | N11 | N10 | N9 | N8
1579a0bf528SMauro Carvalho Chehab * 3[0x00]: N7 | N6 | N5 | N4 | N3 | N2 | N1 | N0
1589a0bf528SMauro Carvalho Chehab * 4[0x80]: 1 | 0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN
1599a0bf528SMauro Carvalho Chehab * 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0
1609a0bf528SMauro Carvalho Chehab * 6[0xc0]: 1 | 1 | 0 | 0 | RSD | 0 | 0 | 0
1619a0bf528SMauro Carvalho Chehab * 7[0x20]: P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 | 0
1629a0bf528SMauro Carvalho Chehab * 8[0xdb]: 1 | 1 | 0 | 1 | 0 | CC | 1 | 1
1639a0bf528SMauro Carvalho Chehab * 9[0x30]: VSD | V2 | V1 | V0 | S3 | S2 | S1 | S0
1649a0bf528SMauro Carvalho Chehab * 10[0xe1]: 1 | 1 | 1 | 0 | 0 | LS2 | LS1 | LS0
1659a0bf528SMauro Carvalho Chehab * 11[0xf5]: WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE
1669a0bf528SMauro Carvalho Chehab * 12[0xf0]: 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0
1679a0bf528SMauro Carvalho Chehab * 13[0x28]: PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR | TL
1689a0bf528SMauro Carvalho Chehab */
1699a0bf528SMauro Carvalho Chehab
zl10036_set_frequency(struct zl10036_state * state,u32 frequency)1709a0bf528SMauro Carvalho Chehab static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency)
1719a0bf528SMauro Carvalho Chehab {
1729a0bf528SMauro Carvalho Chehab u8 buf[2];
1739a0bf528SMauro Carvalho Chehab u32 div, foffset;
1749a0bf528SMauro Carvalho Chehab
1759a0bf528SMauro Carvalho Chehab div = (frequency + _FR/2) / _FR;
1769a0bf528SMauro Carvalho Chehab state->frequency = div * _FR;
1779a0bf528SMauro Carvalho Chehab
1789a0bf528SMauro Carvalho Chehab foffset = frequency - state->frequency;
1799a0bf528SMauro Carvalho Chehab
1809a0bf528SMauro Carvalho Chehab buf[0] = (div >> 8) & 0x7f;
1819a0bf528SMauro Carvalho Chehab buf[1] = (div >> 0) & 0xff;
1829a0bf528SMauro Carvalho Chehab
1839a0bf528SMauro Carvalho Chehab deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__,
1849a0bf528SMauro Carvalho Chehab frequency, state->frequency, foffset, div);
1859a0bf528SMauro Carvalho Chehab
1869a0bf528SMauro Carvalho Chehab return zl10036_write(state, buf, sizeof(buf));
1879a0bf528SMauro Carvalho Chehab }
1889a0bf528SMauro Carvalho Chehab
zl10036_set_bandwidth(struct zl10036_state * state,u32 fbw)1899a0bf528SMauro Carvalho Chehab static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
1909a0bf528SMauro Carvalho Chehab {
1919a0bf528SMauro Carvalho Chehab /* fbw is measured in kHz */
1929a0bf528SMauro Carvalho Chehab u8 br, bf;
1939a0bf528SMauro Carvalho Chehab int ret;
1949a0bf528SMauro Carvalho Chehab u8 buf_bf[] = {
1959a0bf528SMauro Carvalho Chehab 0xc0, 0x00, /* 6/7: rsd=0 bf=0 */
1969a0bf528SMauro Carvalho Chehab };
1979a0bf528SMauro Carvalho Chehab u8 buf_br[] = {
1989a0bf528SMauro Carvalho Chehab 0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/
1999a0bf528SMauro Carvalho Chehab };
2009a0bf528SMauro Carvalho Chehab u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */
2019a0bf528SMauro Carvalho Chehab
2029a0bf528SMauro Carvalho Chehab /* ensure correct values */
2039a0bf528SMauro Carvalho Chehab if (fbw > 35000)
2049a0bf528SMauro Carvalho Chehab fbw = 35000;
2059a0bf528SMauro Carvalho Chehab if (fbw < 8000)
2069a0bf528SMauro Carvalho Chehab fbw = 8000;
2079a0bf528SMauro Carvalho Chehab
2089a0bf528SMauro Carvalho Chehab #define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */
2099a0bf528SMauro Carvalho Chehab
2109a0bf528SMauro Carvalho Chehab /* <= 28,82 MHz */
2119a0bf528SMauro Carvalho Chehab if (fbw <= 28820) {
2129a0bf528SMauro Carvalho Chehab br = _BR_MAXIMUM;
2139a0bf528SMauro Carvalho Chehab } else {
214cba862dcSMauro Carvalho Chehab /*
2159a0bf528SMauro Carvalho Chehab * f(bw)=34,6MHz f(xtal)=10.111MHz
2169a0bf528SMauro Carvalho Chehab * br = (10111/34600) * 63 * 1/K = 14;
2179a0bf528SMauro Carvalho Chehab */
2189a0bf528SMauro Carvalho Chehab br = ((_XTAL * 21 * 1000) / (fbw * 419));
2199a0bf528SMauro Carvalho Chehab }
2209a0bf528SMauro Carvalho Chehab
2219a0bf528SMauro Carvalho Chehab /* ensure correct values */
2229a0bf528SMauro Carvalho Chehab if (br < 4)
2239a0bf528SMauro Carvalho Chehab br = 4;
2249a0bf528SMauro Carvalho Chehab if (br > _BR_MAXIMUM)
2259a0bf528SMauro Carvalho Chehab br = _BR_MAXIMUM;
2269a0bf528SMauro Carvalho Chehab
2279a0bf528SMauro Carvalho Chehab /*
2289a0bf528SMauro Carvalho Chehab * k = 1.257
2299a0bf528SMauro Carvalho Chehab * bf = fbw/_XTAL * br * k - 1 */
2309a0bf528SMauro Carvalho Chehab
2319a0bf528SMauro Carvalho Chehab bf = (fbw * br * 1257) / (_XTAL * 1000) - 1;
2329a0bf528SMauro Carvalho Chehab
2339a0bf528SMauro Carvalho Chehab /* ensure correct values */
2349a0bf528SMauro Carvalho Chehab if (bf > 62)
2359a0bf528SMauro Carvalho Chehab bf = 62;
2369a0bf528SMauro Carvalho Chehab
2379a0bf528SMauro Carvalho Chehab buf_bf[1] = (bf << 1) & 0x7e;
2389a0bf528SMauro Carvalho Chehab buf_br[1] = (br << 2) & 0x7c;
2399a0bf528SMauro Carvalho Chehab deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf);
2409a0bf528SMauro Carvalho Chehab
2419a0bf528SMauro Carvalho Chehab if (br != state->br) {
2429a0bf528SMauro Carvalho Chehab ret = zl10036_write(state, buf_br, sizeof(buf_br));
2439a0bf528SMauro Carvalho Chehab if (ret < 0)
2449a0bf528SMauro Carvalho Chehab return ret;
2459a0bf528SMauro Carvalho Chehab }
2469a0bf528SMauro Carvalho Chehab
2479a0bf528SMauro Carvalho Chehab if (bf != state->bf) {
2489a0bf528SMauro Carvalho Chehab ret = zl10036_write(state, buf_bf, sizeof(buf_bf));
2499a0bf528SMauro Carvalho Chehab if (ret < 0)
2509a0bf528SMauro Carvalho Chehab return ret;
2519a0bf528SMauro Carvalho Chehab
2529a0bf528SMauro Carvalho Chehab /* time = br/(32* fxtal) */
2539a0bf528SMauro Carvalho Chehab /* minimal sleep time to be calculated
2549a0bf528SMauro Carvalho Chehab * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */
2559a0bf528SMauro Carvalho Chehab msleep(1);
2569a0bf528SMauro Carvalho Chehab
2579a0bf528SMauro Carvalho Chehab ret = zl10036_write(state, zl10036_rsd_off,
2589a0bf528SMauro Carvalho Chehab sizeof(zl10036_rsd_off));
2599a0bf528SMauro Carvalho Chehab if (ret < 0)
2609a0bf528SMauro Carvalho Chehab return ret;
2619a0bf528SMauro Carvalho Chehab }
2629a0bf528SMauro Carvalho Chehab
2639a0bf528SMauro Carvalho Chehab state->br = br;
2649a0bf528SMauro Carvalho Chehab state->bf = bf;
2659a0bf528SMauro Carvalho Chehab
2669a0bf528SMauro Carvalho Chehab return 0;
2679a0bf528SMauro Carvalho Chehab }
2689a0bf528SMauro Carvalho Chehab
zl10036_set_gain_params(struct zl10036_state * state,int c)2699a0bf528SMauro Carvalho Chehab static int zl10036_set_gain_params(struct zl10036_state *state,
2709a0bf528SMauro Carvalho Chehab int c)
2719a0bf528SMauro Carvalho Chehab {
2729a0bf528SMauro Carvalho Chehab u8 buf[2];
2739a0bf528SMauro Carvalho Chehab u8 rfg, ba, bg;
2749a0bf528SMauro Carvalho Chehab
2759a0bf528SMauro Carvalho Chehab /* default values */
2769a0bf528SMauro Carvalho Chehab rfg = 0; /* enable when using an lna */
2779a0bf528SMauro Carvalho Chehab ba = 1;
2789a0bf528SMauro Carvalho Chehab bg = 1;
2799a0bf528SMauro Carvalho Chehab
2809a0bf528SMauro Carvalho Chehab /* reg 4 */
2819a0bf528SMauro Carvalho Chehab buf[0] = 0x80 | ((rfg << 5) & 0x20)
2829a0bf528SMauro Carvalho Chehab | ((ba << 3) & 0x18) | ((bg << 1) & 0x06);
2839a0bf528SMauro Carvalho Chehab
2849a0bf528SMauro Carvalho Chehab if (!state->config->rf_loop_enable)
2859a0bf528SMauro Carvalho Chehab buf[0] |= 0x01;
2869a0bf528SMauro Carvalho Chehab
2879a0bf528SMauro Carvalho Chehab /* P0=0 */
2889a0bf528SMauro Carvalho Chehab buf[1] = _RDIV_REG | ((c << 5) & 0x60);
2899a0bf528SMauro Carvalho Chehab
2909a0bf528SMauro Carvalho Chehab deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg);
2919a0bf528SMauro Carvalho Chehab return zl10036_write(state, buf, sizeof(buf));
2929a0bf528SMauro Carvalho Chehab }
2939a0bf528SMauro Carvalho Chehab
zl10036_set_params(struct dvb_frontend * fe)2949a0bf528SMauro Carvalho Chehab static int zl10036_set_params(struct dvb_frontend *fe)
2959a0bf528SMauro Carvalho Chehab {
2969a0bf528SMauro Carvalho Chehab struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2979a0bf528SMauro Carvalho Chehab struct zl10036_state *state = fe->tuner_priv;
2989a0bf528SMauro Carvalho Chehab int ret = 0;
2999a0bf528SMauro Carvalho Chehab u32 frequency = p->frequency;
3009a0bf528SMauro Carvalho Chehab u32 fbw;
3019a0bf528SMauro Carvalho Chehab int i;
3029a0bf528SMauro Carvalho Chehab u8 c;
3039a0bf528SMauro Carvalho Chehab
3049a0bf528SMauro Carvalho Chehab /* ensure correct values
3059a0bf528SMauro Carvalho Chehab * maybe redundant as core already checks this */
306f1b1eabfSMauro Carvalho Chehab if ((frequency < fe->ops.info.frequency_min_hz / kHz)
307f1b1eabfSMauro Carvalho Chehab || (frequency > fe->ops.info.frequency_max_hz / kHz))
3089a0bf528SMauro Carvalho Chehab return -EINVAL;
3099a0bf528SMauro Carvalho Chehab
310cba862dcSMauro Carvalho Chehab /*
3119a0bf528SMauro Carvalho Chehab * alpha = 1.35 for dvb-s
3129a0bf528SMauro Carvalho Chehab * fBW = (alpha*symbolrate)/(2*0.8)
3139a0bf528SMauro Carvalho Chehab * 1.35 / (2*0.8) = 27 / 32
3149a0bf528SMauro Carvalho Chehab */
3159a0bf528SMauro Carvalho Chehab fbw = (27 * p->symbol_rate) / 32;
3169a0bf528SMauro Carvalho Chehab
3179a0bf528SMauro Carvalho Chehab /* scale to kHz */
3189a0bf528SMauro Carvalho Chehab fbw /= 1000;
3199a0bf528SMauro Carvalho Chehab
3209a0bf528SMauro Carvalho Chehab /* Add safe margin of 3MHz */
3219a0bf528SMauro Carvalho Chehab fbw += 3000;
3229a0bf528SMauro Carvalho Chehab
3239a0bf528SMauro Carvalho Chehab /* setting the charge pump - guessed values */
3249a0bf528SMauro Carvalho Chehab if (frequency < 950000)
3259a0bf528SMauro Carvalho Chehab return -EINVAL;
3269a0bf528SMauro Carvalho Chehab else if (frequency < 1250000)
3279a0bf528SMauro Carvalho Chehab c = 0;
3289a0bf528SMauro Carvalho Chehab else if (frequency < 1750000)
3299a0bf528SMauro Carvalho Chehab c = 1;
3309a0bf528SMauro Carvalho Chehab else if (frequency < 2175000)
3319a0bf528SMauro Carvalho Chehab c = 2;
3329a0bf528SMauro Carvalho Chehab else
3339a0bf528SMauro Carvalho Chehab return -EINVAL;
3349a0bf528SMauro Carvalho Chehab
3359a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
3369a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
3379a0bf528SMauro Carvalho Chehab
3389a0bf528SMauro Carvalho Chehab ret = zl10036_set_gain_params(state, c);
3399a0bf528SMauro Carvalho Chehab if (ret < 0)
3409a0bf528SMauro Carvalho Chehab goto error;
3419a0bf528SMauro Carvalho Chehab
3429a0bf528SMauro Carvalho Chehab ret = zl10036_set_frequency(state, p->frequency);
3439a0bf528SMauro Carvalho Chehab if (ret < 0)
3449a0bf528SMauro Carvalho Chehab goto error;
3459a0bf528SMauro Carvalho Chehab
3469a0bf528SMauro Carvalho Chehab ret = zl10036_set_bandwidth(state, fbw);
3479a0bf528SMauro Carvalho Chehab if (ret < 0)
3489a0bf528SMauro Carvalho Chehab goto error;
3499a0bf528SMauro Carvalho Chehab
3509a0bf528SMauro Carvalho Chehab /* wait for tuner lock - no idea if this is really needed */
3519a0bf528SMauro Carvalho Chehab for (i = 0; i < 20; i++) {
3529a0bf528SMauro Carvalho Chehab ret = zl10036_read_status_reg(state);
3539a0bf528SMauro Carvalho Chehab if (ret < 0)
3549a0bf528SMauro Carvalho Chehab goto error;
3559a0bf528SMauro Carvalho Chehab
3569a0bf528SMauro Carvalho Chehab /* check Frequency & Phase Lock Bit */
3579a0bf528SMauro Carvalho Chehab if (ret & STATUS_FL)
3589a0bf528SMauro Carvalho Chehab break;
3599a0bf528SMauro Carvalho Chehab
3609a0bf528SMauro Carvalho Chehab msleep(10);
3619a0bf528SMauro Carvalho Chehab }
3629a0bf528SMauro Carvalho Chehab
3639a0bf528SMauro Carvalho Chehab error:
3649a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
3659a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
3669a0bf528SMauro Carvalho Chehab
3679a0bf528SMauro Carvalho Chehab return ret;
3689a0bf528SMauro Carvalho Chehab }
3699a0bf528SMauro Carvalho Chehab
zl10036_get_frequency(struct dvb_frontend * fe,u32 * frequency)3709a0bf528SMauro Carvalho Chehab static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency)
3719a0bf528SMauro Carvalho Chehab {
3729a0bf528SMauro Carvalho Chehab struct zl10036_state *state = fe->tuner_priv;
3739a0bf528SMauro Carvalho Chehab
3749a0bf528SMauro Carvalho Chehab *frequency = state->frequency;
3759a0bf528SMauro Carvalho Chehab
3769a0bf528SMauro Carvalho Chehab return 0;
3779a0bf528SMauro Carvalho Chehab }
3789a0bf528SMauro Carvalho Chehab
zl10036_init_regs(struct zl10036_state * state)3799a0bf528SMauro Carvalho Chehab static int zl10036_init_regs(struct zl10036_state *state)
3809a0bf528SMauro Carvalho Chehab {
3819a0bf528SMauro Carvalho Chehab int ret;
3829a0bf528SMauro Carvalho Chehab int i;
3839a0bf528SMauro Carvalho Chehab
3849a0bf528SMauro Carvalho Chehab /* could also be one block from reg 2 to 13 and additional 10/11 */
3859a0bf528SMauro Carvalho Chehab u8 zl10036_init_tab[][2] = {
3869a0bf528SMauro Carvalho Chehab { 0x04, 0x00 }, /* 2/3: div=0x400 - arbitrary value */
3879a0bf528SMauro Carvalho Chehab { 0x8b, _RDIV_REG }, /* 4/5: rfg=0 ba=1 bg=1 len=? */
3889a0bf528SMauro Carvalho Chehab /* p0=0 c=0 r=_RDIV_REG */
3899a0bf528SMauro Carvalho Chehab { 0xc0, 0x20 }, /* 6/7: rsd=0 bf=0x10 */
3909a0bf528SMauro Carvalho Chehab { 0xd3, 0x40 }, /* 8/9: from datasheet */
3919a0bf528SMauro Carvalho Chehab { 0xe3, 0x5b }, /* 10/11: lock window level */
3929a0bf528SMauro Carvalho Chehab { 0xf0, 0x28 }, /* 12/13: br=0xa clr=0 tl=0*/
3939a0bf528SMauro Carvalho Chehab { 0xe3, 0xf9 }, /* 10/11: unlock window level */
3949a0bf528SMauro Carvalho Chehab };
3959a0bf528SMauro Carvalho Chehab
3969a0bf528SMauro Carvalho Chehab /* invalid values to trigger writing */
3979a0bf528SMauro Carvalho Chehab state->br = 0xff;
3989a0bf528SMauro Carvalho Chehab state->bf = 0xff;
3999a0bf528SMauro Carvalho Chehab
4009a0bf528SMauro Carvalho Chehab if (!state->config->rf_loop_enable)
4019a0bf528SMauro Carvalho Chehab zl10036_init_tab[1][0] |= 0x01;
4029a0bf528SMauro Carvalho Chehab
4039a0bf528SMauro Carvalho Chehab deb_info("%s\n", __func__);
4049a0bf528SMauro Carvalho Chehab
4059a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) {
4069a0bf528SMauro Carvalho Chehab ret = zl10036_write(state, zl10036_init_tab[i], 2);
4079a0bf528SMauro Carvalho Chehab if (ret < 0)
4089a0bf528SMauro Carvalho Chehab return ret;
4099a0bf528SMauro Carvalho Chehab }
4109a0bf528SMauro Carvalho Chehab
4119a0bf528SMauro Carvalho Chehab return 0;
4129a0bf528SMauro Carvalho Chehab }
4139a0bf528SMauro Carvalho Chehab
zl10036_init(struct dvb_frontend * fe)4149a0bf528SMauro Carvalho Chehab static int zl10036_init(struct dvb_frontend *fe)
4159a0bf528SMauro Carvalho Chehab {
4169a0bf528SMauro Carvalho Chehab struct zl10036_state *state = fe->tuner_priv;
4179a0bf528SMauro Carvalho Chehab int ret = 0;
4189a0bf528SMauro Carvalho Chehab
4199a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
4209a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
4219a0bf528SMauro Carvalho Chehab
4229a0bf528SMauro Carvalho Chehab ret = zl10036_read_status_reg(state);
4239a0bf528SMauro Carvalho Chehab if (ret < 0)
4249a0bf528SMauro Carvalho Chehab return ret;
4259a0bf528SMauro Carvalho Chehab
4269a0bf528SMauro Carvalho Chehab /* Only init if Power-on-Reset bit is set? */
4279a0bf528SMauro Carvalho Chehab ret = zl10036_init_regs(state);
4289a0bf528SMauro Carvalho Chehab
4299a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
4309a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
4319a0bf528SMauro Carvalho Chehab
4329a0bf528SMauro Carvalho Chehab return ret;
4339a0bf528SMauro Carvalho Chehab }
4349a0bf528SMauro Carvalho Chehab
43514c4bf3cSJulia Lawall static const struct dvb_tuner_ops zl10036_tuner_ops = {
4369a0bf528SMauro Carvalho Chehab .info = {
4379a0bf528SMauro Carvalho Chehab .name = "Zarlink ZL10036",
438a3f90c75SMauro Carvalho Chehab .frequency_min_hz = 950 * MHz,
439a3f90c75SMauro Carvalho Chehab .frequency_max_hz = 2175 * MHz
4409a0bf528SMauro Carvalho Chehab },
4419a0bf528SMauro Carvalho Chehab .init = zl10036_init,
442f2709c20SMauro Carvalho Chehab .release = zl10036_release,
4439a0bf528SMauro Carvalho Chehab .sleep = zl10036_sleep,
4449a0bf528SMauro Carvalho Chehab .set_params = zl10036_set_params,
4459a0bf528SMauro Carvalho Chehab .get_frequency = zl10036_get_frequency,
4469a0bf528SMauro Carvalho Chehab };
4479a0bf528SMauro Carvalho Chehab
zl10036_attach(struct dvb_frontend * fe,const struct zl10036_config * config,struct i2c_adapter * i2c)4489a0bf528SMauro Carvalho Chehab struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
4499a0bf528SMauro Carvalho Chehab const struct zl10036_config *config,
4509a0bf528SMauro Carvalho Chehab struct i2c_adapter *i2c)
4519a0bf528SMauro Carvalho Chehab {
4529a0bf528SMauro Carvalho Chehab struct zl10036_state *state;
4539a0bf528SMauro Carvalho Chehab int ret;
4549a0bf528SMauro Carvalho Chehab
4559a0bf528SMauro Carvalho Chehab if (!config) {
4569a0bf528SMauro Carvalho Chehab printk(KERN_ERR "%s: no config specified", __func__);
4579a0bf528SMauro Carvalho Chehab return NULL;
4589a0bf528SMauro Carvalho Chehab }
4599a0bf528SMauro Carvalho Chehab
4609a0bf528SMauro Carvalho Chehab state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
4619a0bf528SMauro Carvalho Chehab if (!state)
4629a0bf528SMauro Carvalho Chehab return NULL;
4639a0bf528SMauro Carvalho Chehab
4649a0bf528SMauro Carvalho Chehab state->config = config;
4659a0bf528SMauro Carvalho Chehab state->i2c = i2c;
4669a0bf528SMauro Carvalho Chehab
4679a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
4689a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
4699a0bf528SMauro Carvalho Chehab
4709a0bf528SMauro Carvalho Chehab ret = zl10036_read_status_reg(state);
4719a0bf528SMauro Carvalho Chehab if (ret < 0) {
4729a0bf528SMauro Carvalho Chehab printk(KERN_ERR "%s: No zl10036 found\n", __func__);
4739a0bf528SMauro Carvalho Chehab goto error;
4749a0bf528SMauro Carvalho Chehab }
4759a0bf528SMauro Carvalho Chehab
4769a0bf528SMauro Carvalho Chehab ret = zl10036_init_regs(state);
4779a0bf528SMauro Carvalho Chehab if (ret < 0) {
4789a0bf528SMauro Carvalho Chehab printk(KERN_ERR "%s: tuner initialization failed\n",
4799a0bf528SMauro Carvalho Chehab __func__);
4809a0bf528SMauro Carvalho Chehab goto error;
4819a0bf528SMauro Carvalho Chehab }
4829a0bf528SMauro Carvalho Chehab
4839a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
4849a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
4859a0bf528SMauro Carvalho Chehab
4869a0bf528SMauro Carvalho Chehab fe->tuner_priv = state;
4879a0bf528SMauro Carvalho Chehab
4889a0bf528SMauro Carvalho Chehab memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops,
4899a0bf528SMauro Carvalho Chehab sizeof(struct dvb_tuner_ops));
4909a0bf528SMauro Carvalho Chehab printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n",
4919a0bf528SMauro Carvalho Chehab __func__, fe->ops.tuner_ops.info.name, config->tuner_address);
4929a0bf528SMauro Carvalho Chehab
4939a0bf528SMauro Carvalho Chehab return fe;
4949a0bf528SMauro Carvalho Chehab
4959a0bf528SMauro Carvalho Chehab error:
4969a0bf528SMauro Carvalho Chehab kfree(state);
4979a0bf528SMauro Carvalho Chehab return NULL;
4989a0bf528SMauro Carvalho Chehab }
499*86495af1SGreg Kroah-Hartman EXPORT_SYMBOL_GPL(zl10036_attach);
5009a0bf528SMauro Carvalho Chehab
5019a0bf528SMauro Carvalho Chehab module_param_named(debug, zl10036_debug, int, 0644);
5029a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
5039a0bf528SMauro Carvalho Chehab MODULE_DESCRIPTION("DVB ZL10036 driver");
5049a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Tino Reichardt");
5059a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Matthias Schwarzott");
5069a0bf528SMauro Carvalho Chehab MODULE_LICENSE("GPL");
507