1 /*
2     Montage Technology TS2020 - Silicon Tuner driver
3     Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
4 
5     Copyright (C) 2009-2012 TurboSight.com
6 
7     This program is free software; you can redistribute it and/or modify
8     it under the terms of the GNU General Public License as published by
9     the Free Software Foundation; either version 2 of the License, or
10     (at your option) any later version.
11 
12     This program is distributed in the hope that it will be useful,
13     but WITHOUT ANY WARRANTY; without even the implied warranty of
14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15     GNU General Public License for more details.
16 
17     You should have received a copy of the GNU General Public License
18     along with this program; if not, write to the Free Software
19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21 
22 #include "dvb_frontend.h"
23 #include "ts2020.h"
24 
25 #define TS2020_XTAL_FREQ   27000 /* in kHz */
26 #define FREQ_OFFSET_LOW_SYM_RATE 3000
27 
28 struct ts2020_priv {
29 	/* i2c details */
30 	int i2c_address;
31 	struct i2c_adapter *i2c;
32 	u8 clk_out_div;
33 	u32 frequency;
34 	u32 frequency_div;
35 };
36 
37 static int ts2020_release(struct dvb_frontend *fe)
38 {
39 	kfree(fe->tuner_priv);
40 	fe->tuner_priv = NULL;
41 	return 0;
42 }
43 
44 static int ts2020_writereg(struct dvb_frontend *fe, int reg, int data)
45 {
46 	struct ts2020_priv *priv = fe->tuner_priv;
47 	u8 buf[] = { reg, data };
48 	struct i2c_msg msg[] = {
49 		{
50 			.addr = priv->i2c_address,
51 			.flags = 0,
52 			.buf = buf,
53 			.len = 2
54 		}
55 	};
56 	int err;
57 
58 	if (fe->ops.i2c_gate_ctrl)
59 		fe->ops.i2c_gate_ctrl(fe, 1);
60 
61 	err = i2c_transfer(priv->i2c, msg, 1);
62 	if (err != 1) {
63 		printk(KERN_ERR
64 		       "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
65 		       __func__, err, reg, data);
66 		return -EREMOTEIO;
67 	}
68 
69 	if (fe->ops.i2c_gate_ctrl)
70 		fe->ops.i2c_gate_ctrl(fe, 0);
71 
72 	return 0;
73 }
74 
75 static int ts2020_readreg(struct dvb_frontend *fe, u8 reg)
76 {
77 	struct ts2020_priv *priv = fe->tuner_priv;
78 	int ret;
79 	u8 b0[] = { reg };
80 	u8 b1[] = { 0 };
81 	struct i2c_msg msg[] = {
82 		{
83 			.addr = priv->i2c_address,
84 			.flags = 0,
85 			.buf = b0,
86 			.len = 1
87 		}, {
88 			.addr = priv->i2c_address,
89 			.flags = I2C_M_RD,
90 			.buf = b1,
91 			.len = 1
92 		}
93 	};
94 
95 	if (fe->ops.i2c_gate_ctrl)
96 		fe->ops.i2c_gate_ctrl(fe, 1);
97 
98 	ret = i2c_transfer(priv->i2c, msg, 2);
99 
100 	if (ret != 2) {
101 		printk(KERN_ERR "%s: reg=0x%x(error=%d)\n",
102 		       __func__, reg, ret);
103 		return ret;
104 	}
105 
106 	if (fe->ops.i2c_gate_ctrl)
107 		fe->ops.i2c_gate_ctrl(fe, 0);
108 
109 	return b1[0];
110 }
111 
112 static int ts2020_sleep(struct dvb_frontend *fe)
113 {
114 	struct ts2020_priv *priv = fe->tuner_priv;
115 	int ret;
116 	u8 buf[] = { 10, 0 };
117 	struct i2c_msg msg = {
118 		.addr = priv->i2c_address,
119 		.flags = 0,
120 		.buf = buf,
121 		.len = 2
122 	};
123 
124 	if (fe->ops.i2c_gate_ctrl)
125 		fe->ops.i2c_gate_ctrl(fe, 1);
126 
127 	ret = i2c_transfer(priv->i2c, &msg, 1);
128 	if (ret != 1)
129 		printk(KERN_ERR "%s: i2c error\n", __func__);
130 
131 	if (fe->ops.i2c_gate_ctrl)
132 		fe->ops.i2c_gate_ctrl(fe, 0);
133 
134 	return (ret == 1) ? 0 : ret;
135 }
136 
137 static int ts2020_init(struct dvb_frontend *fe)
138 {
139 	struct ts2020_priv *priv = fe->tuner_priv;
140 
141 	ts2020_writereg(fe, 0x42, 0x73);
142 	ts2020_writereg(fe, 0x05, priv->clk_out_div);
143 	ts2020_writereg(fe, 0x20, 0x27);
144 	ts2020_writereg(fe, 0x07, 0x02);
145 	ts2020_writereg(fe, 0x11, 0xff);
146 	ts2020_writereg(fe, 0x60, 0xf9);
147 	ts2020_writereg(fe, 0x08, 0x01);
148 	ts2020_writereg(fe, 0x00, 0x41);
149 
150 	return 0;
151 }
152 
153 static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
154 {
155 	int ret;
156 	ret = ts2020_writereg(fe, 0x51, 0x1f - offset);
157 	ret |= ts2020_writereg(fe, 0x51, 0x1f);
158 	ret |= ts2020_writereg(fe, 0x50, offset);
159 	ret |= ts2020_writereg(fe, 0x50, 0x00);
160 	msleep(20);
161 	return ret;
162 }
163 
164 static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
165 {
166 	int reg;
167 
168 	reg = ts2020_readreg(fe, 0x3d);
169 	reg &= 0x7f;
170 	if (reg < 0x16)
171 		reg = 0xa1;
172 	else if (reg == 0x16)
173 		reg = 0x99;
174 	else
175 		reg = 0xf9;
176 
177 	ts2020_writereg(fe, 0x60, reg);
178 	reg = ts2020_tuner_gate_ctrl(fe, 0x08);
179 
180 	return reg;
181 }
182 
183 static int ts2020_set_params(struct dvb_frontend *fe)
184 {
185 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
186 	struct ts2020_priv *priv = fe->tuner_priv;
187 	int ret;
188 	u32 frequency = c->frequency;
189 	s32 offset_khz;
190 	u32 symbol_rate = (c->symbol_rate / 1000);
191 	u32 f3db, gdiv28;
192 	u16 value, ndiv, lpf_coeff;
193 	u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
194 	u8 lo = 0x01, div4 = 0x0;
195 
196 	/* Calculate frequency divider */
197 	if (frequency < priv->frequency_div) {
198 		lo |= 0x10;
199 		div4 = 0x1;
200 		ndiv = (frequency * 14 * 4) / TS2020_XTAL_FREQ;
201 	} else
202 		ndiv = (frequency * 14 * 2) / TS2020_XTAL_FREQ;
203 	ndiv = ndiv + ndiv % 2;
204 	ndiv = ndiv - 1024;
205 
206 	ret = ts2020_writereg(fe, 0x10, 0x80 | lo);
207 
208 	/* Set frequency divider */
209 	ret |= ts2020_writereg(fe, 0x01, (ndiv >> 8) & 0xf);
210 	ret |= ts2020_writereg(fe, 0x02, ndiv & 0xff);
211 
212 	ret |= ts2020_writereg(fe, 0x03, 0x06);
213 	ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
214 	if (ret < 0)
215 		return -ENODEV;
216 
217 	/* Tuner Frequency Range */
218 	ret = ts2020_writereg(fe, 0x10, lo);
219 
220 	ret |= ts2020_tuner_gate_ctrl(fe, 0x08);
221 
222 	/* Tuner RF */
223 	ret |= ts2020_set_tuner_rf(fe);
224 
225 	gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
226 	ret |= ts2020_writereg(fe, 0x04, gdiv28 & 0xff);
227 	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
228 	if (ret < 0)
229 		return -ENODEV;
230 
231 	value = ts2020_readreg(fe, 0x26);
232 
233 	f3db = (symbol_rate * 135) / 200 + 2000;
234 	f3db += FREQ_OFFSET_LOW_SYM_RATE;
235 	if (f3db < 7000)
236 		f3db = 7000;
237 	if (f3db > 40000)
238 		f3db = 40000;
239 
240 	gdiv28 = gdiv28 * 207 / (value * 2 + 151);
241 	mlpf_max = gdiv28 * 135 / 100;
242 	mlpf_min = gdiv28 * 78 / 100;
243 	if (mlpf_max > 63)
244 		mlpf_max = 63;
245 
246 	lpf_coeff = 2766;
247 
248 	nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
249 		(TS2020_XTAL_FREQ / 1000)  + 1) / 2;
250 	if (nlpf > 23)
251 		nlpf = 23;
252 	if (nlpf < 1)
253 		nlpf = 1;
254 
255 	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
256 		* lpf_coeff * 2  / f3db + 1) / 2;
257 
258 	if (lpf_mxdiv < mlpf_min) {
259 		nlpf++;
260 		lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
261 			* lpf_coeff * 2  / f3db + 1) / 2;
262 	}
263 
264 	if (lpf_mxdiv > mlpf_max)
265 		lpf_mxdiv = mlpf_max;
266 
267 	ret = ts2020_writereg(fe, 0x04, lpf_mxdiv);
268 	ret |= ts2020_writereg(fe, 0x06, nlpf);
269 
270 	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
271 
272 	ret |= ts2020_tuner_gate_ctrl(fe, 0x01);
273 
274 	msleep(80);
275 	/* calculate offset assuming 96000kHz*/
276 	offset_khz = (ndiv - ndiv % 2 + 1024) * TS2020_XTAL_FREQ
277 		/ (6 + 8) / (div4 + 1) / 2;
278 
279 	priv->frequency = offset_khz;
280 
281 	return (ret < 0) ? -EINVAL : 0;
282 }
283 
284 static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
285 {
286 	struct ts2020_priv *priv = fe->tuner_priv;
287 	*frequency = priv->frequency;
288 	return 0;
289 }
290 
291 /* read TS2020 signal strength */
292 static int ts2020_read_signal_strength(struct dvb_frontend *fe,
293 						u16 *signal_strength)
294 {
295 	u16 sig_reading, sig_strength;
296 	u8 rfgain, bbgain;
297 
298 	rfgain = ts2020_readreg(fe, 0x3d) & 0x1f;
299 	bbgain = ts2020_readreg(fe, 0x21) & 0x1f;
300 
301 	if (rfgain > 15)
302 		rfgain = 15;
303 	if (bbgain > 13)
304 		bbgain = 13;
305 
306 	sig_reading = rfgain * 2 + bbgain * 3;
307 
308 	sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
309 
310 	/* cook the value to be suitable for szap-s2 human readable output */
311 	*signal_strength = sig_strength * 1000;
312 
313 	return 0;
314 }
315 
316 static struct dvb_tuner_ops ts2020_tuner_ops = {
317 	.info = {
318 		.name = "TS2020",
319 		.frequency_min = 950000,
320 		.frequency_max = 2150000
321 	},
322 	.init = ts2020_init,
323 	.release = ts2020_release,
324 	.sleep = ts2020_sleep,
325 	.set_params = ts2020_set_params,
326 	.get_frequency = ts2020_get_frequency,
327 	.get_rf_strength = ts2020_read_signal_strength,
328 };
329 
330 struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
331 					const struct ts2020_config *config,
332 					struct i2c_adapter *i2c)
333 {
334 	struct ts2020_priv *priv = NULL;
335 	u8 buf;
336 
337 	priv = kzalloc(sizeof(struct ts2020_priv), GFP_KERNEL);
338 	if (priv == NULL)
339 		return NULL;
340 
341 	priv->i2c_address = config->tuner_address;
342 	priv->i2c = i2c;
343 	priv->clk_out_div = config->clk_out_div;
344 	priv->frequency_div = config->frequency_div;
345 	fe->tuner_priv = priv;
346 
347 	if (!priv->frequency_div)
348 		priv->frequency_div = 1060000;
349 
350 	/* Wake Up the tuner */
351 	if ((0x03 & ts2020_readreg(fe, 0x00)) == 0x00) {
352 		ts2020_writereg(fe, 0x00, 0x01);
353 		msleep(2);
354 	}
355 
356 	ts2020_writereg(fe, 0x00, 0x03);
357 	msleep(2);
358 
359 	/* Check the tuner version */
360 	buf = ts2020_readreg(fe, 0x00);
361 	if ((buf == 0x01) || (buf == 0x41) || (buf == 0x81))
362 		printk(KERN_INFO "%s: Find tuner TS2020!\n", __func__);
363 	else {
364 		printk(KERN_ERR "%s: Read tuner reg[0] = %d\n", __func__, buf);
365 		kfree(priv);
366 		return NULL;
367 	}
368 
369 	memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
370 				sizeof(struct dvb_tuner_ops));
371 
372 	return fe;
373 }
374 EXPORT_SYMBOL(ts2020_attach);
375 
376 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
377 MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
378 MODULE_LICENSE("GPL");
379