1 /* 2 * Toshiba TC90522 Demodulator 3 * 4 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 /* 18 * NOTICE: 19 * This driver is incomplete and lacks init/config of the chips, 20 * as the necessary info is not disclosed. 21 * It assumes that users of this driver (such as a PCI bridge of 22 * DTV receiver cards) properly init and configure the chip 23 * via I2C *before* calling this driver's init() function. 24 * 25 * Currently, PT3 driver is the only one that uses this driver, 26 * and contains init/config code in its firmware. 27 * Thus some part of the code might be dependent on PT3 specific config. 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/math64.h> 32 #include <linux/dvb/frontend.h> 33 #include "dvb_math.h" 34 #include "tc90522.h" 35 36 #define TC90522_I2C_THRU_REG 0xfe 37 38 #define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1) 39 40 struct tc90522_state { 41 struct tc90522_config cfg; 42 struct dvb_frontend fe; 43 struct i2c_client *i2c_client; 44 struct i2c_adapter tuner_i2c; 45 46 bool lna; 47 }; 48 49 struct reg_val { 50 u8 reg; 51 u8 val; 52 }; 53 54 static int 55 reg_write(struct tc90522_state *state, const struct reg_val *regs, int num) 56 { 57 int i, ret; 58 struct i2c_msg msg; 59 60 ret = 0; 61 msg.addr = state->i2c_client->addr; 62 msg.flags = 0; 63 msg.len = 2; 64 for (i = 0; i < num; i++) { 65 msg.buf = (u8 *)®s[i]; 66 ret = i2c_transfer(state->i2c_client->adapter, &msg, 1); 67 if (ret == 0) 68 ret = -EIO; 69 if (ret < 0) 70 return ret; 71 } 72 return 0; 73 } 74 75 static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len) 76 { 77 struct i2c_msg msgs[2] = { 78 { 79 .addr = state->i2c_client->addr, 80 .flags = 0, 81 .buf = ®, 82 .len = 1, 83 }, 84 { 85 .addr = state->i2c_client->addr, 86 .flags = I2C_M_RD, 87 .buf = val, 88 .len = len, 89 }, 90 }; 91 int ret; 92 93 ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs)); 94 if (ret == ARRAY_SIZE(msgs)) 95 ret = 0; 96 else if (ret >= 0) 97 ret = -EIO; 98 return ret; 99 } 100 101 static struct tc90522_state *cfg_to_state(struct tc90522_config *c) 102 { 103 return container_of(c, struct tc90522_state, cfg); 104 } 105 106 107 static int tc90522s_set_tsid(struct dvb_frontend *fe) 108 { 109 struct reg_val set_tsid[] = { 110 { 0x8f, 00 }, 111 { 0x90, 00 } 112 }; 113 114 set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8; 115 set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff; 116 return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid)); 117 } 118 119 static int tc90522t_set_layers(struct dvb_frontend *fe) 120 { 121 struct reg_val rv; 122 u8 laysel; 123 124 laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07; 125 laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2; 126 rv.reg = 0x71; 127 rv.val = laysel; 128 return reg_write(fe->demodulator_priv, &rv, 1); 129 } 130 131 /* frontend ops */ 132 133 static int tc90522s_read_status(struct dvb_frontend *fe, enum fe_status *status) 134 { 135 struct tc90522_state *state; 136 int ret; 137 u8 reg; 138 139 state = fe->demodulator_priv; 140 ret = reg_read(state, 0xc3, ®, 1); 141 if (ret < 0) 142 return ret; 143 144 *status = 0; 145 if (reg & 0x80) /* input level under min ? */ 146 return 0; 147 *status |= FE_HAS_SIGNAL; 148 149 if (reg & 0x60) /* carrier? */ 150 return 0; 151 *status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; 152 153 if (reg & 0x10) 154 return 0; 155 if (reg_read(state, 0xc5, ®, 1) < 0 || !(reg & 0x03)) 156 return 0; 157 *status |= FE_HAS_LOCK; 158 return 0; 159 } 160 161 static int tc90522t_read_status(struct dvb_frontend *fe, enum fe_status *status) 162 { 163 struct tc90522_state *state; 164 int ret; 165 u8 reg; 166 167 state = fe->demodulator_priv; 168 ret = reg_read(state, 0x96, ®, 1); 169 if (ret < 0) 170 return ret; 171 172 *status = 0; 173 if (reg & 0xe0) { 174 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI 175 | FE_HAS_SYNC | FE_HAS_LOCK; 176 return 0; 177 } 178 179 ret = reg_read(state, 0x80, ®, 1); 180 if (ret < 0) 181 return ret; 182 183 if (reg & 0xf0) 184 return 0; 185 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; 186 187 if (reg & 0x0c) 188 return 0; 189 *status |= FE_HAS_SYNC | FE_HAS_VITERBI; 190 191 if (reg & 0x02) 192 return 0; 193 *status |= FE_HAS_LOCK; 194 return 0; 195 } 196 197 static const enum fe_code_rate fec_conv_sat[] = { 198 FEC_NONE, /* unused */ 199 FEC_1_2, /* for BPSK */ 200 FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */ 201 FEC_2_3, /* for 8PSK. (trellis code) */ 202 }; 203 204 static int tc90522s_get_frontend(struct dvb_frontend *fe) 205 { 206 struct tc90522_state *state; 207 struct dtv_frontend_properties *c; 208 struct dtv_fe_stats *stats; 209 int ret, i; 210 int layers; 211 u8 val[10]; 212 u32 cndat; 213 214 state = fe->demodulator_priv; 215 c = &fe->dtv_property_cache; 216 c->delivery_system = SYS_ISDBS; 217 c->symbol_rate = 28860000; 218 219 layers = 0; 220 ret = reg_read(state, 0xe6, val, 5); 221 if (ret == 0) { 222 u8 v; 223 224 c->stream_id = val[0] << 8 | val[1]; 225 226 /* high/single layer */ 227 v = (val[2] & 0x70) >> 4; 228 c->modulation = (v == 7) ? PSK_8 : QPSK; 229 c->fec_inner = fec_conv_sat[v]; 230 c->layer[0].fec = c->fec_inner; 231 c->layer[0].modulation = c->modulation; 232 c->layer[0].segment_count = val[3] & 0x3f; /* slots */ 233 234 /* low layer */ 235 v = (val[2] & 0x07); 236 c->layer[1].fec = fec_conv_sat[v]; 237 if (v == 0) /* no low layer */ 238 c->layer[1].segment_count = 0; 239 else 240 c->layer[1].segment_count = val[4] & 0x3f; /* slots */ 241 /* 242 * actually, BPSK if v==1, but not defined in 243 * enum fe_modulation 244 */ 245 c->layer[1].modulation = QPSK; 246 layers = (v > 0) ? 2 : 1; 247 } 248 249 /* statistics */ 250 251 stats = &c->strength; 252 stats->len = 0; 253 /* let the connected tuner set RSSI property cache */ 254 if (fe->ops.tuner_ops.get_rf_strength) { 255 u16 dummy; 256 257 fe->ops.tuner_ops.get_rf_strength(fe, &dummy); 258 } 259 260 stats = &c->cnr; 261 stats->len = 1; 262 stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE; 263 cndat = 0; 264 ret = reg_read(state, 0xbc, val, 2); 265 if (ret == 0) 266 cndat = val[0] << 8 | val[1]; 267 if (cndat >= 3000) { 268 u32 p, p4; 269 s64 cn; 270 271 cndat -= 3000; /* cndat: 4.12 fixed point float */ 272 /* 273 * cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3 274 * + 88977 * P^2 - 89565 * P + 58857 275 * (P = sqrt(cndat) / 64) 276 */ 277 /* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed point float */ 278 /* cn = cnr << 3 */ 279 p = int_sqrt(cndat << 16); 280 p4 = cndat * cndat; 281 cn = div64_s64(-16346LL * p4 * p, 10) >> 35; 282 cn += (14341LL * p4) >> 21; 283 cn -= (50259LL * cndat * p) >> 23; 284 cn += (88977LL * cndat) >> 9; 285 cn -= (89565LL * p) >> 11; 286 cn += 58857 << 3; 287 stats->stat[0].svalue = cn >> 3; 288 stats->stat[0].scale = FE_SCALE_DECIBEL; 289 } 290 291 /* per-layer post viterbi BER (or PER? config dependent?) */ 292 stats = &c->post_bit_error; 293 memset(stats, 0, sizeof(*stats)); 294 stats->len = layers; 295 ret = reg_read(state, 0xeb, val, 10); 296 if (ret < 0) 297 for (i = 0; i < layers; i++) 298 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 299 else { 300 for (i = 0; i < layers; i++) { 301 stats->stat[i].scale = FE_SCALE_COUNTER; 302 stats->stat[i].uvalue = val[i * 5] << 16 303 | val[i * 5 + 1] << 8 | val[i * 5 + 2]; 304 } 305 } 306 stats = &c->post_bit_count; 307 memset(stats, 0, sizeof(*stats)); 308 stats->len = layers; 309 if (ret < 0) 310 for (i = 0; i < layers; i++) 311 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 312 else { 313 for (i = 0; i < layers; i++) { 314 stats->stat[i].scale = FE_SCALE_COUNTER; 315 stats->stat[i].uvalue = 316 val[i * 5 + 3] << 8 | val[i * 5 + 4]; 317 stats->stat[i].uvalue *= 204 * 8; 318 } 319 } 320 321 return 0; 322 } 323 324 325 static const enum fe_transmit_mode tm_conv[] = { 326 TRANSMISSION_MODE_2K, 327 TRANSMISSION_MODE_4K, 328 TRANSMISSION_MODE_8K, 329 0 330 }; 331 332 static const enum fe_code_rate fec_conv_ter[] = { 333 FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0 334 }; 335 336 static const enum fe_modulation mod_conv[] = { 337 DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0 338 }; 339 340 static int tc90522t_get_frontend(struct dvb_frontend *fe) 341 { 342 struct tc90522_state *state; 343 struct dtv_frontend_properties *c; 344 struct dtv_fe_stats *stats; 345 int ret, i; 346 int layers; 347 u8 val[15], mode; 348 u32 cndat; 349 350 state = fe->demodulator_priv; 351 c = &fe->dtv_property_cache; 352 c->delivery_system = SYS_ISDBT; 353 c->bandwidth_hz = 6000000; 354 mode = 1; 355 ret = reg_read(state, 0xb0, val, 1); 356 if (ret == 0) { 357 mode = (val[0] & 0xc0) >> 2; 358 c->transmission_mode = tm_conv[mode]; 359 c->guard_interval = (val[0] & 0x30) >> 4; 360 } 361 362 ret = reg_read(state, 0xb2, val, 6); 363 layers = 0; 364 if (ret == 0) { 365 u8 v; 366 367 c->isdbt_partial_reception = val[0] & 0x01; 368 c->isdbt_sb_mode = (val[0] & 0xc0) == 0x40; 369 370 /* layer A */ 371 v = (val[2] & 0x78) >> 3; 372 if (v == 0x0f) 373 c->layer[0].segment_count = 0; 374 else { 375 layers++; 376 c->layer[0].segment_count = v; 377 c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2]; 378 c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5]; 379 v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7; 380 c->layer[0].interleaving = v; 381 } 382 383 /* layer B */ 384 v = (val[3] & 0x03) << 1 | (val[4] & 0xc0) >> 6; 385 if (v == 0x0f) 386 c->layer[1].segment_count = 0; 387 else { 388 layers++; 389 c->layer[1].segment_count = v; 390 c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5]; 391 c->layer[1].modulation = mod_conv[(val[2] & 0x07)]; 392 c->layer[1].interleaving = (val[3] & 0x1c) >> 2; 393 } 394 395 /* layer C */ 396 v = (val[5] & 0x1e) >> 1; 397 if (v == 0x0f) 398 c->layer[2].segment_count = 0; 399 else { 400 layers++; 401 c->layer[2].segment_count = v; 402 c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)]; 403 c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3]; 404 c->layer[2].interleaving = (val[5] & 0xe0) >> 5; 405 } 406 } 407 408 /* statistics */ 409 410 stats = &c->strength; 411 stats->len = 0; 412 /* let the connected tuner set RSSI property cache */ 413 if (fe->ops.tuner_ops.get_rf_strength) { 414 u16 dummy; 415 416 fe->ops.tuner_ops.get_rf_strength(fe, &dummy); 417 } 418 419 stats = &c->cnr; 420 stats->len = 1; 421 stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE; 422 cndat = 0; 423 ret = reg_read(state, 0x8b, val, 3); 424 if (ret == 0) 425 cndat = val[0] << 16 | val[1] << 8 | val[2]; 426 if (cndat != 0) { 427 u32 p, tmp; 428 s64 cn; 429 430 /* 431 * cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5 432 * (P = 10log10(5505024/cndat)) 433 */ 434 /* cn = cnr << 3 (61.3 fixed point float */ 435 /* p = 10log10(5505024/cndat) << 24 (8.24 fixed point float)*/ 436 p = intlog10(5505024) - intlog10(cndat); 437 p *= 10; 438 439 cn = 24772; 440 cn += div64_s64(43827LL * p, 10) >> 24; 441 tmp = p >> 8; 442 cn += div64_s64(3184LL * tmp * tmp, 10) >> 32; 443 tmp = p >> 13; 444 cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33; 445 tmp = p >> 18; 446 cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24; 447 448 stats->stat[0].svalue = cn >> 3; 449 stats->stat[0].scale = FE_SCALE_DECIBEL; 450 } 451 452 /* per-layer post viterbi BER (or PER? config dependent?) */ 453 stats = &c->post_bit_error; 454 memset(stats, 0, sizeof(*stats)); 455 stats->len = layers; 456 ret = reg_read(state, 0x9d, val, 15); 457 if (ret < 0) 458 for (i = 0; i < layers; i++) 459 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 460 else { 461 for (i = 0; i < layers; i++) { 462 stats->stat[i].scale = FE_SCALE_COUNTER; 463 stats->stat[i].uvalue = val[i * 3] << 16 464 | val[i * 3 + 1] << 8 | val[i * 3 + 2]; 465 } 466 } 467 stats = &c->post_bit_count; 468 memset(stats, 0, sizeof(*stats)); 469 stats->len = layers; 470 if (ret < 0) 471 for (i = 0; i < layers; i++) 472 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 473 else { 474 for (i = 0; i < layers; i++) { 475 stats->stat[i].scale = FE_SCALE_COUNTER; 476 stats->stat[i].uvalue = 477 val[9 + i * 2] << 8 | val[9 + i * 2 + 1]; 478 stats->stat[i].uvalue *= 204 * 8; 479 } 480 } 481 482 return 0; 483 } 484 485 static const struct reg_val reset_sat = { 0x03, 0x01 }; 486 static const struct reg_val reset_ter = { 0x01, 0x40 }; 487 488 static int tc90522_set_frontend(struct dvb_frontend *fe) 489 { 490 struct tc90522_state *state; 491 int ret; 492 493 state = fe->demodulator_priv; 494 495 if (fe->ops.tuner_ops.set_params) 496 ret = fe->ops.tuner_ops.set_params(fe); 497 else 498 ret = -ENODEV; 499 if (ret < 0) 500 goto failed; 501 502 if (fe->ops.delsys[0] == SYS_ISDBS) { 503 ret = tc90522s_set_tsid(fe); 504 if (ret < 0) 505 goto failed; 506 ret = reg_write(state, &reset_sat, 1); 507 } else { 508 ret = tc90522t_set_layers(fe); 509 if (ret < 0) 510 goto failed; 511 ret = reg_write(state, &reset_ter, 1); 512 } 513 if (ret < 0) 514 goto failed; 515 516 return 0; 517 518 failed: 519 dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n", 520 __func__, fe->dvb->num, fe->id); 521 return ret; 522 } 523 524 static int tc90522_get_tune_settings(struct dvb_frontend *fe, 525 struct dvb_frontend_tune_settings *settings) 526 { 527 if (fe->ops.delsys[0] == SYS_ISDBS) { 528 settings->min_delay_ms = 250; 529 settings->step_size = 1000; 530 settings->max_drift = settings->step_size * 2; 531 } else { 532 settings->min_delay_ms = 400; 533 settings->step_size = 142857; 534 settings->max_drift = settings->step_size; 535 } 536 return 0; 537 } 538 539 static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on) 540 { 541 struct reg_val agc_sat[] = { 542 { 0x0a, 0x00 }, 543 { 0x10, 0x30 }, 544 { 0x11, 0x00 }, 545 { 0x03, 0x01 }, 546 }; 547 struct reg_val agc_ter[] = { 548 { 0x25, 0x00 }, 549 { 0x23, 0x4c }, 550 { 0x01, 0x40 }, 551 }; 552 struct tc90522_state *state; 553 struct reg_val *rv; 554 int num; 555 556 state = fe->demodulator_priv; 557 if (fe->ops.delsys[0] == SYS_ISDBS) { 558 agc_sat[0].val = on ? 0xff : 0x00; 559 agc_sat[1].val |= 0x80; 560 agc_sat[1].val |= on ? 0x01 : 0x00; 561 agc_sat[2].val |= on ? 0x40 : 0x00; 562 rv = agc_sat; 563 num = ARRAY_SIZE(agc_sat); 564 } else { 565 agc_ter[0].val = on ? 0x40 : 0x00; 566 agc_ter[1].val |= on ? 0x00 : 0x01; 567 rv = agc_ter; 568 num = ARRAY_SIZE(agc_ter); 569 } 570 return reg_write(state, rv, num); 571 } 572 573 static const struct reg_val sleep_sat = { 0x17, 0x01 }; 574 static const struct reg_val sleep_ter = { 0x03, 0x90 }; 575 576 static int tc90522_sleep(struct dvb_frontend *fe) 577 { 578 struct tc90522_state *state; 579 int ret; 580 581 state = fe->demodulator_priv; 582 if (fe->ops.delsys[0] == SYS_ISDBS) 583 ret = reg_write(state, &sleep_sat, 1); 584 else { 585 ret = reg_write(state, &sleep_ter, 1); 586 if (ret == 0 && fe->ops.set_lna && 587 fe->dtv_property_cache.lna == LNA_AUTO) { 588 fe->dtv_property_cache.lna = 0; 589 ret = fe->ops.set_lna(fe); 590 fe->dtv_property_cache.lna = LNA_AUTO; 591 } 592 } 593 if (ret < 0) 594 dev_warn(&state->tuner_i2c.dev, 595 "(%s) failed. [adap%d-fe%d]\n", 596 __func__, fe->dvb->num, fe->id); 597 return ret; 598 } 599 600 static const struct reg_val wakeup_sat = { 0x17, 0x00 }; 601 static const struct reg_val wakeup_ter = { 0x03, 0x80 }; 602 603 static int tc90522_init(struct dvb_frontend *fe) 604 { 605 struct tc90522_state *state; 606 int ret; 607 608 /* 609 * Because the init sequence is not public, 610 * the parent device/driver should have init'ed the device before. 611 * just wake up the device here. 612 */ 613 614 state = fe->demodulator_priv; 615 if (fe->ops.delsys[0] == SYS_ISDBS) 616 ret = reg_write(state, &wakeup_sat, 1); 617 else { 618 ret = reg_write(state, &wakeup_ter, 1); 619 if (ret == 0 && fe->ops.set_lna && 620 fe->dtv_property_cache.lna == LNA_AUTO) { 621 fe->dtv_property_cache.lna = 1; 622 ret = fe->ops.set_lna(fe); 623 fe->dtv_property_cache.lna = LNA_AUTO; 624 } 625 } 626 if (ret < 0) { 627 dev_warn(&state->tuner_i2c.dev, 628 "(%s) failed. [adap%d-fe%d]\n", 629 __func__, fe->dvb->num, fe->id); 630 return ret; 631 } 632 633 /* prefer 'all-layers' to 'none' as a default */ 634 if (fe->dtv_property_cache.isdbt_layer_enabled == 0) 635 fe->dtv_property_cache.isdbt_layer_enabled = 7; 636 return tc90522_set_if_agc(fe, true); 637 } 638 639 640 /* 641 * tuner I2C adapter functions 642 */ 643 644 static int 645 tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 646 { 647 struct tc90522_state *state; 648 struct i2c_msg *new_msgs; 649 int i, j; 650 int ret, rd_num; 651 u8 wbuf[256]; 652 u8 *p, *bufend; 653 654 if (num <= 0) 655 return -EINVAL; 656 657 rd_num = 0; 658 for (i = 0; i < num; i++) 659 if (msgs[i].flags & I2C_M_RD) 660 rd_num++; 661 new_msgs = kmalloc(sizeof(*new_msgs) * (num + rd_num), GFP_KERNEL); 662 if (!new_msgs) 663 return -ENOMEM; 664 665 state = i2c_get_adapdata(adap); 666 p = wbuf; 667 bufend = wbuf + sizeof(wbuf); 668 for (i = 0, j = 0; i < num; i++, j++) { 669 new_msgs[j].addr = state->i2c_client->addr; 670 new_msgs[j].flags = msgs[i].flags; 671 672 if (msgs[i].flags & I2C_M_RD) { 673 new_msgs[j].flags &= ~I2C_M_RD; 674 if (p + 2 > bufend) 675 break; 676 p[0] = TC90522_I2C_THRU_REG; 677 p[1] = msgs[i].addr << 1 | 0x01; 678 new_msgs[j].buf = p; 679 new_msgs[j].len = 2; 680 p += 2; 681 j++; 682 new_msgs[j].addr = state->i2c_client->addr; 683 new_msgs[j].flags = msgs[i].flags; 684 new_msgs[j].buf = msgs[i].buf; 685 new_msgs[j].len = msgs[i].len; 686 continue; 687 } 688 689 if (p + msgs[i].len + 2 > bufend) 690 break; 691 p[0] = TC90522_I2C_THRU_REG; 692 p[1] = msgs[i].addr << 1; 693 memcpy(p + 2, msgs[i].buf, msgs[i].len); 694 new_msgs[j].buf = p; 695 new_msgs[j].len = msgs[i].len + 2; 696 p += new_msgs[j].len; 697 } 698 699 if (i < num) 700 ret = -ENOMEM; 701 else 702 ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j); 703 if (ret >= 0 && ret < j) 704 ret = -EIO; 705 kfree(new_msgs); 706 return (ret == j) ? num : ret; 707 } 708 709 static u32 tc90522_functionality(struct i2c_adapter *adap) 710 { 711 return I2C_FUNC_I2C; 712 } 713 714 static const struct i2c_algorithm tc90522_tuner_i2c_algo = { 715 .master_xfer = &tc90522_master_xfer, 716 .functionality = &tc90522_functionality, 717 }; 718 719 720 /* 721 * I2C driver functions 722 */ 723 724 static const struct dvb_frontend_ops tc90522_ops_sat = { 725 .delsys = { SYS_ISDBS }, 726 .info = { 727 .name = "Toshiba TC90522 ISDB-S module", 728 .frequency_min = 950000, 729 .frequency_max = 2150000, 730 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | 731 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | 732 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 733 }, 734 735 .init = tc90522_init, 736 .sleep = tc90522_sleep, 737 .set_frontend = tc90522_set_frontend, 738 .get_tune_settings = tc90522_get_tune_settings, 739 740 .get_frontend = tc90522s_get_frontend, 741 .read_status = tc90522s_read_status, 742 }; 743 744 static const struct dvb_frontend_ops tc90522_ops_ter = { 745 .delsys = { SYS_ISDBT }, 746 .info = { 747 .name = "Toshiba TC90522 ISDB-T module", 748 .frequency_min = 470000000, 749 .frequency_max = 770000000, 750 .frequency_stepsize = 142857, 751 .caps = FE_CAN_INVERSION_AUTO | 752 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 753 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 754 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 755 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | 756 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | 757 FE_CAN_HIERARCHY_AUTO, 758 }, 759 760 .init = tc90522_init, 761 .sleep = tc90522_sleep, 762 .set_frontend = tc90522_set_frontend, 763 .get_tune_settings = tc90522_get_tune_settings, 764 765 .get_frontend = tc90522t_get_frontend, 766 .read_status = tc90522t_read_status, 767 }; 768 769 770 static int tc90522_probe(struct i2c_client *client, 771 const struct i2c_device_id *id) 772 { 773 struct tc90522_state *state; 774 struct tc90522_config *cfg; 775 const struct dvb_frontend_ops *ops; 776 struct i2c_adapter *adap; 777 int ret; 778 779 state = kzalloc(sizeof(*state), GFP_KERNEL); 780 if (!state) 781 return -ENOMEM; 782 state->i2c_client = client; 783 784 cfg = client->dev.platform_data; 785 memcpy(&state->cfg, cfg, sizeof(state->cfg)); 786 cfg->fe = state->cfg.fe = &state->fe; 787 ops = id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter; 788 memcpy(&state->fe.ops, ops, sizeof(*ops)); 789 state->fe.demodulator_priv = state; 790 791 adap = &state->tuner_i2c; 792 adap->owner = THIS_MODULE; 793 adap->algo = &tc90522_tuner_i2c_algo; 794 adap->dev.parent = &client->dev; 795 strlcpy(adap->name, "tc90522_sub", sizeof(adap->name)); 796 i2c_set_adapdata(adap, state); 797 ret = i2c_add_adapter(adap); 798 if (ret < 0) 799 goto err; 800 cfg->tuner_i2c = state->cfg.tuner_i2c = adap; 801 802 i2c_set_clientdata(client, &state->cfg); 803 dev_info(&client->dev, "Toshiba TC90522 attached.\n"); 804 return 0; 805 806 err: 807 kfree(state); 808 return ret; 809 } 810 811 static int tc90522_remove(struct i2c_client *client) 812 { 813 struct tc90522_state *state; 814 815 state = cfg_to_state(i2c_get_clientdata(client)); 816 i2c_del_adapter(&state->tuner_i2c); 817 kfree(state); 818 return 0; 819 } 820 821 822 static const struct i2c_device_id tc90522_id[] = { 823 { TC90522_I2C_DEV_SAT, 0 }, 824 { TC90522_I2C_DEV_TER, 1 }, 825 {} 826 }; 827 MODULE_DEVICE_TABLE(i2c, tc90522_id); 828 829 static struct i2c_driver tc90522_driver = { 830 .driver = { 831 .name = "tc90522", 832 }, 833 .probe = tc90522_probe, 834 .remove = tc90522_remove, 835 .id_table = tc90522_id, 836 }; 837 838 module_i2c_driver(tc90522_driver); 839 840 MODULE_DESCRIPTION("Toshiba TC90522 frontend"); 841 MODULE_AUTHOR("Akihiro TSUKADA"); 842 MODULE_LICENSE("GPL"); 843