1 /* 2 * Driver for the ST STV0910 DVB-S/S2 demodulator. 3 * 4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de> 5 * Marcus Metzler <mocm@metzlerbros.de> 6 * developed for Digital Devices GmbH 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 only, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/firmware.h> 24 #include <linux/i2c.h> 25 #include <asm/div64.h> 26 27 #include "dvb_math.h" 28 #include "dvb_frontend.h" 29 #include "stv0910.h" 30 #include "stv0910_regs.h" 31 32 #define EXT_CLOCK 30000000 33 #define TUNING_DELAY 200 34 #define BER_SRC_S 0x20 35 #define BER_SRC_S2 0x20 36 37 static LIST_HEAD(stvlist); 38 39 enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO }; 40 41 enum dvbs2_fectype { DVBS2_64K, DVBS2_16K }; 42 43 enum dvbs2_mod_cod { 44 DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5, 45 DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4, 46 DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10, 47 DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6, 48 DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4, 49 DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10, 50 DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9, 51 DVBS2_32APSK_9_10 52 }; 53 54 enum fe_stv0910_mod_cod { 55 FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25, 56 FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34, 57 FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910, 58 FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56, 59 FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34, 60 FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910, 61 FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89, 62 FE_32APSK_910 63 }; 64 65 enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 }; 66 67 static inline u32 muldiv32(u32 a, u32 b, u32 c) 68 { 69 u64 tmp64; 70 71 tmp64 = (u64)a * (u64)b; 72 do_div(tmp64, c); 73 74 return (u32)tmp64; 75 } 76 77 struct stv_base { 78 struct list_head stvlist; 79 80 u8 adr; 81 struct i2c_adapter *i2c; 82 struct mutex i2c_lock; /* shared I2C access protect */ 83 struct mutex reg_lock; /* shared register write protect */ 84 int count; 85 86 u32 extclk; 87 u32 mclk; 88 }; 89 90 struct stv { 91 struct stv_base *base; 92 struct dvb_frontend fe; 93 int nr; 94 u16 regoff; 95 u8 i2crpt; 96 u8 tscfgh; 97 u8 tsgeneral; 98 u8 tsspeed; 99 u8 single; 100 unsigned long tune_time; 101 102 s32 search_range; 103 u32 started; 104 u32 demod_lock_time; 105 enum receive_mode receive_mode; 106 u32 demod_timeout; 107 u32 fec_timeout; 108 u32 first_time_lock; 109 u8 demod_bits; 110 u32 symbol_rate; 111 112 u8 last_viterbi_rate; 113 enum fe_code_rate puncture_rate; 114 enum fe_stv0910_mod_cod mod_cod; 115 enum dvbs2_fectype fectype; 116 u32 pilots; 117 enum fe_stv0910_roll_off feroll_off; 118 119 int is_standard_broadcast; 120 int is_vcm; 121 122 u32 cur_scrambling_code; 123 124 u32 last_bernumerator; 125 u32 last_berdenominator; 126 u8 berscale; 127 128 u8 vth[6]; 129 }; 130 131 struct sinit_table { 132 u16 address; 133 u8 data; 134 }; 135 136 struct slookup { 137 s16 value; 138 u32 reg_value; 139 }; 140 141 static inline int i2c_write(struct i2c_adapter *adap, u8 adr, 142 u8 *data, int len) 143 { 144 struct i2c_msg msg = {.addr = adr, .flags = 0, 145 .buf = data, .len = len}; 146 147 if (i2c_transfer(adap, &msg, 1) != 1) { 148 dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n", 149 adr, (data[0] << 8) | data[1], 150 (len > 2 ? data[2] : 0)); 151 return -EREMOTEIO; 152 } 153 return 0; 154 } 155 156 static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, u16 reg, u8 val) 157 { 158 u8 msg[3] = {reg >> 8, reg & 0xff, val}; 159 160 return i2c_write(adap, adr, msg, 3); 161 } 162 163 static int write_reg(struct stv *state, u16 reg, u8 val) 164 { 165 return i2c_write_reg16(state->base->i2c, state->base->adr, reg, val); 166 } 167 168 static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, 169 u16 reg, u8 *val, int count) 170 { 171 u8 msg[2] = {reg >> 8, reg & 0xff}; 172 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 173 .buf = msg, .len = 2}, 174 {.addr = adr, .flags = I2C_M_RD, 175 .buf = val, .len = count } }; 176 177 if (i2c_transfer(adapter, msgs, 2) != 2) { 178 dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n", 179 adr, reg); 180 return -EREMOTEIO; 181 } 182 return 0; 183 } 184 185 static int read_reg(struct stv *state, u16 reg, u8 *val) 186 { 187 return i2c_read_regs16(state->base->i2c, state->base->adr, 188 reg, val, 1); 189 } 190 191 static int read_regs(struct stv *state, u16 reg, u8 *val, int len) 192 { 193 return i2c_read_regs16(state->base->i2c, state->base->adr, 194 reg, val, len); 195 } 196 197 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) 198 { 199 int status; 200 u8 tmp; 201 202 mutex_lock(&state->base->reg_lock); 203 status = read_reg(state, reg, &tmp); 204 if (!status) 205 status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); 206 mutex_unlock(&state->base->reg_lock); 207 return status; 208 } 209 210 static const struct slookup s1_sn_lookup[] = { 211 { 0, 9242 }, /* C/N= 0dB */ 212 { 5, 9105 }, /* C/N= 0.5dB */ 213 { 10, 8950 }, /* C/N= 1.0dB */ 214 { 15, 8780 }, /* C/N= 1.5dB */ 215 { 20, 8566 }, /* C/N= 2.0dB */ 216 { 25, 8366 }, /* C/N= 2.5dB */ 217 { 30, 8146 }, /* C/N= 3.0dB */ 218 { 35, 7908 }, /* C/N= 3.5dB */ 219 { 40, 7666 }, /* C/N= 4.0dB */ 220 { 45, 7405 }, /* C/N= 4.5dB */ 221 { 50, 7136 }, /* C/N= 5.0dB */ 222 { 55, 6861 }, /* C/N= 5.5dB */ 223 { 60, 6576 }, /* C/N= 6.0dB */ 224 { 65, 6330 }, /* C/N= 6.5dB */ 225 { 70, 6048 }, /* C/N= 7.0dB */ 226 { 75, 5768 }, /* C/N= 7.5dB */ 227 { 80, 5492 }, /* C/N= 8.0dB */ 228 { 85, 5224 }, /* C/N= 8.5dB */ 229 { 90, 4959 }, /* C/N= 9.0dB */ 230 { 95, 4709 }, /* C/N= 9.5dB */ 231 { 100, 4467 }, /* C/N=10.0dB */ 232 { 105, 4236 }, /* C/N=10.5dB */ 233 { 110, 4013 }, /* C/N=11.0dB */ 234 { 115, 3800 }, /* C/N=11.5dB */ 235 { 120, 3598 }, /* C/N=12.0dB */ 236 { 125, 3406 }, /* C/N=12.5dB */ 237 { 130, 3225 }, /* C/N=13.0dB */ 238 { 135, 3052 }, /* C/N=13.5dB */ 239 { 140, 2889 }, /* C/N=14.0dB */ 240 { 145, 2733 }, /* C/N=14.5dB */ 241 { 150, 2587 }, /* C/N=15.0dB */ 242 { 160, 2318 }, /* C/N=16.0dB */ 243 { 170, 2077 }, /* C/N=17.0dB */ 244 { 180, 1862 }, /* C/N=18.0dB */ 245 { 190, 1670 }, /* C/N=19.0dB */ 246 { 200, 1499 }, /* C/N=20.0dB */ 247 { 210, 1347 }, /* C/N=21.0dB */ 248 { 220, 1213 }, /* C/N=22.0dB */ 249 { 230, 1095 }, /* C/N=23.0dB */ 250 { 240, 992 }, /* C/N=24.0dB */ 251 { 250, 900 }, /* C/N=25.0dB */ 252 { 260, 826 }, /* C/N=26.0dB */ 253 { 270, 758 }, /* C/N=27.0dB */ 254 { 280, 702 }, /* C/N=28.0dB */ 255 { 290, 653 }, /* C/N=29.0dB */ 256 { 300, 613 }, /* C/N=30.0dB */ 257 { 310, 579 }, /* C/N=31.0dB */ 258 { 320, 550 }, /* C/N=32.0dB */ 259 { 330, 526 }, /* C/N=33.0dB */ 260 { 350, 490 }, /* C/N=33.0dB */ 261 { 400, 445 }, /* C/N=40.0dB */ 262 { 450, 430 }, /* C/N=45.0dB */ 263 { 500, 426 }, /* C/N=50.0dB */ 264 { 510, 425 } /* C/N=51.0dB */ 265 }; 266 267 static const struct slookup s2_sn_lookup[] = { 268 { -30, 13950 }, /* C/N=-2.5dB */ 269 { -25, 13580 }, /* C/N=-2.5dB */ 270 { -20, 13150 }, /* C/N=-2.0dB */ 271 { -15, 12760 }, /* C/N=-1.5dB */ 272 { -10, 12345 }, /* C/N=-1.0dB */ 273 { -5, 11900 }, /* C/N=-0.5dB */ 274 { 0, 11520 }, /* C/N= 0dB */ 275 { 5, 11080 }, /* C/N= 0.5dB */ 276 { 10, 10630 }, /* C/N= 1.0dB */ 277 { 15, 10210 }, /* C/N= 1.5dB */ 278 { 20, 9790 }, /* C/N= 2.0dB */ 279 { 25, 9390 }, /* C/N= 2.5dB */ 280 { 30, 8970 }, /* C/N= 3.0dB */ 281 { 35, 8575 }, /* C/N= 3.5dB */ 282 { 40, 8180 }, /* C/N= 4.0dB */ 283 { 45, 7800 }, /* C/N= 4.5dB */ 284 { 50, 7430 }, /* C/N= 5.0dB */ 285 { 55, 7080 }, /* C/N= 5.5dB */ 286 { 60, 6720 }, /* C/N= 6.0dB */ 287 { 65, 6320 }, /* C/N= 6.5dB */ 288 { 70, 6060 }, /* C/N= 7.0dB */ 289 { 75, 5760 }, /* C/N= 7.5dB */ 290 { 80, 5480 }, /* C/N= 8.0dB */ 291 { 85, 5200 }, /* C/N= 8.5dB */ 292 { 90, 4930 }, /* C/N= 9.0dB */ 293 { 95, 4680 }, /* C/N= 9.5dB */ 294 { 100, 4425 }, /* C/N=10.0dB */ 295 { 105, 4210 }, /* C/N=10.5dB */ 296 { 110, 3980 }, /* C/N=11.0dB */ 297 { 115, 3765 }, /* C/N=11.5dB */ 298 { 120, 3570 }, /* C/N=12.0dB */ 299 { 125, 3315 }, /* C/N=12.5dB */ 300 { 130, 3140 }, /* C/N=13.0dB */ 301 { 135, 2980 }, /* C/N=13.5dB */ 302 { 140, 2820 }, /* C/N=14.0dB */ 303 { 145, 2670 }, /* C/N=14.5dB */ 304 { 150, 2535 }, /* C/N=15.0dB */ 305 { 160, 2270 }, /* C/N=16.0dB */ 306 { 170, 2035 }, /* C/N=17.0dB */ 307 { 180, 1825 }, /* C/N=18.0dB */ 308 { 190, 1650 }, /* C/N=19.0dB */ 309 { 200, 1485 }, /* C/N=20.0dB */ 310 { 210, 1340 }, /* C/N=21.0dB */ 311 { 220, 1212 }, /* C/N=22.0dB */ 312 { 230, 1100 }, /* C/N=23.0dB */ 313 { 240, 1000 }, /* C/N=24.0dB */ 314 { 250, 910 }, /* C/N=25.0dB */ 315 { 260, 836 }, /* C/N=26.0dB */ 316 { 270, 772 }, /* C/N=27.0dB */ 317 { 280, 718 }, /* C/N=28.0dB */ 318 { 290, 671 }, /* C/N=29.0dB */ 319 { 300, 635 }, /* C/N=30.0dB */ 320 { 310, 602 }, /* C/N=31.0dB */ 321 { 320, 575 }, /* C/N=32.0dB */ 322 { 330, 550 }, /* C/N=33.0dB */ 323 { 350, 517 }, /* C/N=35.0dB */ 324 { 400, 480 }, /* C/N=40.0dB */ 325 { 450, 466 }, /* C/N=45.0dB */ 326 { 500, 464 }, /* C/N=50.0dB */ 327 { 510, 463 }, /* C/N=51.0dB */ 328 }; 329 330 static const struct slookup padc_lookup[] = { 331 { 0, 118000 }, /* PADC= +0dBm */ 332 { -100, 93600 }, /* PADC= -1dBm */ 333 { -200, 74500 }, /* PADC= -2dBm */ 334 { -300, 59100 }, /* PADC= -3dBm */ 335 { -400, 47000 }, /* PADC= -4dBm */ 336 { -500, 37300 }, /* PADC= -5dBm */ 337 { -600, 29650 }, /* PADC= -6dBm */ 338 { -700, 23520 }, /* PADC= -7dBm */ 339 { -900, 14850 }, /* PADC= -9dBm */ 340 { -1100, 9380 }, /* PADC=-11dBm */ 341 { -1300, 5910 }, /* PADC=-13dBm */ 342 { -1500, 3730 }, /* PADC=-15dBm */ 343 { -1700, 2354 }, /* PADC=-17dBm */ 344 { -1900, 1485 }, /* PADC=-19dBm */ 345 { -2000, 1179 }, /* PADC=-20dBm */ 346 { -2100, 1000 }, /* PADC=-21dBm */ 347 }; 348 349 /********************************************************************* 350 * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame 351 *********************************************************************/ 352 static const u8 s2car_loop[] = { 353 /* 354 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 355 * 20MPon 20MPoff 30MPon 30MPoff 356 */ 357 358 /* FE_QPSK_14 */ 359 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B, 360 /* FE_QPSK_13 */ 361 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B, 362 /* FE_QPSK_25 */ 363 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B, 364 /* FE_QPSK_12 */ 365 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, 366 /* FE_QPSK_35 */ 367 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, 368 /* FE_QPSK_23 */ 369 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, 370 /* FE_QPSK_34 */ 371 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B, 372 /* FE_QPSK_45 */ 373 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B, 374 /* FE_QPSK_56 */ 375 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B, 376 /* FE_QPSK_89 */ 377 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B, 378 /* FE_QPSK_910 */ 379 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B, 380 /* FE_8PSK_35 */ 381 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27, 382 /* FE_8PSK_23 */ 383 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09, 384 /* FE_8PSK_34 */ 385 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A, 386 /* FE_8PSK_56 */ 387 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A, 388 /* FE_8PSK_89 */ 389 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A, 390 /* FE_8PSK_910 */ 391 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A, 392 393 /********************************************************************** 394 * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame 395 **********************************************************************/ 396 397 /* 398 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 399 * 20MPoff 30MPon 30MPoff 400 */ 401 402 /* FE_16APSK_23 */ 403 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A, 404 /* FE_16APSK_34 */ 405 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A, 406 /* FE_16APSK_45 */ 407 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A, 408 /* FE_16APSK_56 */ 409 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A, 410 /* FE_16APSK_89 */ 411 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A, 412 /* FE_16APSK_910 */ 413 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A, 414 /* FE_32APSK_34 */ 415 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 416 /* FE_32APSK_45 */ 417 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 418 /* FE_32APSK_56 */ 419 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 420 /* FE_32APSK_89 */ 421 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 422 /* FE_32APSK_910 */ 423 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 424 }; 425 426 static u8 get_optim_cloop(struct stv *state, 427 enum fe_stv0910_mod_cod mod_cod, u32 pilots) 428 { 429 int i = 0; 430 431 if (mod_cod >= FE_32APSK_910) 432 i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10; 433 else if (mod_cod >= FE_QPSK_14) 434 i = ((int)mod_cod - (int)FE_QPSK_14) * 10; 435 436 if (state->symbol_rate <= 3000000) 437 i += 0; 438 else if (state->symbol_rate <= 7000000) 439 i += 2; 440 else if (state->symbol_rate <= 15000000) 441 i += 4; 442 else if (state->symbol_rate <= 25000000) 443 i += 6; 444 else 445 i += 8; 446 447 if (!pilots) 448 i += 1; 449 450 return s2car_loop[i]; 451 } 452 453 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate) 454 { 455 int status = 0; 456 u8 symb_freq0; 457 u8 symb_freq1; 458 u8 symb_freq2; 459 u8 symb_freq3; 460 u8 tim_offs0; 461 u8 tim_offs1; 462 u8 tim_offs2; 463 u32 symbol_rate; 464 s32 timing_offset; 465 466 *p_symbol_rate = 0; 467 if (!state->started) 468 return status; 469 470 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3); 471 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2); 472 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1); 473 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0); 474 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2); 475 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1); 476 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0); 477 478 symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) | 479 ((u32)symb_freq1 << 8) | (u32)symb_freq0; 480 timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) | 481 (u32)tim_offs0; 482 483 if ((timing_offset & (1 << 23)) != 0) 484 timing_offset |= 0xFF000000; /* Sign extent */ 485 486 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32); 487 timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29); 488 489 *p_symbol_rate = symbol_rate + timing_offset; 490 491 return 0; 492 } 493 494 static int get_signal_parameters(struct stv *state) 495 { 496 u8 tmp; 497 498 if (!state->started) 499 return -EINVAL; 500 501 if (state->receive_mode == RCVMODE_DVBS2) { 502 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); 503 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); 504 state->pilots = (tmp & 0x01) != 0; 505 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1); 506 507 } else if (state->receive_mode == RCVMODE_DVBS) { 508 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); 509 state->puncture_rate = FEC_NONE; 510 switch (tmp & 0x1F) { 511 case 0x0d: 512 state->puncture_rate = FEC_1_2; 513 break; 514 case 0x12: 515 state->puncture_rate = FEC_2_3; 516 break; 517 case 0x15: 518 state->puncture_rate = FEC_3_4; 519 break; 520 case 0x18: 521 state->puncture_rate = FEC_5_6; 522 break; 523 case 0x1a: 524 state->puncture_rate = FEC_7_8; 525 break; 526 } 527 state->is_vcm = 0; 528 state->is_standard_broadcast = 1; 529 state->feroll_off = FE_SAT_35; 530 } 531 return 0; 532 } 533 534 static int tracking_optimization(struct stv *state) 535 { 536 u32 symbol_rate = 0; 537 u8 tmp; 538 539 get_cur_symbol_rate(state, &symbol_rate); 540 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); 541 tmp &= ~0xC0; 542 543 switch (state->receive_mode) { 544 case RCVMODE_DVBS: 545 tmp |= 0x40; 546 break; 547 case RCVMODE_DVBS2: 548 tmp |= 0x80; 549 break; 550 default: 551 tmp |= 0xC0; 552 break; 553 } 554 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); 555 556 if (state->receive_mode == RCVMODE_DVBS2) { 557 /* Disable Reed-Solomon */ 558 write_shared_reg(state, 559 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 560 0x03); 561 562 if (state->fectype == DVBS2_64K) { 563 u8 aclc = get_optim_cloop(state, state->mod_cod, 564 state->pilots); 565 566 if (state->mod_cod <= FE_QPSK_910) { 567 write_reg(state, RSTV0910_P2_ACLC2S2Q + 568 state->regoff, aclc); 569 } else if (state->mod_cod <= FE_8PSK_910) { 570 write_reg(state, RSTV0910_P2_ACLC2S2Q + 571 state->regoff, 0x2a); 572 write_reg(state, RSTV0910_P2_ACLC2S28 + 573 state->regoff, aclc); 574 } else if (state->mod_cod <= FE_16APSK_910) { 575 write_reg(state, RSTV0910_P2_ACLC2S2Q + 576 state->regoff, 0x2a); 577 write_reg(state, RSTV0910_P2_ACLC2S216A + 578 state->regoff, aclc); 579 } else if (state->mod_cod <= FE_32APSK_910) { 580 write_reg(state, RSTV0910_P2_ACLC2S2Q + 581 state->regoff, 0x2a); 582 write_reg(state, RSTV0910_P2_ACLC2S232A + 583 state->regoff, aclc); 584 } 585 } 586 } 587 return 0; 588 } 589 590 static s32 table_lookup(const struct slookup *table, 591 int table_size, u32 reg_value) 592 { 593 s32 value; 594 int imin = 0; 595 int imax = table_size - 1; 596 int i; 597 s32 reg_diff; 598 599 /* Assumes Table[0].RegValue > Table[imax].RegValue */ 600 if (reg_value >= table[0].reg_value) { 601 value = table[0].value; 602 } else if (reg_value <= table[imax].reg_value) { 603 value = table[imax].value; 604 } else { 605 while ((imax - imin) > 1) { 606 i = (imax + imin) / 2; 607 if ((table[imin].reg_value >= reg_value) && 608 (reg_value >= table[i].reg_value)) 609 imax = i; 610 else 611 imin = i; 612 } 613 614 reg_diff = table[imax].reg_value - table[imin].reg_value; 615 value = table[imin].value; 616 if (reg_diff != 0) 617 value += ((s32)(reg_value - table[imin].reg_value) * 618 (s32)(table[imax].value 619 - table[imin].value)) 620 / (reg_diff); 621 } 622 623 return value; 624 } 625 626 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise) 627 { 628 u8 data0; 629 u8 data1; 630 u16 data; 631 int n_lookup; 632 const struct slookup *lookup; 633 634 *signal_to_noise = 0; 635 636 if (!state->started) 637 return -EINVAL; 638 639 if (state->receive_mode == RCVMODE_DVBS2) { 640 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, 641 &data1); 642 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, 643 &data0); 644 n_lookup = ARRAY_SIZE(s2_sn_lookup); 645 lookup = s2_sn_lookup; 646 } else { 647 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, 648 &data1); 649 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, 650 &data0); 651 n_lookup = ARRAY_SIZE(s1_sn_lookup); 652 lookup = s1_sn_lookup; 653 } 654 data = (((u16)data1) << 8) | (u16)data0; 655 *signal_to_noise = table_lookup(lookup, n_lookup, data); 656 return 0; 657 } 658 659 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator, 660 u32 *berdenominator) 661 { 662 u8 regs[3]; 663 664 int status = read_regs(state, 665 RSTV0910_P2_ERRCNT12 + state->regoff, 666 regs, 3); 667 668 if (status) 669 return -EINVAL; 670 671 if ((regs[0] & 0x80) == 0) { 672 state->last_berdenominator = 1 << ((state->berscale * 2) + 673 10 + 3); 674 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) | 675 ((u32)regs[1] << 8) | regs[2]; 676 if (state->last_bernumerator < 256 && state->berscale < 6) { 677 state->berscale += 1; 678 status = write_reg(state, RSTV0910_P2_ERRCTRL1 + 679 state->regoff, 680 0x20 | state->berscale); 681 } else if (state->last_bernumerator > 1024 && 682 state->berscale > 2) { 683 state->berscale -= 1; 684 status = write_reg(state, RSTV0910_P2_ERRCTRL1 + 685 state->regoff, 0x20 | 686 state->berscale); 687 } 688 } 689 *bernumerator = state->last_bernumerator; 690 *berdenominator = state->last_berdenominator; 691 return 0; 692 } 693 694 static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype) 695 { 696 static const u32 nbch[][2] = { 697 { 0, 0}, /* DUMMY_PLF */ 698 {16200, 3240}, /* QPSK_1_4, */ 699 {21600, 5400}, /* QPSK_1_3, */ 700 {25920, 6480}, /* QPSK_2_5, */ 701 {32400, 7200}, /* QPSK_1_2, */ 702 {38880, 9720}, /* QPSK_3_5, */ 703 {43200, 10800}, /* QPSK_2_3, */ 704 {48600, 11880}, /* QPSK_3_4, */ 705 {51840, 12600}, /* QPSK_4_5, */ 706 {54000, 13320}, /* QPSK_5_6, */ 707 {57600, 14400}, /* QPSK_8_9, */ 708 {58320, 16000}, /* QPSK_9_10, */ 709 {43200, 9720}, /* 8PSK_3_5, */ 710 {48600, 10800}, /* 8PSK_2_3, */ 711 {51840, 11880}, /* 8PSK_3_4, */ 712 {54000, 13320}, /* 8PSK_5_6, */ 713 {57600, 14400}, /* 8PSK_8_9, */ 714 {58320, 16000}, /* 8PSK_9_10, */ 715 {43200, 10800}, /* 16APSK_2_3, */ 716 {48600, 11880}, /* 16APSK_3_4, */ 717 {51840, 12600}, /* 16APSK_4_5, */ 718 {54000, 13320}, /* 16APSK_5_6, */ 719 {57600, 14400}, /* 16APSK_8_9, */ 720 {58320, 16000}, /* 16APSK_9_10 */ 721 {48600, 11880}, /* 32APSK_3_4, */ 722 {51840, 12600}, /* 32APSK_4_5, */ 723 {54000, 13320}, /* 32APSK_5_6, */ 724 {57600, 14400}, /* 32APSK_8_9, */ 725 {58320, 16000}, /* 32APSK_9_10 */ 726 }; 727 728 if (mod_cod >= DVBS2_QPSK_1_4 && 729 mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K) 730 return nbch[mod_cod][fectype]; 731 return 64800; 732 } 733 734 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator, 735 u32 *berdenominator) 736 { 737 u8 regs[3]; 738 739 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, 740 regs, 3); 741 742 if (status) 743 return -EINVAL; 744 745 if ((regs[0] & 0x80) == 0) { 746 state->last_berdenominator = 747 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod, 748 state->fectype) << 749 (state->berscale * 2); 750 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) | 751 ((u32)regs[1] << 8) | regs[2]; 752 if (state->last_bernumerator < 256 && state->berscale < 6) { 753 state->berscale += 1; 754 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, 755 0x20 | state->berscale); 756 } else if (state->last_bernumerator > 1024 && 757 state->berscale > 2) { 758 state->berscale -= 1; 759 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, 760 0x20 | state->berscale); 761 } 762 } 763 *bernumerator = state->last_bernumerator; 764 *berdenominator = state->last_berdenominator; 765 return status; 766 } 767 768 static int get_bit_error_rate(struct stv *state, u32 *bernumerator, 769 u32 *berdenominator) 770 { 771 *bernumerator = 0; 772 *berdenominator = 1; 773 774 switch (state->receive_mode) { 775 case RCVMODE_DVBS: 776 return get_bit_error_rate_s(state, 777 bernumerator, berdenominator); 778 case RCVMODE_DVBS2: 779 return get_bit_error_rate_s2(state, 780 bernumerator, berdenominator); 781 default: 782 break; 783 } 784 return 0; 785 } 786 787 static int set_mclock(struct stv *state, u32 master_clock) 788 { 789 u32 idf = 1; 790 u32 odf = 4; 791 u32 quartz = state->base->extclk / 1000000; 792 u32 fphi = master_clock / 1000000; 793 u32 ndiv = (fphi * odf * idf) / quartz; 794 u32 cp = 7; 795 u32 fvco; 796 797 if (ndiv >= 7 && ndiv <= 71) 798 cp = 7; 799 else if (ndiv >= 72 && ndiv <= 79) 800 cp = 8; 801 else if (ndiv >= 80 && ndiv <= 87) 802 cp = 9; 803 else if (ndiv >= 88 && ndiv <= 95) 804 cp = 10; 805 else if (ndiv >= 96 && ndiv <= 103) 806 cp = 11; 807 else if (ndiv >= 104 && ndiv <= 111) 808 cp = 12; 809 else if (ndiv >= 112 && ndiv <= 119) 810 cp = 13; 811 else if (ndiv >= 120 && ndiv <= 127) 812 cp = 14; 813 else if (ndiv >= 128 && ndiv <= 135) 814 cp = 15; 815 else if (ndiv >= 136 && ndiv <= 143) 816 cp = 16; 817 else if (ndiv >= 144 && ndiv <= 151) 818 cp = 17; 819 else if (ndiv >= 152 && ndiv <= 159) 820 cp = 18; 821 else if (ndiv >= 160 && ndiv <= 167) 822 cp = 19; 823 else if (ndiv >= 168 && ndiv <= 175) 824 cp = 20; 825 else if (ndiv >= 176 && ndiv <= 183) 826 cp = 21; 827 else if (ndiv >= 184 && ndiv <= 191) 828 cp = 22; 829 else if (ndiv >= 192 && ndiv <= 199) 830 cp = 23; 831 else if (ndiv >= 200 && ndiv <= 207) 832 cp = 24; 833 else if (ndiv >= 208 && ndiv <= 215) 834 cp = 25; 835 else if (ndiv >= 216 && ndiv <= 223) 836 cp = 26; 837 else if (ndiv >= 224 && ndiv <= 225) 838 cp = 27; 839 840 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf); 841 write_reg(state, RSTV0910_NCOARSE2, odf); 842 write_reg(state, RSTV0910_NCOARSE1, ndiv); 843 844 fvco = (quartz * 2 * ndiv) / idf; 845 state->base->mclk = fvco / (2 * odf) * 1000000; 846 847 return 0; 848 } 849 850 static int stop(struct stv *state) 851 { 852 if (state->started) { 853 u8 tmp; 854 855 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, 856 state->tscfgh | 0x01); 857 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); 858 tmp &= ~0x01; /* release reset DVBS2 packet delin */ 859 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); 860 /* Blind optim*/ 861 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); 862 /* Stop the demod */ 863 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); 864 state->started = 0; 865 } 866 state->receive_mode = RCVMODE_NONE; 867 return 0; 868 } 869 870 static int init_search_param(struct stv *state) 871 { 872 u8 tmp; 873 874 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); 875 tmp |= 0x20; /* Filter_en (no effect if SIS=non-MIS */ 876 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); 877 878 read_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, &tmp); 879 tmp &= ~0x02; /* frame mode = 0 */ 880 write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, tmp); 881 882 write_reg(state, RSTV0910_P2_UPLCCST0 + state->regoff, 0xe0); 883 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0x00); 884 885 read_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, &tmp); 886 tmp &= ~0x01; /* nosync = 0, in case next signal is standard TS */ 887 write_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, tmp); 888 889 read_reg(state, RSTV0910_P2_TSCFGL + state->regoff, &tmp); 890 tmp &= ~0x04; /* embindvb = 0 */ 891 write_reg(state, RSTV0910_P2_TSCFGL + state->regoff, tmp); 892 893 read_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, &tmp); 894 tmp &= ~0x80; /* syncbyte = 0 */ 895 write_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, tmp); 896 897 read_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, &tmp); 898 tmp &= ~0x08; /* token = 0 */ 899 write_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, tmp); 900 901 read_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, &tmp); 902 tmp &= ~0x30; /* hysteresis threshold = 0 */ 903 write_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, tmp); 904 905 read_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, &tmp); 906 tmp = (tmp & ~0x30) | 0x10; /* isi obs mode = 1, observe min ISI */ 907 write_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, tmp); 908 909 return 0; 910 } 911 912 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate) 913 { 914 switch (rate) { 915 case FEC_1_2: 916 return write_reg(state, 917 RSTV0910_P2_PRVIT + state->regoff, 0x01); 918 case FEC_2_3: 919 return write_reg(state, 920 RSTV0910_P2_PRVIT + state->regoff, 0x02); 921 case FEC_3_4: 922 return write_reg(state, 923 RSTV0910_P2_PRVIT + state->regoff, 0x04); 924 case FEC_5_6: 925 return write_reg(state, 926 RSTV0910_P2_PRVIT + state->regoff, 0x08); 927 case FEC_7_8: 928 return write_reg(state, 929 RSTV0910_P2_PRVIT + state->regoff, 0x20); 930 case FEC_NONE: 931 default: 932 return write_reg(state, 933 RSTV0910_P2_PRVIT + state->regoff, 0x2f); 934 } 935 } 936 937 static int set_vth_default(struct stv *state) 938 { 939 state->vth[0] = 0xd7; 940 state->vth[1] = 0x85; 941 state->vth[2] = 0x58; 942 state->vth[3] = 0x3a; 943 state->vth[4] = 0x34; 944 state->vth[5] = 0x28; 945 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); 946 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); 947 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); 948 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); 949 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); 950 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); 951 return 0; 952 } 953 954 static int set_vth(struct stv *state) 955 { 956 static const struct slookup vthlookup_table[] = { 957 {250, 8780}, /* C/N= 1.5dB */ 958 {100, 7405}, /* C/N= 4.5dB */ 959 {40, 6330}, /* C/N= 6.5dB */ 960 {12, 5224}, /* C/N= 8.5dB */ 961 {5, 4236} /* C/N=10.5dB */ 962 }; 963 964 int i; 965 u8 tmp[2]; 966 int status = read_regs(state, 967 RSTV0910_P2_NNOSDATAT1 + state->regoff, 968 tmp, 2); 969 u16 reg_value = (tmp[0] << 8) | tmp[1]; 970 s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table), 971 reg_value); 972 973 for (i = 0; i < 6; i += 1) 974 if (state->vth[i] > vth) 975 state->vth[i] = vth; 976 977 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); 978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); 979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); 980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); 981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); 982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); 983 return status; 984 } 985 986 static int start(struct stv *state, struct dtv_frontend_properties *p) 987 { 988 s32 freq; 989 u8 reg_dmdcfgmd; 990 u16 symb; 991 u32 scrambling_code = 1; 992 993 if (p->symbol_rate < 100000 || p->symbol_rate > 70000000) 994 return -EINVAL; 995 996 state->receive_mode = RCVMODE_NONE; 997 state->demod_lock_time = 0; 998 999 /* Demod Stop */ 1000 if (state->started) 1001 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); 1002 1003 init_search_param(state); 1004 1005 if (p->stream_id != NO_STREAM_ID_FILTER) { 1006 /* 1007 * Backwards compatibility to "crazy" API. 1008 * PRBS X root cannot be 0, so this should always work. 1009 */ 1010 if (p->stream_id & 0xffffff00) 1011 scrambling_code = p->stream_id >> 8; 1012 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, 1013 p->stream_id & 0xff); 1014 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 1015 0xff); 1016 } 1017 1018 if (scrambling_code != state->cur_scrambling_code) { 1019 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, 1020 scrambling_code & 0xff); 1021 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, 1022 (scrambling_code >> 8) & 0xff); 1023 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, 1024 (scrambling_code >> 16) & 0x0f); 1025 state->cur_scrambling_code = scrambling_code; 1026 } 1027 1028 if (p->symbol_rate <= 1000000) { /* SR <=1Msps */ 1029 state->demod_timeout = 3000; 1030 state->fec_timeout = 2000; 1031 } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */ 1032 state->demod_timeout = 2500; 1033 state->fec_timeout = 1300; 1034 } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */ 1035 state->demod_timeout = 1000; 1036 state->fec_timeout = 650; 1037 } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */ 1038 state->demod_timeout = 700; 1039 state->fec_timeout = 350; 1040 } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */ 1041 state->demod_timeout = 400; 1042 state->fec_timeout = 200; 1043 } else { /* SR >=20Msps */ 1044 state->demod_timeout = 300; 1045 state->fec_timeout = 200; 1046 } 1047 1048 /* Set the Init Symbol rate */ 1049 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk); 1050 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, 1051 ((symb >> 8) & 0x7F)); 1052 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); 1053 1054 state->demod_bits |= 0x80; 1055 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits); 1056 1057 /* FE_STV0910_SetSearchStandard */ 1058 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd); 1059 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, 1060 reg_dmdcfgmd |= 0xC0); 1061 1062 write_shared_reg(state, 1063 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00); 1064 1065 /* Disable DSS */ 1066 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); 1067 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); 1068 1069 enable_puncture_rate(state, FEC_NONE); 1070 1071 /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */ 1072 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); 1073 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); 1074 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); 1075 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); 1076 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); 1077 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); 1078 1079 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); 1080 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); 1081 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); 1082 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); 1083 1084 /* 1085 * Reset CAR3, bug DVBS2->DVBS1 lock 1086 * Note: The bit is only pulsed -> no lock on shared register needed 1087 */ 1088 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08); 1089 write_reg(state, RSTV0910_TSTRES0, 0); 1090 1091 set_vth_default(state); 1092 /* Reset demod */ 1093 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); 1094 1095 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); 1096 1097 if (p->symbol_rate <= 5000000) 1098 freq = (state->search_range / 2000) + 80; 1099 else 1100 freq = (state->search_range / 2000) + 1600; 1101 freq = (freq << 16) / (state->base->mclk / 1000); 1102 1103 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, 1104 (freq >> 8) & 0xff); 1105 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); 1106 /* CFR Low Setting */ 1107 freq = -freq; 1108 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, 1109 (freq >> 8) & 0xff); 1110 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); 1111 1112 /* init the demod frequency offset to 0 */ 1113 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); 1114 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); 1115 1116 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); 1117 /* Trigger acq */ 1118 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); 1119 1120 state->demod_lock_time += TUNING_DELAY; 1121 state->started = 1; 1122 1123 return 0; 1124 } 1125 1126 static int init_diseqc(struct stv *state) 1127 { 1128 u16 offs = state->nr ? 0x40 : 0; /* Address offset */ 1129 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32)); 1130 1131 /* Disable receiver */ 1132 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00); 1133 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */ 1134 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */ 1135 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq); 1136 return 0; 1137 } 1138 1139 static int probe(struct stv *state) 1140 { 1141 u8 id; 1142 1143 state->receive_mode = RCVMODE_NONE; 1144 state->started = 0; 1145 1146 if (read_reg(state, RSTV0910_MID, &id) < 0) 1147 return -ENODEV; 1148 1149 if (id != 0x51) 1150 return -EINVAL; 1151 1152 /* Configure the I2C repeater to off */ 1153 write_reg(state, RSTV0910_P1_I2CRPT, 0x24); 1154 /* Configure the I2C repeater to off */ 1155 write_reg(state, RSTV0910_P2_I2CRPT, 0x24); 1156 /* Set the I2C to oversampling ratio */ 1157 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */ 1158 1159 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ 1160 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */ 1161 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ 1162 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */ 1163 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ 1164 1165 if (state->single) 1166 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */ 1167 else 1168 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ 1169 1170 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */ 1171 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */ 1172 1173 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02); 1174 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02); 1175 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04); 1176 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04); 1177 1178 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */ 1179 write_reg(state, RSTV0910_TSTRES0, 0x00); 1180 1181 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00); 1182 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00); 1183 1184 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80); 1185 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80); 1186 1187 set_mclock(state, 135000000); 1188 1189 /* TS output */ 1190 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); 1191 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); 1192 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */ 1193 write_reg(state, RSTV0910_P1_TSCFGL, 0x20); 1194 1195 /* Speed = 67.5 MHz */ 1196 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed); 1197 1198 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); 1199 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); 1200 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */ 1201 write_reg(state, RSTV0910_P2_TSCFGL, 0x20); 1202 1203 /* Speed = 67.5 MHz */ 1204 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed); 1205 1206 /* Reset stream merger */ 1207 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); 1208 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); 1209 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); 1210 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); 1211 1212 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt); 1213 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt); 1214 1215 init_diseqc(state); 1216 return 0; 1217 } 1218 1219 static int gate_ctrl(struct dvb_frontend *fe, int enable) 1220 { 1221 struct stv *state = fe->demodulator_priv; 1222 u8 i2crpt = state->i2crpt & ~0x86; 1223 1224 /* 1225 * mutex_lock note: Concurrent I2C gate bus accesses must be 1226 * prevented (STV0910 = dual demod on a single IC with a single I2C 1227 * gate/bus, and two tuners attached), similar to most (if not all) 1228 * other I2C host interfaces/busses. 1229 * 1230 * enable=1 (open I2C gate) will grab the lock 1231 * enable=0 (close I2C gate) releases the lock 1232 */ 1233 1234 if (enable) { 1235 mutex_lock(&state->base->i2c_lock); 1236 i2crpt |= 0x80; 1237 } else { 1238 i2crpt |= 0x02; 1239 } 1240 1241 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT : 1242 RSTV0910_P1_I2CRPT, i2crpt) < 0) { 1243 /* don't hold the I2C bus lock on failure */ 1244 mutex_unlock(&state->base->i2c_lock); 1245 dev_err(&state->base->i2c->dev, 1246 "%s() write_reg failure (enable=%d)\n", 1247 __func__, enable); 1248 return -EIO; 1249 } 1250 1251 state->i2crpt = i2crpt; 1252 1253 if (!enable) 1254 mutex_unlock(&state->base->i2c_lock); 1255 return 0; 1256 } 1257 1258 static void release(struct dvb_frontend *fe) 1259 { 1260 struct stv *state = fe->demodulator_priv; 1261 1262 state->base->count--; 1263 if (state->base->count == 0) { 1264 list_del(&state->base->stvlist); 1265 kfree(state->base); 1266 } 1267 kfree(state); 1268 } 1269 1270 static int set_parameters(struct dvb_frontend *fe) 1271 { 1272 int stat = 0; 1273 struct stv *state = fe->demodulator_priv; 1274 u32 iffreq; 1275 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1276 1277 stop(state); 1278 if (fe->ops.tuner_ops.set_params) 1279 fe->ops.tuner_ops.set_params(fe); 1280 if (fe->ops.tuner_ops.get_if_frequency) 1281 fe->ops.tuner_ops.get_if_frequency(fe, &iffreq); 1282 state->symbol_rate = p->symbol_rate; 1283 stat = start(state, p); 1284 return stat; 1285 } 1286 1287 static int manage_matype_info(struct stv *state) 1288 { 1289 if (!state->started) 1290 return -EINVAL; 1291 if (state->receive_mode == RCVMODE_DVBS2) { 1292 u8 bbheader[2]; 1293 1294 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, 1295 bbheader, 2); 1296 state->feroll_off = 1297 (enum fe_stv0910_roll_off)(bbheader[0] & 0x03); 1298 state->is_vcm = (bbheader[0] & 0x10) == 0; 1299 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0; 1300 } else if (state->receive_mode == RCVMODE_DVBS) { 1301 state->is_vcm = 0; 1302 state->is_standard_broadcast = 1; 1303 state->feroll_off = FE_SAT_35; 1304 } 1305 return 0; 1306 } 1307 1308 static int read_snr(struct dvb_frontend *fe) 1309 { 1310 struct stv *state = fe->demodulator_priv; 1311 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1312 s32 snrval; 1313 1314 if (!get_signal_to_noise(state, &snrval)) { 1315 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; 1316 p->cnr.stat[0].uvalue = 100 * snrval; /* fix scale */ 1317 } else { 1318 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int read_ber(struct dvb_frontend *fe) 1325 { 1326 struct stv *state = fe->demodulator_priv; 1327 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1328 u32 n, d; 1329 1330 get_bit_error_rate(state, &n, &d); 1331 1332 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1333 p->pre_bit_error.stat[0].uvalue = n; 1334 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1335 p->pre_bit_count.stat[0].uvalue = d; 1336 1337 return 0; 1338 } 1339 1340 static void read_signal_strength(struct dvb_frontend *fe) 1341 { 1342 struct stv *state = fe->demodulator_priv; 1343 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache; 1344 u8 reg[2]; 1345 u16 agc; 1346 s32 padc, power = 0; 1347 int i; 1348 1349 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2); 1350 1351 agc = (((u32)reg[0]) << 8) | reg[1]; 1352 1353 for (i = 0; i < 5; i += 1) { 1354 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2); 1355 power += (u32)reg[0] * (u32)reg[0] 1356 + (u32)reg[1] * (u32)reg[1]; 1357 usleep_range(3000, 4000); 1358 } 1359 power /= 5; 1360 1361 padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352; 1362 1363 p->strength.stat[0].scale = FE_SCALE_DECIBEL; 1364 p->strength.stat[0].svalue = (padc - agc); 1365 } 1366 1367 static int read_status(struct dvb_frontend *fe, enum fe_status *status) 1368 { 1369 struct stv *state = fe->demodulator_priv; 1370 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1371 u8 dmd_state = 0; 1372 u8 dstatus = 0; 1373 enum receive_mode cur_receive_mode = RCVMODE_NONE; 1374 u32 feclock = 0; 1375 1376 *status = 0; 1377 1378 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state); 1379 1380 if (dmd_state & 0x40) { 1381 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus); 1382 if (dstatus & 0x08) 1383 cur_receive_mode = (dmd_state & 0x20) ? 1384 RCVMODE_DVBS : RCVMODE_DVBS2; 1385 } 1386 if (cur_receive_mode == RCVMODE_NONE) { 1387 set_vth(state); 1388 1389 /* reset signal statistics */ 1390 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1391 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1392 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1393 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1394 1395 return 0; 1396 } 1397 1398 *status |= (FE_HAS_SIGNAL 1399 | FE_HAS_CARRIER 1400 | FE_HAS_VITERBI 1401 | FE_HAS_SYNC); 1402 1403 if (state->receive_mode == RCVMODE_NONE) { 1404 state->receive_mode = cur_receive_mode; 1405 state->demod_lock_time = jiffies; 1406 state->first_time_lock = 1; 1407 1408 get_signal_parameters(state); 1409 tracking_optimization(state); 1410 1411 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, 1412 state->tscfgh); 1413 usleep_range(3000, 4000); 1414 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, 1415 state->tscfgh | 0x01); 1416 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, 1417 state->tscfgh); 1418 } 1419 if (dmd_state & 0x40) { 1420 if (state->receive_mode == RCVMODE_DVBS2) { 1421 u8 pdelstatus; 1422 1423 read_reg(state, 1424 RSTV0910_P2_PDELSTATUS1 + state->regoff, 1425 &pdelstatus); 1426 feclock = (pdelstatus & 0x02) != 0; 1427 } else { 1428 u8 vstatus; 1429 1430 read_reg(state, 1431 RSTV0910_P2_VSTATUSVIT + state->regoff, 1432 &vstatus); 1433 feclock = (vstatus & 0x08) != 0; 1434 } 1435 } 1436 1437 if (feclock) { 1438 *status |= FE_HAS_LOCK; 1439 1440 if (state->first_time_lock) { 1441 u8 tmp; 1442 1443 state->first_time_lock = 0; 1444 1445 manage_matype_info(state); 1446 1447 if (state->receive_mode == RCVMODE_DVBS2) { 1448 /* 1449 * FSTV0910_P2_MANUALSX_ROLLOFF, 1450 * FSTV0910_P2_MANUALS2_ROLLOFF = 0 1451 */ 1452 state->demod_bits &= ~0x84; 1453 write_reg(state, 1454 RSTV0910_P2_DEMOD + state->regoff, 1455 state->demod_bits); 1456 read_reg(state, 1457 RSTV0910_P2_PDELCTRL2 + state->regoff, 1458 &tmp); 1459 /* reset DVBS2 packet delinator error counter */ 1460 tmp |= 0x40; 1461 write_reg(state, 1462 RSTV0910_P2_PDELCTRL2 + state->regoff, 1463 tmp); 1464 /* reset DVBS2 packet delinator error counter */ 1465 tmp &= ~0x40; 1466 write_reg(state, 1467 RSTV0910_P2_PDELCTRL2 + state->regoff, 1468 tmp); 1469 1470 state->berscale = 2; 1471 state->last_bernumerator = 0; 1472 state->last_berdenominator = 1; 1473 /* force to PRE BCH Rate */ 1474 write_reg(state, 1475 RSTV0910_P2_ERRCTRL1 + state->regoff, 1476 BER_SRC_S2 | state->berscale); 1477 } else { 1478 state->berscale = 2; 1479 state->last_bernumerator = 0; 1480 state->last_berdenominator = 1; 1481 /* force to PRE RS Rate */ 1482 write_reg(state, 1483 RSTV0910_P2_ERRCTRL1 + state->regoff, 1484 BER_SRC_S | state->berscale); 1485 } 1486 /* Reset the Total packet counter */ 1487 write_reg(state, 1488 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); 1489 /* 1490 * Reset the packet Error counter2 (and Set it to 1491 * infinit error count mode) 1492 */ 1493 write_reg(state, 1494 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); 1495 1496 set_vth_default(state); 1497 if (state->receive_mode == RCVMODE_DVBS) 1498 enable_puncture_rate(state, 1499 state->puncture_rate); 1500 } 1501 } 1502 1503 /* read signal statistics */ 1504 1505 /* read signal strength */ 1506 read_signal_strength(fe); 1507 1508 /* read carrier/noise on FE_HAS_CARRIER */ 1509 if (*status & FE_HAS_CARRIER) 1510 read_snr(fe); 1511 else 1512 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1513 1514 /* read ber */ 1515 if (*status & FE_HAS_VITERBI) { 1516 read_ber(fe); 1517 } else { 1518 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1519 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1520 } 1521 1522 return 0; 1523 } 1524 1525 static int get_frontend(struct dvb_frontend *fe, 1526 struct dtv_frontend_properties *p) 1527 { 1528 struct stv *state = fe->demodulator_priv; 1529 u8 tmp; 1530 1531 if (state->receive_mode == RCVMODE_DVBS2) { 1532 u32 mc; 1533 const enum fe_modulation modcod2mod[0x20] = { 1534 QPSK, QPSK, QPSK, QPSK, 1535 QPSK, QPSK, QPSK, QPSK, 1536 QPSK, QPSK, QPSK, QPSK, 1537 PSK_8, PSK_8, PSK_8, PSK_8, 1538 PSK_8, PSK_8, APSK_16, APSK_16, 1539 APSK_16, APSK_16, APSK_16, APSK_16, 1540 APSK_32, APSK_32, APSK_32, APSK_32, 1541 APSK_32, 1542 }; 1543 const enum fe_code_rate modcod2fec[0x20] = { 1544 FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5, 1545 FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4, 1546 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, 1547 FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6, 1548 FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4, 1549 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, 1550 FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9, 1551 FEC_9_10 1552 }; 1553 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); 1554 mc = ((tmp & 0x7c) >> 2); 1555 p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF; 1556 p->modulation = modcod2mod[mc]; 1557 p->fec_inner = modcod2fec[mc]; 1558 } else if (state->receive_mode == RCVMODE_DVBS) { 1559 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); 1560 switch (tmp & 0x1F) { 1561 case 0x0d: 1562 p->fec_inner = FEC_1_2; 1563 break; 1564 case 0x12: 1565 p->fec_inner = FEC_2_3; 1566 break; 1567 case 0x15: 1568 p->fec_inner = FEC_3_4; 1569 break; 1570 case 0x18: 1571 p->fec_inner = FEC_5_6; 1572 break; 1573 case 0x1a: 1574 p->fec_inner = FEC_7_8; 1575 break; 1576 default: 1577 p->fec_inner = FEC_NONE; 1578 break; 1579 } 1580 p->rolloff = ROLLOFF_35; 1581 } 1582 1583 return 0; 1584 } 1585 1586 static int tune(struct dvb_frontend *fe, bool re_tune, 1587 unsigned int mode_flags, 1588 unsigned int *delay, enum fe_status *status) 1589 { 1590 struct stv *state = fe->demodulator_priv; 1591 int r; 1592 1593 if (re_tune) { 1594 r = set_parameters(fe); 1595 if (r) 1596 return r; 1597 state->tune_time = jiffies; 1598 } 1599 1600 r = read_status(fe, status); 1601 if (r) 1602 return r; 1603 1604 if (*status & FE_HAS_LOCK) 1605 return 0; 1606 *delay = HZ; 1607 1608 return 0; 1609 } 1610 1611 static int get_algo(struct dvb_frontend *fe) 1612 { 1613 return DVBFE_ALGO_HW; 1614 } 1615 1616 static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 1617 { 1618 struct stv *state = fe->demodulator_priv; 1619 u16 offs = state->nr ? 0x40 : 0; 1620 1621 switch (tone) { 1622 case SEC_TONE_ON: 1623 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38); 1624 case SEC_TONE_OFF: 1625 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a); 1626 default: 1627 break; 1628 } 1629 return -EINVAL; 1630 } 1631 1632 static int wait_dis(struct stv *state, u8 flag, u8 val) 1633 { 1634 int i; 1635 u8 stat; 1636 u16 offs = state->nr ? 0x40 : 0; 1637 1638 for (i = 0; i < 10; i++) { 1639 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat); 1640 if ((stat & flag) == val) 1641 return 0; 1642 usleep_range(10000, 11000); 1643 } 1644 return -ETIMEDOUT; 1645 } 1646 1647 static int send_master_cmd(struct dvb_frontend *fe, 1648 struct dvb_diseqc_master_cmd *cmd) 1649 { 1650 struct stv *state = fe->demodulator_priv; 1651 u16 offs = state->nr ? 0x40 : 0; 1652 int i; 1653 1654 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E); 1655 for (i = 0; i < cmd->msg_len; i++) { 1656 wait_dis(state, 0x40, 0x00); 1657 write_reg(state, RSTV0910_P1_DISTXFIFO + offs, cmd->msg[i]); 1658 } 1659 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); 1660 wait_dis(state, 0x20, 0x20); 1661 return 0; 1662 } 1663 1664 static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst) 1665 { 1666 struct stv *state = fe->demodulator_priv; 1667 u16 offs = state->nr ? 0x40 : 0; 1668 u8 value; 1669 1670 if (burst == SEC_MINI_A) { 1671 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3F); 1672 value = 0x00; 1673 } else { 1674 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E); 1675 value = 0xFF; 1676 } 1677 wait_dis(state, 0x40, 0x00); 1678 write_reg(state, RSTV0910_P1_DISTXFIFO + offs, value); 1679 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); 1680 wait_dis(state, 0x20, 0x20); 1681 1682 return 0; 1683 } 1684 1685 static int sleep(struct dvb_frontend *fe) 1686 { 1687 struct stv *state = fe->demodulator_priv; 1688 1689 stop(state); 1690 return 0; 1691 } 1692 1693 static const struct dvb_frontend_ops stv0910_ops = { 1694 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, 1695 .info = { 1696 .name = "ST STV0910", 1697 .frequency_min = 950000, 1698 .frequency_max = 2150000, 1699 .frequency_stepsize = 0, 1700 .frequency_tolerance = 0, 1701 .symbol_rate_min = 100000, 1702 .symbol_rate_max = 70000000, 1703 .caps = FE_CAN_INVERSION_AUTO | 1704 FE_CAN_FEC_AUTO | 1705 FE_CAN_QPSK | 1706 FE_CAN_2G_MODULATION | 1707 FE_CAN_MULTISTREAM 1708 }, 1709 .sleep = sleep, 1710 .release = release, 1711 .i2c_gate_ctrl = gate_ctrl, 1712 .set_frontend = set_parameters, 1713 .get_frontend_algo = get_algo, 1714 .get_frontend = get_frontend, 1715 .tune = tune, 1716 .read_status = read_status, 1717 .set_tone = set_tone, 1718 1719 .diseqc_send_master_cmd = send_master_cmd, 1720 .diseqc_send_burst = send_burst, 1721 }; 1722 1723 static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr) 1724 { 1725 struct stv_base *p; 1726 1727 list_for_each_entry(p, &stvlist, stvlist) 1728 if (p->i2c == i2c && p->adr == adr) 1729 return p; 1730 return NULL; 1731 } 1732 1733 static void stv0910_init_stats(struct stv *state) 1734 { 1735 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache; 1736 1737 p->strength.len = 1; 1738 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1739 p->cnr.len = 1; 1740 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1741 p->pre_bit_error.len = 1; 1742 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1743 p->pre_bit_count.len = 1; 1744 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1745 } 1746 1747 struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, 1748 struct stv0910_cfg *cfg, 1749 int nr) 1750 { 1751 struct stv *state; 1752 struct stv_base *base; 1753 1754 state = kzalloc(sizeof(*state), GFP_KERNEL); 1755 if (!state) 1756 return NULL; 1757 1758 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40); 1759 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00; 1760 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4); 1761 state->tsspeed = 0x28; 1762 state->nr = nr; 1763 state->regoff = state->nr ? 0 : 0x200; 1764 state->search_range = 16000000; 1765 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */ 1766 state->receive_mode = RCVMODE_NONE; 1767 state->cur_scrambling_code = (~0U); 1768 state->single = cfg->single ? 1 : 0; 1769 1770 base = match_base(i2c, cfg->adr); 1771 if (base) { 1772 base->count++; 1773 state->base = base; 1774 } else { 1775 base = kzalloc(sizeof(*base), GFP_KERNEL); 1776 if (!base) 1777 goto fail; 1778 base->i2c = i2c; 1779 base->adr = cfg->adr; 1780 base->count = 1; 1781 base->extclk = cfg->clk ? cfg->clk : 30000000; 1782 1783 mutex_init(&base->i2c_lock); 1784 mutex_init(&base->reg_lock); 1785 state->base = base; 1786 if (probe(state) < 0) { 1787 dev_info(&i2c->dev, "No demod found at adr %02X on %s\n", 1788 cfg->adr, dev_name(&i2c->dev)); 1789 kfree(base); 1790 goto fail; 1791 } 1792 list_add(&base->stvlist, &stvlist); 1793 } 1794 state->fe.ops = stv0910_ops; 1795 state->fe.demodulator_priv = state; 1796 state->nr = nr; 1797 1798 dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n", 1799 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev)); 1800 1801 stv0910_init_stats(state); 1802 1803 return &state->fe; 1804 1805 fail: 1806 kfree(state); 1807 return NULL; 1808 } 1809 EXPORT_SYMBOL_GPL(stv0910_attach); 1810 1811 MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver"); 1812 MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel"); 1813 MODULE_LICENSE("GPL"); 1814