1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for the ST STV0910 DVB-S/S2 demodulator.
4  *
5  * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
6  *                         Marcus Metzler <mocm@metzlerbros.de>
7  *                         developed for Digital Devices GmbH
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * version 2 only, as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/firmware.h>
25 #include <linux/i2c.h>
26 #include <asm/div64.h>
27 
28 #include <media/dvb_frontend.h>
29 #include "stv0910.h"
30 #include "stv0910_regs.h"
31 
32 #define EXT_CLOCK    30000000
33 #define TUNING_DELAY 200
34 #define BER_SRC_S    0x20
35 #define BER_SRC_S2   0x20
36 
37 static LIST_HEAD(stvlist);
38 
39 enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
40 
41 enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
42 
43 enum dvbs2_mod_cod {
44 	DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
45 	DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3,	DVBS2_QPSK_3_4,
46 	DVBS2_QPSK_4_5,	DVBS2_QPSK_5_6,	DVBS2_QPSK_8_9,	DVBS2_QPSK_9_10,
47 	DVBS2_8PSK_3_5,	DVBS2_8PSK_2_3,	DVBS2_8PSK_3_4,	DVBS2_8PSK_5_6,
48 	DVBS2_8PSK_8_9,	DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
49 	DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
50 	DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
51 	DVBS2_32APSK_9_10
52 };
53 
54 enum fe_stv0910_mod_cod {
55 	FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
56 	FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
57 	FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
58 	FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
59 	FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
60 	FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
61 	FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
62 	FE_32APSK_910
63 };
64 
65 enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
66 
67 static inline u32 muldiv32(u32 a, u32 b, u32 c)
68 {
69 	u64 tmp64;
70 
71 	tmp64 = (u64)a * (u64)b;
72 	do_div(tmp64, c);
73 
74 	return (u32)tmp64;
75 }
76 
77 struct stv_base {
78 	struct list_head     stvlist;
79 
80 	u8                   adr;
81 	struct i2c_adapter  *i2c;
82 	struct mutex         i2c_lock; /* shared I2C access protect */
83 	struct mutex         reg_lock; /* shared register write protect */
84 	int                  count;
85 
86 	u32                  extclk;
87 	u32                  mclk;
88 };
89 
90 struct stv {
91 	struct stv_base     *base;
92 	struct dvb_frontend  fe;
93 	int                  nr;
94 	u16                  regoff;
95 	u8                   i2crpt;
96 	u8                   tscfgh;
97 	u8                   tsgeneral;
98 	u8                   tsspeed;
99 	u8                   single;
100 	unsigned long        tune_time;
101 
102 	s32                  search_range;
103 	u32                  started;
104 	u32                  demod_lock_time;
105 	enum receive_mode    receive_mode;
106 	u32                  demod_timeout;
107 	u32                  fec_timeout;
108 	u32                  first_time_lock;
109 	u8                   demod_bits;
110 	u32                  symbol_rate;
111 
112 	u8                       last_viterbi_rate;
113 	enum fe_code_rate        puncture_rate;
114 	enum fe_stv0910_mod_cod  mod_cod;
115 	enum dvbs2_fectype       fectype;
116 	u32                      pilots;
117 	enum fe_stv0910_roll_off feroll_off;
118 
119 	int   is_standard_broadcast;
120 	int   is_vcm;
121 
122 	u32   cur_scrambling_code;
123 
124 	u32   last_bernumerator;
125 	u32   last_berdenominator;
126 	u8    berscale;
127 
128 	u8    vth[6];
129 };
130 
131 struct sinit_table {
132 	u16  address;
133 	u8   data;
134 };
135 
136 struct slookup {
137 	s16  value;
138 	u32  reg_value;
139 };
140 
141 static int write_reg(struct stv *state, u16 reg, u8 val)
142 {
143 	struct i2c_adapter *adap = state->base->i2c;
144 	u8 data[3] = {reg >> 8, reg & 0xff, val};
145 	struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
146 			      .buf = data, .len = 3};
147 
148 	if (i2c_transfer(adap, &msg, 1) != 1) {
149 		dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
150 			 state->base->adr, reg, val);
151 		return -EIO;
152 	}
153 	return 0;
154 }
155 
156 static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
157 				  u16 reg, u8 *val, int count)
158 {
159 	u8 msg[2] = {reg >> 8, reg & 0xff};
160 	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
161 				   .buf  = msg, .len   = 2},
162 				  {.addr = adr, .flags = I2C_M_RD,
163 				   .buf  = val, .len   = count } };
164 
165 	if (i2c_transfer(adapter, msgs, 2) != 2) {
166 		dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
167 			 adr, reg);
168 		return -EIO;
169 	}
170 	return 0;
171 }
172 
173 static int read_reg(struct stv *state, u16 reg, u8 *val)
174 {
175 	return i2c_read_regs16(state->base->i2c, state->base->adr,
176 			       reg, val, 1);
177 }
178 
179 static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
180 {
181 	return i2c_read_regs16(state->base->i2c, state->base->adr,
182 			       reg, val, len);
183 }
184 
185 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
186 {
187 	int status;
188 	u8 tmp;
189 
190 	mutex_lock(&state->base->reg_lock);
191 	status = read_reg(state, reg, &tmp);
192 	if (!status)
193 		status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
194 	mutex_unlock(&state->base->reg_lock);
195 	return status;
196 }
197 
198 static int write_field(struct stv *state, u32 field, u8 val)
199 {
200 	int status;
201 	u8 shift, mask, old, new;
202 
203 	status = read_reg(state, field >> 16, &old);
204 	if (status)
205 		return status;
206 	mask = field & 0xff;
207 	shift = (field >> 12) & 0xf;
208 	new = ((val << shift) & mask) | (old & ~mask);
209 	if (new == old)
210 		return 0;
211 	return write_reg(state, field >> 16, new);
212 }
213 
214 #define SET_FIELD(_reg, _val)					\
215 	write_field(state, state->nr ? FSTV0910_P2_##_reg :	\
216 		    FSTV0910_P1_##_reg, _val)
217 
218 #define SET_REG(_reg, _val)					\
219 	write_reg(state, state->nr ? RSTV0910_P2_##_reg :	\
220 		  RSTV0910_P1_##_reg, _val)
221 
222 #define GET_REG(_reg, _val)					\
223 	read_reg(state, state->nr ? RSTV0910_P2_##_reg :	\
224 		 RSTV0910_P1_##_reg, _val)
225 
226 static const struct slookup s1_sn_lookup[] = {
227 	{   0,    9242  }, /* C/N=   0dB */
228 	{   5,    9105  }, /* C/N= 0.5dB */
229 	{  10,    8950  }, /* C/N= 1.0dB */
230 	{  15,    8780  }, /* C/N= 1.5dB */
231 	{  20,    8566  }, /* C/N= 2.0dB */
232 	{  25,    8366  }, /* C/N= 2.5dB */
233 	{  30,    8146  }, /* C/N= 3.0dB */
234 	{  35,    7908  }, /* C/N= 3.5dB */
235 	{  40,    7666  }, /* C/N= 4.0dB */
236 	{  45,    7405  }, /* C/N= 4.5dB */
237 	{  50,    7136  }, /* C/N= 5.0dB */
238 	{  55,    6861  }, /* C/N= 5.5dB */
239 	{  60,    6576  }, /* C/N= 6.0dB */
240 	{  65,    6330  }, /* C/N= 6.5dB */
241 	{  70,    6048  }, /* C/N= 7.0dB */
242 	{  75,    5768  }, /* C/N= 7.5dB */
243 	{  80,    5492  }, /* C/N= 8.0dB */
244 	{  85,    5224  }, /* C/N= 8.5dB */
245 	{  90,    4959  }, /* C/N= 9.0dB */
246 	{  95,    4709  }, /* C/N= 9.5dB */
247 	{  100,   4467  }, /* C/N=10.0dB */
248 	{  105,   4236  }, /* C/N=10.5dB */
249 	{  110,   4013  }, /* C/N=11.0dB */
250 	{  115,   3800  }, /* C/N=11.5dB */
251 	{  120,   3598  }, /* C/N=12.0dB */
252 	{  125,   3406  }, /* C/N=12.5dB */
253 	{  130,   3225  }, /* C/N=13.0dB */
254 	{  135,   3052  }, /* C/N=13.5dB */
255 	{  140,   2889  }, /* C/N=14.0dB */
256 	{  145,   2733  }, /* C/N=14.5dB */
257 	{  150,   2587  }, /* C/N=15.0dB */
258 	{  160,   2318  }, /* C/N=16.0dB */
259 	{  170,   2077  }, /* C/N=17.0dB */
260 	{  180,   1862  }, /* C/N=18.0dB */
261 	{  190,   1670  }, /* C/N=19.0dB */
262 	{  200,   1499  }, /* C/N=20.0dB */
263 	{  210,   1347  }, /* C/N=21.0dB */
264 	{  220,   1213  }, /* C/N=22.0dB */
265 	{  230,   1095  }, /* C/N=23.0dB */
266 	{  240,    992  }, /* C/N=24.0dB */
267 	{  250,    900  }, /* C/N=25.0dB */
268 	{  260,    826  }, /* C/N=26.0dB */
269 	{  270,    758  }, /* C/N=27.0dB */
270 	{  280,    702  }, /* C/N=28.0dB */
271 	{  290,    653  }, /* C/N=29.0dB */
272 	{  300,    613  }, /* C/N=30.0dB */
273 	{  310,    579  }, /* C/N=31.0dB */
274 	{  320,    550  }, /* C/N=32.0dB */
275 	{  330,    526  }, /* C/N=33.0dB */
276 	{  350,    490  }, /* C/N=33.0dB */
277 	{  400,    445  }, /* C/N=40.0dB */
278 	{  450,    430  }, /* C/N=45.0dB */
279 	{  500,    426  }, /* C/N=50.0dB */
280 	{  510,    425  }  /* C/N=51.0dB */
281 };
282 
283 static const struct slookup s2_sn_lookup[] = {
284 	{  -30,  13950  }, /* C/N=-2.5dB */
285 	{  -25,  13580  }, /* C/N=-2.5dB */
286 	{  -20,  13150  }, /* C/N=-2.0dB */
287 	{  -15,  12760  }, /* C/N=-1.5dB */
288 	{  -10,  12345  }, /* C/N=-1.0dB */
289 	{   -5,  11900  }, /* C/N=-0.5dB */
290 	{    0,  11520  }, /* C/N=   0dB */
291 	{    5,  11080  }, /* C/N= 0.5dB */
292 	{   10,  10630  }, /* C/N= 1.0dB */
293 	{   15,  10210  }, /* C/N= 1.5dB */
294 	{   20,   9790  }, /* C/N= 2.0dB */
295 	{   25,   9390  }, /* C/N= 2.5dB */
296 	{   30,   8970  }, /* C/N= 3.0dB */
297 	{   35,   8575  }, /* C/N= 3.5dB */
298 	{   40,   8180  }, /* C/N= 4.0dB */
299 	{   45,   7800  }, /* C/N= 4.5dB */
300 	{   50,   7430  }, /* C/N= 5.0dB */
301 	{   55,   7080  }, /* C/N= 5.5dB */
302 	{   60,   6720  }, /* C/N= 6.0dB */
303 	{   65,   6320  }, /* C/N= 6.5dB */
304 	{   70,   6060  }, /* C/N= 7.0dB */
305 	{   75,   5760  }, /* C/N= 7.5dB */
306 	{   80,   5480  }, /* C/N= 8.0dB */
307 	{   85,   5200  }, /* C/N= 8.5dB */
308 	{   90,   4930  }, /* C/N= 9.0dB */
309 	{   95,   4680  }, /* C/N= 9.5dB */
310 	{  100,   4425  }, /* C/N=10.0dB */
311 	{  105,   4210  }, /* C/N=10.5dB */
312 	{  110,   3980  }, /* C/N=11.0dB */
313 	{  115,   3765  }, /* C/N=11.5dB */
314 	{  120,   3570  }, /* C/N=12.0dB */
315 	{  125,   3315  }, /* C/N=12.5dB */
316 	{  130,   3140  }, /* C/N=13.0dB */
317 	{  135,   2980  }, /* C/N=13.5dB */
318 	{  140,   2820  }, /* C/N=14.0dB */
319 	{  145,   2670  }, /* C/N=14.5dB */
320 	{  150,   2535  }, /* C/N=15.0dB */
321 	{  160,   2270  }, /* C/N=16.0dB */
322 	{  170,   2035  }, /* C/N=17.0dB */
323 	{  180,   1825  }, /* C/N=18.0dB */
324 	{  190,   1650  }, /* C/N=19.0dB */
325 	{  200,   1485  }, /* C/N=20.0dB */
326 	{  210,   1340  }, /* C/N=21.0dB */
327 	{  220,   1212  }, /* C/N=22.0dB */
328 	{  230,   1100  }, /* C/N=23.0dB */
329 	{  240,   1000  }, /* C/N=24.0dB */
330 	{  250,    910  }, /* C/N=25.0dB */
331 	{  260,    836  }, /* C/N=26.0dB */
332 	{  270,    772  }, /* C/N=27.0dB */
333 	{  280,    718  }, /* C/N=28.0dB */
334 	{  290,    671  }, /* C/N=29.0dB */
335 	{  300,    635  }, /* C/N=30.0dB */
336 	{  310,    602  }, /* C/N=31.0dB */
337 	{  320,    575  }, /* C/N=32.0dB */
338 	{  330,    550  }, /* C/N=33.0dB */
339 	{  350,    517  }, /* C/N=35.0dB */
340 	{  400,    480  }, /* C/N=40.0dB */
341 	{  450,    466  }, /* C/N=45.0dB */
342 	{  500,    464  }, /* C/N=50.0dB */
343 	{  510,    463  }, /* C/N=51.0dB */
344 };
345 
346 static const struct slookup padc_lookup[] = {
347 	{    0,  118000 }, /* PADC= +0dBm */
348 	{ -100,  93600  }, /* PADC= -1dBm */
349 	{ -200,  74500  }, /* PADC= -2dBm */
350 	{ -300,  59100  }, /* PADC= -3dBm */
351 	{ -400,  47000  }, /* PADC= -4dBm */
352 	{ -500,  37300  }, /* PADC= -5dBm */
353 	{ -600,  29650  }, /* PADC= -6dBm */
354 	{ -700,  23520  }, /* PADC= -7dBm */
355 	{ -900,  14850  }, /* PADC= -9dBm */
356 	{ -1100, 9380   }, /* PADC=-11dBm */
357 	{ -1300, 5910   }, /* PADC=-13dBm */
358 	{ -1500, 3730   }, /* PADC=-15dBm */
359 	{ -1700, 2354   }, /* PADC=-17dBm */
360 	{ -1900, 1485   }, /* PADC=-19dBm */
361 	{ -2000, 1179   }, /* PADC=-20dBm */
362 	{ -2100, 1000   }, /* PADC=-21dBm */
363 };
364 
365 /*********************************************************************
366  * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
367  *********************************************************************/
368 static const u8 s2car_loop[] =	{
369 	/*
370 	 * Modcod  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
371 	 * 20MPon 20MPoff 30MPon 30MPoff
372 	 */
373 
374 	/* FE_QPSK_14  */
375 	0x0C,  0x3C,  0x0B,  0x3C,  0x2A,  0x2C,  0x2A,  0x1C,  0x3A,  0x3B,
376 	/* FE_QPSK_13  */
377 	0x0C,  0x3C,  0x0B,  0x3C,  0x2A,  0x2C,  0x3A,  0x0C,  0x3A,  0x2B,
378 	/* FE_QPSK_25  */
379 	0x1C,  0x3C,  0x1B,  0x3C,  0x3A,  0x1C,  0x3A,  0x3B,  0x3A,  0x2B,
380 	/* FE_QPSK_12  */
381 	0x0C,  0x1C,  0x2B,  0x1C,  0x0B,  0x2C,  0x0B,  0x0C,  0x2A,  0x2B,
382 	/* FE_QPSK_35  */
383 	0x1C,  0x1C,  0x2B,  0x1C,  0x0B,  0x2C,  0x0B,  0x0C,  0x2A,  0x2B,
384 	/* FE_QPSK_23  */
385 	0x2C,  0x2C,  0x2B,  0x1C,  0x0B,  0x2C,  0x0B,  0x0C,  0x2A,  0x2B,
386 	/* FE_QPSK_34  */
387 	0x3C,  0x2C,  0x3B,  0x2C,  0x1B,  0x1C,  0x1B,  0x3B,  0x3A,  0x1B,
388 	/* FE_QPSK_45  */
389 	0x0D,  0x3C,  0x3B,  0x2C,  0x1B,  0x1C,  0x1B,  0x3B,  0x3A,  0x1B,
390 	/* FE_QPSK_56  */
391 	0x1D,  0x3C,  0x0C,  0x2C,  0x2B,  0x1C,  0x1B,  0x3B,  0x0B,  0x1B,
392 	/* FE_QPSK_89  */
393 	0x3D,  0x0D,  0x0C,  0x2C,  0x2B,  0x0C,  0x2B,  0x2B,  0x0B,  0x0B,
394 	/* FE_QPSK_910 */
395 	0x1E,  0x0D,  0x1C,  0x2C,  0x3B,  0x0C,  0x2B,  0x2B,  0x1B,  0x0B,
396 	/* FE_8PSK_35  */
397 	0x28,  0x09,  0x28,  0x09,  0x28,  0x09,  0x28,  0x08,  0x28,  0x27,
398 	/* FE_8PSK_23  */
399 	0x19,  0x29,  0x19,  0x29,  0x19,  0x29,  0x38,  0x19,  0x28,  0x09,
400 	/* FE_8PSK_34  */
401 	0x1A,  0x0B,  0x1A,  0x3A,  0x0A,  0x2A,  0x39,  0x2A,  0x39,  0x1A,
402 	/* FE_8PSK_56  */
403 	0x2B,  0x2B,  0x1B,  0x1B,  0x0B,  0x1B,  0x1A,  0x0B,  0x1A,  0x1A,
404 	/* FE_8PSK_89  */
405 	0x0C,  0x0C,  0x3B,  0x3B,  0x1B,  0x1B,  0x2A,  0x0B,  0x2A,  0x2A,
406 	/* FE_8PSK_910 */
407 	0x0C,  0x1C,  0x0C,  0x3B,  0x2B,  0x1B,  0x3A,  0x0B,  0x2A,  0x2A,
408 
409 	/**********************************************************************
410 	 * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
411 	 **********************************************************************/
412 
413 	/*
414 	 * Modcod 2MPon  2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
415 	 * 20MPoff 30MPon 30MPoff
416 	 */
417 
418 	/* FE_16APSK_23  */
419 	0x0A,  0x0A,  0x0A,  0x0A,  0x1A,  0x0A,  0x39,  0x0A,  0x29,  0x0A,
420 	/* FE_16APSK_34  */
421 	0x0A,  0x0A,  0x0A,  0x0A,  0x0B,  0x0A,  0x2A,  0x0A,  0x1A,  0x0A,
422 	/* FE_16APSK_45  */
423 	0x0A,  0x0A,  0x0A,  0x0A,  0x1B,  0x0A,  0x3A,  0x0A,  0x2A,  0x0A,
424 	/* FE_16APSK_56  */
425 	0x0A,  0x0A,  0x0A,  0x0A,  0x1B,  0x0A,  0x3A,  0x0A,  0x2A,  0x0A,
426 	/* FE_16APSK_89  */
427 	0x0A,  0x0A,  0x0A,  0x0A,  0x2B,  0x0A,  0x0B,  0x0A,  0x3A,  0x0A,
428 	/* FE_16APSK_910 */
429 	0x0A,  0x0A,  0x0A,  0x0A,  0x2B,  0x0A,  0x0B,  0x0A,  0x3A,  0x0A,
430 	/* FE_32APSK_34  */
431 	0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
432 	/* FE_32APSK_45  */
433 	0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
434 	/* FE_32APSK_56  */
435 	0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
436 	/* FE_32APSK_89  */
437 	0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
438 	/* FE_32APSK_910 */
439 	0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
440 };
441 
442 static u8 get_optim_cloop(struct stv *state,
443 			  enum fe_stv0910_mod_cod mod_cod, u32 pilots)
444 {
445 	int i = 0;
446 
447 	if (mod_cod >= FE_32APSK_910)
448 		i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
449 	else if (mod_cod >= FE_QPSK_14)
450 		i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
451 
452 	if (state->symbol_rate <= 3000000)
453 		i += 0;
454 	else if (state->symbol_rate <=  7000000)
455 		i += 2;
456 	else if (state->symbol_rate <= 15000000)
457 		i += 4;
458 	else if (state->symbol_rate <= 25000000)
459 		i += 6;
460 	else
461 		i += 8;
462 
463 	if (!pilots)
464 		i += 1;
465 
466 	return s2car_loop[i];
467 }
468 
469 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
470 {
471 	int status = 0;
472 	u8 symb_freq0;
473 	u8 symb_freq1;
474 	u8 symb_freq2;
475 	u8 symb_freq3;
476 	u8 tim_offs0;
477 	u8 tim_offs1;
478 	u8 tim_offs2;
479 	u32 symbol_rate;
480 	s32 timing_offset;
481 
482 	*p_symbol_rate = 0;
483 	if (!state->started)
484 		return status;
485 
486 	read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
487 	read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
488 	read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
489 	read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
490 	read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
491 	read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
492 	read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
493 
494 	symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
495 		((u32)symb_freq1 << 8) | (u32)symb_freq0;
496 	timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
497 		(u32)tim_offs0;
498 
499 	if ((timing_offset & (1 << 23)) != 0)
500 		timing_offset |= 0xFF000000; /* Sign extent */
501 
502 	symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
503 	timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
504 
505 	*p_symbol_rate = symbol_rate + timing_offset;
506 
507 	return 0;
508 }
509 
510 static int get_signal_parameters(struct stv *state)
511 {
512 	u8 tmp;
513 
514 	if (!state->started)
515 		return -EINVAL;
516 
517 	if (state->receive_mode == RCVMODE_DVBS2) {
518 		read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
519 		state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
520 		state->pilots = (tmp & 0x01) != 0;
521 		state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
522 
523 	} else if (state->receive_mode == RCVMODE_DVBS) {
524 		read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
525 		state->puncture_rate = FEC_NONE;
526 		switch (tmp & 0x1F) {
527 		case 0x0d:
528 			state->puncture_rate = FEC_1_2;
529 			break;
530 		case 0x12:
531 			state->puncture_rate = FEC_2_3;
532 			break;
533 		case 0x15:
534 			state->puncture_rate = FEC_3_4;
535 			break;
536 		case 0x18:
537 			state->puncture_rate = FEC_5_6;
538 			break;
539 		case 0x1a:
540 			state->puncture_rate = FEC_7_8;
541 			break;
542 		}
543 		state->is_vcm = 0;
544 		state->is_standard_broadcast = 1;
545 		state->feroll_off = FE_SAT_35;
546 	}
547 	return 0;
548 }
549 
550 static int tracking_optimization(struct stv *state)
551 {
552 	u8 tmp;
553 
554 	read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
555 	tmp &= ~0xC0;
556 
557 	switch (state->receive_mode) {
558 	case RCVMODE_DVBS:
559 		tmp |= 0x40;
560 		break;
561 	case RCVMODE_DVBS2:
562 		tmp |= 0x80;
563 		break;
564 	default:
565 		tmp |= 0xC0;
566 		break;
567 	}
568 	write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
569 
570 	if (state->receive_mode == RCVMODE_DVBS2) {
571 		/* Disable Reed-Solomon */
572 		write_shared_reg(state,
573 				 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
574 				 0x03);
575 
576 		if (state->fectype == DVBS2_64K) {
577 			u8 aclc = get_optim_cloop(state, state->mod_cod,
578 						  state->pilots);
579 
580 			if (state->mod_cod <= FE_QPSK_910) {
581 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
582 					  state->regoff, aclc);
583 			} else if (state->mod_cod <= FE_8PSK_910) {
584 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
585 					  state->regoff, 0x2a);
586 				write_reg(state, RSTV0910_P2_ACLC2S28 +
587 					  state->regoff, aclc);
588 			} else if (state->mod_cod <= FE_16APSK_910) {
589 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
590 					  state->regoff, 0x2a);
591 				write_reg(state, RSTV0910_P2_ACLC2S216A +
592 					  state->regoff, aclc);
593 			} else if (state->mod_cod <= FE_32APSK_910) {
594 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
595 					  state->regoff, 0x2a);
596 				write_reg(state, RSTV0910_P2_ACLC2S232A +
597 					  state->regoff, aclc);
598 			}
599 		}
600 	}
601 	return 0;
602 }
603 
604 static s32 table_lookup(const struct slookup *table,
605 			int table_size, u32 reg_value)
606 {
607 	s32 value;
608 	int imin = 0;
609 	int imax = table_size - 1;
610 	int i;
611 	s32 reg_diff;
612 
613 	/* Assumes Table[0].RegValue > Table[imax].RegValue */
614 	if (reg_value >= table[0].reg_value) {
615 		value = table[0].value;
616 	} else if (reg_value <= table[imax].reg_value) {
617 		value = table[imax].value;
618 	} else {
619 		while ((imax - imin) > 1) {
620 			i = (imax + imin) / 2;
621 			if ((table[imin].reg_value >= reg_value) &&
622 			    (reg_value >= table[i].reg_value))
623 				imax = i;
624 			else
625 				imin = i;
626 		}
627 
628 		reg_diff = table[imax].reg_value - table[imin].reg_value;
629 		value = table[imin].value;
630 		if (reg_diff != 0)
631 			value += ((s32)(reg_value - table[imin].reg_value) *
632 				  (s32)(table[imax].value
633 					- table[imin].value))
634 					/ (reg_diff);
635 	}
636 
637 	return value;
638 }
639 
640 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
641 {
642 	u8 data0;
643 	u8 data1;
644 	u16 data;
645 	int n_lookup;
646 	const struct slookup *lookup;
647 
648 	*signal_to_noise = 0;
649 
650 	if (!state->started)
651 		return -EINVAL;
652 
653 	if (state->receive_mode == RCVMODE_DVBS2) {
654 		read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
655 			 &data1);
656 		read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
657 			 &data0);
658 		n_lookup = ARRAY_SIZE(s2_sn_lookup);
659 		lookup = s2_sn_lookup;
660 	} else {
661 		read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
662 			 &data1);
663 		read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
664 			 &data0);
665 		n_lookup = ARRAY_SIZE(s1_sn_lookup);
666 		lookup = s1_sn_lookup;
667 	}
668 	data = (((u16)data1) << 8) | (u16)data0;
669 	*signal_to_noise = table_lookup(lookup, n_lookup, data);
670 	return 0;
671 }
672 
673 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
674 				u32 *berdenominator)
675 {
676 	u8 regs[3];
677 
678 	int status = read_regs(state,
679 			       RSTV0910_P2_ERRCNT12 + state->regoff,
680 			       regs, 3);
681 
682 	if (status)
683 		return -EINVAL;
684 
685 	if ((regs[0] & 0x80) == 0) {
686 		state->last_berdenominator = 1ULL << ((state->berscale * 2) +
687 						     10 + 3);
688 		state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
689 			((u32)regs[1] << 8) | regs[2];
690 		if (state->last_bernumerator < 256 && state->berscale < 6) {
691 			state->berscale += 1;
692 			status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
693 					   state->regoff,
694 					   0x20 | state->berscale);
695 		} else if (state->last_bernumerator > 1024 &&
696 			   state->berscale > 2) {
697 			state->berscale -= 1;
698 			status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
699 					   state->regoff, 0x20 |
700 					   state->berscale);
701 		}
702 	}
703 	*bernumerator = state->last_bernumerator;
704 	*berdenominator = state->last_berdenominator;
705 	return 0;
706 }
707 
708 static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
709 {
710 	static const u32 nbch[][2] = {
711 		{    0,     0}, /* DUMMY_PLF   */
712 		{16200,  3240}, /* QPSK_1_4,   */
713 		{21600,  5400}, /* QPSK_1_3,   */
714 		{25920,  6480}, /* QPSK_2_5,   */
715 		{32400,  7200}, /* QPSK_1_2,   */
716 		{38880,  9720}, /* QPSK_3_5,   */
717 		{43200, 10800}, /* QPSK_2_3,   */
718 		{48600, 11880}, /* QPSK_3_4,   */
719 		{51840, 12600}, /* QPSK_4_5,   */
720 		{54000, 13320}, /* QPSK_5_6,   */
721 		{57600, 14400}, /* QPSK_8_9,   */
722 		{58320, 16000}, /* QPSK_9_10,  */
723 		{43200,  9720}, /* 8PSK_3_5,   */
724 		{48600, 10800}, /* 8PSK_2_3,   */
725 		{51840, 11880}, /* 8PSK_3_4,   */
726 		{54000, 13320}, /* 8PSK_5_6,   */
727 		{57600, 14400}, /* 8PSK_8_9,   */
728 		{58320, 16000}, /* 8PSK_9_10,  */
729 		{43200, 10800}, /* 16APSK_2_3, */
730 		{48600, 11880}, /* 16APSK_3_4, */
731 		{51840, 12600}, /* 16APSK_4_5, */
732 		{54000, 13320}, /* 16APSK_5_6, */
733 		{57600, 14400}, /* 16APSK_8_9, */
734 		{58320, 16000}, /* 16APSK_9_10 */
735 		{48600, 11880}, /* 32APSK_3_4, */
736 		{51840, 12600}, /* 32APSK_4_5, */
737 		{54000, 13320}, /* 32APSK_5_6, */
738 		{57600, 14400}, /* 32APSK_8_9, */
739 		{58320, 16000}, /* 32APSK_9_10 */
740 	};
741 
742 	if (mod_cod >= DVBS2_QPSK_1_4 &&
743 	    mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
744 		return nbch[mod_cod][fectype];
745 	return 64800;
746 }
747 
748 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
749 				 u32 *berdenominator)
750 {
751 	u8 regs[3];
752 
753 	int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
754 			       regs, 3);
755 
756 	if (status)
757 		return -EINVAL;
758 
759 	if ((regs[0] & 0x80) == 0) {
760 		state->last_berdenominator =
761 			dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
762 				   state->fectype) <<
763 			(state->berscale * 2);
764 		state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
765 			((u32)regs[1] << 8) | regs[2];
766 		if (state->last_bernumerator < 256 && state->berscale < 6) {
767 			state->berscale += 1;
768 			write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
769 				  0x20 | state->berscale);
770 		} else if (state->last_bernumerator > 1024 &&
771 			   state->berscale > 2) {
772 			state->berscale -= 1;
773 			write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
774 				  0x20 | state->berscale);
775 		}
776 	}
777 	*bernumerator = state->last_bernumerator;
778 	*berdenominator = state->last_berdenominator;
779 	return status;
780 }
781 
782 static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
783 			      u32 *berdenominator)
784 {
785 	*bernumerator = 0;
786 	*berdenominator = 1;
787 
788 	switch (state->receive_mode) {
789 	case RCVMODE_DVBS:
790 		return get_bit_error_rate_s(state,
791 					    bernumerator, berdenominator);
792 	case RCVMODE_DVBS2:
793 		return get_bit_error_rate_s2(state,
794 					     bernumerator, berdenominator);
795 	default:
796 		break;
797 	}
798 	return 0;
799 }
800 
801 static int set_mclock(struct stv *state, u32 master_clock)
802 {
803 	u32 idf = 1;
804 	u32 odf = 4;
805 	u32 quartz = state->base->extclk / 1000000;
806 	u32 fphi = master_clock / 1000000;
807 	u32 ndiv = (fphi * odf * idf) / quartz;
808 	u32 cp = 7;
809 	u32 fvco;
810 
811 	if (ndiv >= 7 && ndiv <= 71)
812 		cp = 7;
813 	else if (ndiv >=  72 && ndiv <=  79)
814 		cp = 8;
815 	else if (ndiv >=  80 && ndiv <=  87)
816 		cp = 9;
817 	else if (ndiv >=  88 && ndiv <=  95)
818 		cp = 10;
819 	else if (ndiv >=  96 && ndiv <= 103)
820 		cp = 11;
821 	else if (ndiv >= 104 && ndiv <= 111)
822 		cp = 12;
823 	else if (ndiv >= 112 && ndiv <= 119)
824 		cp = 13;
825 	else if (ndiv >= 120 && ndiv <= 127)
826 		cp = 14;
827 	else if (ndiv >= 128 && ndiv <= 135)
828 		cp = 15;
829 	else if (ndiv >= 136 && ndiv <= 143)
830 		cp = 16;
831 	else if (ndiv >= 144 && ndiv <= 151)
832 		cp = 17;
833 	else if (ndiv >= 152 && ndiv <= 159)
834 		cp = 18;
835 	else if (ndiv >= 160 && ndiv <= 167)
836 		cp = 19;
837 	else if (ndiv >= 168 && ndiv <= 175)
838 		cp = 20;
839 	else if (ndiv >= 176 && ndiv <= 183)
840 		cp = 21;
841 	else if (ndiv >= 184 && ndiv <= 191)
842 		cp = 22;
843 	else if (ndiv >= 192 && ndiv <= 199)
844 		cp = 23;
845 	else if (ndiv >= 200 && ndiv <= 207)
846 		cp = 24;
847 	else if (ndiv >= 208 && ndiv <= 215)
848 		cp = 25;
849 	else if (ndiv >= 216 && ndiv <= 223)
850 		cp = 26;
851 	else if (ndiv >= 224 && ndiv <= 225)
852 		cp = 27;
853 
854 	write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
855 	write_reg(state, RSTV0910_NCOARSE2, odf);
856 	write_reg(state, RSTV0910_NCOARSE1, ndiv);
857 
858 	fvco = (quartz * 2 * ndiv) / idf;
859 	state->base->mclk = fvco / (2 * odf) * 1000000;
860 
861 	return 0;
862 }
863 
864 static int stop(struct stv *state)
865 {
866 	if (state->started) {
867 		u8 tmp;
868 
869 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
870 			  state->tscfgh | 0x01);
871 		read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
872 		tmp &= ~0x01; /* release reset DVBS2 packet delin */
873 		write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
874 		/* Blind optim*/
875 		write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
876 		/* Stop the demod */
877 		write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
878 		state->started = 0;
879 	}
880 	state->receive_mode = RCVMODE_NONE;
881 	return 0;
882 }
883 
884 static void set_pls(struct stv *state, u32 pls_code)
885 {
886 	if (pls_code == state->cur_scrambling_code)
887 		return;
888 
889 	/* PLROOT2 bit 2 = gold code */
890 	write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
891 		  pls_code & 0xff);
892 	write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
893 		  (pls_code >> 8) & 0xff);
894 	write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
895 		  0x04 | ((pls_code >> 16) & 0x03));
896 	state->cur_scrambling_code = pls_code;
897 }
898 
899 static void set_isi(struct stv *state, u32 isi)
900 {
901 	if (isi == NO_STREAM_ID_FILTER)
902 		return;
903 	if (isi == 0x80000000) {
904 		SET_FIELD(FORCE_CONTINUOUS, 1);
905 		SET_FIELD(TSOUT_NOSYNC, 1);
906 	} else {
907 		SET_FIELD(FILTER_EN, 1);
908 		write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
909 			  isi & 0xff);
910 		write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
911 	}
912 	SET_FIELD(ALGOSWRST, 1);
913 	SET_FIELD(ALGOSWRST, 0);
914 }
915 
916 static void set_stream_modes(struct stv *state,
917 			     struct dtv_frontend_properties *p)
918 {
919 	set_isi(state, p->stream_id);
920 	set_pls(state, p->scrambling_sequence_index);
921 }
922 
923 static int init_search_param(struct stv *state,
924 			     struct dtv_frontend_properties *p)
925 {
926 	SET_FIELD(FORCE_CONTINUOUS, 0);
927 	SET_FIELD(FRAME_MODE, 0);
928 	SET_FIELD(FILTER_EN, 0);
929 	SET_FIELD(TSOUT_NOSYNC, 0);
930 	SET_FIELD(TSFIFO_EMBINDVB, 0);
931 	SET_FIELD(TSDEL_SYNCBYTE, 0);
932 	SET_REG(UPLCCST0, 0xe0);
933 	SET_FIELD(TSINS_TOKEN, 0);
934 	SET_FIELD(HYSTERESIS_THRESHOLD, 0);
935 	SET_FIELD(ISIOBS_MODE, 1);
936 
937 	set_stream_modes(state, p);
938 	return 0;
939 }
940 
941 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
942 {
943 	u8 val;
944 
945 	switch (rate) {
946 	case FEC_1_2:
947 		val = 0x01;
948 		break;
949 	case FEC_2_3:
950 		val = 0x02;
951 		break;
952 	case FEC_3_4:
953 		val = 0x04;
954 		break;
955 	case FEC_5_6:
956 		val = 0x08;
957 		break;
958 	case FEC_7_8:
959 		val = 0x20;
960 		break;
961 	case FEC_NONE:
962 	default:
963 		val = 0x2f;
964 		break;
965 	}
966 
967 	return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
968 }
969 
970 static int set_vth_default(struct stv *state)
971 {
972 	state->vth[0] = 0xd7;
973 	state->vth[1] = 0x85;
974 	state->vth[2] = 0x58;
975 	state->vth[3] = 0x3a;
976 	state->vth[4] = 0x34;
977 	state->vth[5] = 0x28;
978 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
979 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
980 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
981 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
982 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
983 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
984 	return 0;
985 }
986 
987 static int set_vth(struct stv *state)
988 {
989 	static const struct slookup vthlookup_table[] = {
990 		{250,	8780}, /* C/N= 1.5dB */
991 		{100,	7405}, /* C/N= 4.5dB */
992 		{40,	6330}, /* C/N= 6.5dB */
993 		{12,	5224}, /* C/N= 8.5dB */
994 		{5,	4236}  /* C/N=10.5dB */
995 	};
996 
997 	int i;
998 	u8 tmp[2];
999 	int status = read_regs(state,
1000 			       RSTV0910_P2_NNOSDATAT1 + state->regoff,
1001 			       tmp, 2);
1002 	u16 reg_value = (tmp[0] << 8) | tmp[1];
1003 	s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
1004 			      reg_value);
1005 
1006 	for (i = 0; i < 6; i += 1)
1007 		if (state->vth[i] > vth)
1008 			state->vth[i] = vth;
1009 
1010 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1011 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1012 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1013 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1014 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1015 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1016 	return status;
1017 }
1018 
1019 static int start(struct stv *state, struct dtv_frontend_properties *p)
1020 {
1021 	s32 freq;
1022 	u8  reg_dmdcfgmd;
1023 	u16 symb;
1024 
1025 	if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
1026 		return -EINVAL;
1027 
1028 	state->receive_mode = RCVMODE_NONE;
1029 	state->demod_lock_time = 0;
1030 
1031 	/* Demod Stop */
1032 	if (state->started)
1033 		write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1034 
1035 	init_search_param(state, p);
1036 
1037 	if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
1038 		state->demod_timeout = 3000;
1039 		state->fec_timeout = 2000;
1040 	} else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
1041 		state->demod_timeout = 2500;
1042 		state->fec_timeout = 1300;
1043 	} else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
1044 		state->demod_timeout = 1000;
1045 		state->fec_timeout = 650;
1046 	} else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
1047 		state->demod_timeout = 700;
1048 		state->fec_timeout = 350;
1049 	} else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
1050 		state->demod_timeout = 400;
1051 		state->fec_timeout = 200;
1052 	} else { /* SR >=20Msps */
1053 		state->demod_timeout = 300;
1054 		state->fec_timeout = 200;
1055 	}
1056 
1057 	/* Set the Init Symbol rate */
1058 	symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1059 	write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1060 		  ((symb >> 8) & 0x7F));
1061 	write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1062 
1063 	state->demod_bits |= 0x80;
1064 	write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1065 
1066 	/* FE_STV0910_SetSearchStandard */
1067 	read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &reg_dmdcfgmd);
1068 	write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1069 		  reg_dmdcfgmd |= 0xC0);
1070 
1071 	write_shared_reg(state,
1072 			 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1073 
1074 	/* Disable DSS */
1075 	write_reg(state, RSTV0910_P2_FECM  + state->regoff, 0x00);
1076 	write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1077 
1078 	enable_puncture_rate(state, FEC_NONE);
1079 
1080 	/* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
1081 	write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1082 	write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1083 	write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1084 	write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1085 	write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1086 	write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1087 
1088 	write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1089 	write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1090 	write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1091 	write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1092 
1093 	/*
1094 	 * Reset CAR3, bug DVBS2->DVBS1 lock
1095 	 * Note: The bit is only pulsed -> no lock on shared register needed
1096 	 */
1097 	write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1098 	write_reg(state, RSTV0910_TSTRES0, 0);
1099 
1100 	set_vth_default(state);
1101 	/* Reset demod */
1102 	write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1103 
1104 	write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1105 
1106 	if (p->symbol_rate <= 5000000)
1107 		freq = (state->search_range / 2000) + 80;
1108 	else
1109 		freq = (state->search_range / 2000) + 1600;
1110 	freq = (freq << 16) / (state->base->mclk / 1000);
1111 
1112 	write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1113 		  (freq >> 8) & 0xff);
1114 	write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1115 	/* CFR Low Setting */
1116 	freq = -freq;
1117 	write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1118 		  (freq >> 8) & 0xff);
1119 	write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1120 
1121 	/* init the demod frequency offset to 0 */
1122 	write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1123 	write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1124 
1125 	write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1126 	/* Trigger acq */
1127 	write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1128 
1129 	state->demod_lock_time += TUNING_DELAY;
1130 	state->started = 1;
1131 
1132 	return 0;
1133 }
1134 
1135 static int init_diseqc(struct stv *state)
1136 {
1137 	u16 offs = state->nr ? 0x40 : 0; /* Address offset */
1138 	u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1139 
1140 	/* Disable receiver */
1141 	write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1142 	write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1143 	write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1144 	write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1145 	return 0;
1146 }
1147 
1148 static int probe(struct stv *state)
1149 {
1150 	u8 id;
1151 
1152 	state->receive_mode = RCVMODE_NONE;
1153 	state->started = 0;
1154 
1155 	if (read_reg(state, RSTV0910_MID, &id) < 0)
1156 		return -ENODEV;
1157 
1158 	if (id != 0x51)
1159 		return -EINVAL;
1160 
1161 	/* Configure the I2C repeater to off */
1162 	write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1163 	/* Configure the I2C repeater to off */
1164 	write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1165 	/* Set the I2C to oversampling ratio */
1166 	write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1167 
1168 	write_reg(state, RSTV0910_OUTCFG,    0x00); /* OUTCFG */
1169 	write_reg(state, RSTV0910_PADCFG,    0x05); /* RFAGC Pads Dev = 05 */
1170 	write_reg(state, RSTV0910_SYNTCTRL,  0x02); /* SYNTCTRL */
1171 	write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1172 	write_reg(state, RSTV0910_CFGEXT,    0x02); /* CFGEXT */
1173 
1174 	if (state->single)
1175 		write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1176 	else
1177 		write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1178 
1179 	write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1180 	write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1181 
1182 	write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1183 	write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1184 	write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1185 	write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1186 
1187 	write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1188 	write_reg(state, RSTV0910_TSTRES0, 0x00);
1189 
1190 	write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1191 	write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1192 
1193 	write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1194 	write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1195 
1196 	set_mclock(state, 135000000);
1197 
1198 	/* TS output */
1199 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1200 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1201 	write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1202 	write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1203 
1204 	write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1205 
1206 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1207 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1208 	write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1209 	write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1210 
1211 	write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1212 
1213 	/* Reset stream merger */
1214 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1215 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1216 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1217 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1218 
1219 	write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1220 	write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1221 
1222 	write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
1223 	write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
1224 
1225 	write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
1226 	write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
1227 
1228 	init_diseqc(state);
1229 	return 0;
1230 }
1231 
1232 static int gate_ctrl(struct dvb_frontend *fe, int enable)
1233 {
1234 	struct stv *state = fe->demodulator_priv;
1235 	u8 i2crpt = state->i2crpt & ~0x86;
1236 
1237 	/*
1238 	 * mutex_lock note: Concurrent I2C gate bus accesses must be
1239 	 * prevented (STV0910 = dual demod on a single IC with a single I2C
1240 	 * gate/bus, and two tuners attached), similar to most (if not all)
1241 	 * other I2C host interfaces/buses.
1242 	 *
1243 	 * enable=1 (open I2C gate) will grab the lock
1244 	 * enable=0 (close I2C gate) releases the lock
1245 	 */
1246 
1247 	if (enable) {
1248 		mutex_lock(&state->base->i2c_lock);
1249 		i2crpt |= 0x80;
1250 	} else {
1251 		i2crpt |= 0x02;
1252 	}
1253 
1254 	if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
1255 		      RSTV0910_P1_I2CRPT, i2crpt) < 0) {
1256 		/* don't hold the I2C bus lock on failure */
1257 		if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1258 			mutex_unlock(&state->base->i2c_lock);
1259 		dev_err(&state->base->i2c->dev,
1260 			"%s() write_reg failure (enable=%d)\n",
1261 			__func__, enable);
1262 		return -EIO;
1263 	}
1264 
1265 	state->i2crpt = i2crpt;
1266 
1267 	if (!enable)
1268 		if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1269 			mutex_unlock(&state->base->i2c_lock);
1270 	return 0;
1271 }
1272 
1273 static void release(struct dvb_frontend *fe)
1274 {
1275 	struct stv *state = fe->demodulator_priv;
1276 
1277 	state->base->count--;
1278 	if (state->base->count == 0) {
1279 		list_del(&state->base->stvlist);
1280 		kfree(state->base);
1281 	}
1282 	kfree(state);
1283 }
1284 
1285 static int set_parameters(struct dvb_frontend *fe)
1286 {
1287 	int stat = 0;
1288 	struct stv *state = fe->demodulator_priv;
1289 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1290 
1291 	stop(state);
1292 	if (fe->ops.tuner_ops.set_params)
1293 		fe->ops.tuner_ops.set_params(fe);
1294 	state->symbol_rate = p->symbol_rate;
1295 	stat = start(state, p);
1296 	return stat;
1297 }
1298 
1299 static int manage_matype_info(struct stv *state)
1300 {
1301 	if (!state->started)
1302 		return -EINVAL;
1303 	if (state->receive_mode == RCVMODE_DVBS2) {
1304 		u8 bbheader[2];
1305 
1306 		read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
1307 			  bbheader, 2);
1308 		state->feroll_off =
1309 			(enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
1310 		state->is_vcm = (bbheader[0] & 0x10) == 0;
1311 		state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1312 	} else if (state->receive_mode == RCVMODE_DVBS) {
1313 		state->is_vcm = 0;
1314 		state->is_standard_broadcast = 1;
1315 		state->feroll_off = FE_SAT_35;
1316 	}
1317 	return 0;
1318 }
1319 
1320 static int read_snr(struct dvb_frontend *fe)
1321 {
1322 	struct stv *state = fe->demodulator_priv;
1323 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1324 	s32 snrval;
1325 
1326 	if (!get_signal_to_noise(state, &snrval)) {
1327 		p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1328 		p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */
1329 	} else {
1330 		p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1331 	}
1332 
1333 	return 0;
1334 }
1335 
1336 static int read_ber(struct dvb_frontend *fe)
1337 {
1338 	struct stv *state = fe->demodulator_priv;
1339 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1340 	u32 n, d;
1341 
1342 	get_bit_error_rate(state, &n, &d);
1343 
1344 	p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1345 	p->pre_bit_error.stat[0].uvalue = n;
1346 	p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1347 	p->pre_bit_count.stat[0].uvalue = d;
1348 
1349 	return 0;
1350 }
1351 
1352 static void read_signal_strength(struct dvb_frontend *fe)
1353 {
1354 	struct stv *state = fe->demodulator_priv;
1355 	struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1356 	u8 reg[2];
1357 	u16 agc;
1358 	s32 padc, power = 0;
1359 	int i;
1360 
1361 	read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
1362 
1363 	agc = (((u32)reg[0]) << 8) | reg[1];
1364 
1365 	for (i = 0; i < 5; i += 1) {
1366 		read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
1367 		power += (u32)reg[0] * (u32)reg[0]
1368 			+ (u32)reg[1] * (u32)reg[1];
1369 		usleep_range(3000, 4000);
1370 	}
1371 	power /= 5;
1372 
1373 	padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
1374 
1375 	p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1376 	p->strength.stat[0].svalue = (padc - agc);
1377 }
1378 
1379 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
1380 {
1381 	struct stv *state = fe->demodulator_priv;
1382 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1383 	u8 dmd_state = 0;
1384 	u8 dstatus  = 0;
1385 	enum receive_mode cur_receive_mode = RCVMODE_NONE;
1386 	u32 feclock = 0;
1387 
1388 	*status = 0;
1389 
1390 	read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1391 
1392 	if (dmd_state & 0x40) {
1393 		read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1394 		if (dstatus & 0x08)
1395 			cur_receive_mode = (dmd_state & 0x20) ?
1396 				RCVMODE_DVBS : RCVMODE_DVBS2;
1397 	}
1398 	if (cur_receive_mode == RCVMODE_NONE) {
1399 		set_vth(state);
1400 
1401 		/* reset signal statistics */
1402 		p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1403 		p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1404 		p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1405 		p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1406 
1407 		return 0;
1408 	}
1409 
1410 	*status |= (FE_HAS_SIGNAL
1411 		| FE_HAS_CARRIER
1412 		| FE_HAS_VITERBI
1413 		| FE_HAS_SYNC);
1414 
1415 	if (state->receive_mode == RCVMODE_NONE) {
1416 		state->receive_mode = cur_receive_mode;
1417 		state->demod_lock_time = jiffies;
1418 		state->first_time_lock = 1;
1419 
1420 		get_signal_parameters(state);
1421 		tracking_optimization(state);
1422 
1423 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1424 			  state->tscfgh);
1425 		usleep_range(3000, 4000);
1426 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1427 			  state->tscfgh | 0x01);
1428 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1429 			  state->tscfgh);
1430 	}
1431 	if (dmd_state & 0x40) {
1432 		if (state->receive_mode == RCVMODE_DVBS2) {
1433 			u8 pdelstatus;
1434 
1435 			read_reg(state,
1436 				 RSTV0910_P2_PDELSTATUS1 + state->regoff,
1437 				 &pdelstatus);
1438 			feclock = (pdelstatus & 0x02) != 0;
1439 		} else {
1440 			u8 vstatus;
1441 
1442 			read_reg(state,
1443 				 RSTV0910_P2_VSTATUSVIT + state->regoff,
1444 				 &vstatus);
1445 			feclock = (vstatus & 0x08) != 0;
1446 		}
1447 	}
1448 
1449 	if (feclock) {
1450 		*status |= FE_HAS_LOCK;
1451 
1452 		if (state->first_time_lock) {
1453 			u8 tmp;
1454 
1455 			state->first_time_lock = 0;
1456 
1457 			manage_matype_info(state);
1458 
1459 			if (state->receive_mode == RCVMODE_DVBS2) {
1460 				/*
1461 				 * FSTV0910_P2_MANUALSX_ROLLOFF,
1462 				 * FSTV0910_P2_MANUALS2_ROLLOFF = 0
1463 				 */
1464 				state->demod_bits &= ~0x84;
1465 				write_reg(state,
1466 					  RSTV0910_P2_DEMOD + state->regoff,
1467 					  state->demod_bits);
1468 				read_reg(state,
1469 					 RSTV0910_P2_PDELCTRL2 + state->regoff,
1470 					 &tmp);
1471 				/* reset DVBS2 packet delinator error counter */
1472 				tmp |= 0x40;
1473 				write_reg(state,
1474 					  RSTV0910_P2_PDELCTRL2 + state->regoff,
1475 					  tmp);
1476 				/* reset DVBS2 packet delinator error counter */
1477 				tmp &= ~0x40;
1478 				write_reg(state,
1479 					  RSTV0910_P2_PDELCTRL2 + state->regoff,
1480 					  tmp);
1481 
1482 				state->berscale = 2;
1483 				state->last_bernumerator = 0;
1484 				state->last_berdenominator = 1;
1485 				/* force to PRE BCH Rate */
1486 				write_reg(state,
1487 					  RSTV0910_P2_ERRCTRL1 + state->regoff,
1488 					  BER_SRC_S2 | state->berscale);
1489 			} else {
1490 				state->berscale = 2;
1491 				state->last_bernumerator = 0;
1492 				state->last_berdenominator = 1;
1493 				/* force to PRE RS Rate */
1494 				write_reg(state,
1495 					  RSTV0910_P2_ERRCTRL1 + state->regoff,
1496 					  BER_SRC_S | state->berscale);
1497 			}
1498 			/* Reset the Total packet counter */
1499 			write_reg(state,
1500 				  RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
1501 			/*
1502 			 * Reset the packet Error counter2 (and Set it to
1503 			 * infinite error count mode)
1504 			 */
1505 			write_reg(state,
1506 				  RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1507 
1508 			set_vth_default(state);
1509 			if (state->receive_mode == RCVMODE_DVBS)
1510 				enable_puncture_rate(state,
1511 						     state->puncture_rate);
1512 		}
1513 
1514 		/* Use highest signaled ModCod for quality */
1515 		if (state->is_vcm) {
1516 			u8 tmp;
1517 			enum fe_stv0910_mod_cod mod_cod;
1518 
1519 			read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
1520 				 &tmp);
1521 			mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
1522 
1523 			if (mod_cod > state->mod_cod)
1524 				state->mod_cod = mod_cod;
1525 		}
1526 	}
1527 
1528 	/* read signal statistics */
1529 
1530 	/* read signal strength */
1531 	read_signal_strength(fe);
1532 
1533 	/* read carrier/noise on FE_HAS_CARRIER */
1534 	if (*status & FE_HAS_CARRIER)
1535 		read_snr(fe);
1536 	else
1537 		p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1538 
1539 	/* read ber */
1540 	if (*status & FE_HAS_VITERBI) {
1541 		read_ber(fe);
1542 	} else {
1543 		p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1544 		p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1545 	}
1546 
1547 	return 0;
1548 }
1549 
1550 static int get_frontend(struct dvb_frontend *fe,
1551 			struct dtv_frontend_properties *p)
1552 {
1553 	struct stv *state = fe->demodulator_priv;
1554 	u8 tmp;
1555 	u32 symbolrate;
1556 
1557 	if (state->receive_mode == RCVMODE_DVBS2) {
1558 		u32 mc;
1559 		const enum fe_modulation modcod2mod[0x20] = {
1560 			QPSK, QPSK, QPSK, QPSK,
1561 			QPSK, QPSK, QPSK, QPSK,
1562 			QPSK, QPSK, QPSK, QPSK,
1563 			PSK_8, PSK_8, PSK_8, PSK_8,
1564 			PSK_8, PSK_8, APSK_16, APSK_16,
1565 			APSK_16, APSK_16, APSK_16, APSK_16,
1566 			APSK_32, APSK_32, APSK_32, APSK_32,
1567 			APSK_32,
1568 		};
1569 		const enum fe_code_rate modcod2fec[0x20] = {
1570 			FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
1571 			FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
1572 			FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1573 			FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
1574 			FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
1575 			FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1576 			FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
1577 			FEC_9_10
1578 		};
1579 		read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1580 		mc = ((tmp & 0x7c) >> 2);
1581 		p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
1582 		p->modulation = modcod2mod[mc];
1583 		p->fec_inner = modcod2fec[mc];
1584 	} else if (state->receive_mode == RCVMODE_DVBS) {
1585 		read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1586 		switch (tmp & 0x1F) {
1587 		case 0x0d:
1588 			p->fec_inner = FEC_1_2;
1589 			break;
1590 		case 0x12:
1591 			p->fec_inner = FEC_2_3;
1592 			break;
1593 		case 0x15:
1594 			p->fec_inner = FEC_3_4;
1595 			break;
1596 		case 0x18:
1597 			p->fec_inner = FEC_5_6;
1598 			break;
1599 		case 0x1a:
1600 			p->fec_inner = FEC_7_8;
1601 			break;
1602 		default:
1603 			p->fec_inner = FEC_NONE;
1604 			break;
1605 		}
1606 		p->rolloff = ROLLOFF_35;
1607 	}
1608 
1609 	if (state->receive_mode != RCVMODE_NONE) {
1610 		get_cur_symbol_rate(state, &symbolrate);
1611 		p->symbol_rate = symbolrate;
1612 	}
1613 	return 0;
1614 }
1615 
1616 static int tune(struct dvb_frontend *fe, bool re_tune,
1617 		unsigned int mode_flags,
1618 		unsigned int *delay, enum fe_status *status)
1619 {
1620 	struct stv *state = fe->demodulator_priv;
1621 	int r;
1622 
1623 	if (re_tune) {
1624 		r = set_parameters(fe);
1625 		if (r)
1626 			return r;
1627 		state->tune_time = jiffies;
1628 	}
1629 
1630 	r = read_status(fe, status);
1631 	if (r)
1632 		return r;
1633 
1634 	if (*status & FE_HAS_LOCK)
1635 		return 0;
1636 	*delay = HZ;
1637 
1638 	return 0;
1639 }
1640 
1641 static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
1642 {
1643 	return DVBFE_ALGO_HW;
1644 }
1645 
1646 static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1647 {
1648 	struct stv *state = fe->demodulator_priv;
1649 	u16 offs = state->nr ? 0x40 : 0;
1650 
1651 	switch (tone) {
1652 	case SEC_TONE_ON:
1653 		return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1654 	case SEC_TONE_OFF:
1655 		return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1656 	default:
1657 		break;
1658 	}
1659 	return -EINVAL;
1660 }
1661 
1662 static int wait_dis(struct stv *state, u8 flag, u8 val)
1663 {
1664 	int i;
1665 	u8 stat;
1666 	u16 offs = state->nr ? 0x40 : 0;
1667 
1668 	for (i = 0; i < 10; i++) {
1669 		read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1670 		if ((stat & flag) == val)
1671 			return 0;
1672 		usleep_range(10000, 11000);
1673 	}
1674 	return -ETIMEDOUT;
1675 }
1676 
1677 static int send_master_cmd(struct dvb_frontend *fe,
1678 			   struct dvb_diseqc_master_cmd *cmd)
1679 {
1680 	struct stv *state = fe->demodulator_priv;
1681 	int i;
1682 
1683 	SET_FIELD(DISEQC_MODE, 2);
1684 	SET_FIELD(DIS_PRECHARGE, 1);
1685 	for (i = 0; i < cmd->msg_len; i++) {
1686 		wait_dis(state, 0x40, 0x00);
1687 		SET_REG(DISTXFIFO, cmd->msg[i]);
1688 	}
1689 	SET_FIELD(DIS_PRECHARGE, 0);
1690 	wait_dis(state, 0x20, 0x20);
1691 	return 0;
1692 }
1693 
1694 static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
1695 {
1696 	struct stv *state = fe->demodulator_priv;
1697 	u8 value;
1698 
1699 	if (burst == SEC_MINI_A) {
1700 		SET_FIELD(DISEQC_MODE, 3);
1701 		value = 0x00;
1702 	} else {
1703 		SET_FIELD(DISEQC_MODE, 2);
1704 		value = 0xFF;
1705 	}
1706 
1707 	SET_FIELD(DIS_PRECHARGE, 1);
1708 	wait_dis(state, 0x40, 0x00);
1709 	SET_REG(DISTXFIFO, value);
1710 	SET_FIELD(DIS_PRECHARGE, 0);
1711 	wait_dis(state, 0x20, 0x20);
1712 
1713 	return 0;
1714 }
1715 
1716 static int sleep(struct dvb_frontend *fe)
1717 {
1718 	struct stv *state = fe->demodulator_priv;
1719 
1720 	stop(state);
1721 	return 0;
1722 }
1723 
1724 static const struct dvb_frontend_ops stv0910_ops = {
1725 	.delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1726 	.info = {
1727 		.name			= "ST STV0910",
1728 		.frequency_min_hz	=  950 * MHz,
1729 		.frequency_max_hz	= 2150 * MHz,
1730 		.symbol_rate_min	= 100000,
1731 		.symbol_rate_max	= 70000000,
1732 		.caps			= FE_CAN_INVERSION_AUTO |
1733 					  FE_CAN_FEC_AUTO       |
1734 					  FE_CAN_QPSK           |
1735 					  FE_CAN_2G_MODULATION  |
1736 					  FE_CAN_MULTISTREAM
1737 	},
1738 	.sleep				= sleep,
1739 	.release			= release,
1740 	.i2c_gate_ctrl			= gate_ctrl,
1741 	.set_frontend			= set_parameters,
1742 	.get_frontend_algo		= get_algo,
1743 	.get_frontend			= get_frontend,
1744 	.tune				= tune,
1745 	.read_status			= read_status,
1746 	.set_tone			= set_tone,
1747 
1748 	.diseqc_send_master_cmd		= send_master_cmd,
1749 	.diseqc_send_burst		= send_burst,
1750 };
1751 
1752 static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
1753 {
1754 	struct stv_base *p;
1755 
1756 	list_for_each_entry(p, &stvlist, stvlist)
1757 		if (p->i2c == i2c && p->adr == adr)
1758 			return p;
1759 	return NULL;
1760 }
1761 
1762 static void stv0910_init_stats(struct stv *state)
1763 {
1764 	struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1765 
1766 	p->strength.len = 1;
1767 	p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1768 	p->cnr.len = 1;
1769 	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1770 	p->pre_bit_error.len = 1;
1771 	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1772 	p->pre_bit_count.len = 1;
1773 	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1774 }
1775 
1776 struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
1777 				    struct stv0910_cfg *cfg,
1778 				    int nr)
1779 {
1780 	struct stv *state;
1781 	struct stv_base *base;
1782 
1783 	state = kzalloc(sizeof(*state), GFP_KERNEL);
1784 	if (!state)
1785 		return NULL;
1786 
1787 	state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1788 	state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1789 	state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
1790 	/* use safe tsspeed value if unspecified through stv0910_cfg */
1791 	state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
1792 	state->nr = nr;
1793 	state->regoff = state->nr ? 0 : 0x200;
1794 	state->search_range = 16000000;
1795 	state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1796 	state->receive_mode = RCVMODE_NONE;
1797 	state->cur_scrambling_code = (~0U);
1798 	state->single = cfg->single ? 1 : 0;
1799 
1800 	base = match_base(i2c, cfg->adr);
1801 	if (base) {
1802 		base->count++;
1803 		state->base = base;
1804 	} else {
1805 		base = kzalloc(sizeof(*base), GFP_KERNEL);
1806 		if (!base)
1807 			goto fail;
1808 		base->i2c = i2c;
1809 		base->adr = cfg->adr;
1810 		base->count = 1;
1811 		base->extclk = cfg->clk ? cfg->clk : 30000000;
1812 
1813 		mutex_init(&base->i2c_lock);
1814 		mutex_init(&base->reg_lock);
1815 		state->base = base;
1816 		if (probe(state) < 0) {
1817 			dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
1818 				 cfg->adr, dev_name(&i2c->dev));
1819 			kfree(base);
1820 			goto fail;
1821 		}
1822 		list_add(&base->stvlist, &stvlist);
1823 	}
1824 	state->fe.ops = stv0910_ops;
1825 	state->fe.demodulator_priv = state;
1826 	state->nr = nr;
1827 
1828 	dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
1829 		 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
1830 
1831 	stv0910_init_stats(state);
1832 
1833 	return &state->fe;
1834 
1835 fail:
1836 	kfree(state);
1837 	return NULL;
1838 }
1839 EXPORT_SYMBOL_GPL(stv0910_attach);
1840 
1841 MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
1842 MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
1843 MODULE_LICENSE("GPL v2");
1844