1bbeae430SDaniel Scheller // SPDX-License-Identifier: GPL-2.0
2cd21b334SDaniel Scheller /*
3cd21b334SDaniel Scheller * Driver for the ST STV0910 DVB-S/S2 demodulator.
4cd21b334SDaniel Scheller *
5cd21b334SDaniel Scheller * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
6cd21b334SDaniel Scheller * Marcus Metzler <mocm@metzlerbros.de>
7cd21b334SDaniel Scheller * developed for Digital Devices GmbH
8cd21b334SDaniel Scheller */
9cd21b334SDaniel Scheller
10cd21b334SDaniel Scheller #include <linux/kernel.h>
11cd21b334SDaniel Scheller #include <linux/module.h>
12cd21b334SDaniel Scheller #include <linux/moduleparam.h>
13cd21b334SDaniel Scheller #include <linux/init.h>
14cd21b334SDaniel Scheller #include <linux/delay.h>
15cd21b334SDaniel Scheller #include <linux/firmware.h>
16cd21b334SDaniel Scheller #include <linux/i2c.h>
17cd21b334SDaniel Scheller #include <asm/div64.h>
18cd21b334SDaniel Scheller
19fada1935SMauro Carvalho Chehab #include <media/dvb_frontend.h>
20cd21b334SDaniel Scheller #include "stv0910.h"
21cd21b334SDaniel Scheller #include "stv0910_regs.h"
22cd21b334SDaniel Scheller
23cd21b334SDaniel Scheller #define EXT_CLOCK 30000000
24cd21b334SDaniel Scheller #define TUNING_DELAY 200
25cd21b334SDaniel Scheller #define BER_SRC_S 0x20
26cd21b334SDaniel Scheller #define BER_SRC_S2 0x20
27cd21b334SDaniel Scheller
28c16ad5deSDaniel Scheller static LIST_HEAD(stvlist);
29cd21b334SDaniel Scheller
30cd21b334SDaniel Scheller enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
31cd21b334SDaniel Scheller
32cd21b334SDaniel Scheller enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
33cd21b334SDaniel Scheller
34cd21b334SDaniel Scheller enum dvbs2_mod_cod {
35cd21b334SDaniel Scheller DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
36cd21b334SDaniel Scheller DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,
37cd21b334SDaniel Scheller DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,
38cd21b334SDaniel Scheller DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,
39cd21b334SDaniel Scheller DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
40cd21b334SDaniel Scheller DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
41cd21b334SDaniel Scheller DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
42cd21b334SDaniel Scheller DVBS2_32APSK_9_10
43cd21b334SDaniel Scheller };
44cd21b334SDaniel Scheller
45cd21b334SDaniel Scheller enum fe_stv0910_mod_cod {
46cd21b334SDaniel Scheller FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
47cd21b334SDaniel Scheller FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
48cd21b334SDaniel Scheller FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
49cd21b334SDaniel Scheller FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
50cd21b334SDaniel Scheller FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
51cd21b334SDaniel Scheller FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
52cd21b334SDaniel Scheller FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
53cd21b334SDaniel Scheller FE_32APSK_910
54cd21b334SDaniel Scheller };
55cd21b334SDaniel Scheller
56cd21b334SDaniel Scheller enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
57cd21b334SDaniel Scheller
muldiv32(u32 a,u32 b,u32 c)58cd21b334SDaniel Scheller static inline u32 muldiv32(u32 a, u32 b, u32 c)
59cd21b334SDaniel Scheller {
60cd21b334SDaniel Scheller u64 tmp64;
61cd21b334SDaniel Scheller
62cd21b334SDaniel Scheller tmp64 = (u64)a * (u64)b;
63cd21b334SDaniel Scheller do_div(tmp64, c);
64cd21b334SDaniel Scheller
65cd21b334SDaniel Scheller return (u32)tmp64;
66cd21b334SDaniel Scheller }
67cd21b334SDaniel Scheller
68cd21b334SDaniel Scheller struct stv_base {
69cd21b334SDaniel Scheller struct list_head stvlist;
70cd21b334SDaniel Scheller
71cd21b334SDaniel Scheller u8 adr;
72cd21b334SDaniel Scheller struct i2c_adapter *i2c;
73ddb6a90dSDaniel Scheller struct mutex i2c_lock; /* shared I2C access protect */
74ddb6a90dSDaniel Scheller struct mutex reg_lock; /* shared register write protect */
75cd21b334SDaniel Scheller int count;
76cd21b334SDaniel Scheller
77cd21b334SDaniel Scheller u32 extclk;
78cd21b334SDaniel Scheller u32 mclk;
79cd21b334SDaniel Scheller };
80cd21b334SDaniel Scheller
81cd21b334SDaniel Scheller struct stv {
82cd21b334SDaniel Scheller struct stv_base *base;
83cd21b334SDaniel Scheller struct dvb_frontend fe;
84cd21b334SDaniel Scheller int nr;
85cd21b334SDaniel Scheller u16 regoff;
86cd21b334SDaniel Scheller u8 i2crpt;
87cd21b334SDaniel Scheller u8 tscfgh;
88cd21b334SDaniel Scheller u8 tsgeneral;
89cd21b334SDaniel Scheller u8 tsspeed;
90cd21b334SDaniel Scheller u8 single;
91cd21b334SDaniel Scheller unsigned long tune_time;
92cd21b334SDaniel Scheller
93cd21b334SDaniel Scheller s32 search_range;
94cd21b334SDaniel Scheller u32 started;
95cd21b334SDaniel Scheller u32 demod_lock_time;
96cd21b334SDaniel Scheller enum receive_mode receive_mode;
97cd21b334SDaniel Scheller u32 demod_timeout;
98cd21b334SDaniel Scheller u32 fec_timeout;
99cd21b334SDaniel Scheller u32 first_time_lock;
100cd21b334SDaniel Scheller u8 demod_bits;
101cd21b334SDaniel Scheller u32 symbol_rate;
102cd21b334SDaniel Scheller
103cd21b334SDaniel Scheller u8 last_viterbi_rate;
104cd21b334SDaniel Scheller enum fe_code_rate puncture_rate;
105cd21b334SDaniel Scheller enum fe_stv0910_mod_cod mod_cod;
106cd21b334SDaniel Scheller enum dvbs2_fectype fectype;
107cd21b334SDaniel Scheller u32 pilots;
108cd21b334SDaniel Scheller enum fe_stv0910_roll_off feroll_off;
109cd21b334SDaniel Scheller
110cd21b334SDaniel Scheller int is_standard_broadcast;
111cd21b334SDaniel Scheller int is_vcm;
112cd21b334SDaniel Scheller
113ea71c62bSDaniel Scheller u32 cur_scrambling_code;
114ea71c62bSDaniel Scheller
115cd21b334SDaniel Scheller u32 last_bernumerator;
116cd21b334SDaniel Scheller u32 last_berdenominator;
117cd21b334SDaniel Scheller u8 berscale;
118cd21b334SDaniel Scheller
119cd21b334SDaniel Scheller u8 vth[6];
120cd21b334SDaniel Scheller };
121cd21b334SDaniel Scheller
122cd21b334SDaniel Scheller struct sinit_table {
123cd21b334SDaniel Scheller u16 address;
124cd21b334SDaniel Scheller u8 data;
125cd21b334SDaniel Scheller };
126cd21b334SDaniel Scheller
127cd21b334SDaniel Scheller struct slookup {
128cd21b334SDaniel Scheller s16 value;
12919bb3b71SDaniel Scheller u32 reg_value;
130cd21b334SDaniel Scheller };
131cd21b334SDaniel Scheller
write_reg(struct stv * state,u16 reg,u8 val)1328042e98cSDaniel Scheller static int write_reg(struct stv *state, u16 reg, u8 val)
133cd21b334SDaniel Scheller {
1348042e98cSDaniel Scheller struct i2c_adapter *adap = state->base->i2c;
1358042e98cSDaniel Scheller u8 data[3] = {reg >> 8, reg & 0xff, val};
1368042e98cSDaniel Scheller struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
1378042e98cSDaniel Scheller .buf = data, .len = 3};
138cd21b334SDaniel Scheller
139cd21b334SDaniel Scheller if (i2c_transfer(adap, &msg, 1) != 1) {
140cd21b334SDaniel Scheller dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
1418042e98cSDaniel Scheller state->base->adr, reg, val);
1428042e98cSDaniel Scheller return -EIO;
143cd21b334SDaniel Scheller }
144cd21b334SDaniel Scheller return 0;
145cd21b334SDaniel Scheller }
146cd21b334SDaniel Scheller
i2c_read_regs16(struct i2c_adapter * adapter,u8 adr,u16 reg,u8 * val,int count)147cd21b334SDaniel Scheller static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
148cd21b334SDaniel Scheller u16 reg, u8 *val, int count)
149cd21b334SDaniel Scheller {
150cd21b334SDaniel Scheller u8 msg[2] = {reg >> 8, reg & 0xff};
151cd21b334SDaniel Scheller struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
152cd21b334SDaniel Scheller .buf = msg, .len = 2},
153cd21b334SDaniel Scheller {.addr = adr, .flags = I2C_M_RD,
154cd21b334SDaniel Scheller .buf = val, .len = count } };
155cd21b334SDaniel Scheller
156cd21b334SDaniel Scheller if (i2c_transfer(adapter, msgs, 2) != 2) {
157cd21b334SDaniel Scheller dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
158cd21b334SDaniel Scheller adr, reg);
1598042e98cSDaniel Scheller return -EIO;
160cd21b334SDaniel Scheller }
161cd21b334SDaniel Scheller return 0;
162cd21b334SDaniel Scheller }
163cd21b334SDaniel Scheller
read_reg(struct stv * state,u16 reg,u8 * val)164cd21b334SDaniel Scheller static int read_reg(struct stv *state, u16 reg, u8 *val)
165cd21b334SDaniel Scheller {
166cd21b334SDaniel Scheller return i2c_read_regs16(state->base->i2c, state->base->adr,
167cd21b334SDaniel Scheller reg, val, 1);
168cd21b334SDaniel Scheller }
169cd21b334SDaniel Scheller
read_regs(struct stv * state,u16 reg,u8 * val,int len)170cd21b334SDaniel Scheller static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
171cd21b334SDaniel Scheller {
172cd21b334SDaniel Scheller return i2c_read_regs16(state->base->i2c, state->base->adr,
173cd21b334SDaniel Scheller reg, val, len);
174cd21b334SDaniel Scheller }
175cd21b334SDaniel Scheller
write_shared_reg(struct stv * state,u16 reg,u8 mask,u8 val)176cd21b334SDaniel Scheller static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
177cd21b334SDaniel Scheller {
178cd21b334SDaniel Scheller int status;
179cd21b334SDaniel Scheller u8 tmp;
180cd21b334SDaniel Scheller
181cd21b334SDaniel Scheller mutex_lock(&state->base->reg_lock);
182cd21b334SDaniel Scheller status = read_reg(state, reg, &tmp);
183cd21b334SDaniel Scheller if (!status)
184cd21b334SDaniel Scheller status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
185cd21b334SDaniel Scheller mutex_unlock(&state->base->reg_lock);
186cd21b334SDaniel Scheller return status;
187cd21b334SDaniel Scheller }
188cd21b334SDaniel Scheller
write_field(struct stv * state,u32 field,u8 val)1896392bc2eSDaniel Scheller static int write_field(struct stv *state, u32 field, u8 val)
190bdd7682bSDaniel Scheller {
191bdd7682bSDaniel Scheller int status;
192bdd7682bSDaniel Scheller u8 shift, mask, old, new;
193bdd7682bSDaniel Scheller
194bdd7682bSDaniel Scheller status = read_reg(state, field >> 16, &old);
195bdd7682bSDaniel Scheller if (status)
196bdd7682bSDaniel Scheller return status;
197bdd7682bSDaniel Scheller mask = field & 0xff;
198bdd7682bSDaniel Scheller shift = (field >> 12) & 0xf;
199bdd7682bSDaniel Scheller new = ((val << shift) & mask) | (old & ~mask);
200bdd7682bSDaniel Scheller if (new == old)
201bdd7682bSDaniel Scheller return 0;
202bdd7682bSDaniel Scheller return write_reg(state, field >> 16, new);
203bdd7682bSDaniel Scheller }
204bdd7682bSDaniel Scheller
205bdd7682bSDaniel Scheller #define SET_FIELD(_reg, _val) \
206bdd7682bSDaniel Scheller write_field(state, state->nr ? FSTV0910_P2_##_reg : \
207bdd7682bSDaniel Scheller FSTV0910_P1_##_reg, _val)
208bdd7682bSDaniel Scheller
209bdd7682bSDaniel Scheller #define SET_REG(_reg, _val) \
210bdd7682bSDaniel Scheller write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
211bdd7682bSDaniel Scheller RSTV0910_P1_##_reg, _val)
212bdd7682bSDaniel Scheller
213bdd7682bSDaniel Scheller #define GET_REG(_reg, _val) \
214bdd7682bSDaniel Scheller read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
215bdd7682bSDaniel Scheller RSTV0910_P1_##_reg, _val)
216bdd7682bSDaniel Scheller
21720e671dfSDaniel Scheller static const struct slookup s1_sn_lookup[] = {
218cd21b334SDaniel Scheller { 0, 9242 }, /* C/N= 0dB */
219cd21b334SDaniel Scheller { 5, 9105 }, /* C/N= 0.5dB */
220cd21b334SDaniel Scheller { 10, 8950 }, /* C/N= 1.0dB */
221cd21b334SDaniel Scheller { 15, 8780 }, /* C/N= 1.5dB */
222cd21b334SDaniel Scheller { 20, 8566 }, /* C/N= 2.0dB */
223cd21b334SDaniel Scheller { 25, 8366 }, /* C/N= 2.5dB */
224cd21b334SDaniel Scheller { 30, 8146 }, /* C/N= 3.0dB */
225cd21b334SDaniel Scheller { 35, 7908 }, /* C/N= 3.5dB */
226cd21b334SDaniel Scheller { 40, 7666 }, /* C/N= 4.0dB */
227cd21b334SDaniel Scheller { 45, 7405 }, /* C/N= 4.5dB */
228cd21b334SDaniel Scheller { 50, 7136 }, /* C/N= 5.0dB */
229cd21b334SDaniel Scheller { 55, 6861 }, /* C/N= 5.5dB */
230cd21b334SDaniel Scheller { 60, 6576 }, /* C/N= 6.0dB */
231cd21b334SDaniel Scheller { 65, 6330 }, /* C/N= 6.5dB */
232cd21b334SDaniel Scheller { 70, 6048 }, /* C/N= 7.0dB */
233cd21b334SDaniel Scheller { 75, 5768 }, /* C/N= 7.5dB */
234cd21b334SDaniel Scheller { 80, 5492 }, /* C/N= 8.0dB */
235cd21b334SDaniel Scheller { 85, 5224 }, /* C/N= 8.5dB */
236cd21b334SDaniel Scheller { 90, 4959 }, /* C/N= 9.0dB */
237cd21b334SDaniel Scheller { 95, 4709 }, /* C/N= 9.5dB */
238cd21b334SDaniel Scheller { 100, 4467 }, /* C/N=10.0dB */
239cd21b334SDaniel Scheller { 105, 4236 }, /* C/N=10.5dB */
240cd21b334SDaniel Scheller { 110, 4013 }, /* C/N=11.0dB */
241cd21b334SDaniel Scheller { 115, 3800 }, /* C/N=11.5dB */
242cd21b334SDaniel Scheller { 120, 3598 }, /* C/N=12.0dB */
243cd21b334SDaniel Scheller { 125, 3406 }, /* C/N=12.5dB */
244cd21b334SDaniel Scheller { 130, 3225 }, /* C/N=13.0dB */
245cd21b334SDaniel Scheller { 135, 3052 }, /* C/N=13.5dB */
246cd21b334SDaniel Scheller { 140, 2889 }, /* C/N=14.0dB */
247cd21b334SDaniel Scheller { 145, 2733 }, /* C/N=14.5dB */
248cd21b334SDaniel Scheller { 150, 2587 }, /* C/N=15.0dB */
249cd21b334SDaniel Scheller { 160, 2318 }, /* C/N=16.0dB */
250cd21b334SDaniel Scheller { 170, 2077 }, /* C/N=17.0dB */
251cd21b334SDaniel Scheller { 180, 1862 }, /* C/N=18.0dB */
252cd21b334SDaniel Scheller { 190, 1670 }, /* C/N=19.0dB */
253cd21b334SDaniel Scheller { 200, 1499 }, /* C/N=20.0dB */
254cd21b334SDaniel Scheller { 210, 1347 }, /* C/N=21.0dB */
255cd21b334SDaniel Scheller { 220, 1213 }, /* C/N=22.0dB */
256cd21b334SDaniel Scheller { 230, 1095 }, /* C/N=23.0dB */
257cd21b334SDaniel Scheller { 240, 992 }, /* C/N=24.0dB */
258cd21b334SDaniel Scheller { 250, 900 }, /* C/N=25.0dB */
259cd21b334SDaniel Scheller { 260, 826 }, /* C/N=26.0dB */
260cd21b334SDaniel Scheller { 270, 758 }, /* C/N=27.0dB */
261cd21b334SDaniel Scheller { 280, 702 }, /* C/N=28.0dB */
262cd21b334SDaniel Scheller { 290, 653 }, /* C/N=29.0dB */
263cd21b334SDaniel Scheller { 300, 613 }, /* C/N=30.0dB */
264cd21b334SDaniel Scheller { 310, 579 }, /* C/N=31.0dB */
265cd21b334SDaniel Scheller { 320, 550 }, /* C/N=32.0dB */
266cd21b334SDaniel Scheller { 330, 526 }, /* C/N=33.0dB */
267cd21b334SDaniel Scheller { 350, 490 }, /* C/N=33.0dB */
268cd21b334SDaniel Scheller { 400, 445 }, /* C/N=40.0dB */
269cd21b334SDaniel Scheller { 450, 430 }, /* C/N=45.0dB */
270cd21b334SDaniel Scheller { 500, 426 }, /* C/N=50.0dB */
271cd21b334SDaniel Scheller { 510, 425 } /* C/N=51.0dB */
272cd21b334SDaniel Scheller };
273cd21b334SDaniel Scheller
27420e671dfSDaniel Scheller static const struct slookup s2_sn_lookup[] = {
275cd21b334SDaniel Scheller { -30, 13950 }, /* C/N=-2.5dB */
276cd21b334SDaniel Scheller { -25, 13580 }, /* C/N=-2.5dB */
277cd21b334SDaniel Scheller { -20, 13150 }, /* C/N=-2.0dB */
278cd21b334SDaniel Scheller { -15, 12760 }, /* C/N=-1.5dB */
279cd21b334SDaniel Scheller { -10, 12345 }, /* C/N=-1.0dB */
280cd21b334SDaniel Scheller { -5, 11900 }, /* C/N=-0.5dB */
281cd21b334SDaniel Scheller { 0, 11520 }, /* C/N= 0dB */
282cd21b334SDaniel Scheller { 5, 11080 }, /* C/N= 0.5dB */
283cd21b334SDaniel Scheller { 10, 10630 }, /* C/N= 1.0dB */
284cd21b334SDaniel Scheller { 15, 10210 }, /* C/N= 1.5dB */
285cd21b334SDaniel Scheller { 20, 9790 }, /* C/N= 2.0dB */
286cd21b334SDaniel Scheller { 25, 9390 }, /* C/N= 2.5dB */
287cd21b334SDaniel Scheller { 30, 8970 }, /* C/N= 3.0dB */
288cd21b334SDaniel Scheller { 35, 8575 }, /* C/N= 3.5dB */
289cd21b334SDaniel Scheller { 40, 8180 }, /* C/N= 4.0dB */
290cd21b334SDaniel Scheller { 45, 7800 }, /* C/N= 4.5dB */
291cd21b334SDaniel Scheller { 50, 7430 }, /* C/N= 5.0dB */
292cd21b334SDaniel Scheller { 55, 7080 }, /* C/N= 5.5dB */
293cd21b334SDaniel Scheller { 60, 6720 }, /* C/N= 6.0dB */
294cd21b334SDaniel Scheller { 65, 6320 }, /* C/N= 6.5dB */
295cd21b334SDaniel Scheller { 70, 6060 }, /* C/N= 7.0dB */
296cd21b334SDaniel Scheller { 75, 5760 }, /* C/N= 7.5dB */
297cd21b334SDaniel Scheller { 80, 5480 }, /* C/N= 8.0dB */
298cd21b334SDaniel Scheller { 85, 5200 }, /* C/N= 8.5dB */
299cd21b334SDaniel Scheller { 90, 4930 }, /* C/N= 9.0dB */
300cd21b334SDaniel Scheller { 95, 4680 }, /* C/N= 9.5dB */
301cd21b334SDaniel Scheller { 100, 4425 }, /* C/N=10.0dB */
302cd21b334SDaniel Scheller { 105, 4210 }, /* C/N=10.5dB */
303cd21b334SDaniel Scheller { 110, 3980 }, /* C/N=11.0dB */
304cd21b334SDaniel Scheller { 115, 3765 }, /* C/N=11.5dB */
305cd21b334SDaniel Scheller { 120, 3570 }, /* C/N=12.0dB */
306cd21b334SDaniel Scheller { 125, 3315 }, /* C/N=12.5dB */
307cd21b334SDaniel Scheller { 130, 3140 }, /* C/N=13.0dB */
308cd21b334SDaniel Scheller { 135, 2980 }, /* C/N=13.5dB */
309cd21b334SDaniel Scheller { 140, 2820 }, /* C/N=14.0dB */
310cd21b334SDaniel Scheller { 145, 2670 }, /* C/N=14.5dB */
311cd21b334SDaniel Scheller { 150, 2535 }, /* C/N=15.0dB */
312cd21b334SDaniel Scheller { 160, 2270 }, /* C/N=16.0dB */
313cd21b334SDaniel Scheller { 170, 2035 }, /* C/N=17.0dB */
314cd21b334SDaniel Scheller { 180, 1825 }, /* C/N=18.0dB */
315cd21b334SDaniel Scheller { 190, 1650 }, /* C/N=19.0dB */
316cd21b334SDaniel Scheller { 200, 1485 }, /* C/N=20.0dB */
317cd21b334SDaniel Scheller { 210, 1340 }, /* C/N=21.0dB */
318cd21b334SDaniel Scheller { 220, 1212 }, /* C/N=22.0dB */
319cd21b334SDaniel Scheller { 230, 1100 }, /* C/N=23.0dB */
320cd21b334SDaniel Scheller { 240, 1000 }, /* C/N=24.0dB */
321cd21b334SDaniel Scheller { 250, 910 }, /* C/N=25.0dB */
322cd21b334SDaniel Scheller { 260, 836 }, /* C/N=26.0dB */
323cd21b334SDaniel Scheller { 270, 772 }, /* C/N=27.0dB */
324cd21b334SDaniel Scheller { 280, 718 }, /* C/N=28.0dB */
325cd21b334SDaniel Scheller { 290, 671 }, /* C/N=29.0dB */
326cd21b334SDaniel Scheller { 300, 635 }, /* C/N=30.0dB */
327cd21b334SDaniel Scheller { 310, 602 }, /* C/N=31.0dB */
328cd21b334SDaniel Scheller { 320, 575 }, /* C/N=32.0dB */
329cd21b334SDaniel Scheller { 330, 550 }, /* C/N=33.0dB */
330cd21b334SDaniel Scheller { 350, 517 }, /* C/N=35.0dB */
331cd21b334SDaniel Scheller { 400, 480 }, /* C/N=40.0dB */
332cd21b334SDaniel Scheller { 450, 466 }, /* C/N=45.0dB */
333cd21b334SDaniel Scheller { 500, 464 }, /* C/N=50.0dB */
334cd21b334SDaniel Scheller { 510, 463 }, /* C/N=51.0dB */
335cd21b334SDaniel Scheller };
336cd21b334SDaniel Scheller
33720e671dfSDaniel Scheller static const struct slookup padc_lookup[] = {
33819bb3b71SDaniel Scheller { 0, 118000 }, /* PADC= +0dBm */
33919bb3b71SDaniel Scheller { -100, 93600 }, /* PADC= -1dBm */
34019bb3b71SDaniel Scheller { -200, 74500 }, /* PADC= -2dBm */
34119bb3b71SDaniel Scheller { -300, 59100 }, /* PADC= -3dBm */
34219bb3b71SDaniel Scheller { -400, 47000 }, /* PADC= -4dBm */
34319bb3b71SDaniel Scheller { -500, 37300 }, /* PADC= -5dBm */
34419bb3b71SDaniel Scheller { -600, 29650 }, /* PADC= -6dBm */
34519bb3b71SDaniel Scheller { -700, 23520 }, /* PADC= -7dBm */
34619bb3b71SDaniel Scheller { -900, 14850 }, /* PADC= -9dBm */
34719bb3b71SDaniel Scheller { -1100, 9380 }, /* PADC=-11dBm */
34819bb3b71SDaniel Scheller { -1300, 5910 }, /* PADC=-13dBm */
34919bb3b71SDaniel Scheller { -1500, 3730 }, /* PADC=-15dBm */
35019bb3b71SDaniel Scheller { -1700, 2354 }, /* PADC=-17dBm */
35119bb3b71SDaniel Scheller { -1900, 1485 }, /* PADC=-19dBm */
35219bb3b71SDaniel Scheller { -2000, 1179 }, /* PADC=-20dBm */
35319bb3b71SDaniel Scheller { -2100, 1000 }, /* PADC=-21dBm */
35419bb3b71SDaniel Scheller };
35519bb3b71SDaniel Scheller
356cd21b334SDaniel Scheller /*********************************************************************
357cd21b334SDaniel Scheller * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
358cd21b334SDaniel Scheller *********************************************************************/
35920e671dfSDaniel Scheller static const u8 s2car_loop[] = {
3604f979d5cSDaniel Scheller /*
3614f979d5cSDaniel Scheller * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
362cd21b334SDaniel Scheller * 20MPon 20MPoff 30MPon 30MPoff
363cd21b334SDaniel Scheller */
364cd21b334SDaniel Scheller
365cd21b334SDaniel Scheller /* FE_QPSK_14 */
366cd21b334SDaniel Scheller 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
367cd21b334SDaniel Scheller /* FE_QPSK_13 */
368cd21b334SDaniel Scheller 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
369cd21b334SDaniel Scheller /* FE_QPSK_25 */
370cd21b334SDaniel Scheller 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
371cd21b334SDaniel Scheller /* FE_QPSK_12 */
372cd21b334SDaniel Scheller 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
373cd21b334SDaniel Scheller /* FE_QPSK_35 */
374cd21b334SDaniel Scheller 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
375cd21b334SDaniel Scheller /* FE_QPSK_23 */
376cd21b334SDaniel Scheller 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
377cd21b334SDaniel Scheller /* FE_QPSK_34 */
378cd21b334SDaniel Scheller 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
379cd21b334SDaniel Scheller /* FE_QPSK_45 */
380cd21b334SDaniel Scheller 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
381cd21b334SDaniel Scheller /* FE_QPSK_56 */
382cd21b334SDaniel Scheller 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
383cd21b334SDaniel Scheller /* FE_QPSK_89 */
384cd21b334SDaniel Scheller 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
385cd21b334SDaniel Scheller /* FE_QPSK_910 */
386cd21b334SDaniel Scheller 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
387cd21b334SDaniel Scheller /* FE_8PSK_35 */
388cd21b334SDaniel Scheller 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
389cd21b334SDaniel Scheller /* FE_8PSK_23 */
390cd21b334SDaniel Scheller 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
391cd21b334SDaniel Scheller /* FE_8PSK_34 */
392cd21b334SDaniel Scheller 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
393cd21b334SDaniel Scheller /* FE_8PSK_56 */
394cd21b334SDaniel Scheller 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
395cd21b334SDaniel Scheller /* FE_8PSK_89 */
396cd21b334SDaniel Scheller 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
397cd21b334SDaniel Scheller /* FE_8PSK_910 */
398cd21b334SDaniel Scheller 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
399cd21b334SDaniel Scheller
400cd21b334SDaniel Scheller /**********************************************************************
401cd21b334SDaniel Scheller * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
402cd21b334SDaniel Scheller **********************************************************************/
403cd21b334SDaniel Scheller
4044f979d5cSDaniel Scheller /*
4054f979d5cSDaniel Scheller * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
406cd21b334SDaniel Scheller * 20MPoff 30MPon 30MPoff
407cd21b334SDaniel Scheller */
408cd21b334SDaniel Scheller
409cd21b334SDaniel Scheller /* FE_16APSK_23 */
410cd21b334SDaniel Scheller 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
411cd21b334SDaniel Scheller /* FE_16APSK_34 */
412cd21b334SDaniel Scheller 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
413cd21b334SDaniel Scheller /* FE_16APSK_45 */
414cd21b334SDaniel Scheller 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
415cd21b334SDaniel Scheller /* FE_16APSK_56 */
416cd21b334SDaniel Scheller 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
417cd21b334SDaniel Scheller /* FE_16APSK_89 */
418cd21b334SDaniel Scheller 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
419cd21b334SDaniel Scheller /* FE_16APSK_910 */
420cd21b334SDaniel Scheller 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
421cd21b334SDaniel Scheller /* FE_32APSK_34 */
422cd21b334SDaniel Scheller 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
423cd21b334SDaniel Scheller /* FE_32APSK_45 */
424cd21b334SDaniel Scheller 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
425cd21b334SDaniel Scheller /* FE_32APSK_56 */
426cd21b334SDaniel Scheller 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
427cd21b334SDaniel Scheller /* FE_32APSK_89 */
428cd21b334SDaniel Scheller 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
429cd21b334SDaniel Scheller /* FE_32APSK_910 */
430cd21b334SDaniel Scheller 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
431cd21b334SDaniel Scheller };
432cd21b334SDaniel Scheller
get_optim_cloop(struct stv * state,enum fe_stv0910_mod_cod mod_cod,u32 pilots)433cd21b334SDaniel Scheller static u8 get_optim_cloop(struct stv *state,
434cd21b334SDaniel Scheller enum fe_stv0910_mod_cod mod_cod, u32 pilots)
435cd21b334SDaniel Scheller {
436cd21b334SDaniel Scheller int i = 0;
437cd21b334SDaniel Scheller
438cd21b334SDaniel Scheller if (mod_cod >= FE_32APSK_910)
439cd21b334SDaniel Scheller i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
440cd21b334SDaniel Scheller else if (mod_cod >= FE_QPSK_14)
441cd21b334SDaniel Scheller i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
442cd21b334SDaniel Scheller
443cd21b334SDaniel Scheller if (state->symbol_rate <= 3000000)
444cd21b334SDaniel Scheller i += 0;
445cd21b334SDaniel Scheller else if (state->symbol_rate <= 7000000)
446cd21b334SDaniel Scheller i += 2;
447cd21b334SDaniel Scheller else if (state->symbol_rate <= 15000000)
448cd21b334SDaniel Scheller i += 4;
449cd21b334SDaniel Scheller else if (state->symbol_rate <= 25000000)
450cd21b334SDaniel Scheller i += 6;
451cd21b334SDaniel Scheller else
452cd21b334SDaniel Scheller i += 8;
453cd21b334SDaniel Scheller
454cd21b334SDaniel Scheller if (!pilots)
455cd21b334SDaniel Scheller i += 1;
456cd21b334SDaniel Scheller
457cd21b334SDaniel Scheller return s2car_loop[i];
458cd21b334SDaniel Scheller }
459cd21b334SDaniel Scheller
get_cur_symbol_rate(struct stv * state,u32 * p_symbol_rate)460cd21b334SDaniel Scheller static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
461cd21b334SDaniel Scheller {
462cd21b334SDaniel Scheller int status = 0;
463cd21b334SDaniel Scheller u8 symb_freq0;
464cd21b334SDaniel Scheller u8 symb_freq1;
465cd21b334SDaniel Scheller u8 symb_freq2;
466cd21b334SDaniel Scheller u8 symb_freq3;
467cd21b334SDaniel Scheller u8 tim_offs0;
468cd21b334SDaniel Scheller u8 tim_offs1;
469cd21b334SDaniel Scheller u8 tim_offs2;
470cd21b334SDaniel Scheller u32 symbol_rate;
471cd21b334SDaniel Scheller s32 timing_offset;
472cd21b334SDaniel Scheller
473cd21b334SDaniel Scheller *p_symbol_rate = 0;
474cd21b334SDaniel Scheller if (!state->started)
475cd21b334SDaniel Scheller return status;
476cd21b334SDaniel Scheller
477cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
478cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
479cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
480cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
481cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
482cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
483cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
484cd21b334SDaniel Scheller
485cd21b334SDaniel Scheller symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
486cd21b334SDaniel Scheller ((u32)symb_freq1 << 8) | (u32)symb_freq0;
487cd21b334SDaniel Scheller timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
488cd21b334SDaniel Scheller (u32)tim_offs0;
489cd21b334SDaniel Scheller
490cd21b334SDaniel Scheller if ((timing_offset & (1 << 23)) != 0)
491cd21b334SDaniel Scheller timing_offset |= 0xFF000000; /* Sign extent */
492cd21b334SDaniel Scheller
493cd21b334SDaniel Scheller symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
494cd21b334SDaniel Scheller timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
495cd21b334SDaniel Scheller
496cd21b334SDaniel Scheller *p_symbol_rate = symbol_rate + timing_offset;
497cd21b334SDaniel Scheller
498cd21b334SDaniel Scheller return 0;
499cd21b334SDaniel Scheller }
500cd21b334SDaniel Scheller
get_signal_parameters(struct stv * state)501cd21b334SDaniel Scheller static int get_signal_parameters(struct stv *state)
502cd21b334SDaniel Scheller {
503cd21b334SDaniel Scheller u8 tmp;
504cd21b334SDaniel Scheller
505cd21b334SDaniel Scheller if (!state->started)
506cd21b334SDaniel Scheller return -EINVAL;
507cd21b334SDaniel Scheller
508cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS2) {
509cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
510cd21b334SDaniel Scheller state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
511cd21b334SDaniel Scheller state->pilots = (tmp & 0x01) != 0;
512cd21b334SDaniel Scheller state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
513cd21b334SDaniel Scheller
514cd21b334SDaniel Scheller } else if (state->receive_mode == RCVMODE_DVBS) {
515cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
516cd21b334SDaniel Scheller state->puncture_rate = FEC_NONE;
517cd21b334SDaniel Scheller switch (tmp & 0x1F) {
518cd21b334SDaniel Scheller case 0x0d:
519cd21b334SDaniel Scheller state->puncture_rate = FEC_1_2;
520cd21b334SDaniel Scheller break;
521cd21b334SDaniel Scheller case 0x12:
522cd21b334SDaniel Scheller state->puncture_rate = FEC_2_3;
523cd21b334SDaniel Scheller break;
524cd21b334SDaniel Scheller case 0x15:
525cd21b334SDaniel Scheller state->puncture_rate = FEC_3_4;
526cd21b334SDaniel Scheller break;
527cd21b334SDaniel Scheller case 0x18:
528cd21b334SDaniel Scheller state->puncture_rate = FEC_5_6;
529cd21b334SDaniel Scheller break;
530cd21b334SDaniel Scheller case 0x1a:
531cd21b334SDaniel Scheller state->puncture_rate = FEC_7_8;
532cd21b334SDaniel Scheller break;
533cd21b334SDaniel Scheller }
534cd21b334SDaniel Scheller state->is_vcm = 0;
535cd21b334SDaniel Scheller state->is_standard_broadcast = 1;
536cd21b334SDaniel Scheller state->feroll_off = FE_SAT_35;
537cd21b334SDaniel Scheller }
538cd21b334SDaniel Scheller return 0;
539cd21b334SDaniel Scheller }
540cd21b334SDaniel Scheller
tracking_optimization(struct stv * state)541cd21b334SDaniel Scheller static int tracking_optimization(struct stv *state)
542cd21b334SDaniel Scheller {
543cd21b334SDaniel Scheller u8 tmp;
544cd21b334SDaniel Scheller
545cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
546cd21b334SDaniel Scheller tmp &= ~0xC0;
547cd21b334SDaniel Scheller
548cd21b334SDaniel Scheller switch (state->receive_mode) {
549cd21b334SDaniel Scheller case RCVMODE_DVBS:
550cd21b334SDaniel Scheller tmp |= 0x40;
551cd21b334SDaniel Scheller break;
552cd21b334SDaniel Scheller case RCVMODE_DVBS2:
553cd21b334SDaniel Scheller tmp |= 0x80;
554cd21b334SDaniel Scheller break;
555cd21b334SDaniel Scheller default:
556cd21b334SDaniel Scheller tmp |= 0xC0;
557cd21b334SDaniel Scheller break;
558cd21b334SDaniel Scheller }
559cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
560cd21b334SDaniel Scheller
561cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS2) {
562cd21b334SDaniel Scheller /* Disable Reed-Solomon */
563cd21b334SDaniel Scheller write_shared_reg(state,
564cd21b334SDaniel Scheller RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
565cd21b334SDaniel Scheller 0x03);
566cd21b334SDaniel Scheller
567cd21b334SDaniel Scheller if (state->fectype == DVBS2_64K) {
568cd21b334SDaniel Scheller u8 aclc = get_optim_cloop(state, state->mod_cod,
569cd21b334SDaniel Scheller state->pilots);
570cd21b334SDaniel Scheller
571cd21b334SDaniel Scheller if (state->mod_cod <= FE_QPSK_910) {
572cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S2Q +
573cd21b334SDaniel Scheller state->regoff, aclc);
574cd21b334SDaniel Scheller } else if (state->mod_cod <= FE_8PSK_910) {
575cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S2Q +
576cd21b334SDaniel Scheller state->regoff, 0x2a);
577cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S28 +
578cd21b334SDaniel Scheller state->regoff, aclc);
579cd21b334SDaniel Scheller } else if (state->mod_cod <= FE_16APSK_910) {
580cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S2Q +
581cd21b334SDaniel Scheller state->regoff, 0x2a);
582cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S216A +
583cd21b334SDaniel Scheller state->regoff, aclc);
584cd21b334SDaniel Scheller } else if (state->mod_cod <= FE_32APSK_910) {
585cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S2Q +
586cd21b334SDaniel Scheller state->regoff, 0x2a);
587cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S232A +
588cd21b334SDaniel Scheller state->regoff, aclc);
589cd21b334SDaniel Scheller }
590cd21b334SDaniel Scheller }
591cd21b334SDaniel Scheller }
592cd21b334SDaniel Scheller return 0;
593cd21b334SDaniel Scheller }
594cd21b334SDaniel Scheller
table_lookup(const struct slookup * table,int table_size,u32 reg_value)59520e671dfSDaniel Scheller static s32 table_lookup(const struct slookup *table,
59619bb3b71SDaniel Scheller int table_size, u32 reg_value)
597cd21b334SDaniel Scheller {
598cd21b334SDaniel Scheller s32 value;
599cd21b334SDaniel Scheller int imin = 0;
600cd21b334SDaniel Scheller int imax = table_size - 1;
601cd21b334SDaniel Scheller int i;
602cd21b334SDaniel Scheller s32 reg_diff;
603cd21b334SDaniel Scheller
604cd21b334SDaniel Scheller /* Assumes Table[0].RegValue > Table[imax].RegValue */
605ddb6a90dSDaniel Scheller if (reg_value >= table[0].reg_value) {
606cd21b334SDaniel Scheller value = table[0].value;
607ddb6a90dSDaniel Scheller } else if (reg_value <= table[imax].reg_value) {
608cd21b334SDaniel Scheller value = table[imax].value;
609ddb6a90dSDaniel Scheller } else {
610ddb6a90dSDaniel Scheller while ((imax - imin) > 1) {
611cd21b334SDaniel Scheller i = (imax + imin) / 2;
612cd21b334SDaniel Scheller if ((table[imin].reg_value >= reg_value) &&
613cd21b334SDaniel Scheller (reg_value >= table[i].reg_value))
614cd21b334SDaniel Scheller imax = i;
615cd21b334SDaniel Scheller else
616cd21b334SDaniel Scheller imin = i;
617cd21b334SDaniel Scheller }
618cd21b334SDaniel Scheller
619cd21b334SDaniel Scheller reg_diff = table[imax].reg_value - table[imin].reg_value;
620cd21b334SDaniel Scheller value = table[imin].value;
621cd21b334SDaniel Scheller if (reg_diff != 0)
622cd21b334SDaniel Scheller value += ((s32)(reg_value - table[imin].reg_value) *
623cd21b334SDaniel Scheller (s32)(table[imax].value
624cd21b334SDaniel Scheller - table[imin].value))
625cd21b334SDaniel Scheller / (reg_diff);
626cd21b334SDaniel Scheller }
627cd21b334SDaniel Scheller
628cd21b334SDaniel Scheller return value;
629cd21b334SDaniel Scheller }
630cd21b334SDaniel Scheller
get_signal_to_noise(struct stv * state,s32 * signal_to_noise)631cd21b334SDaniel Scheller static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
632cd21b334SDaniel Scheller {
633cd21b334SDaniel Scheller u8 data0;
634cd21b334SDaniel Scheller u8 data1;
635cd21b334SDaniel Scheller u16 data;
636cd21b334SDaniel Scheller int n_lookup;
63720e671dfSDaniel Scheller const struct slookup *lookup;
638cd21b334SDaniel Scheller
639cd21b334SDaniel Scheller *signal_to_noise = 0;
640cd21b334SDaniel Scheller
641cd21b334SDaniel Scheller if (!state->started)
642cd21b334SDaniel Scheller return -EINVAL;
643cd21b334SDaniel Scheller
644cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS2) {
645cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
646cd21b334SDaniel Scheller &data1);
647cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
648cd21b334SDaniel Scheller &data0);
649cd21b334SDaniel Scheller n_lookup = ARRAY_SIZE(s2_sn_lookup);
650cd21b334SDaniel Scheller lookup = s2_sn_lookup;
651cd21b334SDaniel Scheller } else {
652cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
653cd21b334SDaniel Scheller &data1);
654cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
655cd21b334SDaniel Scheller &data0);
656cd21b334SDaniel Scheller n_lookup = ARRAY_SIZE(s1_sn_lookup);
657cd21b334SDaniel Scheller lookup = s1_sn_lookup;
658cd21b334SDaniel Scheller }
659cd21b334SDaniel Scheller data = (((u16)data1) << 8) | (u16)data0;
660cd21b334SDaniel Scheller *signal_to_noise = table_lookup(lookup, n_lookup, data);
661cd21b334SDaniel Scheller return 0;
662cd21b334SDaniel Scheller }
663cd21b334SDaniel Scheller
get_bit_error_rate_s(struct stv * state,u32 * bernumerator,u32 * berdenominator)664cd21b334SDaniel Scheller static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
665cd21b334SDaniel Scheller u32 *berdenominator)
666cd21b334SDaniel Scheller {
667cd21b334SDaniel Scheller u8 regs[3];
668cd21b334SDaniel Scheller
669cd21b334SDaniel Scheller int status = read_regs(state,
670cd21b334SDaniel Scheller RSTV0910_P2_ERRCNT12 + state->regoff,
671cd21b334SDaniel Scheller regs, 3);
672cd21b334SDaniel Scheller
673cd21b334SDaniel Scheller if (status)
674cd21b334SDaniel Scheller return -EINVAL;
675cd21b334SDaniel Scheller
676cd21b334SDaniel Scheller if ((regs[0] & 0x80) == 0) {
677f9dc3af8SDaniel Scheller state->last_berdenominator = 1ULL << ((state->berscale * 2) +
678cd21b334SDaniel Scheller 10 + 3);
679cd21b334SDaniel Scheller state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
680cd21b334SDaniel Scheller ((u32)regs[1] << 8) | regs[2];
681cd21b334SDaniel Scheller if (state->last_bernumerator < 256 && state->berscale < 6) {
682cd21b334SDaniel Scheller state->berscale += 1;
683cd21b334SDaniel Scheller status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
684cd21b334SDaniel Scheller state->regoff,
685cd21b334SDaniel Scheller 0x20 | state->berscale);
686cd21b334SDaniel Scheller } else if (state->last_bernumerator > 1024 &&
687cd21b334SDaniel Scheller state->berscale > 2) {
688cd21b334SDaniel Scheller state->berscale -= 1;
689cd21b334SDaniel Scheller status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
690cd21b334SDaniel Scheller state->regoff, 0x20 |
691cd21b334SDaniel Scheller state->berscale);
692cd21b334SDaniel Scheller }
693cd21b334SDaniel Scheller }
694cd21b334SDaniel Scheller *bernumerator = state->last_bernumerator;
695cd21b334SDaniel Scheller *berdenominator = state->last_berdenominator;
696cd21b334SDaniel Scheller return 0;
697cd21b334SDaniel Scheller }
698cd21b334SDaniel Scheller
dvbs2_nbch(enum dvbs2_mod_cod mod_cod,enum dvbs2_fectype fectype)699cd21b334SDaniel Scheller static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
700cd21b334SDaniel Scheller {
70120e671dfSDaniel Scheller static const u32 nbch[][2] = {
70213c81489SDaniel Scheller { 0, 0}, /* DUMMY_PLF */
703cd21b334SDaniel Scheller {16200, 3240}, /* QPSK_1_4, */
704cd21b334SDaniel Scheller {21600, 5400}, /* QPSK_1_3, */
705cd21b334SDaniel Scheller {25920, 6480}, /* QPSK_2_5, */
706cd21b334SDaniel Scheller {32400, 7200}, /* QPSK_1_2, */
707cd21b334SDaniel Scheller {38880, 9720}, /* QPSK_3_5, */
708cd21b334SDaniel Scheller {43200, 10800}, /* QPSK_2_3, */
709cd21b334SDaniel Scheller {48600, 11880}, /* QPSK_3_4, */
710cd21b334SDaniel Scheller {51840, 12600}, /* QPSK_4_5, */
711cd21b334SDaniel Scheller {54000, 13320}, /* QPSK_5_6, */
712cd21b334SDaniel Scheller {57600, 14400}, /* QPSK_8_9, */
713cd21b334SDaniel Scheller {58320, 16000}, /* QPSK_9_10, */
714cd21b334SDaniel Scheller {43200, 9720}, /* 8PSK_3_5, */
715cd21b334SDaniel Scheller {48600, 10800}, /* 8PSK_2_3, */
716cd21b334SDaniel Scheller {51840, 11880}, /* 8PSK_3_4, */
717cd21b334SDaniel Scheller {54000, 13320}, /* 8PSK_5_6, */
718cd21b334SDaniel Scheller {57600, 14400}, /* 8PSK_8_9, */
719cd21b334SDaniel Scheller {58320, 16000}, /* 8PSK_9_10, */
720cd21b334SDaniel Scheller {43200, 10800}, /* 16APSK_2_3, */
721cd21b334SDaniel Scheller {48600, 11880}, /* 16APSK_3_4, */
722cd21b334SDaniel Scheller {51840, 12600}, /* 16APSK_4_5, */
723cd21b334SDaniel Scheller {54000, 13320}, /* 16APSK_5_6, */
724cd21b334SDaniel Scheller {57600, 14400}, /* 16APSK_8_9, */
725cd21b334SDaniel Scheller {58320, 16000}, /* 16APSK_9_10 */
726cd21b334SDaniel Scheller {48600, 11880}, /* 32APSK_3_4, */
727cd21b334SDaniel Scheller {51840, 12600}, /* 32APSK_4_5, */
728cd21b334SDaniel Scheller {54000, 13320}, /* 32APSK_5_6, */
729cd21b334SDaniel Scheller {57600, 14400}, /* 32APSK_8_9, */
730cd21b334SDaniel Scheller {58320, 16000}, /* 32APSK_9_10 */
731cd21b334SDaniel Scheller };
732cd21b334SDaniel Scheller
733cd21b334SDaniel Scheller if (mod_cod >= DVBS2_QPSK_1_4 &&
734cd21b334SDaniel Scheller mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
73513c81489SDaniel Scheller return nbch[mod_cod][fectype];
736cd21b334SDaniel Scheller return 64800;
737cd21b334SDaniel Scheller }
738cd21b334SDaniel Scheller
get_bit_error_rate_s2(struct stv * state,u32 * bernumerator,u32 * berdenominator)739cd21b334SDaniel Scheller static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
740cd21b334SDaniel Scheller u32 *berdenominator)
741cd21b334SDaniel Scheller {
742cd21b334SDaniel Scheller u8 regs[3];
743cd21b334SDaniel Scheller
744cd21b334SDaniel Scheller int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
745cd21b334SDaniel Scheller regs, 3);
746cd21b334SDaniel Scheller
747cd21b334SDaniel Scheller if (status)
748cd21b334SDaniel Scheller return -EINVAL;
749cd21b334SDaniel Scheller
750cd21b334SDaniel Scheller if ((regs[0] & 0x80) == 0) {
751cd21b334SDaniel Scheller state->last_berdenominator =
752cd21b334SDaniel Scheller dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
753cd21b334SDaniel Scheller state->fectype) <<
754cd21b334SDaniel Scheller (state->berscale * 2);
755cd21b334SDaniel Scheller state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
756cd21b334SDaniel Scheller ((u32)regs[1] << 8) | regs[2];
757cd21b334SDaniel Scheller if (state->last_bernumerator < 256 && state->berscale < 6) {
758cd21b334SDaniel Scheller state->berscale += 1;
759cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
760cd21b334SDaniel Scheller 0x20 | state->berscale);
761cd21b334SDaniel Scheller } else if (state->last_bernumerator > 1024 &&
762cd21b334SDaniel Scheller state->berscale > 2) {
763cd21b334SDaniel Scheller state->berscale -= 1;
764cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
765cd21b334SDaniel Scheller 0x20 | state->berscale);
766cd21b334SDaniel Scheller }
767cd21b334SDaniel Scheller }
768cd21b334SDaniel Scheller *bernumerator = state->last_bernumerator;
769cd21b334SDaniel Scheller *berdenominator = state->last_berdenominator;
770cd21b334SDaniel Scheller return status;
771cd21b334SDaniel Scheller }
772cd21b334SDaniel Scheller
get_bit_error_rate(struct stv * state,u32 * bernumerator,u32 * berdenominator)773cd21b334SDaniel Scheller static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
774cd21b334SDaniel Scheller u32 *berdenominator)
775cd21b334SDaniel Scheller {
776cd21b334SDaniel Scheller *bernumerator = 0;
777cd21b334SDaniel Scheller *berdenominator = 1;
778cd21b334SDaniel Scheller
779cd21b334SDaniel Scheller switch (state->receive_mode) {
780cd21b334SDaniel Scheller case RCVMODE_DVBS:
781cd21b334SDaniel Scheller return get_bit_error_rate_s(state,
782cd21b334SDaniel Scheller bernumerator, berdenominator);
783cd21b334SDaniel Scheller case RCVMODE_DVBS2:
784cd21b334SDaniel Scheller return get_bit_error_rate_s2(state,
785cd21b334SDaniel Scheller bernumerator, berdenominator);
786cd21b334SDaniel Scheller default:
787cd21b334SDaniel Scheller break;
788cd21b334SDaniel Scheller }
789cd21b334SDaniel Scheller return 0;
790cd21b334SDaniel Scheller }
791cd21b334SDaniel Scheller
set_mclock(struct stv * state,u32 master_clock)792cd21b334SDaniel Scheller static int set_mclock(struct stv *state, u32 master_clock)
793cd21b334SDaniel Scheller {
794cd21b334SDaniel Scheller u32 idf = 1;
795cd21b334SDaniel Scheller u32 odf = 4;
796cd21b334SDaniel Scheller u32 quartz = state->base->extclk / 1000000;
797cd21b334SDaniel Scheller u32 fphi = master_clock / 1000000;
798cd21b334SDaniel Scheller u32 ndiv = (fphi * odf * idf) / quartz;
799cd21b334SDaniel Scheller u32 cp = 7;
800cd21b334SDaniel Scheller u32 fvco;
801cd21b334SDaniel Scheller
802cd21b334SDaniel Scheller if (ndiv >= 7 && ndiv <= 71)
803cd21b334SDaniel Scheller cp = 7;
804cd21b334SDaniel Scheller else if (ndiv >= 72 && ndiv <= 79)
805cd21b334SDaniel Scheller cp = 8;
806cd21b334SDaniel Scheller else if (ndiv >= 80 && ndiv <= 87)
807cd21b334SDaniel Scheller cp = 9;
808cd21b334SDaniel Scheller else if (ndiv >= 88 && ndiv <= 95)
809cd21b334SDaniel Scheller cp = 10;
810cd21b334SDaniel Scheller else if (ndiv >= 96 && ndiv <= 103)
811cd21b334SDaniel Scheller cp = 11;
812cd21b334SDaniel Scheller else if (ndiv >= 104 && ndiv <= 111)
813cd21b334SDaniel Scheller cp = 12;
814cd21b334SDaniel Scheller else if (ndiv >= 112 && ndiv <= 119)
815cd21b334SDaniel Scheller cp = 13;
816cd21b334SDaniel Scheller else if (ndiv >= 120 && ndiv <= 127)
817cd21b334SDaniel Scheller cp = 14;
818cd21b334SDaniel Scheller else if (ndiv >= 128 && ndiv <= 135)
819cd21b334SDaniel Scheller cp = 15;
820cd21b334SDaniel Scheller else if (ndiv >= 136 && ndiv <= 143)
821cd21b334SDaniel Scheller cp = 16;
822cd21b334SDaniel Scheller else if (ndiv >= 144 && ndiv <= 151)
823cd21b334SDaniel Scheller cp = 17;
824cd21b334SDaniel Scheller else if (ndiv >= 152 && ndiv <= 159)
825cd21b334SDaniel Scheller cp = 18;
826cd21b334SDaniel Scheller else if (ndiv >= 160 && ndiv <= 167)
827cd21b334SDaniel Scheller cp = 19;
828cd21b334SDaniel Scheller else if (ndiv >= 168 && ndiv <= 175)
829cd21b334SDaniel Scheller cp = 20;
830cd21b334SDaniel Scheller else if (ndiv >= 176 && ndiv <= 183)
831cd21b334SDaniel Scheller cp = 21;
832cd21b334SDaniel Scheller else if (ndiv >= 184 && ndiv <= 191)
833cd21b334SDaniel Scheller cp = 22;
834cd21b334SDaniel Scheller else if (ndiv >= 192 && ndiv <= 199)
835cd21b334SDaniel Scheller cp = 23;
836cd21b334SDaniel Scheller else if (ndiv >= 200 && ndiv <= 207)
837cd21b334SDaniel Scheller cp = 24;
838cd21b334SDaniel Scheller else if (ndiv >= 208 && ndiv <= 215)
839cd21b334SDaniel Scheller cp = 25;
840cd21b334SDaniel Scheller else if (ndiv >= 216 && ndiv <= 223)
841cd21b334SDaniel Scheller cp = 26;
842cd21b334SDaniel Scheller else if (ndiv >= 224 && ndiv <= 225)
843cd21b334SDaniel Scheller cp = 27;
844cd21b334SDaniel Scheller
845cd21b334SDaniel Scheller write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
846cd21b334SDaniel Scheller write_reg(state, RSTV0910_NCOARSE2, odf);
847cd21b334SDaniel Scheller write_reg(state, RSTV0910_NCOARSE1, ndiv);
848cd21b334SDaniel Scheller
849cd21b334SDaniel Scheller fvco = (quartz * 2 * ndiv) / idf;
850cd21b334SDaniel Scheller state->base->mclk = fvco / (2 * odf) * 1000000;
851cd21b334SDaniel Scheller
852cd21b334SDaniel Scheller return 0;
853cd21b334SDaniel Scheller }
854cd21b334SDaniel Scheller
stop(struct stv * state)855cd21b334SDaniel Scheller static int stop(struct stv *state)
856cd21b334SDaniel Scheller {
857cd21b334SDaniel Scheller if (state->started) {
858cd21b334SDaniel Scheller u8 tmp;
859cd21b334SDaniel Scheller
860cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
861cd21b334SDaniel Scheller state->tscfgh | 0x01);
862cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
863cd21b334SDaniel Scheller tmp &= ~0x01; /* release reset DVBS2 packet delin */
864cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
865cd21b334SDaniel Scheller /* Blind optim*/
866cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
867cd21b334SDaniel Scheller /* Stop the demod */
868cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
869cd21b334SDaniel Scheller state->started = 0;
870cd21b334SDaniel Scheller }
871cd21b334SDaniel Scheller state->receive_mode = RCVMODE_NONE;
872cd21b334SDaniel Scheller return 0;
873cd21b334SDaniel Scheller }
874cd21b334SDaniel Scheller
set_pls(struct stv * state,u32 pls_code)8756392bc2eSDaniel Scheller static void set_pls(struct stv *state, u32 pls_code)
876cd21b334SDaniel Scheller {
8776392bc2eSDaniel Scheller if (pls_code == state->cur_scrambling_code)
8786392bc2eSDaniel Scheller return;
879cd21b334SDaniel Scheller
8806392bc2eSDaniel Scheller /* PLROOT2 bit 2 = gold code */
8816392bc2eSDaniel Scheller write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
8826392bc2eSDaniel Scheller pls_code & 0xff);
8836392bc2eSDaniel Scheller write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
8846392bc2eSDaniel Scheller (pls_code >> 8) & 0xff);
8856392bc2eSDaniel Scheller write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
8866392bc2eSDaniel Scheller 0x04 | ((pls_code >> 16) & 0x03));
8876392bc2eSDaniel Scheller state->cur_scrambling_code = pls_code;
8886392bc2eSDaniel Scheller }
889cd21b334SDaniel Scheller
set_isi(struct stv * state,u32 isi)8906392bc2eSDaniel Scheller static void set_isi(struct stv *state, u32 isi)
8916392bc2eSDaniel Scheller {
8926392bc2eSDaniel Scheller if (isi == NO_STREAM_ID_FILTER)
8936392bc2eSDaniel Scheller return;
8946392bc2eSDaniel Scheller if (isi == 0x80000000) {
8956392bc2eSDaniel Scheller SET_FIELD(FORCE_CONTINUOUS, 1);
8966392bc2eSDaniel Scheller SET_FIELD(TSOUT_NOSYNC, 1);
8976392bc2eSDaniel Scheller } else {
8986392bc2eSDaniel Scheller SET_FIELD(FILTER_EN, 1);
8996392bc2eSDaniel Scheller write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
9006392bc2eSDaniel Scheller isi & 0xff);
9016392bc2eSDaniel Scheller write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
9026392bc2eSDaniel Scheller }
9036392bc2eSDaniel Scheller SET_FIELD(ALGOSWRST, 1);
9046392bc2eSDaniel Scheller SET_FIELD(ALGOSWRST, 0);
9056392bc2eSDaniel Scheller }
906cd21b334SDaniel Scheller
set_stream_modes(struct stv * state,struct dtv_frontend_properties * p)9076392bc2eSDaniel Scheller static void set_stream_modes(struct stv *state,
9086392bc2eSDaniel Scheller struct dtv_frontend_properties *p)
9096392bc2eSDaniel Scheller {
9106392bc2eSDaniel Scheller set_isi(state, p->stream_id);
9116392bc2eSDaniel Scheller set_pls(state, p->scrambling_sequence_index);
9126392bc2eSDaniel Scheller }
913cd21b334SDaniel Scheller
init_search_param(struct stv * state,struct dtv_frontend_properties * p)9146392bc2eSDaniel Scheller static int init_search_param(struct stv *state,
9156392bc2eSDaniel Scheller struct dtv_frontend_properties *p)
9166392bc2eSDaniel Scheller {
9176392bc2eSDaniel Scheller SET_FIELD(FORCE_CONTINUOUS, 0);
9186392bc2eSDaniel Scheller SET_FIELD(FRAME_MODE, 0);
9196392bc2eSDaniel Scheller SET_FIELD(FILTER_EN, 0);
9206392bc2eSDaniel Scheller SET_FIELD(TSOUT_NOSYNC, 0);
9216392bc2eSDaniel Scheller SET_FIELD(TSFIFO_EMBINDVB, 0);
9226392bc2eSDaniel Scheller SET_FIELD(TSDEL_SYNCBYTE, 0);
9236392bc2eSDaniel Scheller SET_REG(UPLCCST0, 0xe0);
9246392bc2eSDaniel Scheller SET_FIELD(TSINS_TOKEN, 0);
9256392bc2eSDaniel Scheller SET_FIELD(HYSTERESIS_THRESHOLD, 0);
9266392bc2eSDaniel Scheller SET_FIELD(ISIOBS_MODE, 1);
927cd21b334SDaniel Scheller
9286392bc2eSDaniel Scheller set_stream_modes(state, p);
929cd21b334SDaniel Scheller return 0;
930cd21b334SDaniel Scheller }
931cd21b334SDaniel Scheller
enable_puncture_rate(struct stv * state,enum fe_code_rate rate)932cd21b334SDaniel Scheller static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
933cd21b334SDaniel Scheller {
9344b596bd7SDaniel Scheller u8 val;
9354b596bd7SDaniel Scheller
936cd21b334SDaniel Scheller switch (rate) {
937cd21b334SDaniel Scheller case FEC_1_2:
9384b596bd7SDaniel Scheller val = 0x01;
9394b596bd7SDaniel Scheller break;
940cd21b334SDaniel Scheller case FEC_2_3:
9414b596bd7SDaniel Scheller val = 0x02;
9424b596bd7SDaniel Scheller break;
943cd21b334SDaniel Scheller case FEC_3_4:
9444b596bd7SDaniel Scheller val = 0x04;
9454b596bd7SDaniel Scheller break;
946cd21b334SDaniel Scheller case FEC_5_6:
9474b596bd7SDaniel Scheller val = 0x08;
9484b596bd7SDaniel Scheller break;
949cd21b334SDaniel Scheller case FEC_7_8:
9504b596bd7SDaniel Scheller val = 0x20;
9514b596bd7SDaniel Scheller break;
952cd21b334SDaniel Scheller case FEC_NONE:
953cd21b334SDaniel Scheller default:
9544b596bd7SDaniel Scheller val = 0x2f;
9554b596bd7SDaniel Scheller break;
956cd21b334SDaniel Scheller }
9574b596bd7SDaniel Scheller
9584b596bd7SDaniel Scheller return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
959cd21b334SDaniel Scheller }
960cd21b334SDaniel Scheller
set_vth_default(struct stv * state)961cd21b334SDaniel Scheller static int set_vth_default(struct stv *state)
962cd21b334SDaniel Scheller {
963cd21b334SDaniel Scheller state->vth[0] = 0xd7;
964cd21b334SDaniel Scheller state->vth[1] = 0x85;
965cd21b334SDaniel Scheller state->vth[2] = 0x58;
966cd21b334SDaniel Scheller state->vth[3] = 0x3a;
967cd21b334SDaniel Scheller state->vth[4] = 0x34;
968cd21b334SDaniel Scheller state->vth[5] = 0x28;
969cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
970cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
971cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
972cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
973cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
974cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
975cd21b334SDaniel Scheller return 0;
976cd21b334SDaniel Scheller }
977cd21b334SDaniel Scheller
set_vth(struct stv * state)978cd21b334SDaniel Scheller static int set_vth(struct stv *state)
979cd21b334SDaniel Scheller {
98020e671dfSDaniel Scheller static const struct slookup vthlookup_table[] = {
981cd21b334SDaniel Scheller {250, 8780}, /* C/N= 1.5dB */
982cd21b334SDaniel Scheller {100, 7405}, /* C/N= 4.5dB */
983cd21b334SDaniel Scheller {40, 6330}, /* C/N= 6.5dB */
984cd21b334SDaniel Scheller {12, 5224}, /* C/N= 8.5dB */
985cd21b334SDaniel Scheller {5, 4236} /* C/N=10.5dB */
986cd21b334SDaniel Scheller };
987cd21b334SDaniel Scheller
988cd21b334SDaniel Scheller int i;
989cd21b334SDaniel Scheller u8 tmp[2];
990cd21b334SDaniel Scheller int status = read_regs(state,
991cd21b334SDaniel Scheller RSTV0910_P2_NNOSDATAT1 + state->regoff,
992cd21b334SDaniel Scheller tmp, 2);
993cd21b334SDaniel Scheller u16 reg_value = (tmp[0] << 8) | tmp[1];
994cd21b334SDaniel Scheller s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
995cd21b334SDaniel Scheller reg_value);
996cd21b334SDaniel Scheller
997cd21b334SDaniel Scheller for (i = 0; i < 6; i += 1)
998cd21b334SDaniel Scheller if (state->vth[i] > vth)
999cd21b334SDaniel Scheller state->vth[i] = vth;
1000cd21b334SDaniel Scheller
1001cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1002cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1003cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1004cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1005cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1006cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1007cd21b334SDaniel Scheller return status;
1008cd21b334SDaniel Scheller }
1009cd21b334SDaniel Scheller
start(struct stv * state,struct dtv_frontend_properties * p)1010cd21b334SDaniel Scheller static int start(struct stv *state, struct dtv_frontend_properties *p)
1011cd21b334SDaniel Scheller {
1012cd21b334SDaniel Scheller s32 freq;
1013cd21b334SDaniel Scheller u8 reg_dmdcfgmd;
1014cd21b334SDaniel Scheller u16 symb;
1015cd21b334SDaniel Scheller
1016cd21b334SDaniel Scheller if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
1017cd21b334SDaniel Scheller return -EINVAL;
1018cd21b334SDaniel Scheller
1019cd21b334SDaniel Scheller state->receive_mode = RCVMODE_NONE;
1020cd21b334SDaniel Scheller state->demod_lock_time = 0;
1021cd21b334SDaniel Scheller
1022cd21b334SDaniel Scheller /* Demod Stop */
1023cd21b334SDaniel Scheller if (state->started)
1024cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1025cd21b334SDaniel Scheller
10266392bc2eSDaniel Scheller init_search_param(state, p);
1027ea71c62bSDaniel Scheller
1028cd21b334SDaniel Scheller if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
1029cd21b334SDaniel Scheller state->demod_timeout = 3000;
1030cd21b334SDaniel Scheller state->fec_timeout = 2000;
1031cd21b334SDaniel Scheller } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
1032cd21b334SDaniel Scheller state->demod_timeout = 2500;
1033cd21b334SDaniel Scheller state->fec_timeout = 1300;
1034cd21b334SDaniel Scheller } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
1035cd21b334SDaniel Scheller state->demod_timeout = 1000;
1036cd21b334SDaniel Scheller state->fec_timeout = 650;
1037cd21b334SDaniel Scheller } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
1038cd21b334SDaniel Scheller state->demod_timeout = 700;
1039cd21b334SDaniel Scheller state->fec_timeout = 350;
1040cd21b334SDaniel Scheller } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
1041cd21b334SDaniel Scheller state->demod_timeout = 400;
1042cd21b334SDaniel Scheller state->fec_timeout = 200;
1043cd21b334SDaniel Scheller } else { /* SR >=20Msps */
1044cd21b334SDaniel Scheller state->demod_timeout = 300;
1045cd21b334SDaniel Scheller state->fec_timeout = 200;
1046cd21b334SDaniel Scheller }
1047cd21b334SDaniel Scheller
1048cd21b334SDaniel Scheller /* Set the Init Symbol rate */
1049cd21b334SDaniel Scheller symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1050cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1051cd21b334SDaniel Scheller ((symb >> 8) & 0x7F));
1052cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1053cd21b334SDaniel Scheller
1054cd21b334SDaniel Scheller state->demod_bits |= 0x80;
1055cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1056cd21b334SDaniel Scheller
1057cd21b334SDaniel Scheller /* FE_STV0910_SetSearchStandard */
1058cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd);
1059cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1060cd21b334SDaniel Scheller reg_dmdcfgmd |= 0xC0);
1061cd21b334SDaniel Scheller
1062cd21b334SDaniel Scheller write_shared_reg(state,
1063cd21b334SDaniel Scheller RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1064cd21b334SDaniel Scheller
1065cd21b334SDaniel Scheller /* Disable DSS */
1066cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
1067cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1068cd21b334SDaniel Scheller
1069cd21b334SDaniel Scheller enable_puncture_rate(state, FEC_NONE);
1070cd21b334SDaniel Scheller
1071cd21b334SDaniel Scheller /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
1072cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1073cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1074cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1075cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1076cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1077cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1078cd21b334SDaniel Scheller
1079cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1080cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1081cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1082cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1083cd21b334SDaniel Scheller
10844f979d5cSDaniel Scheller /*
10854f979d5cSDaniel Scheller * Reset CAR3, bug DVBS2->DVBS1 lock
10864f979d5cSDaniel Scheller * Note: The bit is only pulsed -> no lock on shared register needed
10874f979d5cSDaniel Scheller */
1088cd21b334SDaniel Scheller write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1089cd21b334SDaniel Scheller write_reg(state, RSTV0910_TSTRES0, 0);
1090cd21b334SDaniel Scheller
1091cd21b334SDaniel Scheller set_vth_default(state);
1092cd21b334SDaniel Scheller /* Reset demod */
1093cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1094cd21b334SDaniel Scheller
1095cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1096cd21b334SDaniel Scheller
1097cd21b334SDaniel Scheller if (p->symbol_rate <= 5000000)
1098cd21b334SDaniel Scheller freq = (state->search_range / 2000) + 80;
1099cd21b334SDaniel Scheller else
1100cd21b334SDaniel Scheller freq = (state->search_range / 2000) + 1600;
1101cd21b334SDaniel Scheller freq = (freq << 16) / (state->base->mclk / 1000);
1102cd21b334SDaniel Scheller
1103cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1104cd21b334SDaniel Scheller (freq >> 8) & 0xff);
1105cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1106cd21b334SDaniel Scheller /* CFR Low Setting */
1107cd21b334SDaniel Scheller freq = -freq;
1108cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1109cd21b334SDaniel Scheller (freq >> 8) & 0xff);
1110cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1111cd21b334SDaniel Scheller
1112cd21b334SDaniel Scheller /* init the demod frequency offset to 0 */
1113cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1114cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1115cd21b334SDaniel Scheller
1116cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1117cd21b334SDaniel Scheller /* Trigger acq */
1118cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1119cd21b334SDaniel Scheller
1120cd21b334SDaniel Scheller state->demod_lock_time += TUNING_DELAY;
1121cd21b334SDaniel Scheller state->started = 1;
1122cd21b334SDaniel Scheller
1123cd21b334SDaniel Scheller return 0;
1124cd21b334SDaniel Scheller }
1125cd21b334SDaniel Scheller
init_diseqc(struct stv * state)1126cd21b334SDaniel Scheller static int init_diseqc(struct stv *state)
1127cd21b334SDaniel Scheller {
1128cd21b334SDaniel Scheller u16 offs = state->nr ? 0x40 : 0; /* Address offset */
1129cd21b334SDaniel Scheller u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1130cd21b334SDaniel Scheller
1131cd21b334SDaniel Scheller /* Disable receiver */
1132cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1133cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1134cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1135cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1136cd21b334SDaniel Scheller return 0;
1137cd21b334SDaniel Scheller }
1138cd21b334SDaniel Scheller
probe(struct stv * state)1139cd21b334SDaniel Scheller static int probe(struct stv *state)
1140cd21b334SDaniel Scheller {
1141cd21b334SDaniel Scheller u8 id;
1142cd21b334SDaniel Scheller
1143cd21b334SDaniel Scheller state->receive_mode = RCVMODE_NONE;
1144cd21b334SDaniel Scheller state->started = 0;
1145cd21b334SDaniel Scheller
1146cd21b334SDaniel Scheller if (read_reg(state, RSTV0910_MID, &id) < 0)
1147cd21b334SDaniel Scheller return -ENODEV;
1148cd21b334SDaniel Scheller
1149cd21b334SDaniel Scheller if (id != 0x51)
1150cd21b334SDaniel Scheller return -EINVAL;
1151cd21b334SDaniel Scheller
1152cd21b334SDaniel Scheller /* Configure the I2C repeater to off */
1153cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1154cd21b334SDaniel Scheller /* Configure the I2C repeater to off */
1155cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1156cd21b334SDaniel Scheller /* Set the I2C to oversampling ratio */
1157cd21b334SDaniel Scheller write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1158cd21b334SDaniel Scheller
1159cd21b334SDaniel Scheller write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
1160cd21b334SDaniel Scheller write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
1161cd21b334SDaniel Scheller write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
1162cd21b334SDaniel Scheller write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1163cd21b334SDaniel Scheller write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
1164cd21b334SDaniel Scheller
1165cd21b334SDaniel Scheller if (state->single)
1166cd21b334SDaniel Scheller write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1167cd21b334SDaniel Scheller else
1168cd21b334SDaniel Scheller write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1169cd21b334SDaniel Scheller
1170cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1171cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1172cd21b334SDaniel Scheller
1173cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1174cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1175cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1176cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1177cd21b334SDaniel Scheller
1178cd21b334SDaniel Scheller write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1179cd21b334SDaniel Scheller write_reg(state, RSTV0910_TSTRES0, 0x00);
1180cd21b334SDaniel Scheller
1181cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1182cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1183cd21b334SDaniel Scheller
1184cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1185cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1186cd21b334SDaniel Scheller
1187cd21b334SDaniel Scheller set_mclock(state, 135000000);
1188cd21b334SDaniel Scheller
1189cd21b334SDaniel Scheller /* TS output */
1190cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1191cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1192cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1193cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1194cd21b334SDaniel Scheller
1195cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1196cd21b334SDaniel Scheller
1197cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1198cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1199cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1200cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1201cd21b334SDaniel Scheller
1202cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1203cd21b334SDaniel Scheller
1204cd21b334SDaniel Scheller /* Reset stream merger */
1205cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1206cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1207cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1208cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1209cd21b334SDaniel Scheller
1210cd21b334SDaniel Scheller write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1211cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1212cd21b334SDaniel Scheller
1213e2c53c8dSDaniel Scheller write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
1214e2c53c8dSDaniel Scheller write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
1215e2c53c8dSDaniel Scheller
1216e2c53c8dSDaniel Scheller write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
1217e2c53c8dSDaniel Scheller write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
1218e2c53c8dSDaniel Scheller
1219cd21b334SDaniel Scheller init_diseqc(state);
1220cd21b334SDaniel Scheller return 0;
1221cd21b334SDaniel Scheller }
1222cd21b334SDaniel Scheller
gate_ctrl(struct dvb_frontend * fe,int enable)1223cd21b334SDaniel Scheller static int gate_ctrl(struct dvb_frontend *fe, int enable)
1224cd21b334SDaniel Scheller {
1225cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1226cd21b334SDaniel Scheller u8 i2crpt = state->i2crpt & ~0x86;
1227cd21b334SDaniel Scheller
12286b852620SDaniel Scheller /*
12296b852620SDaniel Scheller * mutex_lock note: Concurrent I2C gate bus accesses must be
12306b852620SDaniel Scheller * prevented (STV0910 = dual demod on a single IC with a single I2C
12316b852620SDaniel Scheller * gate/bus, and two tuners attached), similar to most (if not all)
1232868c9a17SMauro Carvalho Chehab * other I2C host interfaces/buses.
12336b852620SDaniel Scheller *
12346b852620SDaniel Scheller * enable=1 (open I2C gate) will grab the lock
12356b852620SDaniel Scheller * enable=0 (close I2C gate) releases the lock
12366b852620SDaniel Scheller */
1237cd21b334SDaniel Scheller
12386b852620SDaniel Scheller if (enable) {
12396b852620SDaniel Scheller mutex_lock(&state->base->i2c_lock);
1240cd21b334SDaniel Scheller i2crpt |= 0x80;
12416b852620SDaniel Scheller } else {
1242cd21b334SDaniel Scheller i2crpt |= 0x02;
12436b852620SDaniel Scheller }
1244cd21b334SDaniel Scheller
1245cd21b334SDaniel Scheller if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
12466b852620SDaniel Scheller RSTV0910_P1_I2CRPT, i2crpt) < 0) {
12476b852620SDaniel Scheller /* don't hold the I2C bus lock on failure */
1248aea16005SDaniel Scheller if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
12496b852620SDaniel Scheller mutex_unlock(&state->base->i2c_lock);
12506b852620SDaniel Scheller dev_err(&state->base->i2c->dev,
12516b852620SDaniel Scheller "%s() write_reg failure (enable=%d)\n",
12526b852620SDaniel Scheller __func__, enable);
1253cd21b334SDaniel Scheller return -EIO;
12546b852620SDaniel Scheller }
1255cd21b334SDaniel Scheller
1256cd21b334SDaniel Scheller state->i2crpt = i2crpt;
1257cd21b334SDaniel Scheller
1258cd21b334SDaniel Scheller if (!enable)
1259aea16005SDaniel Scheller if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1260cd21b334SDaniel Scheller mutex_unlock(&state->base->i2c_lock);
1261cd21b334SDaniel Scheller return 0;
1262cd21b334SDaniel Scheller }
1263cd21b334SDaniel Scheller
release(struct dvb_frontend * fe)1264cd21b334SDaniel Scheller static void release(struct dvb_frontend *fe)
1265cd21b334SDaniel Scheller {
1266cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1267cd21b334SDaniel Scheller
1268cd21b334SDaniel Scheller state->base->count--;
1269cd21b334SDaniel Scheller if (state->base->count == 0) {
1270cd21b334SDaniel Scheller list_del(&state->base->stvlist);
1271cd21b334SDaniel Scheller kfree(state->base);
1272cd21b334SDaniel Scheller }
1273cd21b334SDaniel Scheller kfree(state);
1274cd21b334SDaniel Scheller }
1275cd21b334SDaniel Scheller
set_parameters(struct dvb_frontend * fe)1276cd21b334SDaniel Scheller static int set_parameters(struct dvb_frontend *fe)
1277cd21b334SDaniel Scheller {
1278cd21b334SDaniel Scheller int stat = 0;
1279cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1280cd21b334SDaniel Scheller struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1281cd21b334SDaniel Scheller
1282cd21b334SDaniel Scheller stop(state);
1283cd21b334SDaniel Scheller if (fe->ops.tuner_ops.set_params)
1284cd21b334SDaniel Scheller fe->ops.tuner_ops.set_params(fe);
1285cd21b334SDaniel Scheller state->symbol_rate = p->symbol_rate;
1286cd21b334SDaniel Scheller stat = start(state, p);
1287cd21b334SDaniel Scheller return stat;
1288cd21b334SDaniel Scheller }
1289cd21b334SDaniel Scheller
manage_matype_info(struct stv * state)1290cd21b334SDaniel Scheller static int manage_matype_info(struct stv *state)
1291cd21b334SDaniel Scheller {
1292cd21b334SDaniel Scheller if (!state->started)
1293cd21b334SDaniel Scheller return -EINVAL;
1294cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS2) {
1295cd21b334SDaniel Scheller u8 bbheader[2];
1296cd21b334SDaniel Scheller
1297cd21b334SDaniel Scheller read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
1298cd21b334SDaniel Scheller bbheader, 2);
1299cd21b334SDaniel Scheller state->feroll_off =
1300cd21b334SDaniel Scheller (enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
1301cd21b334SDaniel Scheller state->is_vcm = (bbheader[0] & 0x10) == 0;
1302cd21b334SDaniel Scheller state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1303cd21b334SDaniel Scheller } else if (state->receive_mode == RCVMODE_DVBS) {
1304cd21b334SDaniel Scheller state->is_vcm = 0;
1305cd21b334SDaniel Scheller state->is_standard_broadcast = 1;
1306cd21b334SDaniel Scheller state->feroll_off = FE_SAT_35;
1307cd21b334SDaniel Scheller }
1308cd21b334SDaniel Scheller return 0;
1309cd21b334SDaniel Scheller }
1310cd21b334SDaniel Scheller
read_snr(struct dvb_frontend * fe)1311cd21b334SDaniel Scheller static int read_snr(struct dvb_frontend *fe)
1312cd21b334SDaniel Scheller {
1313cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1314cd21b334SDaniel Scheller struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1315cd21b334SDaniel Scheller s32 snrval;
1316cd21b334SDaniel Scheller
1317cd21b334SDaniel Scheller if (!get_signal_to_noise(state, &snrval)) {
1318cd21b334SDaniel Scheller p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1319cea6d239SDaniel Scheller p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */
1320ddb6a90dSDaniel Scheller } else {
1321cd21b334SDaniel Scheller p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1322ddb6a90dSDaniel Scheller }
1323cd21b334SDaniel Scheller
1324cd21b334SDaniel Scheller return 0;
1325cd21b334SDaniel Scheller }
1326cd21b334SDaniel Scheller
read_ber(struct dvb_frontend * fe)1327cd21b334SDaniel Scheller static int read_ber(struct dvb_frontend *fe)
1328cd21b334SDaniel Scheller {
1329cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1330cd21b334SDaniel Scheller struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1331cd21b334SDaniel Scheller u32 n, d;
1332cd21b334SDaniel Scheller
1333cd21b334SDaniel Scheller get_bit_error_rate(state, &n, &d);
1334cd21b334SDaniel Scheller
1335cd21b334SDaniel Scheller p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1336cd21b334SDaniel Scheller p->pre_bit_error.stat[0].uvalue = n;
1337cd21b334SDaniel Scheller p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1338cd21b334SDaniel Scheller p->pre_bit_count.stat[0].uvalue = d;
1339cd21b334SDaniel Scheller
1340cd21b334SDaniel Scheller return 0;
1341cd21b334SDaniel Scheller }
1342cd21b334SDaniel Scheller
read_signal_strength(struct dvb_frontend * fe)1343cd21b334SDaniel Scheller static void read_signal_strength(struct dvb_frontend *fe)
1344cd21b334SDaniel Scheller {
1345cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1346cd21b334SDaniel Scheller struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
134719bb3b71SDaniel Scheller u8 reg[2];
134819bb3b71SDaniel Scheller u16 agc;
134919bb3b71SDaniel Scheller s32 padc, power = 0;
135019bb3b71SDaniel Scheller int i;
1351cd21b334SDaniel Scheller
135219bb3b71SDaniel Scheller read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
135319bb3b71SDaniel Scheller
135419bb3b71SDaniel Scheller agc = (((u32)reg[0]) << 8) | reg[1];
135519bb3b71SDaniel Scheller
135619bb3b71SDaniel Scheller for (i = 0; i < 5; i += 1) {
135719bb3b71SDaniel Scheller read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
135819bb3b71SDaniel Scheller power += (u32)reg[0] * (u32)reg[0]
135919bb3b71SDaniel Scheller + (u32)reg[1] * (u32)reg[1];
136019bb3b71SDaniel Scheller usleep_range(3000, 4000);
136119bb3b71SDaniel Scheller }
136219bb3b71SDaniel Scheller power /= 5;
136319bb3b71SDaniel Scheller
136419bb3b71SDaniel Scheller padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
136519bb3b71SDaniel Scheller
136619bb3b71SDaniel Scheller p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1367399196edSDaniel Scheller p->strength.stat[0].svalue = (padc - agc);
1368cd21b334SDaniel Scheller }
1369cd21b334SDaniel Scheller
read_status(struct dvb_frontend * fe,enum fe_status * status)1370cd21b334SDaniel Scheller static int read_status(struct dvb_frontend *fe, enum fe_status *status)
1371cd21b334SDaniel Scheller {
1372cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1373cd21b334SDaniel Scheller struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1374cd21b334SDaniel Scheller u8 dmd_state = 0;
1375cd21b334SDaniel Scheller u8 dstatus = 0;
1376cd21b334SDaniel Scheller enum receive_mode cur_receive_mode = RCVMODE_NONE;
1377cd21b334SDaniel Scheller u32 feclock = 0;
1378cd21b334SDaniel Scheller
1379cd21b334SDaniel Scheller *status = 0;
1380cd21b334SDaniel Scheller
1381cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1382cd21b334SDaniel Scheller
1383cd21b334SDaniel Scheller if (dmd_state & 0x40) {
1384cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1385cd21b334SDaniel Scheller if (dstatus & 0x08)
1386cd21b334SDaniel Scheller cur_receive_mode = (dmd_state & 0x20) ?
1387cd21b334SDaniel Scheller RCVMODE_DVBS : RCVMODE_DVBS2;
1388cd21b334SDaniel Scheller }
1389cd21b334SDaniel Scheller if (cur_receive_mode == RCVMODE_NONE) {
1390cd21b334SDaniel Scheller set_vth(state);
1391cd21b334SDaniel Scheller
1392cd21b334SDaniel Scheller /* reset signal statistics */
1393cd21b334SDaniel Scheller p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1394cd21b334SDaniel Scheller p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1395cd21b334SDaniel Scheller p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1396cd21b334SDaniel Scheller p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1397cd21b334SDaniel Scheller
1398cd21b334SDaniel Scheller return 0;
1399cd21b334SDaniel Scheller }
1400cd21b334SDaniel Scheller
1401cd21b334SDaniel Scheller *status |= (FE_HAS_SIGNAL
1402cd21b334SDaniel Scheller | FE_HAS_CARRIER
1403cd21b334SDaniel Scheller | FE_HAS_VITERBI
1404cd21b334SDaniel Scheller | FE_HAS_SYNC);
1405cd21b334SDaniel Scheller
1406cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_NONE) {
1407cd21b334SDaniel Scheller state->receive_mode = cur_receive_mode;
1408cd21b334SDaniel Scheller state->demod_lock_time = jiffies;
1409cd21b334SDaniel Scheller state->first_time_lock = 1;
1410cd21b334SDaniel Scheller
1411cd21b334SDaniel Scheller get_signal_parameters(state);
1412cd21b334SDaniel Scheller tracking_optimization(state);
1413cd21b334SDaniel Scheller
1414cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1415cd21b334SDaniel Scheller state->tscfgh);
1416cd21b334SDaniel Scheller usleep_range(3000, 4000);
1417cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1418cd21b334SDaniel Scheller state->tscfgh | 0x01);
1419cd21b334SDaniel Scheller write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1420cd21b334SDaniel Scheller state->tscfgh);
1421cd21b334SDaniel Scheller }
1422cd21b334SDaniel Scheller if (dmd_state & 0x40) {
1423cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS2) {
1424cd21b334SDaniel Scheller u8 pdelstatus;
1425cd21b334SDaniel Scheller
1426cd21b334SDaniel Scheller read_reg(state,
1427cd21b334SDaniel Scheller RSTV0910_P2_PDELSTATUS1 + state->regoff,
1428cd21b334SDaniel Scheller &pdelstatus);
1429cd21b334SDaniel Scheller feclock = (pdelstatus & 0x02) != 0;
1430cd21b334SDaniel Scheller } else {
1431cd21b334SDaniel Scheller u8 vstatus;
1432cd21b334SDaniel Scheller
1433cd21b334SDaniel Scheller read_reg(state,
1434cd21b334SDaniel Scheller RSTV0910_P2_VSTATUSVIT + state->regoff,
1435cd21b334SDaniel Scheller &vstatus);
1436cd21b334SDaniel Scheller feclock = (vstatus & 0x08) != 0;
1437cd21b334SDaniel Scheller }
1438cd21b334SDaniel Scheller }
1439cd21b334SDaniel Scheller
1440cd21b334SDaniel Scheller if (feclock) {
1441cd21b334SDaniel Scheller *status |= FE_HAS_LOCK;
1442cd21b334SDaniel Scheller
1443cd21b334SDaniel Scheller if (state->first_time_lock) {
1444cd21b334SDaniel Scheller u8 tmp;
1445cd21b334SDaniel Scheller
1446cd21b334SDaniel Scheller state->first_time_lock = 0;
1447cd21b334SDaniel Scheller
1448cd21b334SDaniel Scheller manage_matype_info(state);
1449cd21b334SDaniel Scheller
1450cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS2) {
14514f979d5cSDaniel Scheller /*
14524f979d5cSDaniel Scheller * FSTV0910_P2_MANUALSX_ROLLOFF,
1453cd21b334SDaniel Scheller * FSTV0910_P2_MANUALS2_ROLLOFF = 0
1454cd21b334SDaniel Scheller */
1455cd21b334SDaniel Scheller state->demod_bits &= ~0x84;
1456cd21b334SDaniel Scheller write_reg(state,
1457cd21b334SDaniel Scheller RSTV0910_P2_DEMOD + state->regoff,
1458cd21b334SDaniel Scheller state->demod_bits);
1459cd21b334SDaniel Scheller read_reg(state,
1460cd21b334SDaniel Scheller RSTV0910_P2_PDELCTRL2 + state->regoff,
1461cd21b334SDaniel Scheller &tmp);
1462cd21b334SDaniel Scheller /* reset DVBS2 packet delinator error counter */
1463cd21b334SDaniel Scheller tmp |= 0x40;
1464cd21b334SDaniel Scheller write_reg(state,
1465cd21b334SDaniel Scheller RSTV0910_P2_PDELCTRL2 + state->regoff,
1466cd21b334SDaniel Scheller tmp);
1467cd21b334SDaniel Scheller /* reset DVBS2 packet delinator error counter */
1468cd21b334SDaniel Scheller tmp &= ~0x40;
1469cd21b334SDaniel Scheller write_reg(state,
1470cd21b334SDaniel Scheller RSTV0910_P2_PDELCTRL2 + state->regoff,
1471cd21b334SDaniel Scheller tmp);
1472cd21b334SDaniel Scheller
1473cd21b334SDaniel Scheller state->berscale = 2;
1474cd21b334SDaniel Scheller state->last_bernumerator = 0;
1475cd21b334SDaniel Scheller state->last_berdenominator = 1;
1476cd21b334SDaniel Scheller /* force to PRE BCH Rate */
1477cd21b334SDaniel Scheller write_reg(state,
1478cd21b334SDaniel Scheller RSTV0910_P2_ERRCTRL1 + state->regoff,
1479cd21b334SDaniel Scheller BER_SRC_S2 | state->berscale);
1480cd21b334SDaniel Scheller } else {
1481cd21b334SDaniel Scheller state->berscale = 2;
1482cd21b334SDaniel Scheller state->last_bernumerator = 0;
1483cd21b334SDaniel Scheller state->last_berdenominator = 1;
1484cd21b334SDaniel Scheller /* force to PRE RS Rate */
1485cd21b334SDaniel Scheller write_reg(state,
1486cd21b334SDaniel Scheller RSTV0910_P2_ERRCTRL1 + state->regoff,
1487cd21b334SDaniel Scheller BER_SRC_S | state->berscale);
1488cd21b334SDaniel Scheller }
1489cd21b334SDaniel Scheller /* Reset the Total packet counter */
1490cd21b334SDaniel Scheller write_reg(state,
1491cd21b334SDaniel Scheller RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
14924f979d5cSDaniel Scheller /*
14934f979d5cSDaniel Scheller * Reset the packet Error counter2 (and Set it to
1494868c9a17SMauro Carvalho Chehab * infinite error count mode)
1495cd21b334SDaniel Scheller */
1496cd21b334SDaniel Scheller write_reg(state,
1497cd21b334SDaniel Scheller RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1498cd21b334SDaniel Scheller
1499cd21b334SDaniel Scheller set_vth_default(state);
1500cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS)
1501cd21b334SDaniel Scheller enable_puncture_rate(state,
1502cd21b334SDaniel Scheller state->puncture_rate);
1503cd21b334SDaniel Scheller }
15049cc65447SDaniel Scheller
15059cc65447SDaniel Scheller /* Use highest signaled ModCod for quality */
15069cc65447SDaniel Scheller if (state->is_vcm) {
15079cc65447SDaniel Scheller u8 tmp;
15089cc65447SDaniel Scheller enum fe_stv0910_mod_cod mod_cod;
15099cc65447SDaniel Scheller
15109cc65447SDaniel Scheller read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
15119cc65447SDaniel Scheller &tmp);
15129cc65447SDaniel Scheller mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
15139cc65447SDaniel Scheller
15149cc65447SDaniel Scheller if (mod_cod > state->mod_cod)
15159cc65447SDaniel Scheller state->mod_cod = mod_cod;
15169cc65447SDaniel Scheller }
1517cd21b334SDaniel Scheller }
1518cd21b334SDaniel Scheller
1519cd21b334SDaniel Scheller /* read signal statistics */
1520cd21b334SDaniel Scheller
1521cd21b334SDaniel Scheller /* read signal strength */
1522cd21b334SDaniel Scheller read_signal_strength(fe);
1523cd21b334SDaniel Scheller
1524cd21b334SDaniel Scheller /* read carrier/noise on FE_HAS_CARRIER */
1525cd21b334SDaniel Scheller if (*status & FE_HAS_CARRIER)
1526cd21b334SDaniel Scheller read_snr(fe);
1527cd21b334SDaniel Scheller else
1528cd21b334SDaniel Scheller p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1529cd21b334SDaniel Scheller
1530cd21b334SDaniel Scheller /* read ber */
1531ddb6a90dSDaniel Scheller if (*status & FE_HAS_VITERBI) {
1532cd21b334SDaniel Scheller read_ber(fe);
1533ddb6a90dSDaniel Scheller } else {
1534cd21b334SDaniel Scheller p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1535cd21b334SDaniel Scheller p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1536cd21b334SDaniel Scheller }
1537cd21b334SDaniel Scheller
1538cd21b334SDaniel Scheller return 0;
1539cd21b334SDaniel Scheller }
1540cd21b334SDaniel Scheller
get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)1541cd21b334SDaniel Scheller static int get_frontend(struct dvb_frontend *fe,
1542cd21b334SDaniel Scheller struct dtv_frontend_properties *p)
1543cd21b334SDaniel Scheller {
1544cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1545cd21b334SDaniel Scheller u8 tmp;
15460b885dedSDaniel Scheller u32 symbolrate;
1547cd21b334SDaniel Scheller
1548cd21b334SDaniel Scheller if (state->receive_mode == RCVMODE_DVBS2) {
1549cd21b334SDaniel Scheller u32 mc;
155020e671dfSDaniel Scheller const enum fe_modulation modcod2mod[0x20] = {
1551cd21b334SDaniel Scheller QPSK, QPSK, QPSK, QPSK,
1552cd21b334SDaniel Scheller QPSK, QPSK, QPSK, QPSK,
1553cd21b334SDaniel Scheller QPSK, QPSK, QPSK, QPSK,
1554cd21b334SDaniel Scheller PSK_8, PSK_8, PSK_8, PSK_8,
1555cd21b334SDaniel Scheller PSK_8, PSK_8, APSK_16, APSK_16,
1556cd21b334SDaniel Scheller APSK_16, APSK_16, APSK_16, APSK_16,
1557cd21b334SDaniel Scheller APSK_32, APSK_32, APSK_32, APSK_32,
1558cd21b334SDaniel Scheller APSK_32,
1559cd21b334SDaniel Scheller };
156020e671dfSDaniel Scheller const enum fe_code_rate modcod2fec[0x20] = {
1561cd21b334SDaniel Scheller FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
1562cd21b334SDaniel Scheller FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
1563cd21b334SDaniel Scheller FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1564cd21b334SDaniel Scheller FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
1565cd21b334SDaniel Scheller FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
1566cd21b334SDaniel Scheller FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1567cd21b334SDaniel Scheller FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
1568cd21b334SDaniel Scheller FEC_9_10
1569cd21b334SDaniel Scheller };
1570cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1571cd21b334SDaniel Scheller mc = ((tmp & 0x7c) >> 2);
1572cd21b334SDaniel Scheller p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
1573cd21b334SDaniel Scheller p->modulation = modcod2mod[mc];
1574cd21b334SDaniel Scheller p->fec_inner = modcod2fec[mc];
1575cd21b334SDaniel Scheller } else if (state->receive_mode == RCVMODE_DVBS) {
1576cd21b334SDaniel Scheller read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1577cd21b334SDaniel Scheller switch (tmp & 0x1F) {
1578cd21b334SDaniel Scheller case 0x0d:
1579cd21b334SDaniel Scheller p->fec_inner = FEC_1_2;
1580cd21b334SDaniel Scheller break;
1581cd21b334SDaniel Scheller case 0x12:
1582cd21b334SDaniel Scheller p->fec_inner = FEC_2_3;
1583cd21b334SDaniel Scheller break;
1584cd21b334SDaniel Scheller case 0x15:
1585cd21b334SDaniel Scheller p->fec_inner = FEC_3_4;
1586cd21b334SDaniel Scheller break;
1587cd21b334SDaniel Scheller case 0x18:
1588cd21b334SDaniel Scheller p->fec_inner = FEC_5_6;
1589cd21b334SDaniel Scheller break;
1590cd21b334SDaniel Scheller case 0x1a:
1591cd21b334SDaniel Scheller p->fec_inner = FEC_7_8;
1592cd21b334SDaniel Scheller break;
1593cd21b334SDaniel Scheller default:
1594cd21b334SDaniel Scheller p->fec_inner = FEC_NONE;
1595cd21b334SDaniel Scheller break;
1596cd21b334SDaniel Scheller }
1597cd21b334SDaniel Scheller p->rolloff = ROLLOFF_35;
1598cd21b334SDaniel Scheller }
1599cd21b334SDaniel Scheller
16000b885dedSDaniel Scheller if (state->receive_mode != RCVMODE_NONE) {
16010b885dedSDaniel Scheller get_cur_symbol_rate(state, &symbolrate);
16020b885dedSDaniel Scheller p->symbol_rate = symbolrate;
16030b885dedSDaniel Scheller }
1604cd21b334SDaniel Scheller return 0;
1605cd21b334SDaniel Scheller }
1606cd21b334SDaniel Scheller
tune(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)1607cd21b334SDaniel Scheller static int tune(struct dvb_frontend *fe, bool re_tune,
1608cd21b334SDaniel Scheller unsigned int mode_flags,
1609cd21b334SDaniel Scheller unsigned int *delay, enum fe_status *status)
1610cd21b334SDaniel Scheller {
1611cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1612cd21b334SDaniel Scheller int r;
1613cd21b334SDaniel Scheller
1614cd21b334SDaniel Scheller if (re_tune) {
1615cd21b334SDaniel Scheller r = set_parameters(fe);
1616cd21b334SDaniel Scheller if (r)
1617cd21b334SDaniel Scheller return r;
1618cd21b334SDaniel Scheller state->tune_time = jiffies;
1619cd21b334SDaniel Scheller }
1620cd21b334SDaniel Scheller
1621cd21b334SDaniel Scheller r = read_status(fe, status);
1622cd21b334SDaniel Scheller if (r)
1623cd21b334SDaniel Scheller return r;
1624f0e72c29SDaniel Scheller
1625f0e72c29SDaniel Scheller if (*status & FE_HAS_LOCK)
1626f0e72c29SDaniel Scheller return 0;
1627f0e72c29SDaniel Scheller *delay = HZ;
1628f0e72c29SDaniel Scheller
1629cd21b334SDaniel Scheller return 0;
1630cd21b334SDaniel Scheller }
1631cd21b334SDaniel Scheller
get_algo(struct dvb_frontend * fe)16328d718e53SLuc Van Oostenryck static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
1633cd21b334SDaniel Scheller {
1634cd21b334SDaniel Scheller return DVBFE_ALGO_HW;
1635cd21b334SDaniel Scheller }
1636cd21b334SDaniel Scheller
set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)1637cd21b334SDaniel Scheller static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1638cd21b334SDaniel Scheller {
1639cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1640cd21b334SDaniel Scheller u16 offs = state->nr ? 0x40 : 0;
1641cd21b334SDaniel Scheller
1642cd21b334SDaniel Scheller switch (tone) {
1643cd21b334SDaniel Scheller case SEC_TONE_ON:
1644cd21b334SDaniel Scheller return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1645cd21b334SDaniel Scheller case SEC_TONE_OFF:
1646cd21b334SDaniel Scheller return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1647cd21b334SDaniel Scheller default:
1648cd21b334SDaniel Scheller break;
1649cd21b334SDaniel Scheller }
1650cd21b334SDaniel Scheller return -EINVAL;
1651cd21b334SDaniel Scheller }
1652cd21b334SDaniel Scheller
wait_dis(struct stv * state,u8 flag,u8 val)1653cd21b334SDaniel Scheller static int wait_dis(struct stv *state, u8 flag, u8 val)
1654cd21b334SDaniel Scheller {
1655cd21b334SDaniel Scheller int i;
1656cd21b334SDaniel Scheller u8 stat;
1657cd21b334SDaniel Scheller u16 offs = state->nr ? 0x40 : 0;
1658cd21b334SDaniel Scheller
1659cd21b334SDaniel Scheller for (i = 0; i < 10; i++) {
1660cd21b334SDaniel Scheller read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1661cd21b334SDaniel Scheller if ((stat & flag) == val)
1662cd21b334SDaniel Scheller return 0;
1663cd21b334SDaniel Scheller usleep_range(10000, 11000);
1664cd21b334SDaniel Scheller }
1665cd21b334SDaniel Scheller return -ETIMEDOUT;
1666cd21b334SDaniel Scheller }
1667cd21b334SDaniel Scheller
send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)1668cd21b334SDaniel Scheller static int send_master_cmd(struct dvb_frontend *fe,
1669cd21b334SDaniel Scheller struct dvb_diseqc_master_cmd *cmd)
1670cd21b334SDaniel Scheller {
1671cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1672cd21b334SDaniel Scheller int i;
1673cd21b334SDaniel Scheller
1674da2cf18fSDaniel Scheller SET_FIELD(DISEQC_MODE, 2);
1675da2cf18fSDaniel Scheller SET_FIELD(DIS_PRECHARGE, 1);
1676cd21b334SDaniel Scheller for (i = 0; i < cmd->msg_len; i++) {
1677cd21b334SDaniel Scheller wait_dis(state, 0x40, 0x00);
1678da2cf18fSDaniel Scheller SET_REG(DISTXFIFO, cmd->msg[i]);
1679cd21b334SDaniel Scheller }
1680da2cf18fSDaniel Scheller SET_FIELD(DIS_PRECHARGE, 0);
1681cd21b334SDaniel Scheller wait_dis(state, 0x20, 0x20);
1682cd21b334SDaniel Scheller return 0;
1683cd21b334SDaniel Scheller }
1684cd21b334SDaniel Scheller
send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd burst)1685448461afSDaniel Scheller static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
1686448461afSDaniel Scheller {
1687448461afSDaniel Scheller struct stv *state = fe->demodulator_priv;
1688448461afSDaniel Scheller u8 value;
1689448461afSDaniel Scheller
1690448461afSDaniel Scheller if (burst == SEC_MINI_A) {
1691da2cf18fSDaniel Scheller SET_FIELD(DISEQC_MODE, 3);
1692448461afSDaniel Scheller value = 0x00;
1693448461afSDaniel Scheller } else {
1694da2cf18fSDaniel Scheller SET_FIELD(DISEQC_MODE, 2);
1695448461afSDaniel Scheller value = 0xFF;
1696448461afSDaniel Scheller }
1697da2cf18fSDaniel Scheller
1698da2cf18fSDaniel Scheller SET_FIELD(DIS_PRECHARGE, 1);
1699448461afSDaniel Scheller wait_dis(state, 0x40, 0x00);
1700da2cf18fSDaniel Scheller SET_REG(DISTXFIFO, value);
1701da2cf18fSDaniel Scheller SET_FIELD(DIS_PRECHARGE, 0);
1702448461afSDaniel Scheller wait_dis(state, 0x20, 0x20);
1703448461afSDaniel Scheller
1704448461afSDaniel Scheller return 0;
1705448461afSDaniel Scheller }
1706448461afSDaniel Scheller
sleep(struct dvb_frontend * fe)1707cd21b334SDaniel Scheller static int sleep(struct dvb_frontend *fe)
1708cd21b334SDaniel Scheller {
1709cd21b334SDaniel Scheller struct stv *state = fe->demodulator_priv;
1710cd21b334SDaniel Scheller
1711cd21b334SDaniel Scheller stop(state);
1712cd21b334SDaniel Scheller return 0;
1713cd21b334SDaniel Scheller }
1714cd21b334SDaniel Scheller
171520e671dfSDaniel Scheller static const struct dvb_frontend_ops stv0910_ops = {
1716cd21b334SDaniel Scheller .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1717cd21b334SDaniel Scheller .info = {
171820e671dfSDaniel Scheller .name = "ST STV0910",
1719f1b1eabfSMauro Carvalho Chehab .frequency_min_hz = 950 * MHz,
1720f1b1eabfSMauro Carvalho Chehab .frequency_max_hz = 2150 * MHz,
1721e5d9ce4dSDaniel Scheller .symbol_rate_min = 100000,
1722cd21b334SDaniel Scheller .symbol_rate_max = 70000000,
1723cd21b334SDaniel Scheller .caps = FE_CAN_INVERSION_AUTO |
1724cd21b334SDaniel Scheller FE_CAN_FEC_AUTO |
1725cd21b334SDaniel Scheller FE_CAN_QPSK |
1726ea71c62bSDaniel Scheller FE_CAN_2G_MODULATION |
1727ea71c62bSDaniel Scheller FE_CAN_MULTISTREAM
1728cd21b334SDaniel Scheller },
1729cd21b334SDaniel Scheller .sleep = sleep,
1730cd21b334SDaniel Scheller .release = release,
1731cd21b334SDaniel Scheller .i2c_gate_ctrl = gate_ctrl,
17322f4675c0SDaniel Scheller .set_frontend = set_parameters,
1733cd21b334SDaniel Scheller .get_frontend_algo = get_algo,
1734cd21b334SDaniel Scheller .get_frontend = get_frontend,
1735cd21b334SDaniel Scheller .tune = tune,
1736cd21b334SDaniel Scheller .read_status = read_status,
1737cd21b334SDaniel Scheller .set_tone = set_tone,
1738cd21b334SDaniel Scheller
1739cd21b334SDaniel Scheller .diseqc_send_master_cmd = send_master_cmd,
1740448461afSDaniel Scheller .diseqc_send_burst = send_burst,
1741cd21b334SDaniel Scheller };
1742cd21b334SDaniel Scheller
match_base(struct i2c_adapter * i2c,u8 adr)1743cd21b334SDaniel Scheller static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
1744cd21b334SDaniel Scheller {
1745cd21b334SDaniel Scheller struct stv_base *p;
1746cd21b334SDaniel Scheller
1747cd21b334SDaniel Scheller list_for_each_entry(p, &stvlist, stvlist)
1748cd21b334SDaniel Scheller if (p->i2c == i2c && p->adr == adr)
1749cd21b334SDaniel Scheller return p;
1750cd21b334SDaniel Scheller return NULL;
1751cd21b334SDaniel Scheller }
1752cd21b334SDaniel Scheller
stv0910_init_stats(struct stv * state)1753cd21b334SDaniel Scheller static void stv0910_init_stats(struct stv *state)
1754cd21b334SDaniel Scheller {
1755cd21b334SDaniel Scheller struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1756cd21b334SDaniel Scheller
1757cd21b334SDaniel Scheller p->strength.len = 1;
1758cd21b334SDaniel Scheller p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1759cd21b334SDaniel Scheller p->cnr.len = 1;
1760cd21b334SDaniel Scheller p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1761cd21b334SDaniel Scheller p->pre_bit_error.len = 1;
1762cd21b334SDaniel Scheller p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1763cd21b334SDaniel Scheller p->pre_bit_count.len = 1;
1764cd21b334SDaniel Scheller p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1765cd21b334SDaniel Scheller }
1766cd21b334SDaniel Scheller
stv0910_attach(struct i2c_adapter * i2c,struct stv0910_cfg * cfg,int nr)1767cd21b334SDaniel Scheller struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
1768cd21b334SDaniel Scheller struct stv0910_cfg *cfg,
1769cd21b334SDaniel Scheller int nr)
1770cd21b334SDaniel Scheller {
1771cd21b334SDaniel Scheller struct stv *state;
1772cd21b334SDaniel Scheller struct stv_base *base;
1773cd21b334SDaniel Scheller
1774ddb6a90dSDaniel Scheller state = kzalloc(sizeof(*state), GFP_KERNEL);
1775cd21b334SDaniel Scheller if (!state)
1776cd21b334SDaniel Scheller return NULL;
1777cd21b334SDaniel Scheller
1778cd21b334SDaniel Scheller state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1779cd21b334SDaniel Scheller state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1780cd21b334SDaniel Scheller state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
17817069018eSDaniel Scheller /* use safe tsspeed value if unspecified through stv0910_cfg */
17827069018eSDaniel Scheller state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
1783cd21b334SDaniel Scheller state->nr = nr;
1784cd21b334SDaniel Scheller state->regoff = state->nr ? 0 : 0x200;
1785cd21b334SDaniel Scheller state->search_range = 16000000;
1786cd21b334SDaniel Scheller state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1787cd21b334SDaniel Scheller state->receive_mode = RCVMODE_NONE;
1788ea71c62bSDaniel Scheller state->cur_scrambling_code = (~0U);
1789cd21b334SDaniel Scheller state->single = cfg->single ? 1 : 0;
1790cd21b334SDaniel Scheller
1791cd21b334SDaniel Scheller base = match_base(i2c, cfg->adr);
1792cd21b334SDaniel Scheller if (base) {
1793cd21b334SDaniel Scheller base->count++;
1794cd21b334SDaniel Scheller state->base = base;
1795cd21b334SDaniel Scheller } else {
1796ddb6a90dSDaniel Scheller base = kzalloc(sizeof(*base), GFP_KERNEL);
1797cd21b334SDaniel Scheller if (!base)
1798cd21b334SDaniel Scheller goto fail;
1799cd21b334SDaniel Scheller base->i2c = i2c;
1800cd21b334SDaniel Scheller base->adr = cfg->adr;
1801cd21b334SDaniel Scheller base->count = 1;
1802cd21b334SDaniel Scheller base->extclk = cfg->clk ? cfg->clk : 30000000;
1803cd21b334SDaniel Scheller
1804cd21b334SDaniel Scheller mutex_init(&base->i2c_lock);
1805cd21b334SDaniel Scheller mutex_init(&base->reg_lock);
1806cd21b334SDaniel Scheller state->base = base;
1807cd21b334SDaniel Scheller if (probe(state) < 0) {
1808cd21b334SDaniel Scheller dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
1809cd21b334SDaniel Scheller cfg->adr, dev_name(&i2c->dev));
1810cd21b334SDaniel Scheller kfree(base);
1811cd21b334SDaniel Scheller goto fail;
1812cd21b334SDaniel Scheller }
1813cd21b334SDaniel Scheller list_add(&base->stvlist, &stvlist);
1814cd21b334SDaniel Scheller }
1815cd21b334SDaniel Scheller state->fe.ops = stv0910_ops;
1816cd21b334SDaniel Scheller state->fe.demodulator_priv = state;
1817cd21b334SDaniel Scheller state->nr = nr;
1818cd21b334SDaniel Scheller
1819cd21b334SDaniel Scheller dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
1820cd21b334SDaniel Scheller state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
1821cd21b334SDaniel Scheller
1822cd21b334SDaniel Scheller stv0910_init_stats(state);
1823cd21b334SDaniel Scheller
1824cd21b334SDaniel Scheller return &state->fe;
1825cd21b334SDaniel Scheller
1826cd21b334SDaniel Scheller fail:
1827cd21b334SDaniel Scheller kfree(state);
1828cd21b334SDaniel Scheller return NULL;
1829cd21b334SDaniel Scheller }
1830cd21b334SDaniel Scheller EXPORT_SYMBOL_GPL(stv0910_attach);
1831cd21b334SDaniel Scheller
1832cd21b334SDaniel Scheller MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
1833cd21b334SDaniel Scheller MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
1834229b6ea6SDaniel Scheller MODULE_LICENSE("GPL v2");
1835