1 /* 2 STV0900/0903 Multistandard Broadcast Frontend driver 3 Copyright (C) Manu Abraham <abraham.manu@gmail.com> 4 5 Copyright (C) ST Microelectronics 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/init.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/string.h> 26 #include <linux/slab.h> 27 #include <linux/mutex.h> 28 29 #include <linux/dvb/frontend.h> 30 #include "dvb_frontend.h" 31 32 #include "stv6110x.h" /* for demodulator internal modes */ 33 34 #include "stv090x_reg.h" 35 #include "stv090x.h" 36 #include "stv090x_priv.h" 37 38 /* Max transfer size done by I2C transfer functions */ 39 #define MAX_XFER_SIZE 64 40 41 static unsigned int verbose; 42 module_param(verbose, int, 0644); 43 44 /* internal params node */ 45 struct stv090x_dev { 46 /* pointer for internal params, one for each pair of demods */ 47 struct stv090x_internal *internal; 48 struct stv090x_dev *next_dev; 49 }; 50 51 /* first internal params */ 52 static struct stv090x_dev *stv090x_first_dev; 53 54 /* find chip by i2c adapter and i2c address */ 55 static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap, 56 u8 i2c_addr) 57 { 58 struct stv090x_dev *temp_dev = stv090x_first_dev; 59 60 /* 61 Search of the last stv0900 chip or 62 find it by i2c adapter and i2c address */ 63 while ((temp_dev != NULL) && 64 ((temp_dev->internal->i2c_adap != i2c_adap) || 65 (temp_dev->internal->i2c_addr != i2c_addr))) { 66 67 temp_dev = temp_dev->next_dev; 68 } 69 70 return temp_dev; 71 } 72 73 /* deallocating chip */ 74 static void remove_dev(struct stv090x_internal *internal) 75 { 76 struct stv090x_dev *prev_dev = stv090x_first_dev; 77 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, 78 internal->i2c_addr); 79 80 if (del_dev != NULL) { 81 if (del_dev == stv090x_first_dev) { 82 stv090x_first_dev = del_dev->next_dev; 83 } else { 84 while (prev_dev->next_dev != del_dev) 85 prev_dev = prev_dev->next_dev; 86 87 prev_dev->next_dev = del_dev->next_dev; 88 } 89 90 kfree(del_dev); 91 } 92 } 93 94 /* allocating new chip */ 95 static struct stv090x_dev *append_internal(struct stv090x_internal *internal) 96 { 97 struct stv090x_dev *new_dev; 98 struct stv090x_dev *temp_dev; 99 100 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL); 101 if (new_dev != NULL) { 102 new_dev->internal = internal; 103 new_dev->next_dev = NULL; 104 105 /* append to list */ 106 if (stv090x_first_dev == NULL) { 107 stv090x_first_dev = new_dev; 108 } else { 109 temp_dev = stv090x_first_dev; 110 while (temp_dev->next_dev != NULL) 111 temp_dev = temp_dev->next_dev; 112 113 temp_dev->next_dev = new_dev; 114 } 115 } 116 117 return new_dev; 118 } 119 120 121 /* DVBS1 and DSS C/N Lookup table */ 122 static const struct stv090x_tab stv090x_s1cn_tab[] = { 123 { 0, 8917 }, /* 0.0dB */ 124 { 5, 8801 }, /* 0.5dB */ 125 { 10, 8667 }, /* 1.0dB */ 126 { 15, 8522 }, /* 1.5dB */ 127 { 20, 8355 }, /* 2.0dB */ 128 { 25, 8175 }, /* 2.5dB */ 129 { 30, 7979 }, /* 3.0dB */ 130 { 35, 7763 }, /* 3.5dB */ 131 { 40, 7530 }, /* 4.0dB */ 132 { 45, 7282 }, /* 4.5dB */ 133 { 50, 7026 }, /* 5.0dB */ 134 { 55, 6781 }, /* 5.5dB */ 135 { 60, 6514 }, /* 6.0dB */ 136 { 65, 6241 }, /* 6.5dB */ 137 { 70, 5965 }, /* 7.0dB */ 138 { 75, 5690 }, /* 7.5dB */ 139 { 80, 5424 }, /* 8.0dB */ 140 { 85, 5161 }, /* 8.5dB */ 141 { 90, 4902 }, /* 9.0dB */ 142 { 95, 4654 }, /* 9.5dB */ 143 { 100, 4417 }, /* 10.0dB */ 144 { 105, 4186 }, /* 10.5dB */ 145 { 110, 3968 }, /* 11.0dB */ 146 { 115, 3757 }, /* 11.5dB */ 147 { 120, 3558 }, /* 12.0dB */ 148 { 125, 3366 }, /* 12.5dB */ 149 { 130, 3185 }, /* 13.0dB */ 150 { 135, 3012 }, /* 13.5dB */ 151 { 140, 2850 }, /* 14.0dB */ 152 { 145, 2698 }, /* 14.5dB */ 153 { 150, 2550 }, /* 15.0dB */ 154 { 160, 2283 }, /* 16.0dB */ 155 { 170, 2042 }, /* 17.0dB */ 156 { 180, 1827 }, /* 18.0dB */ 157 { 190, 1636 }, /* 19.0dB */ 158 { 200, 1466 }, /* 20.0dB */ 159 { 210, 1315 }, /* 21.0dB */ 160 { 220, 1181 }, /* 22.0dB */ 161 { 230, 1064 }, /* 23.0dB */ 162 { 240, 960 }, /* 24.0dB */ 163 { 250, 869 }, /* 25.0dB */ 164 { 260, 792 }, /* 26.0dB */ 165 { 270, 724 }, /* 27.0dB */ 166 { 280, 665 }, /* 28.0dB */ 167 { 290, 616 }, /* 29.0dB */ 168 { 300, 573 }, /* 30.0dB */ 169 { 310, 537 }, /* 31.0dB */ 170 { 320, 507 }, /* 32.0dB */ 171 { 330, 483 }, /* 33.0dB */ 172 { 400, 398 }, /* 40.0dB */ 173 { 450, 381 }, /* 45.0dB */ 174 { 500, 377 } /* 50.0dB */ 175 }; 176 177 /* DVBS2 C/N Lookup table */ 178 static const struct stv090x_tab stv090x_s2cn_tab[] = { 179 { -30, 13348 }, /* -3.0dB */ 180 { -20, 12640 }, /* -2d.0B */ 181 { -10, 11883 }, /* -1.0dB */ 182 { 0, 11101 }, /* -0.0dB */ 183 { 5, 10718 }, /* 0.5dB */ 184 { 10, 10339 }, /* 1.0dB */ 185 { 15, 9947 }, /* 1.5dB */ 186 { 20, 9552 }, /* 2.0dB */ 187 { 25, 9183 }, /* 2.5dB */ 188 { 30, 8799 }, /* 3.0dB */ 189 { 35, 8422 }, /* 3.5dB */ 190 { 40, 8062 }, /* 4.0dB */ 191 { 45, 7707 }, /* 4.5dB */ 192 { 50, 7353 }, /* 5.0dB */ 193 { 55, 7025 }, /* 5.5dB */ 194 { 60, 6684 }, /* 6.0dB */ 195 { 65, 6331 }, /* 6.5dB */ 196 { 70, 6036 }, /* 7.0dB */ 197 { 75, 5727 }, /* 7.5dB */ 198 { 80, 5437 }, /* 8.0dB */ 199 { 85, 5164 }, /* 8.5dB */ 200 { 90, 4902 }, /* 9.0dB */ 201 { 95, 4653 }, /* 9.5dB */ 202 { 100, 4408 }, /* 10.0dB */ 203 { 105, 4187 }, /* 10.5dB */ 204 { 110, 3961 }, /* 11.0dB */ 205 { 115, 3751 }, /* 11.5dB */ 206 { 120, 3558 }, /* 12.0dB */ 207 { 125, 3368 }, /* 12.5dB */ 208 { 130, 3191 }, /* 13.0dB */ 209 { 135, 3017 }, /* 13.5dB */ 210 { 140, 2862 }, /* 14.0dB */ 211 { 145, 2710 }, /* 14.5dB */ 212 { 150, 2565 }, /* 15.0dB */ 213 { 160, 2300 }, /* 16.0dB */ 214 { 170, 2058 }, /* 17.0dB */ 215 { 180, 1849 }, /* 18.0dB */ 216 { 190, 1663 }, /* 19.0dB */ 217 { 200, 1495 }, /* 20.0dB */ 218 { 210, 1349 }, /* 21.0dB */ 219 { 220, 1222 }, /* 22.0dB */ 220 { 230, 1110 }, /* 23.0dB */ 221 { 240, 1011 }, /* 24.0dB */ 222 { 250, 925 }, /* 25.0dB */ 223 { 260, 853 }, /* 26.0dB */ 224 { 270, 789 }, /* 27.0dB */ 225 { 280, 734 }, /* 28.0dB */ 226 { 290, 690 }, /* 29.0dB */ 227 { 300, 650 }, /* 30.0dB */ 228 { 310, 619 }, /* 31.0dB */ 229 { 320, 593 }, /* 32.0dB */ 230 { 330, 571 }, /* 33.0dB */ 231 { 400, 498 }, /* 40.0dB */ 232 { 450, 484 }, /* 45.0dB */ 233 { 500, 481 } /* 50.0dB */ 234 }; 235 236 /* RF level C/N lookup table */ 237 static const struct stv090x_tab stv090x_rf_tab[] = { 238 { -5, 0xcaa1 }, /* -5dBm */ 239 { -10, 0xc229 }, /* -10dBm */ 240 { -15, 0xbb08 }, /* -15dBm */ 241 { -20, 0xb4bc }, /* -20dBm */ 242 { -25, 0xad5a }, /* -25dBm */ 243 { -30, 0xa298 }, /* -30dBm */ 244 { -35, 0x98a8 }, /* -35dBm */ 245 { -40, 0x8389 }, /* -40dBm */ 246 { -45, 0x59be }, /* -45dBm */ 247 { -50, 0x3a14 }, /* -50dBm */ 248 { -55, 0x2d11 }, /* -55dBm */ 249 { -60, 0x210d }, /* -60dBm */ 250 { -65, 0xa14f }, /* -65dBm */ 251 { -70, 0x07aa } /* -70dBm */ 252 }; 253 254 255 static struct stv090x_reg stv0900_initval[] = { 256 257 { STV090x_OUTCFG, 0x00 }, 258 { STV090x_MODECFG, 0xff }, 259 { STV090x_AGCRF1CFG, 0x11 }, 260 { STV090x_AGCRF2CFG, 0x13 }, 261 { STV090x_TSGENERAL1X, 0x14 }, 262 { STV090x_TSTTNR2, 0x21 }, 263 { STV090x_TSTTNR4, 0x21 }, 264 { STV090x_P2_DISTXCTL, 0x22 }, 265 { STV090x_P2_F22TX, 0xc0 }, 266 { STV090x_P2_F22RX, 0xc0 }, 267 { STV090x_P2_DISRXCTL, 0x00 }, 268 { STV090x_P2_DMDCFGMD, 0xF9 }, 269 { STV090x_P2_DEMOD, 0x08 }, 270 { STV090x_P2_DMDCFG3, 0xc4 }, 271 { STV090x_P2_CARFREQ, 0xed }, 272 { STV090x_P2_LDT, 0xd0 }, 273 { STV090x_P2_LDT2, 0xb8 }, 274 { STV090x_P2_TMGCFG, 0xd2 }, 275 { STV090x_P2_TMGTHRISE, 0x20 }, 276 { STV090x_P1_TMGCFG, 0xd2 }, 277 278 { STV090x_P2_TMGTHFALL, 0x00 }, 279 { STV090x_P2_FECSPY, 0x88 }, 280 { STV090x_P2_FSPYDATA, 0x3a }, 281 { STV090x_P2_FBERCPT4, 0x00 }, 282 { STV090x_P2_FSPYBER, 0x10 }, 283 { STV090x_P2_ERRCTRL1, 0x35 }, 284 { STV090x_P2_ERRCTRL2, 0xc1 }, 285 { STV090x_P2_CFRICFG, 0xf8 }, 286 { STV090x_P2_NOSCFG, 0x1c }, 287 { STV090x_P2_DMDTOM, 0x20 }, 288 { STV090x_P2_CORRELMANT, 0x70 }, 289 { STV090x_P2_CORRELABS, 0x88 }, 290 { STV090x_P2_AGC2O, 0x5b }, 291 { STV090x_P2_AGC2REF, 0x38 }, 292 { STV090x_P2_CARCFG, 0xe4 }, 293 { STV090x_P2_ACLC, 0x1A }, 294 { STV090x_P2_BCLC, 0x09 }, 295 { STV090x_P2_CARHDR, 0x08 }, 296 { STV090x_P2_KREFTMG, 0xc1 }, 297 { STV090x_P2_SFRUPRATIO, 0xf0 }, 298 { STV090x_P2_SFRLOWRATIO, 0x70 }, 299 { STV090x_P2_SFRSTEP, 0x58 }, 300 { STV090x_P2_TMGCFG2, 0x01 }, 301 { STV090x_P2_CAR2CFG, 0x26 }, 302 { STV090x_P2_BCLC2S2Q, 0x86 }, 303 { STV090x_P2_BCLC2S28, 0x86 }, 304 { STV090x_P2_SMAPCOEF7, 0x77 }, 305 { STV090x_P2_SMAPCOEF6, 0x85 }, 306 { STV090x_P2_SMAPCOEF5, 0x77 }, 307 { STV090x_P2_TSCFGL, 0x20 }, 308 { STV090x_P2_DMDCFG2, 0x3b }, 309 { STV090x_P2_MODCODLST0, 0xff }, 310 { STV090x_P2_MODCODLST1, 0xff }, 311 { STV090x_P2_MODCODLST2, 0xff }, 312 { STV090x_P2_MODCODLST3, 0xff }, 313 { STV090x_P2_MODCODLST4, 0xff }, 314 { STV090x_P2_MODCODLST5, 0xff }, 315 { STV090x_P2_MODCODLST6, 0xff }, 316 { STV090x_P2_MODCODLST7, 0xcc }, 317 { STV090x_P2_MODCODLST8, 0xcc }, 318 { STV090x_P2_MODCODLST9, 0xcc }, 319 { STV090x_P2_MODCODLSTA, 0xcc }, 320 { STV090x_P2_MODCODLSTB, 0xcc }, 321 { STV090x_P2_MODCODLSTC, 0xcc }, 322 { STV090x_P2_MODCODLSTD, 0xcc }, 323 { STV090x_P2_MODCODLSTE, 0xcc }, 324 { STV090x_P2_MODCODLSTF, 0xcf }, 325 { STV090x_P1_DISTXCTL, 0x22 }, 326 { STV090x_P1_F22TX, 0xc0 }, 327 { STV090x_P1_F22RX, 0xc0 }, 328 { STV090x_P1_DISRXCTL, 0x00 }, 329 { STV090x_P1_DMDCFGMD, 0xf9 }, 330 { STV090x_P1_DEMOD, 0x08 }, 331 { STV090x_P1_DMDCFG3, 0xc4 }, 332 { STV090x_P1_DMDTOM, 0x20 }, 333 { STV090x_P1_CARFREQ, 0xed }, 334 { STV090x_P1_LDT, 0xd0 }, 335 { STV090x_P1_LDT2, 0xb8 }, 336 { STV090x_P1_TMGCFG, 0xd2 }, 337 { STV090x_P1_TMGTHRISE, 0x20 }, 338 { STV090x_P1_TMGTHFALL, 0x00 }, 339 { STV090x_P1_SFRUPRATIO, 0xf0 }, 340 { STV090x_P1_SFRLOWRATIO, 0x70 }, 341 { STV090x_P1_TSCFGL, 0x20 }, 342 { STV090x_P1_FECSPY, 0x88 }, 343 { STV090x_P1_FSPYDATA, 0x3a }, 344 { STV090x_P1_FBERCPT4, 0x00 }, 345 { STV090x_P1_FSPYBER, 0x10 }, 346 { STV090x_P1_ERRCTRL1, 0x35 }, 347 { STV090x_P1_ERRCTRL2, 0xc1 }, 348 { STV090x_P1_CFRICFG, 0xf8 }, 349 { STV090x_P1_NOSCFG, 0x1c }, 350 { STV090x_P1_CORRELMANT, 0x70 }, 351 { STV090x_P1_CORRELABS, 0x88 }, 352 { STV090x_P1_AGC2O, 0x5b }, 353 { STV090x_P1_AGC2REF, 0x38 }, 354 { STV090x_P1_CARCFG, 0xe4 }, 355 { STV090x_P1_ACLC, 0x1A }, 356 { STV090x_P1_BCLC, 0x09 }, 357 { STV090x_P1_CARHDR, 0x08 }, 358 { STV090x_P1_KREFTMG, 0xc1 }, 359 { STV090x_P1_SFRSTEP, 0x58 }, 360 { STV090x_P1_TMGCFG2, 0x01 }, 361 { STV090x_P1_CAR2CFG, 0x26 }, 362 { STV090x_P1_BCLC2S2Q, 0x86 }, 363 { STV090x_P1_BCLC2S28, 0x86 }, 364 { STV090x_P1_SMAPCOEF7, 0x77 }, 365 { STV090x_P1_SMAPCOEF6, 0x85 }, 366 { STV090x_P1_SMAPCOEF5, 0x77 }, 367 { STV090x_P1_DMDCFG2, 0x3b }, 368 { STV090x_P1_MODCODLST0, 0xff }, 369 { STV090x_P1_MODCODLST1, 0xff }, 370 { STV090x_P1_MODCODLST2, 0xff }, 371 { STV090x_P1_MODCODLST3, 0xff }, 372 { STV090x_P1_MODCODLST4, 0xff }, 373 { STV090x_P1_MODCODLST5, 0xff }, 374 { STV090x_P1_MODCODLST6, 0xff }, 375 { STV090x_P1_MODCODLST7, 0xcc }, 376 { STV090x_P1_MODCODLST8, 0xcc }, 377 { STV090x_P1_MODCODLST9, 0xcc }, 378 { STV090x_P1_MODCODLSTA, 0xcc }, 379 { STV090x_P1_MODCODLSTB, 0xcc }, 380 { STV090x_P1_MODCODLSTC, 0xcc }, 381 { STV090x_P1_MODCODLSTD, 0xcc }, 382 { STV090x_P1_MODCODLSTE, 0xcc }, 383 { STV090x_P1_MODCODLSTF, 0xcf }, 384 { STV090x_GENCFG, 0x1d }, 385 { STV090x_NBITER_NF4, 0x37 }, 386 { STV090x_NBITER_NF5, 0x29 }, 387 { STV090x_NBITER_NF6, 0x37 }, 388 { STV090x_NBITER_NF7, 0x33 }, 389 { STV090x_NBITER_NF8, 0x31 }, 390 { STV090x_NBITER_NF9, 0x2f }, 391 { STV090x_NBITER_NF10, 0x39 }, 392 { STV090x_NBITER_NF11, 0x3a }, 393 { STV090x_NBITER_NF12, 0x29 }, 394 { STV090x_NBITER_NF13, 0x37 }, 395 { STV090x_NBITER_NF14, 0x33 }, 396 { STV090x_NBITER_NF15, 0x2f }, 397 { STV090x_NBITER_NF16, 0x39 }, 398 { STV090x_NBITER_NF17, 0x3a }, 399 { STV090x_NBITERNOERR, 0x04 }, 400 { STV090x_GAINLLR_NF4, 0x0C }, 401 { STV090x_GAINLLR_NF5, 0x0F }, 402 { STV090x_GAINLLR_NF6, 0x11 }, 403 { STV090x_GAINLLR_NF7, 0x14 }, 404 { STV090x_GAINLLR_NF8, 0x17 }, 405 { STV090x_GAINLLR_NF9, 0x19 }, 406 { STV090x_GAINLLR_NF10, 0x20 }, 407 { STV090x_GAINLLR_NF11, 0x21 }, 408 { STV090x_GAINLLR_NF12, 0x0D }, 409 { STV090x_GAINLLR_NF13, 0x0F }, 410 { STV090x_GAINLLR_NF14, 0x13 }, 411 { STV090x_GAINLLR_NF15, 0x1A }, 412 { STV090x_GAINLLR_NF16, 0x1F }, 413 { STV090x_GAINLLR_NF17, 0x21 }, 414 { STV090x_RCCFGH, 0x20 }, 415 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ 416 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ 417 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ 418 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */ 419 }; 420 421 static struct stv090x_reg stv0903_initval[] = { 422 { STV090x_OUTCFG, 0x00 }, 423 { STV090x_AGCRF1CFG, 0x11 }, 424 { STV090x_STOPCLK1, 0x48 }, 425 { STV090x_STOPCLK2, 0x14 }, 426 { STV090x_TSTTNR1, 0x27 }, 427 { STV090x_TSTTNR2, 0x21 }, 428 { STV090x_P1_DISTXCTL, 0x22 }, 429 { STV090x_P1_F22TX, 0xc0 }, 430 { STV090x_P1_F22RX, 0xc0 }, 431 { STV090x_P1_DISRXCTL, 0x00 }, 432 { STV090x_P1_DMDCFGMD, 0xF9 }, 433 { STV090x_P1_DEMOD, 0x08 }, 434 { STV090x_P1_DMDCFG3, 0xc4 }, 435 { STV090x_P1_CARFREQ, 0xed }, 436 { STV090x_P1_TNRCFG2, 0x82 }, 437 { STV090x_P1_LDT, 0xd0 }, 438 { STV090x_P1_LDT2, 0xb8 }, 439 { STV090x_P1_TMGCFG, 0xd2 }, 440 { STV090x_P1_TMGTHRISE, 0x20 }, 441 { STV090x_P1_TMGTHFALL, 0x00 }, 442 { STV090x_P1_SFRUPRATIO, 0xf0 }, 443 { STV090x_P1_SFRLOWRATIO, 0x70 }, 444 { STV090x_P1_TSCFGL, 0x20 }, 445 { STV090x_P1_FECSPY, 0x88 }, 446 { STV090x_P1_FSPYDATA, 0x3a }, 447 { STV090x_P1_FBERCPT4, 0x00 }, 448 { STV090x_P1_FSPYBER, 0x10 }, 449 { STV090x_P1_ERRCTRL1, 0x35 }, 450 { STV090x_P1_ERRCTRL2, 0xc1 }, 451 { STV090x_P1_CFRICFG, 0xf8 }, 452 { STV090x_P1_NOSCFG, 0x1c }, 453 { STV090x_P1_DMDTOM, 0x20 }, 454 { STV090x_P1_CORRELMANT, 0x70 }, 455 { STV090x_P1_CORRELABS, 0x88 }, 456 { STV090x_P1_AGC2O, 0x5b }, 457 { STV090x_P1_AGC2REF, 0x38 }, 458 { STV090x_P1_CARCFG, 0xe4 }, 459 { STV090x_P1_ACLC, 0x1A }, 460 { STV090x_P1_BCLC, 0x09 }, 461 { STV090x_P1_CARHDR, 0x08 }, 462 { STV090x_P1_KREFTMG, 0xc1 }, 463 { STV090x_P1_SFRSTEP, 0x58 }, 464 { STV090x_P1_TMGCFG2, 0x01 }, 465 { STV090x_P1_CAR2CFG, 0x26 }, 466 { STV090x_P1_BCLC2S2Q, 0x86 }, 467 { STV090x_P1_BCLC2S28, 0x86 }, 468 { STV090x_P1_SMAPCOEF7, 0x77 }, 469 { STV090x_P1_SMAPCOEF6, 0x85 }, 470 { STV090x_P1_SMAPCOEF5, 0x77 }, 471 { STV090x_P1_DMDCFG2, 0x3b }, 472 { STV090x_P1_MODCODLST0, 0xff }, 473 { STV090x_P1_MODCODLST1, 0xff }, 474 { STV090x_P1_MODCODLST2, 0xff }, 475 { STV090x_P1_MODCODLST3, 0xff }, 476 { STV090x_P1_MODCODLST4, 0xff }, 477 { STV090x_P1_MODCODLST5, 0xff }, 478 { STV090x_P1_MODCODLST6, 0xff }, 479 { STV090x_P1_MODCODLST7, 0xcc }, 480 { STV090x_P1_MODCODLST8, 0xcc }, 481 { STV090x_P1_MODCODLST9, 0xcc }, 482 { STV090x_P1_MODCODLSTA, 0xcc }, 483 { STV090x_P1_MODCODLSTB, 0xcc }, 484 { STV090x_P1_MODCODLSTC, 0xcc }, 485 { STV090x_P1_MODCODLSTD, 0xcc }, 486 { STV090x_P1_MODCODLSTE, 0xcc }, 487 { STV090x_P1_MODCODLSTF, 0xcf }, 488 { STV090x_GENCFG, 0x1c }, 489 { STV090x_NBITER_NF4, 0x37 }, 490 { STV090x_NBITER_NF5, 0x29 }, 491 { STV090x_NBITER_NF6, 0x37 }, 492 { STV090x_NBITER_NF7, 0x33 }, 493 { STV090x_NBITER_NF8, 0x31 }, 494 { STV090x_NBITER_NF9, 0x2f }, 495 { STV090x_NBITER_NF10, 0x39 }, 496 { STV090x_NBITER_NF11, 0x3a }, 497 { STV090x_NBITER_NF12, 0x29 }, 498 { STV090x_NBITER_NF13, 0x37 }, 499 { STV090x_NBITER_NF14, 0x33 }, 500 { STV090x_NBITER_NF15, 0x2f }, 501 { STV090x_NBITER_NF16, 0x39 }, 502 { STV090x_NBITER_NF17, 0x3a }, 503 { STV090x_NBITERNOERR, 0x04 }, 504 { STV090x_GAINLLR_NF4, 0x0C }, 505 { STV090x_GAINLLR_NF5, 0x0F }, 506 { STV090x_GAINLLR_NF6, 0x11 }, 507 { STV090x_GAINLLR_NF7, 0x14 }, 508 { STV090x_GAINLLR_NF8, 0x17 }, 509 { STV090x_GAINLLR_NF9, 0x19 }, 510 { STV090x_GAINLLR_NF10, 0x20 }, 511 { STV090x_GAINLLR_NF11, 0x21 }, 512 { STV090x_GAINLLR_NF12, 0x0D }, 513 { STV090x_GAINLLR_NF13, 0x0F }, 514 { STV090x_GAINLLR_NF14, 0x13 }, 515 { STV090x_GAINLLR_NF15, 0x1A }, 516 { STV090x_GAINLLR_NF16, 0x1F }, 517 { STV090x_GAINLLR_NF17, 0x21 }, 518 { STV090x_RCCFGH, 0x20 }, 519 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ 520 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ 521 }; 522 523 static struct stv090x_reg stv0900_cut20_val[] = { 524 525 { STV090x_P2_DMDCFG3, 0xe8 }, 526 { STV090x_P2_DMDCFG4, 0x10 }, 527 { STV090x_P2_CARFREQ, 0x38 }, 528 { STV090x_P2_CARHDR, 0x20 }, 529 { STV090x_P2_KREFTMG, 0x5a }, 530 { STV090x_P2_SMAPCOEF7, 0x06 }, 531 { STV090x_P2_SMAPCOEF6, 0x00 }, 532 { STV090x_P2_SMAPCOEF5, 0x04 }, 533 { STV090x_P2_NOSCFG, 0x0c }, 534 { STV090x_P1_DMDCFG3, 0xe8 }, 535 { STV090x_P1_DMDCFG4, 0x10 }, 536 { STV090x_P1_CARFREQ, 0x38 }, 537 { STV090x_P1_CARHDR, 0x20 }, 538 { STV090x_P1_KREFTMG, 0x5a }, 539 { STV090x_P1_SMAPCOEF7, 0x06 }, 540 { STV090x_P1_SMAPCOEF6, 0x00 }, 541 { STV090x_P1_SMAPCOEF5, 0x04 }, 542 { STV090x_P1_NOSCFG, 0x0c }, 543 { STV090x_GAINLLR_NF4, 0x21 }, 544 { STV090x_GAINLLR_NF5, 0x21 }, 545 { STV090x_GAINLLR_NF6, 0x20 }, 546 { STV090x_GAINLLR_NF7, 0x1F }, 547 { STV090x_GAINLLR_NF8, 0x1E }, 548 { STV090x_GAINLLR_NF9, 0x1E }, 549 { STV090x_GAINLLR_NF10, 0x1D }, 550 { STV090x_GAINLLR_NF11, 0x1B }, 551 { STV090x_GAINLLR_NF12, 0x20 }, 552 { STV090x_GAINLLR_NF13, 0x20 }, 553 { STV090x_GAINLLR_NF14, 0x20 }, 554 { STV090x_GAINLLR_NF15, 0x20 }, 555 { STV090x_GAINLLR_NF16, 0x20 }, 556 { STV090x_GAINLLR_NF17, 0x21 }, 557 }; 558 559 static struct stv090x_reg stv0903_cut20_val[] = { 560 { STV090x_P1_DMDCFG3, 0xe8 }, 561 { STV090x_P1_DMDCFG4, 0x10 }, 562 { STV090x_P1_CARFREQ, 0x38 }, 563 { STV090x_P1_CARHDR, 0x20 }, 564 { STV090x_P1_KREFTMG, 0x5a }, 565 { STV090x_P1_SMAPCOEF7, 0x06 }, 566 { STV090x_P1_SMAPCOEF6, 0x00 }, 567 { STV090x_P1_SMAPCOEF5, 0x04 }, 568 { STV090x_P1_NOSCFG, 0x0c }, 569 { STV090x_GAINLLR_NF4, 0x21 }, 570 { STV090x_GAINLLR_NF5, 0x21 }, 571 { STV090x_GAINLLR_NF6, 0x20 }, 572 { STV090x_GAINLLR_NF7, 0x1F }, 573 { STV090x_GAINLLR_NF8, 0x1E }, 574 { STV090x_GAINLLR_NF9, 0x1E }, 575 { STV090x_GAINLLR_NF10, 0x1D }, 576 { STV090x_GAINLLR_NF11, 0x1B }, 577 { STV090x_GAINLLR_NF12, 0x20 }, 578 { STV090x_GAINLLR_NF13, 0x20 }, 579 { STV090x_GAINLLR_NF14, 0x20 }, 580 { STV090x_GAINLLR_NF15, 0x20 }, 581 { STV090x_GAINLLR_NF16, 0x20 }, 582 { STV090x_GAINLLR_NF17, 0x21 } 583 }; 584 585 /* Cut 2.0 Long Frame Tracking CR loop */ 586 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = { 587 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 588 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e }, 589 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e }, 590 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d }, 591 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 592 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 593 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 594 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 595 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 596 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d }, 597 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d }, 598 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d }, 599 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, 600 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, 601 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } 602 }; 603 604 /* Cut 3.0 Long Frame Tracking CR loop */ 605 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = { 606 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 607 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b }, 608 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 609 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 610 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 611 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 612 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 613 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 614 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 615 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 }, 616 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a }, 617 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a }, 618 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b }, 619 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b }, 620 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b } 621 }; 622 623 /* Cut 2.0 Long Frame Tracking CR Loop */ 624 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = { 625 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 626 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c }, 627 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c }, 628 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 629 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 630 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 631 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 632 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 633 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 634 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 635 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 636 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c } 637 }; 638 639 /* Cut 3.0 Long Frame Tracking CR Loop */ 640 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = { 641 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 642 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a }, 643 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a }, 644 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 645 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 646 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 647 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 648 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 649 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 650 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 651 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 652 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } 653 }; 654 655 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = { 656 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 657 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e }, 658 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e }, 659 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e } 660 }; 661 662 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = { 663 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 664 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b }, 665 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b }, 666 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b } 667 }; 668 669 /* Cut 2.0 Short Frame Tracking CR Loop */ 670 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { 671 /* MODCOD 2M 5M 10M 20M 30M */ 672 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d }, 673 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c }, 674 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }, 675 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d } 676 }; 677 678 /* Cut 3.0 Short Frame Tracking CR Loop */ 679 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { 680 /* MODCOD 2M 5M 10M 20M 30M */ 681 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, 682 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, 683 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, 684 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A } 685 }; 686 687 static inline s32 comp2(s32 __x, s32 __width) 688 { 689 if (__width == 32) 690 return __x; 691 else 692 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x; 693 } 694 695 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) 696 { 697 const struct stv090x_config *config = state->config; 698 int ret; 699 700 u8 b0[] = { reg >> 8, reg & 0xff }; 701 u8 buf; 702 703 struct i2c_msg msg[] = { 704 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, 705 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } 706 }; 707 708 ret = i2c_transfer(state->i2c, msg, 2); 709 if (ret != 2) { 710 if (ret != -ERESTARTSYS) 711 dprintk(FE_ERROR, 1, 712 "Read error, Reg=[0x%02x], Status=%d", 713 reg, ret); 714 715 return ret < 0 ? ret : -EREMOTEIO; 716 } 717 if (unlikely(*state->verbose >= FE_DEBUGREG)) 718 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x", 719 reg, buf); 720 721 return (unsigned int) buf; 722 } 723 724 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) 725 { 726 const struct stv090x_config *config = state->config; 727 int ret; 728 u8 buf[MAX_XFER_SIZE]; 729 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; 730 731 if (2 + count > sizeof(buf)) { 732 printk(KERN_WARNING 733 "%s: i2c wr reg=%04x: len=%d is too big!\n", 734 KBUILD_MODNAME, reg, count); 735 return -EINVAL; 736 } 737 738 buf[0] = reg >> 8; 739 buf[1] = reg & 0xff; 740 memcpy(&buf[2], data, count); 741 742 dprintk(FE_DEBUGREG, 1, "%s [0x%04x]: %*ph", 743 __func__, reg, count, data); 744 745 ret = i2c_transfer(state->i2c, &i2c_msg, 1); 746 if (ret != 1) { 747 if (ret != -ERESTARTSYS) 748 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", 749 reg, data[0], count, ret); 750 return ret < 0 ? ret : -EREMOTEIO; 751 } 752 753 return 0; 754 } 755 756 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) 757 { 758 return stv090x_write_regs(state, reg, &data, 1); 759 } 760 761 static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) 762 { 763 u32 reg; 764 765 /* 766 * NOTE! A lock is used as a FSM to control the state in which 767 * access is serialized between two tuners on the same demod. 768 * This has nothing to do with a lock to protect a critical section 769 * which may in some other cases be confused with protecting I/O 770 * access to the demodulator gate. 771 * In case of any error, the lock is unlocked and exit within the 772 * relevant operations themselves. 773 */ 774 if (enable) { 775 if (state->config->tuner_i2c_lock) 776 state->config->tuner_i2c_lock(&state->frontend, 1); 777 else 778 mutex_lock(&state->internal->tuner_lock); 779 } 780 781 reg = STV090x_READ_DEMOD(state, I2CRPT); 782 if (enable) { 783 dprintk(FE_DEBUG, 1, "Enable Gate"); 784 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); 785 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) 786 goto err; 787 788 } else { 789 dprintk(FE_DEBUG, 1, "Disable Gate"); 790 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); 791 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) 792 goto err; 793 } 794 795 if (!enable) { 796 if (state->config->tuner_i2c_lock) 797 state->config->tuner_i2c_lock(&state->frontend, 0); 798 else 799 mutex_unlock(&state->internal->tuner_lock); 800 } 801 802 return 0; 803 err: 804 dprintk(FE_ERROR, 1, "I/O error"); 805 if (state->config->tuner_i2c_lock) 806 state->config->tuner_i2c_lock(&state->frontend, 0); 807 else 808 mutex_unlock(&state->internal->tuner_lock); 809 return -1; 810 } 811 812 static void stv090x_get_lock_tmg(struct stv090x_state *state) 813 { 814 switch (state->algo) { 815 case STV090x_BLIND_SEARCH: 816 dprintk(FE_DEBUG, 1, "Blind Search"); 817 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ 818 state->DemodTimeout = 1500; 819 state->FecTimeout = 400; 820 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ 821 state->DemodTimeout = 1000; 822 state->FecTimeout = 300; 823 } else { /*SR >20Msps*/ 824 state->DemodTimeout = 700; 825 state->FecTimeout = 100; 826 } 827 break; 828 829 case STV090x_COLD_SEARCH: 830 case STV090x_WARM_SEARCH: 831 default: 832 dprintk(FE_DEBUG, 1, "Normal Search"); 833 if (state->srate <= 1000000) { /*SR <=1Msps*/ 834 state->DemodTimeout = 4500; 835 state->FecTimeout = 1700; 836 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ 837 state->DemodTimeout = 2500; 838 state->FecTimeout = 1100; 839 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ 840 state->DemodTimeout = 1000; 841 state->FecTimeout = 550; 842 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ 843 state->DemodTimeout = 700; 844 state->FecTimeout = 250; 845 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ 846 state->DemodTimeout = 400; 847 state->FecTimeout = 130; 848 } else { /*SR >20Msps*/ 849 state->DemodTimeout = 300; 850 state->FecTimeout = 100; 851 } 852 break; 853 } 854 855 if (state->algo == STV090x_WARM_SEARCH) 856 state->DemodTimeout /= 2; 857 } 858 859 static int stv090x_set_srate(struct stv090x_state *state, u32 srate) 860 { 861 u32 sym; 862 863 if (srate > 60000000) { 864 sym = (srate << 4); /* SR * 2^16 / master_clk */ 865 sym /= (state->internal->mclk >> 12); 866 } else if (srate > 6000000) { 867 sym = (srate << 6); 868 sym /= (state->internal->mclk >> 10); 869 } else { 870 sym = (srate << 9); 871 sym /= (state->internal->mclk >> 7); 872 } 873 874 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ 875 goto err; 876 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ 877 goto err; 878 879 return 0; 880 err: 881 dprintk(FE_ERROR, 1, "I/O error"); 882 return -1; 883 } 884 885 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) 886 { 887 u32 sym; 888 889 srate = 105 * (srate / 100); 890 if (srate > 60000000) { 891 sym = (srate << 4); /* SR * 2^16 / master_clk */ 892 sym /= (state->internal->mclk >> 12); 893 } else if (srate > 6000000) { 894 sym = (srate << 6); 895 sym /= (state->internal->mclk >> 10); 896 } else { 897 sym = (srate << 9); 898 sym /= (state->internal->mclk >> 7); 899 } 900 901 if (sym < 0x7fff) { 902 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ 903 goto err; 904 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ 905 goto err; 906 } else { 907 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ 908 goto err; 909 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ 910 goto err; 911 } 912 913 return 0; 914 err: 915 dprintk(FE_ERROR, 1, "I/O error"); 916 return -1; 917 } 918 919 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) 920 { 921 u32 sym; 922 923 srate = 95 * (srate / 100); 924 if (srate > 60000000) { 925 sym = (srate << 4); /* SR * 2^16 / master_clk */ 926 sym /= (state->internal->mclk >> 12); 927 } else if (srate > 6000000) { 928 sym = (srate << 6); 929 sym /= (state->internal->mclk >> 10); 930 } else { 931 sym = (srate << 9); 932 sym /= (state->internal->mclk >> 7); 933 } 934 935 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ 936 goto err; 937 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ 938 goto err; 939 return 0; 940 err: 941 dprintk(FE_ERROR, 1, "I/O error"); 942 return -1; 943 } 944 945 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff) 946 { 947 u32 ro; 948 949 switch (rolloff) { 950 case STV090x_RO_20: 951 ro = 20; 952 break; 953 case STV090x_RO_25: 954 ro = 25; 955 break; 956 case STV090x_RO_35: 957 default: 958 ro = 35; 959 break; 960 } 961 962 return srate + (srate * ro) / 100; 963 } 964 965 static int stv090x_set_vit_thacq(struct stv090x_state *state) 966 { 967 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) 968 goto err; 969 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) 970 goto err; 971 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) 972 goto err; 973 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) 974 goto err; 975 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) 976 goto err; 977 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) 978 goto err; 979 return 0; 980 err: 981 dprintk(FE_ERROR, 1, "I/O error"); 982 return -1; 983 } 984 985 static int stv090x_set_vit_thtracq(struct stv090x_state *state) 986 { 987 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) 988 goto err; 989 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) 990 goto err; 991 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) 992 goto err; 993 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) 994 goto err; 995 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) 996 goto err; 997 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) 998 goto err; 999 return 0; 1000 err: 1001 dprintk(FE_ERROR, 1, "I/O error"); 1002 return -1; 1003 } 1004 1005 static int stv090x_set_viterbi(struct stv090x_state *state) 1006 { 1007 switch (state->search_mode) { 1008 case STV090x_SEARCH_AUTO: 1009 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ 1010 goto err; 1011 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ 1012 goto err; 1013 break; 1014 case STV090x_SEARCH_DVBS1: 1015 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ 1016 goto err; 1017 switch (state->fec) { 1018 case STV090x_PR12: 1019 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1020 goto err; 1021 break; 1022 1023 case STV090x_PR23: 1024 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1025 goto err; 1026 break; 1027 1028 case STV090x_PR34: 1029 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) 1030 goto err; 1031 break; 1032 1033 case STV090x_PR56: 1034 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) 1035 goto err; 1036 break; 1037 1038 case STV090x_PR78: 1039 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) 1040 goto err; 1041 break; 1042 1043 default: 1044 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ 1045 goto err; 1046 break; 1047 } 1048 break; 1049 case STV090x_SEARCH_DSS: 1050 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) 1051 goto err; 1052 switch (state->fec) { 1053 case STV090x_PR12: 1054 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1055 goto err; 1056 break; 1057 1058 case STV090x_PR23: 1059 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1060 goto err; 1061 break; 1062 1063 case STV090x_PR67: 1064 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) 1065 goto err; 1066 break; 1067 1068 default: 1069 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ 1070 goto err; 1071 break; 1072 } 1073 break; 1074 default: 1075 break; 1076 } 1077 return 0; 1078 err: 1079 dprintk(FE_ERROR, 1, "I/O error"); 1080 return -1; 1081 } 1082 1083 static int stv090x_stop_modcod(struct stv090x_state *state) 1084 { 1085 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1086 goto err; 1087 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 1088 goto err; 1089 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 1090 goto err; 1091 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 1092 goto err; 1093 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 1094 goto err; 1095 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 1096 goto err; 1097 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 1098 goto err; 1099 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) 1100 goto err; 1101 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) 1102 goto err; 1103 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) 1104 goto err; 1105 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) 1106 goto err; 1107 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) 1108 goto err; 1109 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) 1110 goto err; 1111 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) 1112 goto err; 1113 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 1114 goto err; 1115 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) 1116 goto err; 1117 return 0; 1118 err: 1119 dprintk(FE_ERROR, 1, "I/O error"); 1120 return -1; 1121 } 1122 1123 static int stv090x_activate_modcod(struct stv090x_state *state) 1124 { 1125 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1126 goto err; 1127 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) 1128 goto err; 1129 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) 1130 goto err; 1131 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) 1132 goto err; 1133 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) 1134 goto err; 1135 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) 1136 goto err; 1137 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) 1138 goto err; 1139 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 1140 goto err; 1141 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 1142 goto err; 1143 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 1144 goto err; 1145 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 1146 goto err; 1147 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 1148 goto err; 1149 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 1150 goto err; 1151 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 1152 goto err; 1153 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) 1154 goto err; 1155 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 1156 goto err; 1157 1158 return 0; 1159 err: 1160 dprintk(FE_ERROR, 1, "I/O error"); 1161 return -1; 1162 } 1163 1164 static int stv090x_activate_modcod_single(struct stv090x_state *state) 1165 { 1166 1167 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1168 goto err; 1169 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) 1170 goto err; 1171 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) 1172 goto err; 1173 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) 1174 goto err; 1175 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) 1176 goto err; 1177 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) 1178 goto err; 1179 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) 1180 goto err; 1181 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) 1182 goto err; 1183 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) 1184 goto err; 1185 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) 1186 goto err; 1187 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) 1188 goto err; 1189 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) 1190 goto err; 1191 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) 1192 goto err; 1193 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) 1194 goto err; 1195 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) 1196 goto err; 1197 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) 1198 goto err; 1199 1200 return 0; 1201 1202 err: 1203 dprintk(FE_ERROR, 1, "I/O error"); 1204 return -1; 1205 } 1206 1207 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) 1208 { 1209 u32 reg; 1210 1211 switch (state->demod) { 1212 case STV090x_DEMODULATOR_0: 1213 mutex_lock(&state->internal->demod_lock); 1214 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1215 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); 1216 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1217 goto err; 1218 mutex_unlock(&state->internal->demod_lock); 1219 break; 1220 1221 case STV090x_DEMODULATOR_1: 1222 mutex_lock(&state->internal->demod_lock); 1223 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1224 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); 1225 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1226 goto err; 1227 mutex_unlock(&state->internal->demod_lock); 1228 break; 1229 1230 default: 1231 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 1232 break; 1233 } 1234 return 0; 1235 err: 1236 mutex_unlock(&state->internal->demod_lock); 1237 dprintk(FE_ERROR, 1, "I/O error"); 1238 return -1; 1239 } 1240 1241 static int stv090x_dvbs_track_crl(struct stv090x_state *state) 1242 { 1243 if (state->internal->dev_ver >= 0x30) { 1244 /* Set ACLC BCLC optimised value vs SR */ 1245 if (state->srate >= 15000000) { 1246 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) 1247 goto err; 1248 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) 1249 goto err; 1250 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { 1251 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) 1252 goto err; 1253 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) 1254 goto err; 1255 } else if (state->srate < 7000000) { 1256 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) 1257 goto err; 1258 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) 1259 goto err; 1260 } 1261 1262 } else { 1263 /* Cut 2.0 */ 1264 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) 1265 goto err; 1266 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1267 goto err; 1268 } 1269 return 0; 1270 err: 1271 dprintk(FE_ERROR, 1, "I/O error"); 1272 return -1; 1273 } 1274 1275 static int stv090x_delivery_search(struct stv090x_state *state) 1276 { 1277 u32 reg; 1278 1279 switch (state->search_mode) { 1280 case STV090x_SEARCH_DVBS1: 1281 case STV090x_SEARCH_DSS: 1282 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1283 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1284 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1285 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1286 goto err; 1287 1288 /* Activate Viterbi decoder in legacy search, 1289 * do not use FRESVIT1, might impact VITERBI2 1290 */ 1291 if (stv090x_vitclk_ctl(state, 0) < 0) 1292 goto err; 1293 1294 if (stv090x_dvbs_track_crl(state) < 0) 1295 goto err; 1296 1297 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ 1298 goto err; 1299 1300 if (stv090x_set_vit_thacq(state) < 0) 1301 goto err; 1302 if (stv090x_set_viterbi(state) < 0) 1303 goto err; 1304 break; 1305 1306 case STV090x_SEARCH_DVBS2: 1307 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1308 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1309 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1310 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1311 goto err; 1312 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1313 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1314 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1315 goto err; 1316 1317 if (stv090x_vitclk_ctl(state, 1) < 0) 1318 goto err; 1319 1320 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ 1321 goto err; 1322 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1323 goto err; 1324 1325 if (state->internal->dev_ver <= 0x20) { 1326 /* enable S2 carrier loop */ 1327 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1328 goto err; 1329 } else { 1330 /* > Cut 3: Stop carrier 3 */ 1331 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1332 goto err; 1333 } 1334 1335 if (state->demod_mode != STV090x_SINGLE) { 1336 /* Cut 2: enable link during search */ 1337 if (stv090x_activate_modcod(state) < 0) 1338 goto err; 1339 } else { 1340 /* Single demodulator 1341 * Authorize SHORT and LONG frames, 1342 * QPSK, 8PSK, 16APSK and 32APSK 1343 */ 1344 if (stv090x_activate_modcod_single(state) < 0) 1345 goto err; 1346 } 1347 1348 if (stv090x_set_vit_thtracq(state) < 0) 1349 goto err; 1350 break; 1351 1352 case STV090x_SEARCH_AUTO: 1353 default: 1354 /* enable DVB-S2 and DVB-S2 in Auto MODE */ 1355 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1356 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1357 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1358 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1359 goto err; 1360 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1361 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1362 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1363 goto err; 1364 1365 if (stv090x_vitclk_ctl(state, 0) < 0) 1366 goto err; 1367 1368 if (stv090x_dvbs_track_crl(state) < 0) 1369 goto err; 1370 1371 if (state->internal->dev_ver <= 0x20) { 1372 /* enable S2 carrier loop */ 1373 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1374 goto err; 1375 } else { 1376 /* > Cut 3: Stop carrier 3 */ 1377 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1378 goto err; 1379 } 1380 1381 if (state->demod_mode != STV090x_SINGLE) { 1382 /* Cut 2: enable link during search */ 1383 if (stv090x_activate_modcod(state) < 0) 1384 goto err; 1385 } else { 1386 /* Single demodulator 1387 * Authorize SHORT and LONG frames, 1388 * QPSK, 8PSK, 16APSK and 32APSK 1389 */ 1390 if (stv090x_activate_modcod_single(state) < 0) 1391 goto err; 1392 } 1393 1394 if (stv090x_set_vit_thacq(state) < 0) 1395 goto err; 1396 1397 if (stv090x_set_viterbi(state) < 0) 1398 goto err; 1399 break; 1400 } 1401 return 0; 1402 err: 1403 dprintk(FE_ERROR, 1, "I/O error"); 1404 return -1; 1405 } 1406 1407 static int stv090x_start_search(struct stv090x_state *state) 1408 { 1409 u32 reg, freq_abs; 1410 s16 freq; 1411 1412 /* Reset demodulator */ 1413 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1414 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); 1415 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1416 goto err; 1417 1418 if (state->internal->dev_ver <= 0x20) { 1419 if (state->srate <= 5000000) { 1420 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) 1421 goto err; 1422 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) 1423 goto err; 1424 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) 1425 goto err; 1426 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) 1427 goto err; 1428 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) 1429 goto err; 1430 1431 /*enlarge the timing bandwidth for Low SR*/ 1432 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) 1433 goto err; 1434 } else { 1435 /* If the symbol rate is >5 Msps 1436 Set The carrier search up and low to auto mode */ 1437 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 1438 goto err; 1439 /*reduce the timing bandwidth for high SR*/ 1440 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 1441 goto err; 1442 } 1443 } else { 1444 /* >= Cut 3 */ 1445 if (state->srate <= 5000000) { 1446 /* enlarge the timing bandwidth for Low SR */ 1447 STV090x_WRITE_DEMOD(state, RTCS2, 0x68); 1448 } else { 1449 /* reduce timing bandwidth for high SR */ 1450 STV090x_WRITE_DEMOD(state, RTCS2, 0x44); 1451 } 1452 1453 /* Set CFR min and max to manual mode */ 1454 STV090x_WRITE_DEMOD(state, CARCFG, 0x46); 1455 1456 if (state->algo == STV090x_WARM_SEARCH) { 1457 /* WARM Start 1458 * CFR min = -1MHz, 1459 * CFR max = +1MHz 1460 */ 1461 freq_abs = 1000 << 16; 1462 freq_abs /= (state->internal->mclk / 1000); 1463 freq = (s16) freq_abs; 1464 } else { 1465 /* COLD Start 1466 * CFR min =- (SearchRange / 2 + 600KHz) 1467 * CFR max = +(SearchRange / 2 + 600KHz) 1468 * (600KHz for the tuner step size) 1469 */ 1470 freq_abs = (state->search_range / 2000) + 600; 1471 freq_abs = freq_abs << 16; 1472 freq_abs /= (state->internal->mclk / 1000); 1473 freq = (s16) freq_abs; 1474 } 1475 1476 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) 1477 goto err; 1478 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) 1479 goto err; 1480 1481 freq *= -1; 1482 1483 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) 1484 goto err; 1485 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) 1486 goto err; 1487 1488 } 1489 1490 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) 1491 goto err; 1492 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) 1493 goto err; 1494 1495 if (state->internal->dev_ver >= 0x20) { 1496 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 1497 goto err; 1498 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 1499 goto err; 1500 1501 if ((state->search_mode == STV090x_SEARCH_DVBS1) || 1502 (state->search_mode == STV090x_SEARCH_DSS) || 1503 (state->search_mode == STV090x_SEARCH_AUTO)) { 1504 1505 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 1506 goto err; 1507 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) 1508 goto err; 1509 } 1510 } 1511 1512 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) 1513 goto err; 1514 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) 1515 goto err; 1516 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) 1517 goto err; 1518 1519 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1520 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1521 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1522 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1523 goto err; 1524 reg = STV090x_READ_DEMOD(state, DMDCFG2); 1525 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); 1526 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) 1527 goto err; 1528 1529 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) 1530 goto err; 1531 1532 if (state->internal->dev_ver >= 0x20) { 1533 /*Frequency offset detector setting*/ 1534 if (state->srate < 2000000) { 1535 if (state->internal->dev_ver <= 0x20) { 1536 /* Cut 2 */ 1537 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) 1538 goto err; 1539 } else { 1540 /* Cut 3 */ 1541 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) 1542 goto err; 1543 } 1544 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) 1545 goto err; 1546 } else if (state->srate < 10000000) { 1547 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) 1548 goto err; 1549 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1550 goto err; 1551 } else { 1552 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) 1553 goto err; 1554 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1555 goto err; 1556 } 1557 } else { 1558 if (state->srate < 10000000) { 1559 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) 1560 goto err; 1561 } else { 1562 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) 1563 goto err; 1564 } 1565 } 1566 1567 switch (state->algo) { 1568 case STV090x_WARM_SEARCH: 1569 /* The symbol rate and the exact 1570 * carrier Frequency are known 1571 */ 1572 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1573 goto err; 1574 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 1575 goto err; 1576 break; 1577 1578 case STV090x_COLD_SEARCH: 1579 /* The symbol rate is known */ 1580 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1581 goto err; 1582 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 1583 goto err; 1584 break; 1585 1586 default: 1587 break; 1588 } 1589 return 0; 1590 err: 1591 dprintk(FE_ERROR, 1, "I/O error"); 1592 return -1; 1593 } 1594 1595 static int stv090x_get_agc2_min_level(struct stv090x_state *state) 1596 { 1597 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; 1598 s32 i, j, steps, dir; 1599 1600 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1601 goto err; 1602 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1603 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1604 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1605 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1606 goto err; 1607 1608 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ 1609 goto err; 1610 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1611 goto err; 1612 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ 1613 goto err; 1614 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1615 goto err; 1616 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ 1617 goto err; 1618 if (stv090x_set_srate(state, 1000000) < 0) 1619 goto err; 1620 1621 steps = state->search_range / 1000000; 1622 if (steps <= 0) 1623 steps = 1; 1624 1625 dir = 1; 1626 freq_step = (1000000 * 256) / (state->internal->mclk / 256); 1627 freq_init = 0; 1628 1629 for (i = 0; i < steps; i++) { 1630 if (dir > 0) 1631 freq_init = freq_init + (freq_step * i); 1632 else 1633 freq_init = freq_init - (freq_step * i); 1634 1635 dir *= -1; 1636 1637 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ 1638 goto err; 1639 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) 1640 goto err; 1641 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) 1642 goto err; 1643 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ 1644 goto err; 1645 msleep(10); 1646 1647 agc2 = 0; 1648 for (j = 0; j < 10; j++) { 1649 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1650 STV090x_READ_DEMOD(state, AGC2I0); 1651 } 1652 agc2 /= 10; 1653 if (agc2 < agc2_min) 1654 agc2_min = agc2; 1655 } 1656 1657 return agc2_min; 1658 err: 1659 dprintk(FE_ERROR, 1, "I/O error"); 1660 return -1; 1661 } 1662 1663 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) 1664 { 1665 u8 r3, r2, r1, r0; 1666 s32 srate, int_1, int_2, tmp_1, tmp_2; 1667 1668 r3 = STV090x_READ_DEMOD(state, SFR3); 1669 r2 = STV090x_READ_DEMOD(state, SFR2); 1670 r1 = STV090x_READ_DEMOD(state, SFR1); 1671 r0 = STV090x_READ_DEMOD(state, SFR0); 1672 1673 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0); 1674 1675 int_1 = clk >> 16; 1676 int_2 = srate >> 16; 1677 1678 tmp_1 = clk % 0x10000; 1679 tmp_2 = srate % 0x10000; 1680 1681 srate = (int_1 * int_2) + 1682 ((int_1 * tmp_2) >> 16) + 1683 ((int_2 * tmp_1) >> 16); 1684 1685 return srate; 1686 } 1687 1688 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) 1689 { 1690 struct dvb_frontend *fe = &state->frontend; 1691 1692 int tmg_lock = 0, i; 1693 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; 1694 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; 1695 u32 agc2th; 1696 1697 if (state->internal->dev_ver >= 0x30) 1698 agc2th = 0x2e00; 1699 else 1700 agc2th = 0x1f00; 1701 1702 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1703 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ 1704 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1705 goto err; 1706 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) 1707 goto err; 1708 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) 1709 goto err; 1710 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) 1711 goto err; 1712 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) 1713 goto err; 1714 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1715 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); 1716 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1717 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1718 goto err; 1719 1720 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) 1721 goto err; 1722 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1723 goto err; 1724 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) 1725 goto err; 1726 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1727 goto err; 1728 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) 1729 goto err; 1730 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) 1731 goto err; 1732 1733 if (state->internal->dev_ver >= 0x30) { 1734 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) 1735 goto err; 1736 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) 1737 goto err; 1738 1739 } else if (state->internal->dev_ver >= 0x20) { 1740 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) 1741 goto err; 1742 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) 1743 goto err; 1744 } 1745 1746 if (state->srate <= 2000000) 1747 car_step = 1000; 1748 else if (state->srate <= 5000000) 1749 car_step = 2000; 1750 else if (state->srate <= 12000000) 1751 car_step = 3000; 1752 else 1753 car_step = 5000; 1754 1755 steps = -1 + ((state->search_range / 1000) / car_step); 1756 steps /= 2; 1757 steps = (2 * steps) + 1; 1758 if (steps < 0) 1759 steps = 1; 1760 else if (steps > 10) { 1761 steps = 11; 1762 car_step = (state->search_range / 1000) / 10; 1763 } 1764 cur_step = 0; 1765 dir = 1; 1766 freq = state->frequency; 1767 1768 while ((!tmg_lock) && (cur_step < steps)) { 1769 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ 1770 goto err; 1771 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 1772 goto err; 1773 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 1774 goto err; 1775 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) 1776 goto err; 1777 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) 1778 goto err; 1779 /* trigger acquisition */ 1780 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) 1781 goto err; 1782 msleep(50); 1783 for (i = 0; i < 10; i++) { 1784 reg = STV090x_READ_DEMOD(state, DSTATUS); 1785 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 1786 tmg_cpt++; 1787 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1788 STV090x_READ_DEMOD(state, AGC2I0); 1789 } 1790 agc2 /= 10; 1791 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1792 cur_step++; 1793 dir *= -1; 1794 if ((tmg_cpt >= 5) && (agc2 < agc2th) && 1795 (srate_coarse < 50000000) && (srate_coarse > 850000)) 1796 tmg_lock = 1; 1797 else if (cur_step < steps) { 1798 if (dir > 0) 1799 freq += cur_step * car_step; 1800 else 1801 freq -= cur_step * car_step; 1802 1803 /* Setup tuner */ 1804 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1805 goto err; 1806 1807 if (state->config->tuner_set_frequency) { 1808 if (state->config->tuner_set_frequency(fe, freq) < 0) 1809 goto err_gateoff; 1810 } 1811 1812 if (state->config->tuner_set_bandwidth) { 1813 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 1814 goto err_gateoff; 1815 } 1816 1817 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1818 goto err; 1819 1820 msleep(50); 1821 1822 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1823 goto err; 1824 1825 if (state->config->tuner_get_status) { 1826 if (state->config->tuner_get_status(fe, ®) < 0) 1827 goto err_gateoff; 1828 } 1829 1830 if (reg) 1831 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 1832 else 1833 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 1834 1835 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1836 goto err; 1837 1838 } 1839 } 1840 if (!tmg_lock) 1841 srate_coarse = 0; 1842 else 1843 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1844 1845 return srate_coarse; 1846 1847 err_gateoff: 1848 stv090x_i2c_gate_ctrl(state, 0); 1849 err: 1850 dprintk(FE_ERROR, 1, "I/O error"); 1851 return -1; 1852 } 1853 1854 static u32 stv090x_srate_srch_fine(struct stv090x_state *state) 1855 { 1856 u32 srate_coarse, freq_coarse, sym, reg; 1857 1858 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1859 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; 1860 freq_coarse |= STV090x_READ_DEMOD(state, CFR1); 1861 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1862 1863 if (sym < state->srate) 1864 srate_coarse = 0; 1865 else { 1866 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ 1867 goto err; 1868 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 1869 goto err; 1870 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 1871 goto err; 1872 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 1873 goto err; 1874 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 1875 goto err; 1876 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1877 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 1878 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1879 goto err; 1880 1881 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1882 goto err; 1883 1884 if (state->internal->dev_ver >= 0x30) { 1885 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) 1886 goto err; 1887 } else if (state->internal->dev_ver >= 0x20) { 1888 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 1889 goto err; 1890 } 1891 1892 if (srate_coarse > 3000000) { 1893 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1894 sym = (sym / 1000) * 65536; 1895 sym /= (state->internal->mclk / 1000); 1896 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1897 goto err; 1898 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1899 goto err; 1900 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */ 1901 sym = (sym / 1000) * 65536; 1902 sym /= (state->internal->mclk / 1000); 1903 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1904 goto err; 1905 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1906 goto err; 1907 sym = (srate_coarse / 1000) * 65536; 1908 sym /= (state->internal->mclk / 1000); 1909 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1910 goto err; 1911 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1912 goto err; 1913 } else { 1914 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1915 sym = (sym / 100) * 65536; 1916 sym /= (state->internal->mclk / 100); 1917 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1918 goto err; 1919 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1920 goto err; 1921 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */ 1922 sym = (sym / 100) * 65536; 1923 sym /= (state->internal->mclk / 100); 1924 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1925 goto err; 1926 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1927 goto err; 1928 sym = (srate_coarse / 100) * 65536; 1929 sym /= (state->internal->mclk / 100); 1930 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1931 goto err; 1932 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1933 goto err; 1934 } 1935 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 1936 goto err; 1937 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) 1938 goto err; 1939 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) 1940 goto err; 1941 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ 1942 goto err; 1943 } 1944 1945 return srate_coarse; 1946 1947 err: 1948 dprintk(FE_ERROR, 1, "I/O error"); 1949 return -1; 1950 } 1951 1952 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) 1953 { 1954 s32 timer = 0, lock = 0; 1955 u32 reg; 1956 u8 stat; 1957 1958 while ((timer < timeout) && (!lock)) { 1959 reg = STV090x_READ_DEMOD(state, DMDSTATE); 1960 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 1961 1962 switch (stat) { 1963 case 0: /* searching */ 1964 case 1: /* first PLH detected */ 1965 default: 1966 dprintk(FE_DEBUG, 1, "Demodulator searching .."); 1967 lock = 0; 1968 break; 1969 case 2: /* DVB-S2 mode */ 1970 case 3: /* DVB-S1/legacy mode */ 1971 reg = STV090x_READ_DEMOD(state, DSTATUS); 1972 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 1973 break; 1974 } 1975 1976 if (!lock) 1977 msleep(10); 1978 else 1979 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK"); 1980 1981 timer += 10; 1982 } 1983 return lock; 1984 } 1985 1986 static int stv090x_blind_search(struct stv090x_state *state) 1987 { 1988 u32 agc2, reg, srate_coarse; 1989 s32 cpt_fail, agc2_ovflw, i; 1990 u8 k_ref, k_max, k_min; 1991 int coarse_fail = 0; 1992 int lock; 1993 1994 k_max = 110; 1995 k_min = 10; 1996 1997 agc2 = stv090x_get_agc2_min_level(state); 1998 1999 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { 2000 lock = 0; 2001 } else { 2002 2003 if (state->internal->dev_ver <= 0x20) { 2004 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 2005 goto err; 2006 } else { 2007 /* > Cut 3 */ 2008 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) 2009 goto err; 2010 } 2011 2012 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 2013 goto err; 2014 2015 if (state->internal->dev_ver >= 0x20) { 2016 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 2017 goto err; 2018 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 2019 goto err; 2020 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 2021 goto err; 2022 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ 2023 goto err; 2024 } 2025 2026 k_ref = k_max; 2027 do { 2028 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) 2029 goto err; 2030 if (stv090x_srate_srch_coarse(state) != 0) { 2031 srate_coarse = stv090x_srate_srch_fine(state); 2032 if (srate_coarse != 0) { 2033 stv090x_get_lock_tmg(state); 2034 lock = stv090x_get_dmdlock(state, 2035 state->DemodTimeout); 2036 } else { 2037 lock = 0; 2038 } 2039 } else { 2040 cpt_fail = 0; 2041 agc2_ovflw = 0; 2042 for (i = 0; i < 10; i++) { 2043 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 2044 STV090x_READ_DEMOD(state, AGC2I0); 2045 if (agc2 >= 0xff00) 2046 agc2_ovflw++; 2047 reg = STV090x_READ_DEMOD(state, DSTATUS2); 2048 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && 2049 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) 2050 2051 cpt_fail++; 2052 } 2053 if ((cpt_fail > 7) || (agc2_ovflw > 7)) 2054 coarse_fail = 1; 2055 2056 lock = 0; 2057 } 2058 k_ref -= 20; 2059 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); 2060 } 2061 2062 return lock; 2063 2064 err: 2065 dprintk(FE_ERROR, 1, "I/O error"); 2066 return -1; 2067 } 2068 2069 static int stv090x_chk_tmg(struct stv090x_state *state) 2070 { 2071 u32 reg; 2072 s32 tmg_cpt = 0, i; 2073 u8 freq, tmg_thh, tmg_thl; 2074 int tmg_lock = 0; 2075 2076 freq = STV090x_READ_DEMOD(state, CARFREQ); 2077 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); 2078 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); 2079 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 2080 goto err; 2081 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 2082 goto err; 2083 2084 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2085 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ 2086 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2087 goto err; 2088 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) 2089 goto err; 2090 2091 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) 2092 goto err; 2093 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) 2094 goto err; 2095 2096 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ 2097 goto err; 2098 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2099 goto err; 2100 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) 2101 goto err; 2102 2103 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ 2104 goto err; 2105 msleep(10); 2106 2107 for (i = 0; i < 10; i++) { 2108 reg = STV090x_READ_DEMOD(state, DSTATUS); 2109 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 2110 tmg_cpt++; 2111 msleep(1); 2112 } 2113 if (tmg_cpt >= 3) 2114 tmg_lock = 1; 2115 2116 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 2117 goto err; 2118 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ 2119 goto err; 2120 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ 2121 goto err; 2122 2123 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) 2124 goto err; 2125 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) 2126 goto err; 2127 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) 2128 goto err; 2129 2130 return tmg_lock; 2131 2132 err: 2133 dprintk(FE_ERROR, 1, "I/O error"); 2134 return -1; 2135 } 2136 2137 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) 2138 { 2139 struct dvb_frontend *fe = &state->frontend; 2140 2141 u32 reg; 2142 s32 car_step, steps, cur_step, dir, freq, timeout_lock; 2143 int lock; 2144 2145 if (state->srate >= 10000000) 2146 timeout_lock = timeout_dmd / 3; 2147 else 2148 timeout_lock = timeout_dmd / 2; 2149 2150 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ 2151 if (lock) 2152 return lock; 2153 2154 if (state->srate >= 10000000) { 2155 if (stv090x_chk_tmg(state)) { 2156 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2157 goto err; 2158 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2159 goto err; 2160 return stv090x_get_dmdlock(state, timeout_dmd); 2161 } 2162 return 0; 2163 } 2164 2165 if (state->srate <= 4000000) 2166 car_step = 1000; 2167 else if (state->srate <= 7000000) 2168 car_step = 2000; 2169 else if (state->srate <= 10000000) 2170 car_step = 3000; 2171 else 2172 car_step = 5000; 2173 2174 steps = (state->search_range / 1000) / car_step; 2175 steps /= 2; 2176 steps = 2 * (steps + 1); 2177 if (steps < 0) 2178 steps = 2; 2179 else if (steps > 12) 2180 steps = 12; 2181 2182 cur_step = 1; 2183 dir = 1; 2184 2185 freq = state->frequency; 2186 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; 2187 while ((cur_step <= steps) && (!lock)) { 2188 if (dir > 0) 2189 freq += cur_step * car_step; 2190 else 2191 freq -= cur_step * car_step; 2192 2193 /* Setup tuner */ 2194 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2195 goto err; 2196 2197 if (state->config->tuner_set_frequency) { 2198 if (state->config->tuner_set_frequency(fe, freq) < 0) 2199 goto err_gateoff; 2200 } 2201 2202 if (state->config->tuner_set_bandwidth) { 2203 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 2204 goto err_gateoff; 2205 } 2206 2207 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2208 goto err; 2209 2210 msleep(50); 2211 2212 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2213 goto err; 2214 2215 if (state->config->tuner_get_status) { 2216 if (state->config->tuner_get_status(fe, ®) < 0) 2217 goto err_gateoff; 2218 } 2219 2220 if (reg) 2221 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 2222 else 2223 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 2224 2225 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2226 goto err; 2227 2228 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); 2229 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 2230 goto err; 2231 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2232 goto err; 2233 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2234 goto err; 2235 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2236 goto err; 2237 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); 2238 2239 dir *= -1; 2240 cur_step++; 2241 } 2242 2243 return lock; 2244 2245 err_gateoff: 2246 stv090x_i2c_gate_ctrl(state, 0); 2247 err: 2248 dprintk(FE_ERROR, 1, "I/O error"); 2249 return -1; 2250 } 2251 2252 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) 2253 { 2254 s32 timeout, inc, steps_max, srate, car_max; 2255 2256 srate = state->srate; 2257 car_max = state->search_range / 1000; 2258 car_max += car_max / 10; 2259 car_max = 65536 * (car_max / 2); 2260 car_max /= (state->internal->mclk / 1000); 2261 2262 if (car_max > 0x4000) 2263 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */ 2264 2265 inc = srate; 2266 inc /= state->internal->mclk / 1000; 2267 inc *= 256; 2268 inc *= 256; 2269 inc /= 1000; 2270 2271 switch (state->search_mode) { 2272 case STV090x_SEARCH_DVBS1: 2273 case STV090x_SEARCH_DSS: 2274 inc *= 3; /* freq step = 3% of srate */ 2275 timeout = 20; 2276 break; 2277 2278 case STV090x_SEARCH_DVBS2: 2279 inc *= 4; 2280 timeout = 25; 2281 break; 2282 2283 case STV090x_SEARCH_AUTO: 2284 default: 2285 inc *= 3; 2286 timeout = 25; 2287 break; 2288 } 2289 inc /= 100; 2290 if ((inc > car_max) || (inc < 0)) 2291 inc = car_max / 2; /* increment <= 1/8 Mclk */ 2292 2293 timeout *= 27500; /* 27.5 Msps reference */ 2294 if (srate > 0) 2295 timeout /= (srate / 1000); 2296 2297 if ((timeout > 100) || (timeout < 0)) 2298 timeout = 100; 2299 2300 steps_max = (car_max / inc) + 1; /* min steps = 3 */ 2301 if ((steps_max > 100) || (steps_max < 0)) { 2302 steps_max = 100; /* max steps <= 100 */ 2303 inc = car_max / steps_max; 2304 } 2305 *freq_inc = inc; 2306 *timeout_sw = timeout; 2307 *steps = steps_max; 2308 2309 return 0; 2310 } 2311 2312 static int stv090x_chk_signal(struct stv090x_state *state) 2313 { 2314 s32 offst_car, agc2, car_max; 2315 int no_signal; 2316 2317 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; 2318 offst_car |= STV090x_READ_DEMOD(state, CFR1); 2319 offst_car = comp2(offst_car, 16); 2320 2321 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; 2322 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); 2323 car_max = state->search_range / 1000; 2324 2325 car_max += (car_max / 10); /* 10% margin */ 2326 car_max = (65536 * car_max / 2); 2327 car_max /= state->internal->mclk / 1000; 2328 2329 if (car_max > 0x4000) 2330 car_max = 0x4000; 2331 2332 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) { 2333 no_signal = 1; 2334 dprintk(FE_DEBUG, 1, "No Signal"); 2335 } else { 2336 no_signal = 0; 2337 dprintk(FE_DEBUG, 1, "Found Signal"); 2338 } 2339 2340 return no_signal; 2341 } 2342 2343 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) 2344 { 2345 int no_signal, lock = 0; 2346 s32 cpt_step = 0, offst_freq, car_max; 2347 u32 reg; 2348 2349 car_max = state->search_range / 1000; 2350 car_max += (car_max / 10); 2351 car_max = (65536 * car_max / 2); 2352 car_max /= (state->internal->mclk / 1000); 2353 if (car_max > 0x4000) 2354 car_max = 0x4000; 2355 2356 if (zigzag) 2357 offst_freq = 0; 2358 else 2359 offst_freq = -car_max + inc; 2360 2361 do { 2362 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) 2363 goto err; 2364 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) 2365 goto err; 2366 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) 2367 goto err; 2368 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 2369 goto err; 2370 2371 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2372 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ 2373 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2374 goto err; 2375 2376 if (zigzag) { 2377 if (offst_freq >= 0) 2378 offst_freq = -offst_freq - 2 * inc; 2379 else 2380 offst_freq = -offst_freq; 2381 } else { 2382 offst_freq += 2 * inc; 2383 } 2384 2385 cpt_step++; 2386 2387 lock = stv090x_get_dmdlock(state, timeout); 2388 no_signal = stv090x_chk_signal(state); 2389 2390 } while ((!lock) && 2391 (!no_signal) && 2392 ((offst_freq - inc) < car_max) && 2393 ((offst_freq + inc) > -car_max) && 2394 (cpt_step < steps_max)); 2395 2396 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2397 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); 2398 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2399 goto err; 2400 2401 return lock; 2402 err: 2403 dprintk(FE_ERROR, 1, "I/O error"); 2404 return -1; 2405 } 2406 2407 static int stv090x_sw_algo(struct stv090x_state *state) 2408 { 2409 int no_signal, zigzag, lock = 0; 2410 u32 reg; 2411 2412 s32 dvbs2_fly_wheel; 2413 s32 inc, timeout_step, trials, steps_max; 2414 2415 /* get params */ 2416 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); 2417 2418 switch (state->search_mode) { 2419 case STV090x_SEARCH_DVBS1: 2420 case STV090x_SEARCH_DSS: 2421 /* accelerate the frequency detector */ 2422 if (state->internal->dev_ver >= 0x20) { 2423 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) 2424 goto err; 2425 } 2426 2427 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) 2428 goto err; 2429 zigzag = 0; 2430 break; 2431 2432 case STV090x_SEARCH_DVBS2: 2433 if (state->internal->dev_ver >= 0x20) { 2434 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2435 goto err; 2436 } 2437 2438 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2439 goto err; 2440 zigzag = 1; 2441 break; 2442 2443 case STV090x_SEARCH_AUTO: 2444 default: 2445 /* accelerate the frequency detector */ 2446 if (state->internal->dev_ver >= 0x20) { 2447 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) 2448 goto err; 2449 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2450 goto err; 2451 } 2452 2453 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) 2454 goto err; 2455 zigzag = 0; 2456 break; 2457 } 2458 2459 trials = 0; 2460 do { 2461 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); 2462 no_signal = stv090x_chk_signal(state); 2463 trials++; 2464 2465 /*run the SW search 2 times maximum*/ 2466 if (lock || no_signal || (trials == 2)) { 2467 /*Check if the demod is not losing lock in DVBS2*/ 2468 if (state->internal->dev_ver >= 0x20) { 2469 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 2470 goto err; 2471 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 2472 goto err; 2473 } 2474 2475 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2476 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { 2477 /*Check if the demod is not losing lock in DVBS2*/ 2478 msleep(timeout_step); 2479 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2480 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2481 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */ 2482 msleep(timeout_step); 2483 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2484 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2485 } 2486 if (dvbs2_fly_wheel < 0xd) { 2487 /*FALSE lock, The demod is losing lock */ 2488 lock = 0; 2489 if (trials < 2) { 2490 if (state->internal->dev_ver >= 0x20) { 2491 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2492 goto err; 2493 } 2494 2495 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2496 goto err; 2497 } 2498 } 2499 } 2500 } 2501 } while ((!lock) && (trials < 2) && (!no_signal)); 2502 2503 return lock; 2504 err: 2505 dprintk(FE_ERROR, 1, "I/O error"); 2506 return -1; 2507 } 2508 2509 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) 2510 { 2511 u32 reg; 2512 enum stv090x_delsys delsys; 2513 2514 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2515 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) 2516 delsys = STV090x_DVBS2; 2517 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { 2518 reg = STV090x_READ_DEMOD(state, FECM); 2519 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) 2520 delsys = STV090x_DSS; 2521 else 2522 delsys = STV090x_DVBS1; 2523 } else { 2524 delsys = STV090x_ERROR; 2525 } 2526 2527 return delsys; 2528 } 2529 2530 /* in Hz */ 2531 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) 2532 { 2533 s32 derot, int_1, int_2, tmp_1, tmp_2; 2534 2535 derot = STV090x_READ_DEMOD(state, CFR2) << 16; 2536 derot |= STV090x_READ_DEMOD(state, CFR1) << 8; 2537 derot |= STV090x_READ_DEMOD(state, CFR0); 2538 2539 derot = comp2(derot, 24); 2540 int_1 = mclk >> 12; 2541 int_2 = derot >> 12; 2542 2543 /* carrier_frequency = MasterClock * Reg / 2^24 */ 2544 tmp_1 = mclk % 0x1000; 2545 tmp_2 = derot % 0x1000; 2546 2547 derot = (int_1 * int_2) + 2548 ((int_1 * tmp_2) >> 12) + 2549 ((int_2 * tmp_1) >> 12); 2550 2551 return derot; 2552 } 2553 2554 static int stv090x_get_viterbi(struct stv090x_state *state) 2555 { 2556 u32 reg, rate; 2557 2558 reg = STV090x_READ_DEMOD(state, VITCURPUN); 2559 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); 2560 2561 switch (rate) { 2562 case 13: 2563 state->fec = STV090x_PR12; 2564 break; 2565 2566 case 18: 2567 state->fec = STV090x_PR23; 2568 break; 2569 2570 case 21: 2571 state->fec = STV090x_PR34; 2572 break; 2573 2574 case 24: 2575 state->fec = STV090x_PR56; 2576 break; 2577 2578 case 25: 2579 state->fec = STV090x_PR67; 2580 break; 2581 2582 case 26: 2583 state->fec = STV090x_PR78; 2584 break; 2585 2586 default: 2587 state->fec = STV090x_PRERR; 2588 break; 2589 } 2590 2591 return 0; 2592 } 2593 2594 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) 2595 { 2596 struct dvb_frontend *fe = &state->frontend; 2597 2598 u8 tmg; 2599 u32 reg; 2600 s32 i = 0, offst_freq; 2601 2602 msleep(5); 2603 2604 if (state->algo == STV090x_BLIND_SEARCH) { 2605 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2606 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); 2607 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) { 2608 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2609 msleep(5); 2610 i += 5; 2611 } 2612 } 2613 state->delsys = stv090x_get_std(state); 2614 2615 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2616 goto err; 2617 2618 if (state->config->tuner_get_frequency) { 2619 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2620 goto err_gateoff; 2621 } 2622 2623 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2624 goto err; 2625 2626 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; 2627 state->frequency += offst_freq; 2628 2629 if (stv090x_get_viterbi(state) < 0) 2630 goto err; 2631 2632 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2633 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2634 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2635 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; 2636 reg = STV090x_READ_DEMOD(state, TMGOBS); 2637 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); 2638 reg = STV090x_READ_DEMOD(state, FECM); 2639 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); 2640 2641 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { 2642 2643 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2644 goto err; 2645 2646 if (state->config->tuner_get_frequency) { 2647 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2648 goto err_gateoff; 2649 } 2650 2651 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2652 goto err; 2653 2654 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2655 return STV090x_RANGEOK; 2656 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) 2657 return STV090x_RANGEOK; 2658 } else { 2659 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2660 return STV090x_RANGEOK; 2661 } 2662 2663 return STV090x_OUTOFRANGE; 2664 2665 err_gateoff: 2666 stv090x_i2c_gate_ctrl(state, 0); 2667 err: 2668 dprintk(FE_ERROR, 1, "I/O error"); 2669 return -1; 2670 } 2671 2672 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) 2673 { 2674 s32 offst_tmg; 2675 2676 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; 2677 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; 2678 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); 2679 2680 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */ 2681 if (!offst_tmg) 2682 offst_tmg = 1; 2683 2684 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg); 2685 offst_tmg /= 320; 2686 2687 return offst_tmg; 2688 } 2689 2690 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) 2691 { 2692 u8 aclc = 0x29; 2693 s32 i; 2694 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low; 2695 2696 if (state->internal->dev_ver == 0x20) { 2697 car_loop = stv090x_s2_crl_cut20; 2698 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20; 2699 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20; 2700 } else { 2701 /* >= Cut 3 */ 2702 car_loop = stv090x_s2_crl_cut30; 2703 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30; 2704 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30; 2705 } 2706 2707 if (modcod < STV090x_QPSK_12) { 2708 i = 0; 2709 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod)) 2710 i++; 2711 2712 if (i >= 3) 2713 i = 2; 2714 2715 } else { 2716 i = 0; 2717 while ((i < 14) && (modcod != car_loop[i].modcod)) 2718 i++; 2719 2720 if (i >= 14) { 2721 i = 0; 2722 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod)) 2723 i++; 2724 2725 if (i >= 11) 2726 i = 10; 2727 } 2728 } 2729 2730 if (modcod <= STV090x_QPSK_25) { 2731 if (pilots) { 2732 if (state->srate <= 3000000) 2733 aclc = car_loop_qpsk_low[i].crl_pilots_on_2; 2734 else if (state->srate <= 7000000) 2735 aclc = car_loop_qpsk_low[i].crl_pilots_on_5; 2736 else if (state->srate <= 15000000) 2737 aclc = car_loop_qpsk_low[i].crl_pilots_on_10; 2738 else if (state->srate <= 25000000) 2739 aclc = car_loop_qpsk_low[i].crl_pilots_on_20; 2740 else 2741 aclc = car_loop_qpsk_low[i].crl_pilots_on_30; 2742 } else { 2743 if (state->srate <= 3000000) 2744 aclc = car_loop_qpsk_low[i].crl_pilots_off_2; 2745 else if (state->srate <= 7000000) 2746 aclc = car_loop_qpsk_low[i].crl_pilots_off_5; 2747 else if (state->srate <= 15000000) 2748 aclc = car_loop_qpsk_low[i].crl_pilots_off_10; 2749 else if (state->srate <= 25000000) 2750 aclc = car_loop_qpsk_low[i].crl_pilots_off_20; 2751 else 2752 aclc = car_loop_qpsk_low[i].crl_pilots_off_30; 2753 } 2754 2755 } else if (modcod <= STV090x_8PSK_910) { 2756 if (pilots) { 2757 if (state->srate <= 3000000) 2758 aclc = car_loop[i].crl_pilots_on_2; 2759 else if (state->srate <= 7000000) 2760 aclc = car_loop[i].crl_pilots_on_5; 2761 else if (state->srate <= 15000000) 2762 aclc = car_loop[i].crl_pilots_on_10; 2763 else if (state->srate <= 25000000) 2764 aclc = car_loop[i].crl_pilots_on_20; 2765 else 2766 aclc = car_loop[i].crl_pilots_on_30; 2767 } else { 2768 if (state->srate <= 3000000) 2769 aclc = car_loop[i].crl_pilots_off_2; 2770 else if (state->srate <= 7000000) 2771 aclc = car_loop[i].crl_pilots_off_5; 2772 else if (state->srate <= 15000000) 2773 aclc = car_loop[i].crl_pilots_off_10; 2774 else if (state->srate <= 25000000) 2775 aclc = car_loop[i].crl_pilots_off_20; 2776 else 2777 aclc = car_loop[i].crl_pilots_off_30; 2778 } 2779 } else { /* 16APSK and 32APSK */ 2780 /* 2781 * This should never happen in practice, except if 2782 * something is really wrong at the car_loop table. 2783 */ 2784 if (i >= 11) 2785 i = 10; 2786 if (state->srate <= 3000000) 2787 aclc = car_loop_apsk_low[i].crl_pilots_on_2; 2788 else if (state->srate <= 7000000) 2789 aclc = car_loop_apsk_low[i].crl_pilots_on_5; 2790 else if (state->srate <= 15000000) 2791 aclc = car_loop_apsk_low[i].crl_pilots_on_10; 2792 else if (state->srate <= 25000000) 2793 aclc = car_loop_apsk_low[i].crl_pilots_on_20; 2794 else 2795 aclc = car_loop_apsk_low[i].crl_pilots_on_30; 2796 } 2797 2798 return aclc; 2799 } 2800 2801 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) 2802 { 2803 struct stv090x_short_frame_crloop *short_crl = NULL; 2804 s32 index = 0; 2805 u8 aclc = 0x0b; 2806 2807 switch (state->modulation) { 2808 case STV090x_QPSK: 2809 default: 2810 index = 0; 2811 break; 2812 case STV090x_8PSK: 2813 index = 1; 2814 break; 2815 case STV090x_16APSK: 2816 index = 2; 2817 break; 2818 case STV090x_32APSK: 2819 index = 3; 2820 break; 2821 } 2822 2823 if (state->internal->dev_ver >= 0x30) { 2824 /* Cut 3.0 and up */ 2825 short_crl = stv090x_s2_short_crl_cut30; 2826 } else { 2827 /* Cut 2.0 and up: we don't support cuts older than 2.0 */ 2828 short_crl = stv090x_s2_short_crl_cut20; 2829 } 2830 2831 if (state->srate <= 3000000) 2832 aclc = short_crl[index].crl_2; 2833 else if (state->srate <= 7000000) 2834 aclc = short_crl[index].crl_5; 2835 else if (state->srate <= 15000000) 2836 aclc = short_crl[index].crl_10; 2837 else if (state->srate <= 25000000) 2838 aclc = short_crl[index].crl_20; 2839 else 2840 aclc = short_crl[index].crl_30; 2841 2842 return aclc; 2843 } 2844 2845 static int stv090x_optimize_track(struct stv090x_state *state) 2846 { 2847 struct dvb_frontend *fe = &state->frontend; 2848 2849 enum stv090x_modcod modcod; 2850 2851 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0; 2852 u32 reg; 2853 2854 srate = stv090x_get_srate(state, state->internal->mclk); 2855 srate += stv090x_get_tmgoffst(state, srate); 2856 2857 switch (state->delsys) { 2858 case STV090x_DVBS1: 2859 case STV090x_DSS: 2860 if (state->search_mode == STV090x_SEARCH_AUTO) { 2861 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2862 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2863 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 2864 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2865 goto err; 2866 } 2867 reg = STV090x_READ_DEMOD(state, DEMOD); 2868 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 2869 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); 2870 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 2871 goto err; 2872 2873 if (state->internal->dev_ver >= 0x30) { 2874 if (stv090x_get_viterbi(state) < 0) 2875 goto err; 2876 2877 if (state->fec == STV090x_PR12) { 2878 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) 2879 goto err; 2880 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2881 goto err; 2882 } else { 2883 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) 2884 goto err; 2885 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2886 goto err; 2887 } 2888 } 2889 2890 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 2891 goto err; 2892 break; 2893 2894 case STV090x_DVBS2: 2895 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2896 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 2897 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2898 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2899 goto err; 2900 if (state->internal->dev_ver >= 0x30) { 2901 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) 2902 goto err; 2903 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) 2904 goto err; 2905 } 2906 if (state->frame_len == STV090x_LONG_FRAME) { 2907 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2908 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2909 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2910 aclc = stv090x_optimize_carloop(state, modcod, pilots); 2911 if (modcod <= STV090x_QPSK_910) { 2912 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); 2913 } else if (modcod <= STV090x_8PSK_910) { 2914 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2915 goto err; 2916 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2917 goto err; 2918 } 2919 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { 2920 if (modcod <= STV090x_16APSK_910) { 2921 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2922 goto err; 2923 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2924 goto err; 2925 } else { 2926 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2927 goto err; 2928 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2929 goto err; 2930 } 2931 } 2932 } else { 2933 /*Carrier loop setting for short frame*/ 2934 aclc = stv090x_optimize_carloop_short(state); 2935 if (state->modulation == STV090x_QPSK) { 2936 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) 2937 goto err; 2938 } else if (state->modulation == STV090x_8PSK) { 2939 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2940 goto err; 2941 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2942 goto err; 2943 } else if (state->modulation == STV090x_16APSK) { 2944 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2945 goto err; 2946 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2947 goto err; 2948 } else if (state->modulation == STV090x_32APSK) { 2949 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2950 goto err; 2951 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2952 goto err; 2953 } 2954 } 2955 2956 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */ 2957 break; 2958 2959 case STV090x_ERROR: 2960 default: 2961 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2962 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2963 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2964 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2965 goto err; 2966 break; 2967 } 2968 2969 f_1 = STV090x_READ_DEMOD(state, CFR2); 2970 f_0 = STV090x_READ_DEMOD(state, CFR1); 2971 reg = STV090x_READ_DEMOD(state, TMGOBS); 2972 2973 if (state->algo == STV090x_BLIND_SEARCH) { 2974 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); 2975 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2976 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); 2977 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 2978 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2979 goto err; 2980 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 2981 goto err; 2982 2983 if (stv090x_set_srate(state, srate) < 0) 2984 goto err; 2985 blind_tune = 1; 2986 2987 if (stv090x_dvbs_track_crl(state) < 0) 2988 goto err; 2989 } 2990 2991 if (state->internal->dev_ver >= 0x20) { 2992 if ((state->search_mode == STV090x_SEARCH_DVBS1) || 2993 (state->search_mode == STV090x_SEARCH_DSS) || 2994 (state->search_mode == STV090x_SEARCH_AUTO)) { 2995 2996 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) 2997 goto err; 2998 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) 2999 goto err; 3000 } 3001 } 3002 3003 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 3004 goto err; 3005 3006 /* AUTO tracking MODE */ 3007 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) 3008 goto err; 3009 /* AUTO tracking MODE */ 3010 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) 3011 goto err; 3012 3013 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || 3014 (state->srate < 10000000)) { 3015 /* update initial carrier freq with the found freq offset */ 3016 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3017 goto err; 3018 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3019 goto err; 3020 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; 3021 3022 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { 3023 3024 if (state->algo != STV090x_WARM_SEARCH) { 3025 3026 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3027 goto err; 3028 3029 if (state->config->tuner_set_bandwidth) { 3030 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3031 goto err_gateoff; 3032 } 3033 3034 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3035 goto err; 3036 3037 } 3038 } 3039 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) 3040 msleep(50); /* blind search: wait 50ms for SR stabilization */ 3041 else 3042 msleep(5); 3043 3044 stv090x_get_lock_tmg(state); 3045 3046 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { 3047 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3048 goto err; 3049 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3050 goto err; 3051 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3052 goto err; 3053 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3054 goto err; 3055 3056 i = 0; 3057 3058 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { 3059 3060 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3061 goto err; 3062 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3063 goto err; 3064 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3065 goto err; 3066 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3067 goto err; 3068 i++; 3069 } 3070 } 3071 3072 } 3073 3074 if (state->internal->dev_ver >= 0x20) { 3075 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 3076 goto err; 3077 } 3078 3079 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) 3080 stv090x_set_vit_thtracq(state); 3081 3082 return 0; 3083 3084 err_gateoff: 3085 stv090x_i2c_gate_ctrl(state, 0); 3086 err: 3087 dprintk(FE_ERROR, 1, "I/O error"); 3088 return -1; 3089 } 3090 3091 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) 3092 { 3093 s32 timer = 0, lock = 0, stat; 3094 u32 reg; 3095 3096 while ((timer < timeout) && (!lock)) { 3097 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3098 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3099 3100 switch (stat) { 3101 case 0: /* searching */ 3102 case 1: /* first PLH detected */ 3103 default: 3104 lock = 0; 3105 break; 3106 3107 case 2: /* DVB-S2 mode */ 3108 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3109 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); 3110 break; 3111 3112 case 3: /* DVB-S1/legacy mode */ 3113 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3114 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); 3115 break; 3116 } 3117 if (!lock) { 3118 msleep(10); 3119 timer += 10; 3120 } 3121 } 3122 return lock; 3123 } 3124 3125 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) 3126 { 3127 u32 reg; 3128 s32 timer = 0; 3129 int lock; 3130 3131 lock = stv090x_get_dmdlock(state, timeout_dmd); 3132 if (lock) 3133 lock = stv090x_get_feclock(state, timeout_fec); 3134 3135 if (lock) { 3136 lock = 0; 3137 3138 while ((timer < timeout_fec) && (!lock)) { 3139 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3140 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); 3141 msleep(1); 3142 timer++; 3143 } 3144 } 3145 3146 return lock; 3147 } 3148 3149 static int stv090x_set_s2rolloff(struct stv090x_state *state) 3150 { 3151 u32 reg; 3152 3153 if (state->internal->dev_ver <= 0x20) { 3154 /* rolloff to auto mode if DVBS2 */ 3155 reg = STV090x_READ_DEMOD(state, DEMOD); 3156 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); 3157 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3158 goto err; 3159 } else { 3160 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3161 reg = STV090x_READ_DEMOD(state, DEMOD); 3162 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); 3163 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3164 goto err; 3165 } 3166 return 0; 3167 err: 3168 dprintk(FE_ERROR, 1, "I/O error"); 3169 return -1; 3170 } 3171 3172 3173 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) 3174 { 3175 struct dvb_frontend *fe = &state->frontend; 3176 enum stv090x_signal_state signal_state = STV090x_NOCARRIER; 3177 u32 reg; 3178 s32 agc1_power, power_iq = 0, i; 3179 int lock = 0, low_sr = 0; 3180 3181 reg = STV090x_READ_DEMOD(state, TSCFGH); 3182 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ 3183 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3184 goto err; 3185 3186 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ 3187 goto err; 3188 3189 if (state->internal->dev_ver >= 0x20) { 3190 if (state->srate > 5000000) { 3191 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 3192 goto err; 3193 } else { 3194 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) 3195 goto err; 3196 } 3197 } 3198 3199 stv090x_get_lock_tmg(state); 3200 3201 if (state->algo == STV090x_BLIND_SEARCH) { 3202 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ 3203 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ 3204 goto err; 3205 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3206 goto err; 3207 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */ 3208 goto err; 3209 } else { 3210 /* known srate */ 3211 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 3212 goto err; 3213 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 3214 goto err; 3215 3216 if (state->srate < 2000000) { 3217 /* SR < 2MSPS */ 3218 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) 3219 goto err; 3220 } else { 3221 /* SR >= 2Msps */ 3222 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3223 goto err; 3224 } 3225 3226 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 3227 goto err; 3228 3229 if (state->internal->dev_ver >= 0x20) { 3230 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) 3231 goto err; 3232 if (state->algo == STV090x_COLD_SEARCH) 3233 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; 3234 else if (state->algo == STV090x_WARM_SEARCH) 3235 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; 3236 } 3237 3238 /* if cold start or warm (Symbolrate is known) 3239 * use a Narrow symbol rate scan range 3240 */ 3241 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ 3242 goto err; 3243 3244 if (stv090x_set_srate(state, state->srate) < 0) 3245 goto err; 3246 3247 if (stv090x_set_max_srate(state, state->internal->mclk, 3248 state->srate) < 0) 3249 goto err; 3250 if (stv090x_set_min_srate(state, state->internal->mclk, 3251 state->srate) < 0) 3252 goto err; 3253 3254 if (state->srate >= 10000000) 3255 low_sr = 0; 3256 else 3257 low_sr = 1; 3258 } 3259 3260 /* Setup tuner */ 3261 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3262 goto err; 3263 3264 if (state->config->tuner_set_bbgain) { 3265 reg = state->config->tuner_bbgain; 3266 if (reg == 0) 3267 reg = 10; /* default: 10dB */ 3268 if (state->config->tuner_set_bbgain(fe, reg) < 0) 3269 goto err_gateoff; 3270 } 3271 3272 if (state->config->tuner_set_frequency) { 3273 if (state->config->tuner_set_frequency(fe, state->frequency) < 0) 3274 goto err_gateoff; 3275 } 3276 3277 if (state->config->tuner_set_bandwidth) { 3278 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3279 goto err_gateoff; 3280 } 3281 3282 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3283 goto err; 3284 3285 msleep(50); 3286 3287 if (state->config->tuner_get_status) { 3288 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3289 goto err; 3290 if (state->config->tuner_get_status(fe, ®) < 0) 3291 goto err_gateoff; 3292 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3293 goto err; 3294 3295 if (reg) 3296 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 3297 else { 3298 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 3299 return STV090x_NOCARRIER; 3300 } 3301 } 3302 3303 msleep(10); 3304 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), 3305 STV090x_READ_DEMOD(state, AGCIQIN0)); 3306 3307 if (agc1_power == 0) { 3308 /* If AGC1 integrator value is 0 3309 * then read POWERI, POWERQ 3310 */ 3311 for (i = 0; i < 5; i++) { 3312 power_iq += (STV090x_READ_DEMOD(state, POWERI) + 3313 STV090x_READ_DEMOD(state, POWERQ)) >> 1; 3314 } 3315 power_iq /= 5; 3316 } 3317 3318 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { 3319 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); 3320 lock = 0; 3321 signal_state = STV090x_NOAGC1; 3322 } else { 3323 reg = STV090x_READ_DEMOD(state, DEMOD); 3324 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); 3325 3326 if (state->internal->dev_ver <= 0x20) { 3327 /* rolloff to auto mode if DVBS2 */ 3328 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); 3329 } else { 3330 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3331 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); 3332 } 3333 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3334 goto err; 3335 3336 if (stv090x_delivery_search(state) < 0) 3337 goto err; 3338 3339 if (state->algo != STV090x_BLIND_SEARCH) { 3340 if (stv090x_start_search(state) < 0) 3341 goto err; 3342 } 3343 } 3344 3345 if (signal_state == STV090x_NOAGC1) 3346 return signal_state; 3347 3348 if (state->algo == STV090x_BLIND_SEARCH) 3349 lock = stv090x_blind_search(state); 3350 3351 else if (state->algo == STV090x_COLD_SEARCH) 3352 lock = stv090x_get_coldlock(state, state->DemodTimeout); 3353 3354 else if (state->algo == STV090x_WARM_SEARCH) 3355 lock = stv090x_get_dmdlock(state, state->DemodTimeout); 3356 3357 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { 3358 if (!low_sr) { 3359 if (stv090x_chk_tmg(state)) 3360 lock = stv090x_sw_algo(state); 3361 } 3362 } 3363 3364 if (lock) 3365 signal_state = stv090x_get_sig_params(state); 3366 3367 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */ 3368 stv090x_optimize_track(state); 3369 3370 if (state->internal->dev_ver >= 0x20) { 3371 /* >= Cut 2.0 :release TS reset after 3372 * demod lock and optimized Tracking 3373 */ 3374 reg = STV090x_READ_DEMOD(state, TSCFGH); 3375 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3376 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3377 goto err; 3378 3379 msleep(3); 3380 3381 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ 3382 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3383 goto err; 3384 3385 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3386 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3387 goto err; 3388 } 3389 3390 lock = stv090x_get_lock(state, state->FecTimeout, 3391 state->FecTimeout); 3392 if (lock) { 3393 if (state->delsys == STV090x_DVBS2) { 3394 stv090x_set_s2rolloff(state); 3395 3396 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3397 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); 3398 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3399 goto err; 3400 /* Reset DVBS2 packet delinator error counter */ 3401 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3402 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); 3403 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3404 goto err; 3405 3406 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */ 3407 goto err; 3408 } else { 3409 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 3410 goto err; 3411 } 3412 /* Reset the Total packet counter */ 3413 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) 3414 goto err; 3415 /* Reset the packet Error counter2 */ 3416 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3417 goto err; 3418 } else { 3419 signal_state = STV090x_NODATA; 3420 stv090x_chk_signal(state); 3421 } 3422 } 3423 return signal_state; 3424 3425 err_gateoff: 3426 stv090x_i2c_gate_ctrl(state, 0); 3427 err: 3428 dprintk(FE_ERROR, 1, "I/O error"); 3429 return -1; 3430 } 3431 3432 static int stv090x_set_mis(struct stv090x_state *state, int mis) 3433 { 3434 u32 reg; 3435 3436 if (mis < 0 || mis > 255) { 3437 dprintk(FE_DEBUG, 1, "Disable MIS filtering"); 3438 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 3439 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00); 3440 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 3441 goto err; 3442 } else { 3443 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); 3444 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 3445 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01); 3446 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 3447 goto err; 3448 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) 3449 goto err; 3450 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0) 3451 goto err; 3452 } 3453 return 0; 3454 err: 3455 dprintk(FE_ERROR, 1, "I/O error"); 3456 return -1; 3457 } 3458 3459 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe) 3460 { 3461 struct stv090x_state *state = fe->demodulator_priv; 3462 struct dtv_frontend_properties *props = &fe->dtv_property_cache; 3463 3464 if (props->frequency == 0) 3465 return DVBFE_ALGO_SEARCH_INVALID; 3466 3467 switch (props->delivery_system) { 3468 case SYS_DSS: 3469 state->delsys = STV090x_DSS; 3470 break; 3471 case SYS_DVBS: 3472 state->delsys = STV090x_DVBS1; 3473 break; 3474 case SYS_DVBS2: 3475 state->delsys = STV090x_DVBS2; 3476 break; 3477 default: 3478 return DVBFE_ALGO_SEARCH_INVALID; 3479 } 3480 3481 state->frequency = props->frequency; 3482 state->srate = props->symbol_rate; 3483 state->search_mode = STV090x_SEARCH_AUTO; 3484 state->algo = STV090x_COLD_SEARCH; 3485 state->fec = STV090x_PRERR; 3486 if (state->srate > 10000000) { 3487 dprintk(FE_DEBUG, 1, "Search range: 10 MHz"); 3488 state->search_range = 10000000; 3489 } else { 3490 dprintk(FE_DEBUG, 1, "Search range: 5 MHz"); 3491 state->search_range = 5000000; 3492 } 3493 3494 stv090x_set_mis(state, props->stream_id); 3495 3496 if (stv090x_algo(state) == STV090x_RANGEOK) { 3497 dprintk(FE_DEBUG, 1, "Search success!"); 3498 return DVBFE_ALGO_SEARCH_SUCCESS; 3499 } else { 3500 dprintk(FE_DEBUG, 1, "Search failed!"); 3501 return DVBFE_ALGO_SEARCH_FAILED; 3502 } 3503 3504 return DVBFE_ALGO_SEARCH_ERROR; 3505 } 3506 3507 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) 3508 { 3509 struct stv090x_state *state = fe->demodulator_priv; 3510 u32 reg, dstatus; 3511 u8 search_state; 3512 3513 *status = 0; 3514 3515 dstatus = STV090x_READ_DEMOD(state, DSTATUS); 3516 if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD)) 3517 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; 3518 3519 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3520 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3521 3522 switch (search_state) { 3523 case 0: /* searching */ 3524 case 1: /* first PLH detected */ 3525 default: 3526 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)"); 3527 break; 3528 3529 case 2: /* DVB-S2 mode */ 3530 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); 3531 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { 3532 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3533 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { 3534 *status |= FE_HAS_VITERBI; 3535 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3536 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) 3537 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 3538 } 3539 } 3540 break; 3541 3542 case 3: /* DVB-S1/legacy mode */ 3543 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S"); 3544 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { 3545 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3546 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { 3547 *status |= FE_HAS_VITERBI; 3548 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3549 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) 3550 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 3551 } 3552 } 3553 break; 3554 } 3555 3556 return 0; 3557 } 3558 3559 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) 3560 { 3561 struct stv090x_state *state = fe->demodulator_priv; 3562 3563 s32 count_4, count_3, count_2, count_1, count_0, count; 3564 u32 reg, h, m, l; 3565 enum fe_status status; 3566 3567 stv090x_read_status(fe, &status); 3568 if (!(status & FE_HAS_LOCK)) { 3569 *per = 1 << 23; /* Max PER */ 3570 } else { 3571 /* Counter 2 */ 3572 reg = STV090x_READ_DEMOD(state, ERRCNT22); 3573 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); 3574 3575 reg = STV090x_READ_DEMOD(state, ERRCNT21); 3576 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); 3577 3578 reg = STV090x_READ_DEMOD(state, ERRCNT20); 3579 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); 3580 3581 *per = ((h << 16) | (m << 8) | l); 3582 3583 count_4 = STV090x_READ_DEMOD(state, FBERCPT4); 3584 count_3 = STV090x_READ_DEMOD(state, FBERCPT3); 3585 count_2 = STV090x_READ_DEMOD(state, FBERCPT2); 3586 count_1 = STV090x_READ_DEMOD(state, FBERCPT1); 3587 count_0 = STV090x_READ_DEMOD(state, FBERCPT0); 3588 3589 if ((!count_4) && (!count_3)) { 3590 count = (count_2 & 0xff) << 16; 3591 count |= (count_1 & 0xff) << 8; 3592 count |= count_0 & 0xff; 3593 } else { 3594 count = 1 << 24; 3595 } 3596 if (count == 0) 3597 *per = 1; 3598 } 3599 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) 3600 goto err; 3601 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3602 goto err; 3603 3604 return 0; 3605 err: 3606 dprintk(FE_ERROR, 1, "I/O error"); 3607 return -1; 3608 } 3609 3610 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) 3611 { 3612 int res = 0; 3613 int min = 0, med; 3614 3615 if ((val >= tab[min].read && val < tab[max].read) || 3616 (val >= tab[max].read && val < tab[min].read)) { 3617 while ((max - min) > 1) { 3618 med = (max + min) / 2; 3619 if ((val >= tab[min].read && val < tab[med].read) || 3620 (val >= tab[med].read && val < tab[min].read)) 3621 max = med; 3622 else 3623 min = med; 3624 } 3625 res = ((val - tab[min].read) * 3626 (tab[max].real - tab[min].real) / 3627 (tab[max].read - tab[min].read)) + 3628 tab[min].real; 3629 } else { 3630 if (tab[min].read < tab[max].read) { 3631 if (val < tab[min].read) 3632 res = tab[min].real; 3633 else if (val >= tab[max].read) 3634 res = tab[max].real; 3635 } else { 3636 if (val >= tab[min].read) 3637 res = tab[min].real; 3638 else if (val < tab[max].read) 3639 res = tab[max].real; 3640 } 3641 } 3642 3643 return res; 3644 } 3645 3646 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 3647 { 3648 struct stv090x_state *state = fe->demodulator_priv; 3649 u32 reg; 3650 s32 agc_0, agc_1, agc; 3651 s32 str; 3652 3653 reg = STV090x_READ_DEMOD(state, AGCIQIN1); 3654 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3655 reg = STV090x_READ_DEMOD(state, AGCIQIN0); 3656 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3657 agc = MAKEWORD16(agc_1, agc_0); 3658 3659 str = stv090x_table_lookup(stv090x_rf_tab, 3660 ARRAY_SIZE(stv090x_rf_tab) - 1, agc); 3661 if (agc > stv090x_rf_tab[0].read) 3662 str = 0; 3663 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) 3664 str = -100; 3665 *strength = (str + 100) * 0xFFFF / 100; 3666 3667 return 0; 3668 } 3669 3670 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) 3671 { 3672 struct stv090x_state *state = fe->demodulator_priv; 3673 u32 reg_0, reg_1, reg, i; 3674 s32 val_0, val_1, val = 0; 3675 u8 lock_f; 3676 s32 div; 3677 u32 last; 3678 3679 switch (state->delsys) { 3680 case STV090x_DVBS2: 3681 reg = STV090x_READ_DEMOD(state, DSTATUS); 3682 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3683 if (lock_f) { 3684 msleep(5); 3685 for (i = 0; i < 16; i++) { 3686 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); 3687 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); 3688 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); 3689 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD); 3690 val += MAKEWORD16(val_1, val_0); 3691 msleep(1); 3692 } 3693 val /= 16; 3694 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1; 3695 div = stv090x_s2cn_tab[last].real - 3696 stv090x_s2cn_tab[3].real; 3697 val = stv090x_table_lookup(stv090x_s2cn_tab, last, val); 3698 if (val < 0) 3699 val = 0; 3700 *cnr = val * 0xFFFF / div; 3701 } 3702 break; 3703 3704 case STV090x_DVBS1: 3705 case STV090x_DSS: 3706 reg = STV090x_READ_DEMOD(state, DSTATUS); 3707 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3708 if (lock_f) { 3709 msleep(5); 3710 for (i = 0; i < 16; i++) { 3711 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); 3712 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); 3713 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); 3714 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD); 3715 val += MAKEWORD16(val_1, val_0); 3716 msleep(1); 3717 } 3718 val /= 16; 3719 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1; 3720 div = stv090x_s1cn_tab[last].real - 3721 stv090x_s1cn_tab[0].real; 3722 val = stv090x_table_lookup(stv090x_s1cn_tab, last, val); 3723 *cnr = val * 0xFFFF / div; 3724 } 3725 break; 3726 default: 3727 break; 3728 } 3729 3730 return 0; 3731 } 3732 3733 static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 3734 { 3735 struct stv090x_state *state = fe->demodulator_priv; 3736 u32 reg; 3737 3738 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3739 switch (tone) { 3740 case SEC_TONE_ON: 3741 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3742 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3743 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3744 goto err; 3745 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3746 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3747 goto err; 3748 break; 3749 3750 case SEC_TONE_OFF: 3751 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3752 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3753 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3754 goto err; 3755 break; 3756 default: 3757 return -EINVAL; 3758 } 3759 3760 return 0; 3761 err: 3762 dprintk(FE_ERROR, 1, "I/O error"); 3763 return -1; 3764 } 3765 3766 3767 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe) 3768 { 3769 return DVBFE_ALGO_CUSTOM; 3770 } 3771 3772 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd) 3773 { 3774 struct stv090x_state *state = fe->demodulator_priv; 3775 u32 reg, idle = 0, fifo_full = 1; 3776 int i; 3777 3778 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3779 3780 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 3781 (state->config->diseqc_envelope_mode) ? 4 : 2); 3782 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3783 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3784 goto err; 3785 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3786 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3787 goto err; 3788 3789 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3790 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3791 goto err; 3792 3793 for (i = 0; i < cmd->msg_len; i++) { 3794 3795 while (fifo_full) { 3796 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3797 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3798 } 3799 3800 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) 3801 goto err; 3802 } 3803 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3804 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3805 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3806 goto err; 3807 3808 i = 0; 3809 3810 while ((!idle) && (i < 10)) { 3811 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3812 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3813 msleep(10); 3814 i++; 3815 } 3816 3817 return 0; 3818 err: 3819 dprintk(FE_ERROR, 1, "I/O error"); 3820 return -1; 3821 } 3822 3823 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, 3824 enum fe_sec_mini_cmd burst) 3825 { 3826 struct stv090x_state *state = fe->demodulator_priv; 3827 u32 reg, idle = 0, fifo_full = 1; 3828 u8 mode, value; 3829 int i; 3830 3831 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3832 3833 if (burst == SEC_MINI_A) { 3834 mode = (state->config->diseqc_envelope_mode) ? 5 : 3; 3835 value = 0x00; 3836 } else { 3837 mode = (state->config->diseqc_envelope_mode) ? 4 : 2; 3838 value = 0xFF; 3839 } 3840 3841 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); 3842 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3843 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3844 goto err; 3845 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3846 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3847 goto err; 3848 3849 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3850 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3851 goto err; 3852 3853 while (fifo_full) { 3854 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3855 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3856 } 3857 3858 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) 3859 goto err; 3860 3861 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3862 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3863 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3864 goto err; 3865 3866 i = 0; 3867 3868 while ((!idle) && (i < 10)) { 3869 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3870 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3871 msleep(10); 3872 i++; 3873 } 3874 3875 return 0; 3876 err: 3877 dprintk(FE_ERROR, 1, "I/O error"); 3878 return -1; 3879 } 3880 3881 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply) 3882 { 3883 struct stv090x_state *state = fe->demodulator_priv; 3884 u32 reg = 0, i = 0, rx_end = 0; 3885 3886 while ((rx_end != 1) && (i < 10)) { 3887 msleep(10); 3888 i++; 3889 reg = STV090x_READ_DEMOD(state, DISRX_ST0); 3890 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); 3891 } 3892 3893 if (rx_end) { 3894 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); 3895 for (i = 0; i < reply->msg_len; i++) 3896 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); 3897 } 3898 3899 return 0; 3900 } 3901 3902 static int stv090x_sleep(struct dvb_frontend *fe) 3903 { 3904 struct stv090x_state *state = fe->demodulator_priv; 3905 u32 reg; 3906 u8 full_standby = 0; 3907 3908 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3909 goto err; 3910 3911 if (state->config->tuner_sleep) { 3912 if (state->config->tuner_sleep(fe) < 0) 3913 goto err_gateoff; 3914 } 3915 3916 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3917 goto err; 3918 3919 dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep", 3920 state->device == STV0900 ? "STV0900" : "STV0903", 3921 state->demod); 3922 3923 mutex_lock(&state->internal->demod_lock); 3924 3925 switch (state->demod) { 3926 case STV090x_DEMODULATOR_0: 3927 /* power off ADC 1 */ 3928 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3929 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); 3930 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 3931 goto err_unlock; 3932 /* power off DiSEqC 1 */ 3933 reg = stv090x_read_reg(state, STV090x_TSTTNR2); 3934 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); 3935 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) 3936 goto err_unlock; 3937 3938 /* check whether path 2 is already sleeping, that is when 3939 ADC2 is off */ 3940 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 3941 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0) 3942 full_standby = 1; 3943 3944 /* stop clocks */ 3945 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 3946 /* packet delineator 1 clock */ 3947 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1); 3948 /* ADC 1 clock */ 3949 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1); 3950 /* FEC clock is shared between the two paths, only stop it 3951 when full standby is possible */ 3952 if (full_standby) 3953 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); 3954 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 3955 goto err_unlock; 3956 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 3957 /* sampling 1 clock */ 3958 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); 3959 /* viterbi 1 clock */ 3960 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1); 3961 /* TS clock is shared between the two paths, only stop it 3962 when full standby is possible */ 3963 if (full_standby) 3964 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); 3965 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 3966 goto err_unlock; 3967 break; 3968 3969 case STV090x_DEMODULATOR_1: 3970 /* power off ADC 2 */ 3971 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 3972 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); 3973 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 3974 goto err_unlock; 3975 /* power off DiSEqC 2 */ 3976 reg = stv090x_read_reg(state, STV090x_TSTTNR4); 3977 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); 3978 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) 3979 goto err_unlock; 3980 3981 /* check whether path 1 is already sleeping, that is when 3982 ADC1 is off */ 3983 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3984 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0) 3985 full_standby = 1; 3986 3987 /* stop clocks */ 3988 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 3989 /* packet delineator 2 clock */ 3990 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1); 3991 /* ADC 2 clock */ 3992 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1); 3993 /* FEC clock is shared between the two paths, only stop it 3994 when full standby is possible */ 3995 if (full_standby) 3996 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); 3997 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 3998 goto err_unlock; 3999 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4000 /* sampling 2 clock */ 4001 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); 4002 /* viterbi 2 clock */ 4003 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1); 4004 /* TS clock is shared between the two paths, only stop it 4005 when full standby is possible */ 4006 if (full_standby) 4007 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); 4008 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4009 goto err_unlock; 4010 break; 4011 4012 default: 4013 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 4014 break; 4015 } 4016 4017 if (full_standby) { 4018 /* general power off */ 4019 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4020 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); 4021 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 4022 goto err_unlock; 4023 } 4024 4025 mutex_unlock(&state->internal->demod_lock); 4026 return 0; 4027 4028 err_gateoff: 4029 stv090x_i2c_gate_ctrl(state, 0); 4030 goto err; 4031 err_unlock: 4032 mutex_unlock(&state->internal->demod_lock); 4033 err: 4034 dprintk(FE_ERROR, 1, "I/O error"); 4035 return -1; 4036 } 4037 4038 static int stv090x_wakeup(struct dvb_frontend *fe) 4039 { 4040 struct stv090x_state *state = fe->demodulator_priv; 4041 u32 reg; 4042 4043 dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby", 4044 state->device == STV0900 ? "STV0900" : "STV0903", 4045 state->demod); 4046 4047 mutex_lock(&state->internal->demod_lock); 4048 4049 /* general power on */ 4050 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4051 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); 4052 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 4053 goto err; 4054 4055 switch (state->demod) { 4056 case STV090x_DEMODULATOR_0: 4057 /* power on ADC 1 */ 4058 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4059 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); 4060 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4061 goto err; 4062 /* power on DiSEqC 1 */ 4063 reg = stv090x_read_reg(state, STV090x_TSTTNR2); 4064 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1); 4065 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) 4066 goto err; 4067 4068 /* activate clocks */ 4069 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 4070 /* packet delineator 1 clock */ 4071 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0); 4072 /* ADC 1 clock */ 4073 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0); 4074 /* FEC clock */ 4075 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); 4076 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 4077 goto err; 4078 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4079 /* sampling 1 clock */ 4080 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0); 4081 /* viterbi 1 clock */ 4082 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0); 4083 /* TS clock */ 4084 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); 4085 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4086 goto err; 4087 break; 4088 4089 case STV090x_DEMODULATOR_1: 4090 /* power on ADC 2 */ 4091 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 4092 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1); 4093 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 4094 goto err; 4095 /* power on DiSEqC 2 */ 4096 reg = stv090x_read_reg(state, STV090x_TSTTNR4); 4097 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1); 4098 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) 4099 goto err; 4100 4101 /* activate clocks */ 4102 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 4103 /* packet delineator 2 clock */ 4104 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0); 4105 /* ADC 2 clock */ 4106 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0); 4107 /* FEC clock */ 4108 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); 4109 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 4110 goto err; 4111 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4112 /* sampling 2 clock */ 4113 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0); 4114 /* viterbi 2 clock */ 4115 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0); 4116 /* TS clock */ 4117 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); 4118 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4119 goto err; 4120 break; 4121 4122 default: 4123 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 4124 break; 4125 } 4126 4127 mutex_unlock(&state->internal->demod_lock); 4128 return 0; 4129 err: 4130 mutex_unlock(&state->internal->demod_lock); 4131 dprintk(FE_ERROR, 1, "I/O error"); 4132 return -1; 4133 } 4134 4135 static void stv090x_release(struct dvb_frontend *fe) 4136 { 4137 struct stv090x_state *state = fe->demodulator_priv; 4138 4139 state->internal->num_used--; 4140 if (state->internal->num_used <= 0) { 4141 4142 dprintk(FE_ERROR, 1, "Actually removing"); 4143 4144 remove_dev(state->internal); 4145 kfree(state->internal); 4146 } 4147 4148 kfree(state); 4149 } 4150 4151 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) 4152 { 4153 u32 reg = 0; 4154 4155 reg = stv090x_read_reg(state, STV090x_GENCFG); 4156 4157 switch (ldpc_mode) { 4158 case STV090x_DUAL: 4159 default: 4160 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { 4161 /* set LDPC to dual mode */ 4162 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) 4163 goto err; 4164 4165 state->demod_mode = STV090x_DUAL; 4166 4167 reg = stv090x_read_reg(state, STV090x_TSTRES0); 4168 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 4169 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4170 goto err; 4171 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 4172 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4173 goto err; 4174 4175 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 4176 goto err; 4177 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 4178 goto err; 4179 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 4180 goto err; 4181 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 4182 goto err; 4183 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 4184 goto err; 4185 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 4186 goto err; 4187 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 4188 goto err; 4189 4190 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 4191 goto err; 4192 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 4193 goto err; 4194 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 4195 goto err; 4196 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 4197 goto err; 4198 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 4199 goto err; 4200 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 4201 goto err; 4202 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 4203 goto err; 4204 4205 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 4206 goto err; 4207 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 4208 goto err; 4209 } 4210 break; 4211 4212 case STV090x_SINGLE: 4213 if (stv090x_stop_modcod(state) < 0) 4214 goto err; 4215 if (stv090x_activate_modcod_single(state) < 0) 4216 goto err; 4217 4218 if (state->demod == STV090x_DEMODULATOR_1) { 4219 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ 4220 goto err; 4221 } else { 4222 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ 4223 goto err; 4224 } 4225 4226 reg = stv090x_read_reg(state, STV090x_TSTRES0); 4227 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 4228 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4229 goto err; 4230 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 4231 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4232 goto err; 4233 4234 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 4235 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); 4236 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4237 goto err; 4238 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); 4239 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4240 goto err; 4241 break; 4242 } 4243 4244 return 0; 4245 err: 4246 dprintk(FE_ERROR, 1, "I/O error"); 4247 return -1; 4248 } 4249 4250 /* return (Hz), clk in Hz*/ 4251 static u32 stv090x_get_mclk(struct stv090x_state *state) 4252 { 4253 const struct stv090x_config *config = state->config; 4254 u32 div, reg; 4255 u8 ratio; 4256 4257 div = stv090x_read_reg(state, STV090x_NCOARSE); 4258 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4259 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; 4260 4261 return (div + 1) * config->xtal / ratio; /* kHz */ 4262 } 4263 4264 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) 4265 { 4266 const struct stv090x_config *config = state->config; 4267 u32 reg, div, clk_sel; 4268 4269 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4270 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); 4271 4272 div = ((clk_sel * mclk) / config->xtal) - 1; 4273 4274 reg = stv090x_read_reg(state, STV090x_NCOARSE); 4275 STV090x_SETFIELD(reg, M_DIV_FIELD, div); 4276 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) 4277 goto err; 4278 4279 state->internal->mclk = stv090x_get_mclk(state); 4280 4281 /*Set the DiseqC frequency to 22KHz */ 4282 div = state->internal->mclk / 704000; 4283 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) 4284 goto err; 4285 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) 4286 goto err; 4287 4288 return 0; 4289 err: 4290 dprintk(FE_ERROR, 1, "I/O error"); 4291 return -1; 4292 } 4293 4294 static int stv0900_set_tspath(struct stv090x_state *state) 4295 { 4296 u32 reg; 4297 4298 if (state->internal->dev_ver >= 0x20) { 4299 switch (state->config->ts1_mode) { 4300 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4301 case STV090x_TSMODE_DVBCI: 4302 switch (state->config->ts2_mode) { 4303 case STV090x_TSMODE_SERIAL_PUNCTURED: 4304 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4305 default: 4306 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); 4307 break; 4308 4309 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4310 case STV090x_TSMODE_DVBCI: 4311 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ 4312 goto err; 4313 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4314 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4315 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4316 goto err; 4317 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4318 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4319 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4320 goto err; 4321 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4322 goto err; 4323 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4324 goto err; 4325 break; 4326 } 4327 break; 4328 4329 case STV090x_TSMODE_SERIAL_PUNCTURED: 4330 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4331 default: 4332 switch (state->config->ts2_mode) { 4333 case STV090x_TSMODE_SERIAL_PUNCTURED: 4334 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4335 default: 4336 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4337 goto err; 4338 break; 4339 4340 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4341 case STV090x_TSMODE_DVBCI: 4342 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) 4343 goto err; 4344 break; 4345 } 4346 break; 4347 } 4348 } else { 4349 switch (state->config->ts1_mode) { 4350 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4351 case STV090x_TSMODE_DVBCI: 4352 switch (state->config->ts2_mode) { 4353 case STV090x_TSMODE_SERIAL_PUNCTURED: 4354 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4355 default: 4356 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); 4357 break; 4358 4359 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4360 case STV090x_TSMODE_DVBCI: 4361 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); 4362 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4363 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4364 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4365 goto err; 4366 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4367 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); 4368 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4369 goto err; 4370 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4371 goto err; 4372 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4373 goto err; 4374 break; 4375 } 4376 break; 4377 4378 case STV090x_TSMODE_SERIAL_PUNCTURED: 4379 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4380 default: 4381 switch (state->config->ts2_mode) { 4382 case STV090x_TSMODE_SERIAL_PUNCTURED: 4383 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4384 default: 4385 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); 4386 break; 4387 4388 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4389 case STV090x_TSMODE_DVBCI: 4390 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); 4391 break; 4392 } 4393 break; 4394 } 4395 } 4396 4397 switch (state->config->ts1_mode) { 4398 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4399 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4400 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4401 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4402 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4403 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4404 goto err; 4405 break; 4406 4407 case STV090x_TSMODE_DVBCI: 4408 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4409 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4410 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4411 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4412 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4413 goto err; 4414 break; 4415 4416 case STV090x_TSMODE_SERIAL_PUNCTURED: 4417 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4418 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4419 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4420 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4421 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4422 goto err; 4423 break; 4424 4425 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4426 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4427 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4428 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4429 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4430 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4431 goto err; 4432 break; 4433 4434 default: 4435 break; 4436 } 4437 4438 switch (state->config->ts2_mode) { 4439 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4440 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4441 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4442 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4443 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4444 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4445 goto err; 4446 break; 4447 4448 case STV090x_TSMODE_DVBCI: 4449 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4450 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4451 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4452 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4453 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4454 goto err; 4455 break; 4456 4457 case STV090x_TSMODE_SERIAL_PUNCTURED: 4458 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4459 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4460 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4461 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4462 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4463 goto err; 4464 break; 4465 4466 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4467 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4468 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4469 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4470 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4471 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4472 goto err; 4473 break; 4474 4475 default: 4476 break; 4477 } 4478 4479 if (state->config->ts1_clk > 0) { 4480 u32 speed; 4481 4482 switch (state->config->ts1_mode) { 4483 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4484 case STV090x_TSMODE_DVBCI: 4485 default: 4486 speed = state->internal->mclk / 4487 (state->config->ts1_clk / 4); 4488 if (speed < 0x08) 4489 speed = 0x08; 4490 if (speed > 0xFF) 4491 speed = 0xFF; 4492 break; 4493 case STV090x_TSMODE_SERIAL_PUNCTURED: 4494 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4495 speed = state->internal->mclk / 4496 (state->config->ts1_clk / 32); 4497 if (speed < 0x20) 4498 speed = 0x20; 4499 if (speed > 0xFF) 4500 speed = 0xFF; 4501 break; 4502 } 4503 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4504 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4505 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4506 goto err; 4507 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) 4508 goto err; 4509 } 4510 4511 if (state->config->ts2_clk > 0) { 4512 u32 speed; 4513 4514 switch (state->config->ts2_mode) { 4515 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4516 case STV090x_TSMODE_DVBCI: 4517 default: 4518 speed = state->internal->mclk / 4519 (state->config->ts2_clk / 4); 4520 if (speed < 0x08) 4521 speed = 0x08; 4522 if (speed > 0xFF) 4523 speed = 0xFF; 4524 break; 4525 case STV090x_TSMODE_SERIAL_PUNCTURED: 4526 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4527 speed = state->internal->mclk / 4528 (state->config->ts2_clk / 32); 4529 if (speed < 0x20) 4530 speed = 0x20; 4531 if (speed > 0xFF) 4532 speed = 0xFF; 4533 break; 4534 } 4535 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4536 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4537 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4538 goto err; 4539 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) 4540 goto err; 4541 } 4542 4543 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4544 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4545 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4546 goto err; 4547 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4548 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4549 goto err; 4550 4551 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4552 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4553 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4554 goto err; 4555 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4556 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4557 goto err; 4558 4559 return 0; 4560 err: 4561 dprintk(FE_ERROR, 1, "I/O error"); 4562 return -1; 4563 } 4564 4565 static int stv0903_set_tspath(struct stv090x_state *state) 4566 { 4567 u32 reg; 4568 4569 if (state->internal->dev_ver >= 0x20) { 4570 switch (state->config->ts1_mode) { 4571 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4572 case STV090x_TSMODE_DVBCI: 4573 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); 4574 break; 4575 4576 case STV090x_TSMODE_SERIAL_PUNCTURED: 4577 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4578 default: 4579 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c); 4580 break; 4581 } 4582 } else { 4583 switch (state->config->ts1_mode) { 4584 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4585 case STV090x_TSMODE_DVBCI: 4586 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); 4587 break; 4588 4589 case STV090x_TSMODE_SERIAL_PUNCTURED: 4590 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4591 default: 4592 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); 4593 break; 4594 } 4595 } 4596 4597 switch (state->config->ts1_mode) { 4598 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4599 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4600 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4601 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4602 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4603 goto err; 4604 break; 4605 4606 case STV090x_TSMODE_DVBCI: 4607 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4608 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4609 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4610 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4611 goto err; 4612 break; 4613 4614 case STV090x_TSMODE_SERIAL_PUNCTURED: 4615 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4616 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4617 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4618 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4619 goto err; 4620 break; 4621 4622 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4623 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4624 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4625 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4626 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4627 goto err; 4628 break; 4629 4630 default: 4631 break; 4632 } 4633 4634 if (state->config->ts1_clk > 0) { 4635 u32 speed; 4636 4637 switch (state->config->ts1_mode) { 4638 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4639 case STV090x_TSMODE_DVBCI: 4640 default: 4641 speed = state->internal->mclk / 4642 (state->config->ts1_clk / 4); 4643 if (speed < 0x08) 4644 speed = 0x08; 4645 if (speed > 0xFF) 4646 speed = 0xFF; 4647 break; 4648 case STV090x_TSMODE_SERIAL_PUNCTURED: 4649 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4650 speed = state->internal->mclk / 4651 (state->config->ts1_clk / 32); 4652 if (speed < 0x20) 4653 speed = 0x20; 4654 if (speed > 0xFF) 4655 speed = 0xFF; 4656 break; 4657 } 4658 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4659 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4660 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4661 goto err; 4662 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) 4663 goto err; 4664 } 4665 4666 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4667 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4668 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4669 goto err; 4670 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4671 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4672 goto err; 4673 4674 return 0; 4675 err: 4676 dprintk(FE_ERROR, 1, "I/O error"); 4677 return -1; 4678 } 4679 4680 static int stv090x_init(struct dvb_frontend *fe) 4681 { 4682 struct stv090x_state *state = fe->demodulator_priv; 4683 const struct stv090x_config *config = state->config; 4684 u32 reg; 4685 4686 if (state->internal->mclk == 0) { 4687 /* call tuner init to configure the tuner's clock output 4688 divider directly before setting up the master clock of 4689 the stv090x. */ 4690 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4691 goto err; 4692 4693 if (config->tuner_init) { 4694 if (config->tuner_init(fe) < 0) 4695 goto err_gateoff; 4696 } 4697 4698 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4699 goto err; 4700 4701 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ 4702 msleep(5); 4703 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 4704 0x20 | config->clk_mode) < 0) 4705 goto err; 4706 stv090x_get_mclk(state); 4707 } 4708 4709 if (stv090x_wakeup(fe) < 0) { 4710 dprintk(FE_ERROR, 1, "Error waking device"); 4711 goto err; 4712 } 4713 4714 if (stv090x_ldpc_mode(state, state->demod_mode) < 0) 4715 goto err; 4716 4717 reg = STV090x_READ_DEMOD(state, TNRCFG2); 4718 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); 4719 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) 4720 goto err; 4721 reg = STV090x_READ_DEMOD(state, DEMOD); 4722 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 4723 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 4724 goto err; 4725 4726 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4727 goto err; 4728 4729 if (config->tuner_set_mode) { 4730 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0) 4731 goto err_gateoff; 4732 } 4733 4734 if (config->tuner_init) { 4735 if (config->tuner_init(fe) < 0) 4736 goto err_gateoff; 4737 } 4738 4739 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4740 goto err; 4741 4742 if (state->device == STV0900) { 4743 if (stv0900_set_tspath(state) < 0) 4744 goto err; 4745 } else { 4746 if (stv0903_set_tspath(state) < 0) 4747 goto err; 4748 } 4749 4750 return 0; 4751 4752 err_gateoff: 4753 stv090x_i2c_gate_ctrl(state, 0); 4754 err: 4755 dprintk(FE_ERROR, 1, "I/O error"); 4756 return -1; 4757 } 4758 4759 static int stv090x_setup(struct dvb_frontend *fe) 4760 { 4761 struct stv090x_state *state = fe->demodulator_priv; 4762 const struct stv090x_config *config = state->config; 4763 const struct stv090x_reg *stv090x_initval = NULL; 4764 const struct stv090x_reg *stv090x_cut20_val = NULL; 4765 unsigned long t1_size = 0, t2_size = 0; 4766 u32 reg = 0; 4767 4768 int i; 4769 4770 if (state->device == STV0900) { 4771 dprintk(FE_DEBUG, 1, "Initializing STV0900"); 4772 stv090x_initval = stv0900_initval; 4773 t1_size = ARRAY_SIZE(stv0900_initval); 4774 stv090x_cut20_val = stv0900_cut20_val; 4775 t2_size = ARRAY_SIZE(stv0900_cut20_val); 4776 } else if (state->device == STV0903) { 4777 dprintk(FE_DEBUG, 1, "Initializing STV0903"); 4778 stv090x_initval = stv0903_initval; 4779 t1_size = ARRAY_SIZE(stv0903_initval); 4780 stv090x_cut20_val = stv0903_cut20_val; 4781 t2_size = ARRAY_SIZE(stv0903_cut20_val); 4782 } 4783 4784 /* STV090x init */ 4785 4786 /* Stop Demod */ 4787 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) 4788 goto err; 4789 if (state->device == STV0900) 4790 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) 4791 goto err; 4792 4793 msleep(5); 4794 4795 /* Set No Tuner Mode */ 4796 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) 4797 goto err; 4798 if (state->device == STV0900) 4799 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) 4800 goto err; 4801 4802 /* I2C repeater OFF */ 4803 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); 4804 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) 4805 goto err; 4806 if (state->device == STV0900) 4807 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) 4808 goto err; 4809 4810 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ 4811 goto err; 4812 msleep(5); 4813 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ 4814 goto err; 4815 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ 4816 goto err; 4817 msleep(5); 4818 4819 /* write initval */ 4820 dprintk(FE_DEBUG, 1, "Setting up initial values"); 4821 for (i = 0; i < t1_size; i++) { 4822 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) 4823 goto err; 4824 } 4825 4826 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); 4827 if (state->internal->dev_ver >= 0x20) { 4828 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4829 goto err; 4830 4831 /* write cut20_val*/ 4832 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values"); 4833 for (i = 0; i < t2_size; i++) { 4834 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) 4835 goto err; 4836 } 4837 4838 } else if (state->internal->dev_ver < 0x20) { 4839 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!", 4840 state->internal->dev_ver); 4841 4842 goto err; 4843 } else if (state->internal->dev_ver > 0x30) { 4844 /* we shouldn't bail out from here */ 4845 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!", 4846 state->internal->dev_ver); 4847 } 4848 4849 /* ADC1 range */ 4850 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4851 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, 4852 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1); 4853 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4854 goto err; 4855 4856 /* ADC2 range */ 4857 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 4858 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, 4859 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1); 4860 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 4861 goto err; 4862 4863 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) 4864 goto err; 4865 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) 4866 goto err; 4867 4868 return 0; 4869 err: 4870 dprintk(FE_ERROR, 1, "I/O error"); 4871 return -1; 4872 } 4873 4874 static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, 4875 u8 value, u8 xor_value) 4876 { 4877 struct stv090x_state *state = fe->demodulator_priv; 4878 u8 reg = 0; 4879 4880 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir); 4881 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value); 4882 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value); 4883 4884 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); 4885 } 4886 4887 static const struct dvb_frontend_ops stv090x_ops = { 4888 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, 4889 .info = { 4890 .name = "STV090x Multistandard", 4891 .frequency_min = 950000, 4892 .frequency_max = 2150000, 4893 .frequency_stepsize = 0, 4894 .frequency_tolerance = 0, 4895 .symbol_rate_min = 1000000, 4896 .symbol_rate_max = 45000000, 4897 .caps = FE_CAN_INVERSION_AUTO | 4898 FE_CAN_FEC_AUTO | 4899 FE_CAN_QPSK | 4900 FE_CAN_2G_MODULATION 4901 }, 4902 4903 .release = stv090x_release, 4904 .init = stv090x_init, 4905 4906 .sleep = stv090x_sleep, 4907 .get_frontend_algo = stv090x_frontend_algo, 4908 4909 .diseqc_send_master_cmd = stv090x_send_diseqc_msg, 4910 .diseqc_send_burst = stv090x_send_diseqc_burst, 4911 .diseqc_recv_slave_reply = stv090x_recv_slave_reply, 4912 .set_tone = stv090x_set_tone, 4913 4914 .search = stv090x_search, 4915 .read_status = stv090x_read_status, 4916 .read_ber = stv090x_read_per, 4917 .read_signal_strength = stv090x_read_signal_strength, 4918 .read_snr = stv090x_read_cnr, 4919 }; 4920 4921 4922 struct dvb_frontend *stv090x_attach(struct stv090x_config *config, 4923 struct i2c_adapter *i2c, 4924 enum stv090x_demodulator demod) 4925 { 4926 struct stv090x_state *state = NULL; 4927 struct stv090x_dev *temp_int; 4928 4929 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL); 4930 if (state == NULL) 4931 goto error; 4932 4933 state->verbose = &verbose; 4934 state->config = config; 4935 state->i2c = i2c; 4936 state->frontend.ops = stv090x_ops; 4937 state->frontend.demodulator_priv = state; 4938 state->demod = demod; 4939 state->demod_mode = config->demod_mode; /* Single or Dual mode */ 4940 state->device = config->device; 4941 state->rolloff = STV090x_RO_35; /* default */ 4942 4943 temp_int = find_dev(state->i2c, 4944 state->config->address); 4945 4946 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) { 4947 state->internal = temp_int->internal; 4948 state->internal->num_used++; 4949 dprintk(FE_INFO, 1, "Found Internal Structure!"); 4950 } else { 4951 state->internal = kmalloc(sizeof(struct stv090x_internal), 4952 GFP_KERNEL); 4953 if (!state->internal) 4954 goto error; 4955 temp_int = append_internal(state->internal); 4956 if (!temp_int) { 4957 kfree(state->internal); 4958 goto error; 4959 } 4960 state->internal->num_used = 1; 4961 state->internal->mclk = 0; 4962 state->internal->dev_ver = 0; 4963 state->internal->i2c_adap = state->i2c; 4964 state->internal->i2c_addr = state->config->address; 4965 dprintk(FE_INFO, 1, "Create New Internal Structure!"); 4966 4967 mutex_init(&state->internal->demod_lock); 4968 mutex_init(&state->internal->tuner_lock); 4969 4970 if (stv090x_setup(&state->frontend) < 0) { 4971 dprintk(FE_ERROR, 1, "Error setting up device"); 4972 goto err_remove; 4973 } 4974 } 4975 4976 if (state->internal->dev_ver >= 0x30) 4977 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM; 4978 4979 /* workaround for stuck DiSEqC output */ 4980 if (config->diseqc_envelope_mode) 4981 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); 4982 4983 config->set_gpio = stv090x_set_gpio; 4984 4985 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", 4986 state->device == STV0900 ? "STV0900" : "STV0903", 4987 demod, 4988 state->internal->dev_ver); 4989 4990 return &state->frontend; 4991 4992 err_remove: 4993 remove_dev(state->internal); 4994 kfree(state->internal); 4995 error: 4996 kfree(state); 4997 return NULL; 4998 } 4999 EXPORT_SYMBOL(stv090x_attach); 5000 MODULE_PARM_DESC(verbose, "Set Verbosity level"); 5001 MODULE_AUTHOR("Manu Abraham"); 5002 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend"); 5003 MODULE_LICENSE("GPL"); 5004