1 /*
2  * stv0900_sw.c
3  *
4  * Driver for ST STV0900 satellite demodulator IC.
5  *
6  * Copyright (C) ST Microelectronics.
7  * Copyright (C) 2009 NetUP Inc.
8  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24  */
25 
26 #include "stv0900.h"
27 #include "stv0900_reg.h"
28 #include "stv0900_priv.h"
29 
30 s32 shiftx(s32 x, int demod, s32 shift)
31 {
32 	if (demod == 1)
33 		return x - shift;
34 
35 	return x;
36 }
37 
38 int stv0900_check_signal_presence(struct stv0900_internal *intp,
39 					enum fe_stv0900_demod_num demod)
40 {
41 	s32	carr_offset,
42 		agc2_integr,
43 		max_carrier;
44 
45 	int no_signal = FALSE;
46 
47 	carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
48 					| stv0900_read_reg(intp, CFR1);
49 	carr_offset = ge2comp(carr_offset, 16);
50 	agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
51 					| stv0900_read_reg(intp, AGC2I0);
52 	max_carrier = intp->srch_range[demod] / 1000;
53 
54 	max_carrier += (max_carrier / 10);
55 	max_carrier = 65536 * (max_carrier / 2);
56 	max_carrier /= intp->mclk / 1000;
57 	if (max_carrier > 0x4000)
58 		max_carrier = 0x4000;
59 
60 	if ((agc2_integr > 0x2000)
61 			|| (carr_offset > (2 * max_carrier))
62 			|| (carr_offset < (-2 * max_carrier)))
63 		no_signal = TRUE;
64 
65 	return no_signal;
66 }
67 
68 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
69 				s32 *frequency_inc, s32 *sw_timeout,
70 				s32 *steps,
71 				enum fe_stv0900_demod_num demod)
72 {
73 	s32 timeout, freq_inc, max_steps, srate, max_carrier;
74 
75 	enum fe_stv0900_search_standard	standard;
76 
77 	srate = intp->symbol_rate[demod];
78 	max_carrier = intp->srch_range[demod] / 1000;
79 	max_carrier += max_carrier / 10;
80 	standard = intp->srch_standard[demod];
81 
82 	max_carrier = 65536 * (max_carrier / 2);
83 	max_carrier /= intp->mclk / 1000;
84 
85 	if (max_carrier > 0x4000)
86 		max_carrier = 0x4000;
87 
88 	freq_inc = srate;
89 	freq_inc /= intp->mclk >> 10;
90 	freq_inc = freq_inc << 6;
91 
92 	switch (standard) {
93 	case STV0900_SEARCH_DVBS1:
94 	case STV0900_SEARCH_DSS:
95 		freq_inc *= 3;
96 		timeout = 20;
97 		break;
98 	case STV0900_SEARCH_DVBS2:
99 		freq_inc *= 4;
100 		timeout = 25;
101 		break;
102 	case STV0900_AUTO_SEARCH:
103 	default:
104 		freq_inc *= 3;
105 		timeout = 25;
106 		break;
107 	}
108 
109 	freq_inc /= 100;
110 
111 	if ((freq_inc > max_carrier) || (freq_inc < 0))
112 		freq_inc = max_carrier / 2;
113 
114 	timeout *= 27500;
115 
116 	if (srate > 0)
117 		timeout /= srate / 1000;
118 
119 	if ((timeout > 100) || (timeout < 0))
120 		timeout = 100;
121 
122 	max_steps = (max_carrier / freq_inc) + 1;
123 
124 	if ((max_steps > 100) || (max_steps < 0)) {
125 		max_steps =  100;
126 		freq_inc = max_carrier / max_steps;
127 	}
128 
129 	*frequency_inc = freq_inc;
130 	*sw_timeout = timeout;
131 	*steps = max_steps;
132 
133 }
134 
135 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
136 				s32 FreqIncr, s32 Timeout, int zigzag,
137 				s32 MaxStep, enum fe_stv0900_demod_num demod)
138 {
139 	int	no_signal,
140 		lock = FALSE;
141 	s32	stepCpt,
142 		freqOffset,
143 		max_carrier;
144 
145 	max_carrier = intp->srch_range[demod] / 1000;
146 	max_carrier += (max_carrier / 10);
147 
148 	max_carrier = 65536 * (max_carrier / 2);
149 	max_carrier /= intp->mclk / 1000;
150 
151 	if (max_carrier > 0x4000)
152 		max_carrier = 0x4000;
153 
154 	if (zigzag == TRUE)
155 		freqOffset = 0;
156 	else
157 		freqOffset = -max_carrier + FreqIncr;
158 
159 	stepCpt = 0;
160 
161 	do {
162 		stv0900_write_reg(intp, DMDISTATE, 0x1c);
163 		stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
164 		stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
165 		stv0900_write_reg(intp, DMDISTATE, 0x18);
166 		stv0900_write_bits(intp, ALGOSWRST, 1);
167 
168 		if (intp->chip_id == 0x12) {
169 			stv0900_write_bits(intp, RST_HWARE, 1);
170 			stv0900_write_bits(intp, RST_HWARE, 0);
171 		}
172 
173 		if (zigzag == TRUE) {
174 			if (freqOffset >= 0)
175 				freqOffset = -freqOffset - 2 * FreqIncr;
176 			else
177 				freqOffset = -freqOffset;
178 		} else
179 			freqOffset += + 2 * FreqIncr;
180 
181 		stepCpt++;
182 		lock = stv0900_get_demod_lock(intp, demod, Timeout);
183 		no_signal = stv0900_check_signal_presence(intp, demod);
184 
185 	} while ((lock == FALSE)
186 			&& (no_signal == FALSE)
187 			&& ((freqOffset - FreqIncr) <  max_carrier)
188 			&& ((freqOffset + FreqIncr) > -max_carrier)
189 			&& (stepCpt < MaxStep));
190 
191 	stv0900_write_bits(intp, ALGOSWRST, 0);
192 
193 	return lock;
194 }
195 
196 static int stv0900_sw_algo(struct stv0900_internal *intp,
197 				enum fe_stv0900_demod_num demod)
198 {
199 	int	lock = FALSE,
200 		no_signal,
201 		zigzag;
202 	s32	s2fw,
203 		fqc_inc,
204 		sft_stp_tout,
205 		trial_cntr,
206 		max_steps;
207 
208 	stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
209 					&max_steps, demod);
210 	switch (intp->srch_standard[demod]) {
211 	case STV0900_SEARCH_DVBS1:
212 	case STV0900_SEARCH_DSS:
213 		if (intp->chip_id >= 0x20)
214 			stv0900_write_reg(intp, CARFREQ, 0x3b);
215 		else
216 			stv0900_write_reg(intp, CARFREQ, 0xef);
217 
218 		stv0900_write_reg(intp, DMDCFGMD, 0x49);
219 		zigzag = FALSE;
220 		break;
221 	case STV0900_SEARCH_DVBS2:
222 		if (intp->chip_id >= 0x20)
223 			stv0900_write_reg(intp, CORRELABS, 0x79);
224 		else
225 			stv0900_write_reg(intp, CORRELABS, 0x68);
226 
227 		stv0900_write_reg(intp, DMDCFGMD, 0x89);
228 
229 		zigzag = TRUE;
230 		break;
231 	case STV0900_AUTO_SEARCH:
232 	default:
233 		if (intp->chip_id >= 0x20) {
234 			stv0900_write_reg(intp, CARFREQ, 0x3b);
235 			stv0900_write_reg(intp, CORRELABS, 0x79);
236 		} else {
237 			stv0900_write_reg(intp, CARFREQ, 0xef);
238 			stv0900_write_reg(intp, CORRELABS, 0x68);
239 		}
240 
241 		stv0900_write_reg(intp, DMDCFGMD, 0xc9);
242 		zigzag = FALSE;
243 		break;
244 	}
245 
246 	trial_cntr = 0;
247 	do {
248 		lock = stv0900_search_carr_sw_loop(intp,
249 						fqc_inc,
250 						sft_stp_tout,
251 						zigzag,
252 						max_steps,
253 						demod);
254 		no_signal = stv0900_check_signal_presence(intp, demod);
255 		trial_cntr++;
256 		if ((lock == TRUE)
257 				|| (no_signal == TRUE)
258 				|| (trial_cntr == 2)) {
259 
260 			if (intp->chip_id >= 0x20) {
261 				stv0900_write_reg(intp, CARFREQ, 0x49);
262 				stv0900_write_reg(intp, CORRELABS, 0x9e);
263 			} else {
264 				stv0900_write_reg(intp, CARFREQ, 0xed);
265 				stv0900_write_reg(intp, CORRELABS, 0x88);
266 			}
267 
268 			if ((stv0900_get_bits(intp, HEADER_MODE) ==
269 						STV0900_DVBS2_FOUND) &&
270 							(lock == TRUE)) {
271 				msleep(sft_stp_tout);
272 				s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
273 
274 				if (s2fw < 0xd) {
275 					msleep(sft_stp_tout);
276 					s2fw = stv0900_get_bits(intp,
277 								FLYWHEEL_CPT);
278 				}
279 
280 				if (s2fw < 0xd) {
281 					lock = FALSE;
282 
283 					if (trial_cntr < 2) {
284 						if (intp->chip_id >= 0x20)
285 							stv0900_write_reg(intp,
286 								CORRELABS,
287 								0x79);
288 						else
289 							stv0900_write_reg(intp,
290 								CORRELABS,
291 								0x68);
292 
293 						stv0900_write_reg(intp,
294 								DMDCFGMD,
295 								0x89);
296 					}
297 				}
298 			}
299 		}
300 
301 	} while ((lock == FALSE)
302 		&& (trial_cntr < 2)
303 		&& (no_signal == FALSE));
304 
305 	return lock;
306 }
307 
308 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
309 					u32 mclk,
310 					enum fe_stv0900_demod_num demod)
311 {
312 	s32	rem1, rem2, intval1, intval2, srate;
313 
314 	srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
315 		(stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
316 		(stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
317 		(stv0900_get_bits(intp, SYMB_FREQ0));
318 	dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
319 		srate, stv0900_get_bits(intp, SYMB_FREQ0),
320 		stv0900_get_bits(intp, SYMB_FREQ1),
321 		stv0900_get_bits(intp, SYMB_FREQ2),
322 		stv0900_get_bits(intp, SYMB_FREQ3));
323 
324 	intval1 = (mclk) >> 16;
325 	intval2 = (srate) >> 16;
326 
327 	rem1 = (mclk) % 0x10000;
328 	rem2 = (srate) % 0x10000;
329 	srate =	(intval1 * intval2) +
330 		((intval1 * rem2) >> 16) +
331 		((intval2 * rem1) >> 16);
332 
333 	return srate;
334 }
335 
336 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
337 					u32 mclk, u32 srate,
338 					enum fe_stv0900_demod_num demod)
339 {
340 	u32 symb;
341 
342 	dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
343 							srate, demod);
344 
345 	if (srate > 60000000) {
346 		symb = srate << 4;
347 		symb /= (mclk >> 12);
348 	} else if (srate > 6000000) {
349 		symb = srate << 6;
350 		symb /= (mclk >> 10);
351 	} else {
352 		symb = srate << 9;
353 		symb /= (mclk >> 7);
354 	}
355 
356 	stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
357 	stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
358 }
359 
360 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
361 					u32 mclk, u32 srate,
362 					enum fe_stv0900_demod_num demod)
363 {
364 	u32 symb;
365 
366 	srate = 105 * (srate / 100);
367 
368 	if (srate > 60000000) {
369 		symb = srate << 4;
370 		symb /= (mclk >> 12);
371 	} else if (srate > 6000000) {
372 		symb = srate << 6;
373 		symb /= (mclk >> 10);
374 	} else {
375 		symb = srate << 9;
376 		symb /= (mclk >> 7);
377 	}
378 
379 	if (symb < 0x7fff) {
380 		stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
381 		stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
382 	} else {
383 		stv0900_write_reg(intp, SFRUP1, 0x7f);
384 		stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
385 	}
386 }
387 
388 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
389 					u32 mclk, u32 srate,
390 					enum fe_stv0900_demod_num demod)
391 {
392 	u32	symb;
393 
394 	srate = 95 * (srate / 100);
395 	if (srate > 60000000) {
396 		symb = srate << 4;
397 		symb /= (mclk >> 12);
398 
399 	} else if (srate > 6000000) {
400 		symb = srate << 6;
401 		symb /= (mclk >> 10);
402 
403 	} else {
404 		symb = srate << 9;
405 		symb /= (mclk >> 7);
406 	}
407 
408 	stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
409 	stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
410 }
411 
412 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
413 					u32 srate,
414 					enum fe_stv0900_demod_num demod)
415 {
416 	s32 timingoffset;
417 
418 
419 	timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
420 		       (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
421 		       (stv0900_read_reg(intp, TMGREG2 + 2));
422 
423 	timingoffset = ge2comp(timingoffset, 24);
424 
425 
426 	if (timingoffset == 0)
427 		timingoffset = 1;
428 
429 	timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
430 	timingoffset /= 320;
431 
432 	return timingoffset;
433 }
434 
435 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
436 					enum fe_stv0900_demod_num demod)
437 {
438 	s32 rolloff;
439 
440 	if (intp->chip_id == 0x10) {
441 		stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
442 		rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
443 		stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
444 	} else if (intp->chip_id <= 0x20)
445 		stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
446 	else /* cut 3.0 */
447 		stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
448 }
449 
450 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
451 {
452 	u32 rolloff;
453 
454 	switch (ro) {
455 	case STV0900_20:
456 		rolloff = 20;
457 		break;
458 	case STV0900_25:
459 		rolloff = 25;
460 		break;
461 	case STV0900_35:
462 	default:
463 		rolloff = 35;
464 		break;
465 	}
466 
467 	return srate  + (srate * rolloff) / 100;
468 }
469 
470 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
471 				enum fe_stv0900_demod_num demod)
472 {
473 	int timingLock = FALSE;
474 	s32	i,
475 		timingcpt = 0;
476 	u8	car_freq,
477 		tmg_th_high,
478 		tmg_th_low;
479 
480 	car_freq = stv0900_read_reg(intp, CARFREQ);
481 	tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
482 	tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
483 	stv0900_write_reg(intp, TMGTHRISE, 0x20);
484 	stv0900_write_reg(intp, TMGTHFALL, 0x0);
485 	stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
486 	stv0900_write_reg(intp, RTC, 0x80);
487 	stv0900_write_reg(intp, RTCS2, 0x40);
488 	stv0900_write_reg(intp, CARFREQ, 0x0);
489 	stv0900_write_reg(intp, CFRINIT1, 0x0);
490 	stv0900_write_reg(intp, CFRINIT0, 0x0);
491 	stv0900_write_reg(intp, AGC2REF, 0x65);
492 	stv0900_write_reg(intp, DMDISTATE, 0x18);
493 	msleep(7);
494 
495 	for (i = 0; i < 10; i++) {
496 		if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
497 			timingcpt++;
498 
499 		msleep(1);
500 	}
501 
502 	if (timingcpt >= 3)
503 		timingLock = TRUE;
504 
505 	stv0900_write_reg(intp, AGC2REF, 0x38);
506 	stv0900_write_reg(intp, RTC, 0x88);
507 	stv0900_write_reg(intp, RTCS2, 0x68);
508 	stv0900_write_reg(intp, CARFREQ, car_freq);
509 	stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
510 	stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
511 
512 	return	timingLock;
513 }
514 
515 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
516 					s32 demod_timeout)
517 {
518 	struct stv0900_state *state = fe->demodulator_priv;
519 	struct stv0900_internal *intp = state->internal;
520 	enum fe_stv0900_demod_num demod = state->demod;
521 	int	lock = FALSE,
522 		d = demod;
523 	s32	srate,
524 		search_range,
525 		locktimeout,
526 		currier_step,
527 		nb_steps,
528 		current_step,
529 		direction,
530 		tuner_freq,
531 		timeout,
532 		freq;
533 
534 	srate = intp->symbol_rate[d];
535 	search_range = intp->srch_range[d];
536 
537 	if (srate >= 10000000)
538 		locktimeout = demod_timeout / 3;
539 	else
540 		locktimeout = demod_timeout / 2;
541 
542 	lock = stv0900_get_demod_lock(intp, d, locktimeout);
543 
544 	if (lock != FALSE)
545 		return lock;
546 
547 	if (srate >= 10000000) {
548 		if (stv0900_check_timing_lock(intp, d) == TRUE) {
549 			stv0900_write_reg(intp, DMDISTATE, 0x1f);
550 			stv0900_write_reg(intp, DMDISTATE, 0x15);
551 			lock = stv0900_get_demod_lock(intp, d, demod_timeout);
552 		} else
553 			lock = FALSE;
554 
555 		return lock;
556 	}
557 
558 	if (intp->chip_id <= 0x20) {
559 		if (srate <= 1000000)
560 			currier_step = 500;
561 		else if (srate <= 4000000)
562 			currier_step = 1000;
563 		else if (srate <= 7000000)
564 			currier_step = 2000;
565 		else if (srate <= 10000000)
566 			currier_step = 3000;
567 		else
568 			currier_step = 5000;
569 
570 		if (srate >= 2000000) {
571 			timeout = (demod_timeout / 3);
572 			if (timeout > 1000)
573 				timeout = 1000;
574 		} else
575 			timeout = (demod_timeout / 2);
576 	} else {
577 		/*cut 3.0 */
578 		currier_step = srate / 4000;
579 		timeout = (demod_timeout * 3) / 4;
580 	}
581 
582 	nb_steps = ((search_range / 1000) / currier_step);
583 
584 	if ((nb_steps % 2) != 0)
585 		nb_steps += 1;
586 
587 	if (nb_steps <= 0)
588 		nb_steps = 2;
589 	else if (nb_steps > 12)
590 		nb_steps = 12;
591 
592 	current_step = 1;
593 	direction = 1;
594 
595 	if (intp->chip_id <= 0x20) {
596 		tuner_freq = intp->freq[d];
597 		intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
598 				intp->rolloff) + intp->symbol_rate[d];
599 	} else
600 		tuner_freq = 0;
601 
602 	while ((current_step <= nb_steps) && (lock == FALSE)) {
603 		if (direction > 0)
604 			tuner_freq += (current_step * currier_step);
605 		else
606 			tuner_freq -= (current_step * currier_step);
607 
608 		if (intp->chip_id <= 0x20) {
609 			if (intp->tuner_type[d] == 3)
610 				stv0900_set_tuner_auto(intp, tuner_freq,
611 						intp->bw[d], demod);
612 			else
613 				stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
614 
615 			stv0900_write_reg(intp, DMDISTATE, 0x1c);
616 			stv0900_write_reg(intp, CFRINIT1, 0);
617 			stv0900_write_reg(intp, CFRINIT0, 0);
618 			stv0900_write_reg(intp, DMDISTATE, 0x1f);
619 			stv0900_write_reg(intp, DMDISTATE, 0x15);
620 		} else {
621 			stv0900_write_reg(intp, DMDISTATE, 0x1c);
622 			freq = (tuner_freq * 65536) / (intp->mclk / 1000);
623 			stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
624 			stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
625 			stv0900_write_reg(intp, DMDISTATE, 0x1f);
626 			stv0900_write_reg(intp, DMDISTATE, 0x05);
627 		}
628 
629 		lock = stv0900_get_demod_lock(intp, d, timeout);
630 		direction *= -1;
631 		current_step++;
632 	}
633 
634 	return	lock;
635 }
636 
637 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
638 					s32 srate,
639 					enum fe_stv0900_search_algo algo)
640 {
641 	switch (algo) {
642 	case STV0900_BLIND_SEARCH:
643 		if (srate <= 1500000) {
644 			(*demod_timeout) = 1500;
645 			(*fec_timeout) = 400;
646 		} else if (srate <= 5000000) {
647 			(*demod_timeout) = 1000;
648 			(*fec_timeout) = 300;
649 		} else {
650 			(*demod_timeout) = 700;
651 			(*fec_timeout) = 100;
652 		}
653 
654 		break;
655 	case STV0900_COLD_START:
656 	case STV0900_WARM_START:
657 	default:
658 		if (srate <= 1000000) {
659 			(*demod_timeout) = 3000;
660 			(*fec_timeout) = 1700;
661 		} else if (srate <= 2000000) {
662 			(*demod_timeout) = 2500;
663 			(*fec_timeout) = 1100;
664 		} else if (srate <= 5000000) {
665 			(*demod_timeout) = 1000;
666 			(*fec_timeout) = 550;
667 		} else if (srate <= 10000000) {
668 			(*demod_timeout) = 700;
669 			(*fec_timeout) = 250;
670 		} else if (srate <= 20000000) {
671 			(*demod_timeout) = 400;
672 			(*fec_timeout) = 130;
673 		} else {
674 			(*demod_timeout) = 300;
675 			(*fec_timeout) = 100;
676 		}
677 
678 		break;
679 
680 	}
681 
682 	if (algo == STV0900_WARM_START)
683 		(*demod_timeout) /= 2;
684 }
685 
686 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
687 					enum fe_stv0900_demod_num demod)
688 {
689 
690 	s32 vth_reg = VTH12;
691 
692 	dprintk("%s\n", __func__);
693 
694 	stv0900_write_reg(intp, vth_reg++, 0xd0);
695 	stv0900_write_reg(intp, vth_reg++, 0x7d);
696 	stv0900_write_reg(intp, vth_reg++, 0x53);
697 	stv0900_write_reg(intp, vth_reg++, 0x2f);
698 	stv0900_write_reg(intp, vth_reg++, 0x24);
699 	stv0900_write_reg(intp, vth_reg++, 0x1f);
700 }
701 
702 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
703 				   enum fe_stv0900_search_standard standard,
704 				   enum fe_stv0900_fec fec,
705 				   enum fe_stv0900_demod_num demod)
706 {
707 	dprintk("%s: ViterbiStandard = ", __func__);
708 
709 	switch (standard) {
710 	case STV0900_AUTO_SEARCH:
711 		dprintk("Auto\n");
712 		stv0900_write_reg(intp, FECM, 0x10);
713 		stv0900_write_reg(intp, PRVIT, 0x3f);
714 		break;
715 	case STV0900_SEARCH_DVBS1:
716 		dprintk("DVBS1\n");
717 		stv0900_write_reg(intp, FECM, 0x00);
718 		switch (fec) {
719 		case STV0900_FEC_UNKNOWN:
720 		default:
721 			stv0900_write_reg(intp, PRVIT, 0x2f);
722 			break;
723 		case STV0900_FEC_1_2:
724 			stv0900_write_reg(intp, PRVIT, 0x01);
725 			break;
726 		case STV0900_FEC_2_3:
727 			stv0900_write_reg(intp, PRVIT, 0x02);
728 			break;
729 		case STV0900_FEC_3_4:
730 			stv0900_write_reg(intp, PRVIT, 0x04);
731 			break;
732 		case STV0900_FEC_5_6:
733 			stv0900_write_reg(intp, PRVIT, 0x08);
734 			break;
735 		case STV0900_FEC_7_8:
736 			stv0900_write_reg(intp, PRVIT, 0x20);
737 			break;
738 		}
739 
740 		break;
741 	case STV0900_SEARCH_DSS:
742 		dprintk("DSS\n");
743 		stv0900_write_reg(intp, FECM, 0x80);
744 		switch (fec) {
745 		case STV0900_FEC_UNKNOWN:
746 		default:
747 			stv0900_write_reg(intp, PRVIT, 0x13);
748 			break;
749 		case STV0900_FEC_1_2:
750 			stv0900_write_reg(intp, PRVIT, 0x01);
751 			break;
752 		case STV0900_FEC_2_3:
753 			stv0900_write_reg(intp, PRVIT, 0x02);
754 			break;
755 		case STV0900_FEC_6_7:
756 			stv0900_write_reg(intp, PRVIT, 0x10);
757 			break;
758 		}
759 		break;
760 	default:
761 		break;
762 	}
763 }
764 
765 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
766 						enum fe_stv0900_demod_num demod)
767 {
768 	enum fe_stv0900_fec prate;
769 	s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
770 
771 	switch (rate_fld) {
772 	case 13:
773 		prate = STV0900_FEC_1_2;
774 		break;
775 	case 18:
776 		prate = STV0900_FEC_2_3;
777 		break;
778 	case 21:
779 		prate = STV0900_FEC_3_4;
780 		break;
781 	case 24:
782 		prate = STV0900_FEC_5_6;
783 		break;
784 	case 25:
785 		prate = STV0900_FEC_6_7;
786 		break;
787 	case 26:
788 		prate = STV0900_FEC_7_8;
789 		break;
790 	default:
791 		prate = STV0900_FEC_UNKNOWN;
792 		break;
793 	}
794 
795 	return prate;
796 }
797 
798 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
799 					enum fe_stv0900_demod_num demod,
800 					u32 srate)
801 {
802 	if (intp->chip_id >= 0x30) {
803 		if (srate >= 15000000) {
804 			stv0900_write_reg(intp, ACLC, 0x2b);
805 			stv0900_write_reg(intp, BCLC, 0x1a);
806 		} else if ((srate >= 7000000) && (15000000 > srate)) {
807 			stv0900_write_reg(intp, ACLC, 0x0c);
808 			stv0900_write_reg(intp, BCLC, 0x1b);
809 		} else if (srate < 7000000) {
810 			stv0900_write_reg(intp, ACLC, 0x2c);
811 			stv0900_write_reg(intp, BCLC, 0x1c);
812 		}
813 
814 	} else { /*cut 2.0 and 1.x*/
815 		stv0900_write_reg(intp, ACLC, 0x1a);
816 		stv0900_write_reg(intp, BCLC, 0x09);
817 	}
818 
819 }
820 
821 static void stv0900_track_optimization(struct dvb_frontend *fe)
822 {
823 	struct stv0900_state *state = fe->demodulator_priv;
824 	struct stv0900_internal *intp = state->internal;
825 	enum fe_stv0900_demod_num demod = state->demod;
826 
827 	s32	srate,
828 		pilots,
829 		aclc,
830 		freq1,
831 		freq0,
832 		i = 0,
833 		timed,
834 		timef,
835 		blind_tun_sw = 0,
836 		modulation;
837 
838 	enum fe_stv0900_modcode foundModcod;
839 
840 	dprintk("%s\n", __func__);
841 
842 	srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
843 	srate += stv0900_get_timing_offst(intp, srate, demod);
844 
845 	switch (intp->result[demod].standard) {
846 	case STV0900_DVBS1_STANDARD:
847 	case STV0900_DSS_STANDARD:
848 		dprintk("%s: found DVB-S or DSS\n", __func__);
849 		if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
850 			stv0900_write_bits(intp, DVBS1_ENABLE, 1);
851 			stv0900_write_bits(intp, DVBS2_ENABLE, 0);
852 		}
853 
854 		stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
855 		stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
856 
857 		if (intp->chip_id < 0x30) {
858 			stv0900_write_reg(intp, ERRCTRL1, 0x75);
859 			break;
860 		}
861 
862 		if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
863 			stv0900_write_reg(intp, GAUSSR0, 0x98);
864 			stv0900_write_reg(intp, CCIR0, 0x18);
865 		} else {
866 			stv0900_write_reg(intp, GAUSSR0, 0x18);
867 			stv0900_write_reg(intp, CCIR0, 0x18);
868 		}
869 
870 		stv0900_write_reg(intp, ERRCTRL1, 0x75);
871 		break;
872 	case STV0900_DVBS2_STANDARD:
873 		dprintk("%s: found DVB-S2\n", __func__);
874 		stv0900_write_bits(intp, DVBS1_ENABLE, 0);
875 		stv0900_write_bits(intp, DVBS2_ENABLE, 1);
876 		stv0900_write_reg(intp, ACLC, 0);
877 		stv0900_write_reg(intp, BCLC, 0);
878 		if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
879 			foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
880 			pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
881 			aclc = stv0900_get_optim_carr_loop(srate,
882 							foundModcod,
883 							pilots,
884 							intp->chip_id);
885 			if (foundModcod <= STV0900_QPSK_910)
886 				stv0900_write_reg(intp, ACLC2S2Q, aclc);
887 			else if (foundModcod <= STV0900_8PSK_910) {
888 				stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
889 				stv0900_write_reg(intp, ACLC2S28, aclc);
890 			}
891 
892 			if ((intp->demod_mode == STV0900_SINGLE) &&
893 					(foundModcod > STV0900_8PSK_910)) {
894 				if (foundModcod <= STV0900_16APSK_910) {
895 					stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
896 					stv0900_write_reg(intp, ACLC2S216A,
897 									aclc);
898 				} else if (foundModcod <= STV0900_32APSK_910) {
899 					stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
900 					stv0900_write_reg(intp,	ACLC2S232A,
901 									aclc);
902 				}
903 			}
904 
905 		} else {
906 			modulation = intp->result[demod].modulation;
907 			aclc = stv0900_get_optim_short_carr_loop(srate,
908 					modulation, intp->chip_id);
909 			if (modulation == STV0900_QPSK)
910 				stv0900_write_reg(intp, ACLC2S2Q, aclc);
911 			else if (modulation == STV0900_8PSK) {
912 				stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
913 				stv0900_write_reg(intp, ACLC2S28, aclc);
914 			} else if (modulation == STV0900_16APSK) {
915 				stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
916 				stv0900_write_reg(intp, ACLC2S216A, aclc);
917 			} else if (modulation == STV0900_32APSK) {
918 				stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
919 				stv0900_write_reg(intp, ACLC2S232A, aclc);
920 			}
921 
922 		}
923 
924 		if (intp->chip_id <= 0x11) {
925 			if (intp->demod_mode != STV0900_SINGLE)
926 				stv0900_activate_s2_modcod(intp, demod);
927 
928 		}
929 
930 		stv0900_write_reg(intp, ERRCTRL1, 0x67);
931 		break;
932 	case STV0900_UNKNOWN_STANDARD:
933 	default:
934 		dprintk("%s: found unknown standard\n", __func__);
935 		stv0900_write_bits(intp, DVBS1_ENABLE, 1);
936 		stv0900_write_bits(intp, DVBS2_ENABLE, 1);
937 		break;
938 	}
939 
940 	freq1 = stv0900_read_reg(intp, CFR2);
941 	freq0 = stv0900_read_reg(intp, CFR1);
942 	if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
943 		stv0900_write_reg(intp, SFRSTEP, 0x00);
944 		stv0900_write_bits(intp, SCAN_ENABLE, 0);
945 		stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
946 		stv0900_write_reg(intp, TMGCFG2, 0xc1);
947 		stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
948 		blind_tun_sw = 1;
949 		if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
950 			stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
951 
952 	}
953 
954 	if (intp->chip_id >= 0x20) {
955 		if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
956 				(intp->srch_standard[demod] ==
957 							STV0900_SEARCH_DSS) ||
958 				(intp->srch_standard[demod] ==
959 							STV0900_AUTO_SEARCH)) {
960 			stv0900_write_reg(intp, VAVSRVIT, 0x0a);
961 			stv0900_write_reg(intp, VITSCALE, 0x0);
962 		}
963 	}
964 
965 	if (intp->chip_id < 0x20)
966 		stv0900_write_reg(intp, CARHDR, 0x08);
967 
968 	if (intp->chip_id == 0x10)
969 		stv0900_write_reg(intp, CORRELEXP, 0x0a);
970 
971 	stv0900_write_reg(intp, AGC2REF, 0x38);
972 
973 	if ((intp->chip_id >= 0x20) ||
974 			(blind_tun_sw == 1) ||
975 			(intp->symbol_rate[demod] < 10000000)) {
976 		stv0900_write_reg(intp, CFRINIT1, freq1);
977 		stv0900_write_reg(intp, CFRINIT0, freq0);
978 		intp->bw[demod] = stv0900_carrier_width(srate,
979 					intp->rolloff) + 10000000;
980 
981 		if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
982 			if (intp->srch_algo[demod] != STV0900_WARM_START) {
983 				if (intp->tuner_type[demod] == 3)
984 					stv0900_set_tuner_auto(intp,
985 							intp->freq[demod],
986 							intp->bw[demod],
987 							demod);
988 				else
989 					stv0900_set_bandwidth(fe,
990 							intp->bw[demod]);
991 			}
992 		}
993 
994 		if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
995 				(intp->symbol_rate[demod] < 10000000))
996 			msleep(50);
997 		else
998 			msleep(5);
999 
1000 		stv0900_get_lock_timeout(&timed, &timef, srate,
1001 						STV0900_WARM_START);
1002 
1003 		if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
1004 			stv0900_write_reg(intp, DMDISTATE, 0x1f);
1005 			stv0900_write_reg(intp, CFRINIT1, freq1);
1006 			stv0900_write_reg(intp, CFRINIT0, freq0);
1007 			stv0900_write_reg(intp, DMDISTATE, 0x18);
1008 			i = 0;
1009 			while ((stv0900_get_demod_lock(intp,
1010 							demod,
1011 							timed / 2) == FALSE) &&
1012 						(i <= 2)) {
1013 				stv0900_write_reg(intp, DMDISTATE, 0x1f);
1014 				stv0900_write_reg(intp, CFRINIT1, freq1);
1015 				stv0900_write_reg(intp, CFRINIT0, freq0);
1016 				stv0900_write_reg(intp, DMDISTATE, 0x18);
1017 				i++;
1018 			}
1019 		}
1020 
1021 	}
1022 
1023 	if (intp->chip_id >= 0x20)
1024 		stv0900_write_reg(intp, CARFREQ, 0x49);
1025 
1026 	if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1027 			(intp->result[demod].standard == STV0900_DSS_STANDARD))
1028 		stv0900_set_viterbi_tracq(intp, demod);
1029 
1030 }
1031 
1032 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1033 				enum fe_stv0900_demod_num demod, s32 time_out)
1034 {
1035 	s32 timer = 0, lock = 0;
1036 
1037 	enum fe_stv0900_search_state dmd_state;
1038 
1039 	dprintk("%s\n", __func__);
1040 
1041 	dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1042 
1043 	while ((timer < time_out) && (lock == 0)) {
1044 		switch (dmd_state) {
1045 		case STV0900_SEARCH:
1046 		case STV0900_PLH_DETECTED:
1047 		default:
1048 			lock = 0;
1049 			break;
1050 		case STV0900_DVBS2_FOUND:
1051 			lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1052 			break;
1053 		case STV0900_DVBS_FOUND:
1054 			lock = stv0900_get_bits(intp, LOCKEDVIT);
1055 			break;
1056 		}
1057 
1058 		if (lock == 0) {
1059 			msleep(10);
1060 			timer += 10;
1061 		}
1062 	}
1063 
1064 	if (lock)
1065 		dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1066 	else
1067 		dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1068 
1069 	return lock;
1070 }
1071 
1072 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1073 				enum fe_stv0900_demod_num demod,
1074 				s32 dmd_timeout, s32 fec_timeout)
1075 {
1076 
1077 	s32 timer = 0, lock = 0;
1078 
1079 	dprintk("%s\n", __func__);
1080 
1081 	lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1082 
1083 	if (lock)
1084 		lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
1085 
1086 	if (lock) {
1087 		lock = 0;
1088 
1089 		dprintk("%s: Timer = %d, time_out = %d\n",
1090 				__func__, timer, fec_timeout);
1091 
1092 		while ((timer < fec_timeout) && (lock == 0)) {
1093 			lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1094 			msleep(1);
1095 			timer++;
1096 		}
1097 	}
1098 
1099 	if (lock)
1100 		dprintk("%s: DEMOD LOCK OK\n", __func__);
1101 	else
1102 		dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1103 
1104 	if (lock)
1105 		return TRUE;
1106 	else
1107 		return FALSE;
1108 }
1109 
1110 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1111 						enum fe_stv0900_demod_num demod)
1112 {
1113 	struct stv0900_state *state = fe->demodulator_priv;
1114 	struct stv0900_internal *intp = state->internal;
1115 	enum fe_stv0900_tracking_standard fnd_standard;
1116 
1117 	int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1118 
1119 	switch (hdr_mode) {
1120 	case 2:
1121 		fnd_standard = STV0900_DVBS2_STANDARD;
1122 		break;
1123 	case 3:
1124 		if (stv0900_get_bits(intp, DSS_DVB) == 1)
1125 			fnd_standard = STV0900_DSS_STANDARD;
1126 		else
1127 			fnd_standard = STV0900_DVBS1_STANDARD;
1128 
1129 		break;
1130 	default:
1131 		fnd_standard = STV0900_UNKNOWN_STANDARD;
1132 	}
1133 
1134 	dprintk("%s: standard %d\n", __func__, fnd_standard);
1135 
1136 	return fnd_standard;
1137 }
1138 
1139 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1140 					enum fe_stv0900_demod_num demod)
1141 {
1142 	s32	derot,
1143 		rem1,
1144 		rem2,
1145 		intval1,
1146 		intval2;
1147 
1148 	derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1149 		(stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1150 		(stv0900_get_bits(intp, CAR_FREQ0));
1151 
1152 	derot = ge2comp(derot, 24);
1153 	intval1 = mclk >> 12;
1154 	intval2 = derot >> 12;
1155 	rem1 = mclk % 0x1000;
1156 	rem2 = derot % 0x1000;
1157 	derot = (intval1 * intval2) +
1158 		((intval1 * rem2) >> 12) +
1159 		((intval2 * rem1) >> 12);
1160 
1161 	return derot;
1162 }
1163 
1164 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1165 {
1166 	struct dvb_frontend_ops	*frontend_ops = NULL;
1167 	struct dvb_tuner_ops *tuner_ops = NULL;
1168 	u32 freq = 0;
1169 
1170 	frontend_ops = &fe->ops;
1171 	tuner_ops = &frontend_ops->tuner_ops;
1172 
1173 	if (tuner_ops->get_frequency) {
1174 		if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1175 			dprintk("%s: Invalid parameter\n", __func__);
1176 		else
1177 			dprintk("%s: Frequency=%d\n", __func__, freq);
1178 
1179 	}
1180 
1181 	return freq;
1182 }
1183 
1184 static enum
1185 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1186 {
1187 	struct stv0900_state *state = fe->demodulator_priv;
1188 	struct stv0900_internal *intp = state->internal;
1189 	enum fe_stv0900_demod_num demod = state->demod;
1190 	enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1191 	struct stv0900_signal_info *result = &intp->result[demod];
1192 	s32	offsetFreq,
1193 		srate_offset;
1194 	int	i = 0,
1195 		d = demod;
1196 
1197 	u8 timing;
1198 
1199 	msleep(5);
1200 	if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1201 		timing = stv0900_read_reg(intp, TMGREG2);
1202 		i = 0;
1203 		stv0900_write_reg(intp, SFRSTEP, 0x5c);
1204 
1205 		while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1206 			timing = stv0900_read_reg(intp, TMGREG2);
1207 			msleep(5);
1208 			i += 5;
1209 		}
1210 	}
1211 
1212 	result->standard = stv0900_get_standard(fe, d);
1213 	if (intp->tuner_type[demod] == 3)
1214 		result->frequency = stv0900_get_freq_auto(intp, d);
1215 	else
1216 		result->frequency = stv0900_get_tuner_freq(fe);
1217 
1218 	offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1219 	result->frequency += offsetFreq;
1220 	result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1221 	srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1222 	result->symbol_rate += srate_offset;
1223 	result->fec = stv0900_get_vit_fec(intp, d);
1224 	result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1225 	result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1226 	result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1227 	result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1228 
1229 	dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
1230 
1231 	switch (result->standard) {
1232 	case STV0900_DVBS2_STANDARD:
1233 		result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1234 		if (result->modcode <= STV0900_QPSK_910)
1235 			result->modulation = STV0900_QPSK;
1236 		else if (result->modcode <= STV0900_8PSK_910)
1237 			result->modulation = STV0900_8PSK;
1238 		else if (result->modcode <= STV0900_16APSK_910)
1239 			result->modulation = STV0900_16APSK;
1240 		else if (result->modcode <= STV0900_32APSK_910)
1241 			result->modulation = STV0900_32APSK;
1242 		else
1243 			result->modulation = STV0900_UNKNOWN;
1244 		break;
1245 	case STV0900_DVBS1_STANDARD:
1246 	case STV0900_DSS_STANDARD:
1247 		result->spectrum = stv0900_get_bits(intp, IQINV);
1248 		result->modulation = STV0900_QPSK;
1249 		break;
1250 	default:
1251 		break;
1252 	}
1253 
1254 	if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1255 				(intp->symbol_rate[d] < 10000000)) {
1256 		offsetFreq = result->frequency - intp->freq[d];
1257 		if (intp->tuner_type[demod] == 3)
1258 			intp->freq[d] = stv0900_get_freq_auto(intp, d);
1259 		else
1260 			intp->freq[d] = stv0900_get_tuner_freq(fe);
1261 
1262 		if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1263 			range = STV0900_RANGEOK;
1264 		else if (ABS(offsetFreq) <=
1265 				(stv0900_carrier_width(result->symbol_rate,
1266 						result->rolloff) / 2000))
1267 			range = STV0900_RANGEOK;
1268 
1269 	} else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1270 		range = STV0900_RANGEOK;
1271 
1272 	dprintk("%s: range %d\n", __func__, range);
1273 
1274 	return range;
1275 }
1276 
1277 static enum
1278 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1279 {
1280 	struct stv0900_state *state = fe->demodulator_priv;
1281 	struct stv0900_internal *intp = state->internal;
1282 	enum fe_stv0900_demod_num demod = state->demod;
1283 	enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1284 
1285 	s32	srate,
1286 		demod_timeout,
1287 		fec_timeout,
1288 		freq1,
1289 		freq0;
1290 
1291 	intp->result[demod].locked = FALSE;
1292 
1293 	if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1294 		srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1295 		srate += stv0900_get_timing_offst(intp, srate, demod);
1296 		if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1297 			stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1298 
1299 		stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1300 					srate, STV0900_WARM_START);
1301 		freq1 = stv0900_read_reg(intp, CFR2);
1302 		freq0 = stv0900_read_reg(intp, CFR1);
1303 		stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1304 		stv0900_write_bits(intp, SPECINV_CONTROL,
1305 					STV0900_IQ_FORCE_SWAPPED);
1306 		stv0900_write_reg(intp, DMDISTATE, 0x1c);
1307 		stv0900_write_reg(intp, CFRINIT1, freq1);
1308 		stv0900_write_reg(intp, CFRINIT0, freq0);
1309 		stv0900_write_reg(intp, DMDISTATE, 0x18);
1310 		if (stv0900_wait_for_lock(intp, demod,
1311 				demod_timeout, fec_timeout) == TRUE) {
1312 			intp->result[demod].locked = TRUE;
1313 			signal_type = stv0900_get_signal_params(fe);
1314 			stv0900_track_optimization(fe);
1315 		} else {
1316 			stv0900_write_bits(intp, SPECINV_CONTROL,
1317 					STV0900_IQ_FORCE_NORMAL);
1318 			stv0900_write_reg(intp, DMDISTATE, 0x1c);
1319 			stv0900_write_reg(intp, CFRINIT1, freq1);
1320 			stv0900_write_reg(intp, CFRINIT0, freq0);
1321 			stv0900_write_reg(intp, DMDISTATE, 0x18);
1322 			if (stv0900_wait_for_lock(intp, demod,
1323 					demod_timeout, fec_timeout) == TRUE) {
1324 				intp->result[demod].locked = TRUE;
1325 				signal_type = stv0900_get_signal_params(fe);
1326 				stv0900_track_optimization(fe);
1327 			}
1328 
1329 		}
1330 
1331 	} else
1332 		intp->result[demod].locked = FALSE;
1333 
1334 	return signal_type;
1335 }
1336 
1337 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1338 					enum fe_stv0900_demod_num demod)
1339 {
1340 	u32 minagc2level = 0xffff,
1341 		agc2level,
1342 		init_freq, freq_step;
1343 
1344 	s32 i, j, nb_steps, direction;
1345 
1346 	dprintk("%s\n", __func__);
1347 
1348 	stv0900_write_reg(intp, AGC2REF, 0x38);
1349 	stv0900_write_bits(intp, SCAN_ENABLE, 0);
1350 	stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1351 
1352 	stv0900_write_bits(intp, AUTO_GUP, 1);
1353 	stv0900_write_bits(intp, AUTO_GLOW, 1);
1354 
1355 	stv0900_write_reg(intp, DMDT0M, 0x0);
1356 
1357 	stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1358 	nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1359 	nb_steps /= 2;
1360 	nb_steps = (2 * nb_steps) + 1;
1361 
1362 	if (nb_steps < 0)
1363 		nb_steps = 1;
1364 
1365 	direction = 1;
1366 
1367 	freq_step = (1000000 << 8) / (intp->mclk >> 8);
1368 
1369 	init_freq = 0;
1370 
1371 	for (i = 0; i < nb_steps; i++) {
1372 		if (direction > 0)
1373 			init_freq = init_freq + (freq_step * i);
1374 		else
1375 			init_freq = init_freq - (freq_step * i);
1376 
1377 		direction *= -1;
1378 		stv0900_write_reg(intp, DMDISTATE, 0x5C);
1379 		stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1380 		stv0900_write_reg(intp, CFRINIT0, init_freq  & 0xff);
1381 		stv0900_write_reg(intp, DMDISTATE, 0x58);
1382 		msleep(10);
1383 		agc2level = 0;
1384 
1385 		for (j = 0; j < 10; j++)
1386 			agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1387 					| stv0900_read_reg(intp, AGC2I0);
1388 
1389 		agc2level /= 10;
1390 
1391 		if (agc2level < minagc2level)
1392 			minagc2level = agc2level;
1393 
1394 	}
1395 
1396 	return (u16)minagc2level;
1397 }
1398 
1399 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1400 {
1401 	struct stv0900_state *state = fe->demodulator_priv;
1402 	struct stv0900_internal *intp = state->internal;
1403 	enum fe_stv0900_demod_num demod = state->demod;
1404 	int timing_lck = FALSE;
1405 	s32 i, timingcpt = 0,
1406 		direction = 1,
1407 		nb_steps,
1408 		current_step = 0,
1409 		tuner_freq;
1410 	u32 agc2_th,
1411 		coarse_srate = 0,
1412 		agc2_integr = 0,
1413 		currier_step = 1200;
1414 
1415 	if (intp->chip_id >= 0x30)
1416 		agc2_th = 0x2e00;
1417 	else
1418 		agc2_th = 0x1f00;
1419 
1420 	stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1421 	stv0900_write_reg(intp, TMGCFG, 0x12);
1422 	stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1423 	stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1424 	stv0900_write_bits(intp, SCAN_ENABLE, 1);
1425 	stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1426 	stv0900_write_reg(intp, SFRUP1, 0x83);
1427 	stv0900_write_reg(intp, SFRUP0, 0xc0);
1428 	stv0900_write_reg(intp, SFRLOW1, 0x82);
1429 	stv0900_write_reg(intp, SFRLOW0, 0xa0);
1430 	stv0900_write_reg(intp, DMDT0M, 0x0);
1431 	stv0900_write_reg(intp, AGC2REF, 0x50);
1432 
1433 	if (intp->chip_id >= 0x30) {
1434 		stv0900_write_reg(intp, CARFREQ, 0x99);
1435 		stv0900_write_reg(intp, SFRSTEP, 0x98);
1436 	} else if (intp->chip_id >= 0x20) {
1437 		stv0900_write_reg(intp, CARFREQ, 0x6a);
1438 		stv0900_write_reg(intp, SFRSTEP, 0x95);
1439 	} else {
1440 		stv0900_write_reg(intp, CARFREQ, 0xed);
1441 		stv0900_write_reg(intp, SFRSTEP, 0x73);
1442 	}
1443 
1444 	if (intp->symbol_rate[demod] <= 2000000)
1445 		currier_step = 1000;
1446 	else if (intp->symbol_rate[demod] <= 5000000)
1447 		currier_step = 2000;
1448 	else if (intp->symbol_rate[demod] <= 12000000)
1449 		currier_step = 3000;
1450 	else
1451 			currier_step = 5000;
1452 
1453 	nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1454 	nb_steps /= 2;
1455 	nb_steps = (2 * nb_steps) + 1;
1456 
1457 	if (nb_steps < 0)
1458 		nb_steps = 1;
1459 	else if (nb_steps > 10) {
1460 		nb_steps = 11;
1461 		currier_step = (intp->srch_range[demod] / 1000) / 10;
1462 	}
1463 
1464 	current_step = 0;
1465 	direction = 1;
1466 
1467 	tuner_freq = intp->freq[demod];
1468 
1469 	while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1470 		stv0900_write_reg(intp, DMDISTATE, 0x5f);
1471 		stv0900_write_bits(intp, DEMOD_MODE, 0);
1472 
1473 		msleep(50);
1474 
1475 		for (i = 0; i < 10; i++) {
1476 			if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1477 				timingcpt++;
1478 
1479 			agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1480 					stv0900_read_reg(intp, AGC2I0);
1481 		}
1482 
1483 		agc2_integr /= 10;
1484 		coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1485 		current_step++;
1486 		direction *= -1;
1487 
1488 		dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
1489 			" tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1490 			tuner_freq, agc2_integr, coarse_srate, timingcpt);
1491 
1492 		if ((timingcpt >= 5) &&
1493 				(agc2_integr < agc2_th) &&
1494 				(coarse_srate < 55000000) &&
1495 				(coarse_srate > 850000))
1496 			timing_lck = TRUE;
1497 		else if (current_step < nb_steps) {
1498 			if (direction > 0)
1499 				tuner_freq += (current_step * currier_step);
1500 			else
1501 				tuner_freq -= (current_step * currier_step);
1502 
1503 			if (intp->tuner_type[demod] == 3)
1504 				stv0900_set_tuner_auto(intp, tuner_freq,
1505 						intp->bw[demod], demod);
1506 			else
1507 				stv0900_set_tuner(fe, tuner_freq,
1508 						intp->bw[demod]);
1509 		}
1510 	}
1511 
1512 	if (timing_lck == FALSE)
1513 		coarse_srate = 0;
1514 	else
1515 		coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1516 
1517 	return coarse_srate;
1518 }
1519 
1520 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1521 {
1522 	struct stv0900_state *state = fe->demodulator_priv;
1523 	struct stv0900_internal *intp = state->internal;
1524 	enum fe_stv0900_demod_num demod = state->demod;
1525 	u32	coarse_srate,
1526 		coarse_freq,
1527 		symb,
1528 		symbmax,
1529 		symbmin,
1530 		symbcomp;
1531 
1532 	coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1533 
1534 	if (coarse_srate > 3000000) {
1535 		symbmax = 13 * (coarse_srate / 10);
1536 		symbmax = (symbmax / 1000) * 65536;
1537 		symbmax /= (intp->mclk / 1000);
1538 
1539 		symbmin = 10 * (coarse_srate / 13);
1540 		symbmin = (symbmin / 1000)*65536;
1541 		symbmin /= (intp->mclk / 1000);
1542 
1543 		symb = (coarse_srate / 1000) * 65536;
1544 		symb /= (intp->mclk / 1000);
1545 	} else {
1546 		symbmax = 13 * (coarse_srate / 10);
1547 		symbmax = (symbmax / 100) * 65536;
1548 		symbmax /= (intp->mclk / 100);
1549 
1550 		symbmin = 10 * (coarse_srate / 14);
1551 		symbmin = (symbmin / 100) * 65536;
1552 		symbmin /= (intp->mclk / 100);
1553 
1554 		symb = (coarse_srate / 100) * 65536;
1555 		symb /= (intp->mclk / 100);
1556 	}
1557 
1558 	symbcomp = 13 * (coarse_srate / 10);
1559 		coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1560 					| stv0900_read_reg(intp, CFR1);
1561 
1562 	if (symbcomp < intp->symbol_rate[demod])
1563 		coarse_srate = 0;
1564 	else {
1565 		stv0900_write_reg(intp, DMDISTATE, 0x1f);
1566 		stv0900_write_reg(intp, TMGCFG2, 0xc1);
1567 		stv0900_write_reg(intp, TMGTHRISE, 0x20);
1568 		stv0900_write_reg(intp, TMGTHFALL, 0x00);
1569 		stv0900_write_reg(intp, TMGCFG, 0xd2);
1570 		stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1571 		stv0900_write_reg(intp, AGC2REF, 0x38);
1572 
1573 		if (intp->chip_id >= 0x30)
1574 			stv0900_write_reg(intp, CARFREQ, 0x79);
1575 		else if (intp->chip_id >= 0x20)
1576 			stv0900_write_reg(intp, CARFREQ, 0x49);
1577 		else
1578 			stv0900_write_reg(intp, CARFREQ, 0xed);
1579 
1580 		stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1581 		stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1582 
1583 		stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1584 		stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1585 
1586 		stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1587 		stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1588 
1589 		stv0900_write_reg(intp, DMDT0M, 0x20);
1590 		stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1591 		stv0900_write_reg(intp, CFRINIT0, coarse_freq  & 0xff);
1592 		stv0900_write_reg(intp, DMDISTATE, 0x15);
1593 	}
1594 
1595 	return coarse_srate;
1596 }
1597 
1598 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1599 {
1600 	struct stv0900_state *state = fe->demodulator_priv;
1601 	struct stv0900_internal *intp = state->internal;
1602 	enum fe_stv0900_demod_num demod = state->demod;
1603 	u8	k_ref_tmg,
1604 		k_ref_tmg_max,
1605 		k_ref_tmg_min;
1606 	u32	coarse_srate,
1607 		agc2_th;
1608 	int	lock = FALSE,
1609 		coarse_fail = FALSE;
1610 	s32	demod_timeout = 500,
1611 		fec_timeout = 50,
1612 		fail_cpt,
1613 		i,
1614 		agc2_overflow;
1615 	u16	agc2_int;
1616 	u8	dstatus2;
1617 
1618 	dprintk("%s\n", __func__);
1619 
1620 	if (intp->chip_id < 0x20) {
1621 		k_ref_tmg_max = 233;
1622 		k_ref_tmg_min = 143;
1623 	} else {
1624 		k_ref_tmg_max = 110;
1625 		k_ref_tmg_min = 10;
1626 	}
1627 
1628 	if (intp->chip_id <= 0x20)
1629 		agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1630 	else
1631 		agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1632 
1633 	agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1634 
1635 	dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
1636 	if (agc2_int > agc2_th)
1637 		return FALSE;
1638 
1639 	if (intp->chip_id == 0x10)
1640 		stv0900_write_reg(intp, CORRELEXP, 0xaa);
1641 
1642 	if (intp->chip_id < 0x20)
1643 		stv0900_write_reg(intp, CARHDR, 0x55);
1644 	else
1645 		stv0900_write_reg(intp, CARHDR, 0x20);
1646 
1647 	if (intp->chip_id <= 0x20)
1648 		stv0900_write_reg(intp, CARCFG, 0xc4);
1649 	else
1650 		stv0900_write_reg(intp, CARCFG, 0x6);
1651 
1652 	stv0900_write_reg(intp, RTCS2, 0x44);
1653 
1654 	if (intp->chip_id >= 0x20) {
1655 		stv0900_write_reg(intp, EQUALCFG, 0x41);
1656 		stv0900_write_reg(intp, FFECFG, 0x41);
1657 		stv0900_write_reg(intp, VITSCALE, 0x82);
1658 		stv0900_write_reg(intp, VAVSRVIT, 0x0);
1659 	}
1660 
1661 	k_ref_tmg = k_ref_tmg_max;
1662 
1663 	do {
1664 		stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1665 		if (stv0900_search_srate_coarse(fe) != 0) {
1666 			coarse_srate = stv0900_search_srate_fine(fe);
1667 
1668 			if (coarse_srate != 0) {
1669 				stv0900_get_lock_timeout(&demod_timeout,
1670 							&fec_timeout,
1671 							coarse_srate,
1672 							STV0900_BLIND_SEARCH);
1673 				lock = stv0900_get_demod_lock(intp,
1674 							demod,
1675 							demod_timeout);
1676 			} else
1677 				lock = FALSE;
1678 		} else {
1679 			fail_cpt = 0;
1680 			agc2_overflow = 0;
1681 
1682 			for (i = 0; i < 10; i++) {
1683 				agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1684 					| stv0900_read_reg(intp, AGC2I0);
1685 
1686 				if (agc2_int >= 0xff00)
1687 					agc2_overflow++;
1688 
1689 				dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1690 
1691 				if (((dstatus2 & 0x1) == 0x1) &&
1692 						((dstatus2 >> 7) == 1))
1693 					fail_cpt++;
1694 			}
1695 
1696 			if ((fail_cpt > 7) || (agc2_overflow > 7))
1697 				coarse_fail = TRUE;
1698 
1699 			lock = FALSE;
1700 		}
1701 		k_ref_tmg -= 30;
1702 	} while ((k_ref_tmg >= k_ref_tmg_min) &&
1703 				(lock == FALSE) &&
1704 				(coarse_fail == FALSE));
1705 
1706 	return lock;
1707 }
1708 
1709 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1710 					enum fe_stv0900_demod_num demod)
1711 {
1712 	s32 vth_reg = VTH12;
1713 
1714 	dprintk("%s\n", __func__);
1715 
1716 	stv0900_write_reg(intp, vth_reg++, 0x96);
1717 	stv0900_write_reg(intp, vth_reg++, 0x64);
1718 	stv0900_write_reg(intp, vth_reg++, 0x36);
1719 	stv0900_write_reg(intp, vth_reg++, 0x23);
1720 	stv0900_write_reg(intp, vth_reg++, 0x1e);
1721 	stv0900_write_reg(intp, vth_reg++, 0x19);
1722 }
1723 
1724 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1725 					enum fe_stv0900_demod_num demod)
1726 {
1727 
1728 	dprintk("%s\n", __func__);
1729 
1730 	switch (intp->srch_standard[demod]) {
1731 	case STV0900_SEARCH_DVBS1:
1732 		dprintk("Search Standard = DVBS1\n");
1733 		break;
1734 	case STV0900_SEARCH_DSS:
1735 		dprintk("Search Standard = DSS\n");
1736 		break;
1737 	case STV0900_SEARCH_DVBS2:
1738 		dprintk("Search Standard = DVBS2\n");
1739 		break;
1740 	case STV0900_AUTO_SEARCH:
1741 	default:
1742 		dprintk("Search Standard = AUTO\n");
1743 		break;
1744 	}
1745 
1746 	switch (intp->srch_standard[demod]) {
1747 	case STV0900_SEARCH_DVBS1:
1748 	case STV0900_SEARCH_DSS:
1749 		stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1750 		stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1751 		stv0900_write_bits(intp, STOP_CLKVIT, 0);
1752 		stv0900_set_dvbs1_track_car_loop(intp,
1753 						demod,
1754 						intp->symbol_rate[demod]);
1755 		stv0900_write_reg(intp, CAR2CFG, 0x22);
1756 
1757 		stv0900_set_viterbi_acq(intp, demod);
1758 		stv0900_set_viterbi_standard(intp,
1759 					intp->srch_standard[demod],
1760 					intp->fec[demod], demod);
1761 
1762 		break;
1763 	case STV0900_SEARCH_DVBS2:
1764 		stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1765 		stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1766 		stv0900_write_bits(intp, STOP_CLKVIT, 1);
1767 		stv0900_write_reg(intp, ACLC, 0x1a);
1768 		stv0900_write_reg(intp, BCLC, 0x09);
1769 		if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1770 			stv0900_write_reg(intp, CAR2CFG, 0x26);
1771 		else
1772 			stv0900_write_reg(intp, CAR2CFG, 0x66);
1773 
1774 		if (intp->demod_mode != STV0900_SINGLE) {
1775 			if (intp->chip_id <= 0x11)
1776 				stv0900_stop_all_s2_modcod(intp, demod);
1777 			else
1778 				stv0900_activate_s2_modcod(intp, demod);
1779 
1780 		} else
1781 			stv0900_activate_s2_modcod_single(intp, demod);
1782 
1783 		stv0900_set_viterbi_tracq(intp, demod);
1784 
1785 		break;
1786 	case STV0900_AUTO_SEARCH:
1787 	default:
1788 		stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1789 		stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1790 		stv0900_write_bits(intp, STOP_CLKVIT, 0);
1791 		stv0900_write_reg(intp, ACLC, 0x1a);
1792 		stv0900_write_reg(intp, BCLC, 0x09);
1793 		stv0900_set_dvbs1_track_car_loop(intp,
1794 						demod,
1795 						intp->symbol_rate[demod]);
1796 		if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1797 			stv0900_write_reg(intp, CAR2CFG, 0x26);
1798 		else
1799 			stv0900_write_reg(intp, CAR2CFG, 0x66);
1800 
1801 		if (intp->demod_mode != STV0900_SINGLE) {
1802 			if (intp->chip_id <= 0x11)
1803 				stv0900_stop_all_s2_modcod(intp, demod);
1804 			else
1805 				stv0900_activate_s2_modcod(intp, demod);
1806 
1807 		} else
1808 			stv0900_activate_s2_modcod_single(intp, demod);
1809 
1810 		stv0900_set_viterbi_tracq(intp, demod);
1811 		stv0900_set_viterbi_standard(intp,
1812 						intp->srch_standard[demod],
1813 						intp->fec[demod], demod);
1814 
1815 		break;
1816 	}
1817 }
1818 
1819 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1820 {
1821 	struct stv0900_state *state = fe->demodulator_priv;
1822 	struct stv0900_internal *intp = state->internal;
1823 	enum fe_stv0900_demod_num demod = state->demod;
1824 
1825 	s32 demod_timeout = 500, fec_timeout = 50;
1826 	s32 aq_power, agc1_power, i;
1827 
1828 	int lock = FALSE, low_sr = FALSE;
1829 
1830 	enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1831 	enum fe_stv0900_search_algo algo;
1832 	int no_signal = FALSE;
1833 
1834 	dprintk("%s\n", __func__);
1835 
1836 	algo = intp->srch_algo[demod];
1837 	stv0900_write_bits(intp, RST_HWARE, 1);
1838 	stv0900_write_reg(intp, DMDISTATE, 0x5c);
1839 	if (intp->chip_id >= 0x20) {
1840 		if (intp->symbol_rate[demod] > 5000000)
1841 			stv0900_write_reg(intp, CORRELABS, 0x9e);
1842 		else
1843 			stv0900_write_reg(intp, CORRELABS, 0x82);
1844 	} else
1845 		stv0900_write_reg(intp, CORRELABS, 0x88);
1846 
1847 	stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1848 				intp->symbol_rate[demod],
1849 				intp->srch_algo[demod]);
1850 
1851 	if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1852 		intp->bw[demod] = 2 * 36000000;
1853 
1854 		stv0900_write_reg(intp, TMGCFG2, 0xc0);
1855 		stv0900_write_reg(intp, CORRELMANT, 0x70);
1856 
1857 		stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1858 	} else {
1859 		stv0900_write_reg(intp, DMDT0M, 0x20);
1860 		stv0900_write_reg(intp, TMGCFG, 0xd2);
1861 
1862 		if (intp->symbol_rate[demod] < 2000000)
1863 			stv0900_write_reg(intp, CORRELMANT, 0x63);
1864 		else
1865 			stv0900_write_reg(intp, CORRELMANT, 0x70);
1866 
1867 		stv0900_write_reg(intp, AGC2REF, 0x38);
1868 
1869 		intp->bw[demod] =
1870 				stv0900_carrier_width(intp->symbol_rate[demod],
1871 								intp->rolloff);
1872 		if (intp->chip_id >= 0x20) {
1873 			stv0900_write_reg(intp, KREFTMG, 0x5a);
1874 
1875 			if (intp->srch_algo[demod] == STV0900_COLD_START) {
1876 				intp->bw[demod] += 10000000;
1877 				intp->bw[demod] *= 15;
1878 				intp->bw[demod] /= 10;
1879 			} else if (intp->srch_algo[demod] == STV0900_WARM_START)
1880 				intp->bw[demod] += 10000000;
1881 
1882 		} else {
1883 			stv0900_write_reg(intp, KREFTMG, 0xc1);
1884 			intp->bw[demod] += 10000000;
1885 			intp->bw[demod] *= 15;
1886 			intp->bw[demod] /= 10;
1887 		}
1888 
1889 		stv0900_write_reg(intp, TMGCFG2, 0xc1);
1890 
1891 		stv0900_set_symbol_rate(intp, intp->mclk,
1892 					intp->symbol_rate[demod], demod);
1893 		stv0900_set_max_symbol_rate(intp, intp->mclk,
1894 					intp->symbol_rate[demod], demod);
1895 		stv0900_set_min_symbol_rate(intp, intp->mclk,
1896 					intp->symbol_rate[demod], demod);
1897 		if (intp->symbol_rate[demod] >= 10000000)
1898 			low_sr = FALSE;
1899 		else
1900 			low_sr = TRUE;
1901 
1902 	}
1903 
1904 	if (intp->tuner_type[demod] == 3)
1905 		stv0900_set_tuner_auto(intp, intp->freq[demod],
1906 				intp->bw[demod], demod);
1907 	else
1908 		stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1909 
1910 	agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1911 				stv0900_get_bits(intp, AGCIQ_VALUE0));
1912 
1913 	aq_power = 0;
1914 
1915 	if (agc1_power == 0) {
1916 		for (i = 0; i < 5; i++)
1917 			aq_power += (stv0900_get_bits(intp, POWER_I) +
1918 					stv0900_get_bits(intp, POWER_Q)) / 2;
1919 
1920 		aq_power /= 5;
1921 	}
1922 
1923 	if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1924 		intp->result[demod].locked = FALSE;
1925 		signal_type = STV0900_NOAGC1;
1926 		dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1927 	} else {
1928 		stv0900_write_bits(intp, SPECINV_CONTROL,
1929 					intp->srch_iq_inv[demod]);
1930 		if (intp->chip_id <= 0x20) /*cut 2.0*/
1931 			stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1932 		else /*cut 3.0*/
1933 			stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1934 
1935 		stv0900_set_search_standard(intp, demod);
1936 
1937 		if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1938 			stv0900_start_search(intp, demod);
1939 	}
1940 
1941 	if (signal_type == STV0900_NOAGC1)
1942 		return signal_type;
1943 
1944 	if (intp->chip_id == 0x12) {
1945 		stv0900_write_bits(intp, RST_HWARE, 0);
1946 		msleep(3);
1947 		stv0900_write_bits(intp, RST_HWARE, 1);
1948 		stv0900_write_bits(intp, RST_HWARE, 0);
1949 	}
1950 
1951 	if (algo == STV0900_BLIND_SEARCH)
1952 		lock = stv0900_blind_search_algo(fe);
1953 	else if (algo == STV0900_COLD_START)
1954 		lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1955 	else if (algo == STV0900_WARM_START)
1956 		lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1957 
1958 	if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1959 		if (low_sr == FALSE) {
1960 			if (stv0900_check_timing_lock(intp, demod) == TRUE)
1961 				lock = stv0900_sw_algo(intp, demod);
1962 		}
1963 	}
1964 
1965 	if (lock == TRUE)
1966 		signal_type = stv0900_get_signal_params(fe);
1967 
1968 	if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1969 		stv0900_track_optimization(fe);
1970 		if (intp->chip_id <= 0x11) {
1971 			if ((stv0900_get_standard(fe, 0) ==
1972 						STV0900_DVBS1_STANDARD) &&
1973 			   (stv0900_get_standard(fe, 1) ==
1974 						STV0900_DVBS1_STANDARD)) {
1975 				msleep(20);
1976 				stv0900_write_bits(intp, RST_HWARE, 0);
1977 			} else {
1978 				stv0900_write_bits(intp, RST_HWARE, 0);
1979 				msleep(3);
1980 				stv0900_write_bits(intp, RST_HWARE, 1);
1981 				stv0900_write_bits(intp, RST_HWARE, 0);
1982 			}
1983 
1984 		} else if (intp->chip_id >= 0x20) {
1985 			stv0900_write_bits(intp, RST_HWARE, 0);
1986 			msleep(3);
1987 			stv0900_write_bits(intp, RST_HWARE, 1);
1988 			stv0900_write_bits(intp, RST_HWARE, 0);
1989 		}
1990 
1991 		if (stv0900_wait_for_lock(intp, demod,
1992 					fec_timeout, fec_timeout) == TRUE) {
1993 			lock = TRUE;
1994 			intp->result[demod].locked = TRUE;
1995 			if (intp->result[demod].standard ==
1996 						STV0900_DVBS2_STANDARD) {
1997 				stv0900_set_dvbs2_rolloff(intp, demod);
1998 				stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
1999 				stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
2000 				stv0900_write_reg(intp, ERRCTRL1, 0x67);
2001 			} else {
2002 				stv0900_write_reg(intp, ERRCTRL1, 0x75);
2003 			}
2004 
2005 			stv0900_write_reg(intp, FBERCPT4, 0);
2006 			stv0900_write_reg(intp, ERRCTRL2, 0xc1);
2007 		} else {
2008 			lock = FALSE;
2009 			signal_type = STV0900_NODATA;
2010 			no_signal = stv0900_check_signal_presence(intp, demod);
2011 
2012 				intp->result[demod].locked = FALSE;
2013 		}
2014 	}
2015 
2016 	if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2017 		return signal_type;
2018 
2019 	if (intp->chip_id > 0x11) {
2020 		intp->result[demod].locked = FALSE;
2021 		return signal_type;
2022 	}
2023 
2024 	if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2025 	   (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
2026 		signal_type = stv0900_dvbs1_acq_workaround(fe);
2027 
2028 	return signal_type;
2029 }
2030 
2031