1 /* 2 * stv0900_core.c 3 * 4 * Driver for ST STV0900 satellite demodulator IC. 5 * 6 * Copyright (C) ST Microelectronics. 7 * Copyright (C) 2009 NetUP Inc. 8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/string.h> 29 #include <linux/slab.h> 30 #include <linux/i2c.h> 31 32 #include "stv0900.h" 33 #include "stv0900_reg.h" 34 #include "stv0900_priv.h" 35 #include "stv0900_init.h" 36 37 int stvdebug = 1; 38 module_param_named(debug, stvdebug, int, 0644); 39 40 /* internal params node */ 41 struct stv0900_inode { 42 /* pointer for internal params, one for each pair of demods */ 43 struct stv0900_internal *internal; 44 struct stv0900_inode *next_inode; 45 }; 46 47 /* first internal params */ 48 static struct stv0900_inode *stv0900_first_inode; 49 50 /* find chip by i2c adapter and i2c address */ 51 static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap, 52 u8 i2c_addr) 53 { 54 struct stv0900_inode *temp_chip = stv0900_first_inode; 55 56 if (temp_chip != NULL) { 57 /* 58 Search of the last stv0900 chip or 59 find it by i2c adapter and i2c address */ 60 while ((temp_chip != NULL) && 61 ((temp_chip->internal->i2c_adap != i2c_adap) || 62 (temp_chip->internal->i2c_addr != i2c_addr))) 63 64 temp_chip = temp_chip->next_inode; 65 66 } 67 68 return temp_chip; 69 } 70 71 /* deallocating chip */ 72 static void remove_inode(struct stv0900_internal *internal) 73 { 74 struct stv0900_inode *prev_node = stv0900_first_inode; 75 struct stv0900_inode *del_node = find_inode(internal->i2c_adap, 76 internal->i2c_addr); 77 78 if (del_node != NULL) { 79 if (del_node == stv0900_first_inode) { 80 stv0900_first_inode = del_node->next_inode; 81 } else { 82 while (prev_node->next_inode != del_node) 83 prev_node = prev_node->next_inode; 84 85 if (del_node->next_inode == NULL) 86 prev_node->next_inode = NULL; 87 else 88 prev_node->next_inode = 89 prev_node->next_inode->next_inode; 90 } 91 92 kfree(del_node); 93 } 94 } 95 96 /* allocating new chip */ 97 static struct stv0900_inode *append_internal(struct stv0900_internal *internal) 98 { 99 struct stv0900_inode *new_node = stv0900_first_inode; 100 101 if (new_node == NULL) { 102 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL); 103 stv0900_first_inode = new_node; 104 } else { 105 while (new_node->next_inode != NULL) 106 new_node = new_node->next_inode; 107 108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), 109 GFP_KERNEL); 110 if (new_node->next_inode != NULL) 111 new_node = new_node->next_inode; 112 else 113 new_node = NULL; 114 } 115 116 if (new_node != NULL) { 117 new_node->internal = internal; 118 new_node->next_inode = NULL; 119 } 120 121 return new_node; 122 } 123 124 s32 ge2comp(s32 a, s32 width) 125 { 126 if (width == 32) 127 return a; 128 else 129 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a; 130 } 131 132 void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr, 133 u8 reg_data) 134 { 135 u8 data[3]; 136 int ret; 137 struct i2c_msg i2cmsg = { 138 .addr = intp->i2c_addr, 139 .flags = 0, 140 .len = 3, 141 .buf = data, 142 }; 143 144 data[0] = MSB(reg_addr); 145 data[1] = LSB(reg_addr); 146 data[2] = reg_data; 147 148 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1); 149 if (ret != 1) 150 dprintk("%s: i2c error %d\n", __func__, ret); 151 } 152 153 u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg) 154 { 155 int ret; 156 u8 b0[] = { MSB(reg), LSB(reg) }; 157 u8 buf = 0; 158 struct i2c_msg msg[] = { 159 { 160 .addr = intp->i2c_addr, 161 .flags = 0, 162 .buf = b0, 163 .len = 2, 164 }, { 165 .addr = intp->i2c_addr, 166 .flags = I2C_M_RD, 167 .buf = &buf, 168 .len = 1, 169 }, 170 }; 171 172 ret = i2c_transfer(intp->i2c_adap, msg, 2); 173 if (ret != 2) 174 dprintk("%s: i2c error %d, reg[0x%02x]\n", 175 __func__, ret, reg); 176 177 return buf; 178 } 179 180 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos) 181 { 182 u8 position = 0, i = 0; 183 184 (*mask) = label & 0xff; 185 186 while ((position == 0) && (i < 8)) { 187 position = ((*mask) >> i) & 0x01; 188 i++; 189 } 190 191 (*pos) = (i - 1); 192 } 193 194 void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val) 195 { 196 u8 reg, mask, pos; 197 198 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff); 199 extract_mask_pos(label, &mask, &pos); 200 201 val = mask & (val << pos); 202 203 reg = (reg & (~mask)) | val; 204 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg); 205 206 } 207 208 u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label) 209 { 210 u8 val = 0xff; 211 u8 mask, pos; 212 213 extract_mask_pos(label, &mask, &pos); 214 215 val = stv0900_read_reg(intp, label >> 16); 216 val = (val & mask) >> pos; 217 218 return val; 219 } 220 221 static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp) 222 { 223 s32 i; 224 225 if (intp == NULL) 226 return STV0900_INVALID_HANDLE; 227 228 intp->chip_id = stv0900_read_reg(intp, R0900_MID); 229 230 if (intp->errs != STV0900_NO_ERROR) 231 return intp->errs; 232 233 /*Startup sequence*/ 234 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c); 235 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c); 236 msleep(3); 237 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c); 238 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f); 239 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20); 240 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20); 241 stv0900_write_reg(intp, R0900_NCOARSE, 0x13); 242 msleep(3); 243 stv0900_write_reg(intp, R0900_I2CCFG, 0x08); 244 245 switch (intp->clkmode) { 246 case 0: 247 case 2: 248 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 249 | intp->clkmode); 250 break; 251 default: 252 /* preserve SELOSCI bit */ 253 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL); 254 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i); 255 break; 256 } 257 258 msleep(3); 259 for (i = 0; i < 181; i++) 260 stv0900_write_reg(intp, STV0900_InitVal[i][0], 261 STV0900_InitVal[i][1]); 262 263 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) { 264 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c); 265 for (i = 0; i < 32; i++) 266 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0], 267 STV0900_Cut20_AddOnVal[i][1]); 268 } 269 270 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c); 271 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c); 272 273 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01); 274 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21); 275 276 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20); 277 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20); 278 279 stv0900_write_reg(intp, R0900_TSTRES0, 0x80); 280 stv0900_write_reg(intp, R0900_TSTRES0, 0x00); 281 282 return STV0900_NO_ERROR; 283 } 284 285 static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk) 286 { 287 u32 mclk = 90000000, div = 0, ad_div = 0; 288 289 div = stv0900_get_bits(intp, F0900_M_DIV); 290 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); 291 292 mclk = (div + 1) * ext_clk / ad_div; 293 294 dprintk("%s: Calculated Mclk = %d\n", __func__, mclk); 295 296 return mclk; 297 } 298 299 static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk) 300 { 301 u32 m_div, clk_sel; 302 303 if (intp == NULL) 304 return STV0900_INVALID_HANDLE; 305 306 if (intp->errs) 307 return STV0900_I2C_ERROR; 308 309 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk, 310 intp->quartz); 311 312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); 313 m_div = ((clk_sel * mclk) / intp->quartz) - 1; 314 stv0900_write_bits(intp, F0900_M_DIV, m_div); 315 intp->mclk = stv0900_get_mclk_freq(intp, 316 intp->quartz); 317 318 /*Set the DiseqC frequency to 22KHz */ 319 /* 320 Formula: 321 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg) 322 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg) 323 */ 324 m_div = intp->mclk / 704000; 325 stv0900_write_reg(intp, R0900_P1_F22TX, m_div); 326 stv0900_write_reg(intp, R0900_P1_F22RX, m_div); 327 328 stv0900_write_reg(intp, R0900_P2_F22TX, m_div); 329 stv0900_write_reg(intp, R0900_P2_F22RX, m_div); 330 331 if ((intp->errs)) 332 return STV0900_I2C_ERROR; 333 334 return STV0900_NO_ERROR; 335 } 336 337 static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr, 338 enum fe_stv0900_demod_num demod) 339 { 340 u32 lsb, msb, hsb, err_val; 341 342 switch (cntr) { 343 case 0: 344 default: 345 hsb = stv0900_get_bits(intp, ERR_CNT12); 346 msb = stv0900_get_bits(intp, ERR_CNT11); 347 lsb = stv0900_get_bits(intp, ERR_CNT10); 348 break; 349 case 1: 350 hsb = stv0900_get_bits(intp, ERR_CNT22); 351 msb = stv0900_get_bits(intp, ERR_CNT21); 352 lsb = stv0900_get_bits(intp, ERR_CNT20); 353 break; 354 } 355 356 err_val = (hsb << 16) + (msb << 8) + (lsb); 357 358 return err_val; 359 } 360 361 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 362 { 363 struct stv0900_state *state = fe->demodulator_priv; 364 struct stv0900_internal *intp = state->internal; 365 enum fe_stv0900_demod_num demod = state->demod; 366 367 stv0900_write_bits(intp, I2CT_ON, enable); 368 369 return 0; 370 } 371 372 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp, 373 enum fe_stv0900_clock_type path1_ts, 374 enum fe_stv0900_clock_type path2_ts) 375 { 376 377 dprintk("%s\n", __func__); 378 379 if (intp->chip_id >= 0x20) { 380 switch (path1_ts) { 381 case STV0900_PARALLEL_PUNCT_CLOCK: 382 case STV0900_DVBCI_CLOCK: 383 switch (path2_ts) { 384 case STV0900_SERIAL_PUNCT_CLOCK: 385 case STV0900_SERIAL_CONT_CLOCK: 386 default: 387 stv0900_write_reg(intp, R0900_TSGENERAL, 388 0x00); 389 break; 390 case STV0900_PARALLEL_PUNCT_CLOCK: 391 case STV0900_DVBCI_CLOCK: 392 stv0900_write_reg(intp, R0900_TSGENERAL, 393 0x06); 394 stv0900_write_bits(intp, 395 F0900_P1_TSFIFO_MANSPEED, 3); 396 stv0900_write_bits(intp, 397 F0900_P2_TSFIFO_MANSPEED, 0); 398 stv0900_write_reg(intp, 399 R0900_P1_TSSPEED, 0x14); 400 stv0900_write_reg(intp, 401 R0900_P2_TSSPEED, 0x28); 402 break; 403 } 404 break; 405 case STV0900_SERIAL_PUNCT_CLOCK: 406 case STV0900_SERIAL_CONT_CLOCK: 407 default: 408 switch (path2_ts) { 409 case STV0900_SERIAL_PUNCT_CLOCK: 410 case STV0900_SERIAL_CONT_CLOCK: 411 default: 412 stv0900_write_reg(intp, 413 R0900_TSGENERAL, 0x0C); 414 break; 415 case STV0900_PARALLEL_PUNCT_CLOCK: 416 case STV0900_DVBCI_CLOCK: 417 stv0900_write_reg(intp, 418 R0900_TSGENERAL, 0x0A); 419 dprintk("%s: 0x0a\n", __func__); 420 break; 421 } 422 break; 423 } 424 } else { 425 switch (path1_ts) { 426 case STV0900_PARALLEL_PUNCT_CLOCK: 427 case STV0900_DVBCI_CLOCK: 428 switch (path2_ts) { 429 case STV0900_SERIAL_PUNCT_CLOCK: 430 case STV0900_SERIAL_CONT_CLOCK: 431 default: 432 stv0900_write_reg(intp, R0900_TSGENERAL1X, 433 0x10); 434 break; 435 case STV0900_PARALLEL_PUNCT_CLOCK: 436 case STV0900_DVBCI_CLOCK: 437 stv0900_write_reg(intp, R0900_TSGENERAL1X, 438 0x16); 439 stv0900_write_bits(intp, 440 F0900_P1_TSFIFO_MANSPEED, 3); 441 stv0900_write_bits(intp, 442 F0900_P2_TSFIFO_MANSPEED, 0); 443 stv0900_write_reg(intp, R0900_P1_TSSPEED, 444 0x14); 445 stv0900_write_reg(intp, R0900_P2_TSSPEED, 446 0x28); 447 break; 448 } 449 450 break; 451 case STV0900_SERIAL_PUNCT_CLOCK: 452 case STV0900_SERIAL_CONT_CLOCK: 453 default: 454 switch (path2_ts) { 455 case STV0900_SERIAL_PUNCT_CLOCK: 456 case STV0900_SERIAL_CONT_CLOCK: 457 default: 458 stv0900_write_reg(intp, R0900_TSGENERAL1X, 459 0x14); 460 break; 461 case STV0900_PARALLEL_PUNCT_CLOCK: 462 case STV0900_DVBCI_CLOCK: 463 stv0900_write_reg(intp, R0900_TSGENERAL1X, 464 0x12); 465 dprintk("%s: 0x12\n", __func__); 466 break; 467 } 468 469 break; 470 } 471 } 472 473 switch (path1_ts) { 474 case STV0900_PARALLEL_PUNCT_CLOCK: 475 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00); 476 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00); 477 break; 478 case STV0900_DVBCI_CLOCK: 479 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00); 480 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01); 481 break; 482 case STV0900_SERIAL_PUNCT_CLOCK: 483 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01); 484 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00); 485 break; 486 case STV0900_SERIAL_CONT_CLOCK: 487 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01); 488 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01); 489 break; 490 default: 491 break; 492 } 493 494 switch (path2_ts) { 495 case STV0900_PARALLEL_PUNCT_CLOCK: 496 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00); 497 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00); 498 break; 499 case STV0900_DVBCI_CLOCK: 500 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00); 501 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01); 502 break; 503 case STV0900_SERIAL_PUNCT_CLOCK: 504 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01); 505 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00); 506 break; 507 case STV0900_SERIAL_CONT_CLOCK: 508 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01); 509 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01); 510 break; 511 default: 512 break; 513 } 514 515 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1); 516 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0); 517 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1); 518 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0); 519 } 520 521 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency, 522 u32 bandwidth) 523 { 524 struct dvb_frontend_ops *frontend_ops = NULL; 525 struct dvb_tuner_ops *tuner_ops = NULL; 526 527 frontend_ops = &fe->ops; 528 tuner_ops = &frontend_ops->tuner_ops; 529 530 if (tuner_ops->set_frequency) { 531 if ((tuner_ops->set_frequency(fe, frequency)) < 0) 532 dprintk("%s: Invalid parameter\n", __func__); 533 else 534 dprintk("%s: Frequency=%d\n", __func__, frequency); 535 536 } 537 538 if (tuner_ops->set_bandwidth) { 539 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0) 540 dprintk("%s: Invalid parameter\n", __func__); 541 else 542 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth); 543 544 } 545 } 546 547 void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth) 548 { 549 struct dvb_frontend_ops *frontend_ops = NULL; 550 struct dvb_tuner_ops *tuner_ops = NULL; 551 552 frontend_ops = &fe->ops; 553 tuner_ops = &frontend_ops->tuner_ops; 554 555 if (tuner_ops->set_bandwidth) { 556 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0) 557 dprintk("%s: Invalid parameter\n", __func__); 558 else 559 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth); 560 561 } 562 } 563 564 u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod) 565 { 566 u32 freq, round; 567 /* Formulat : 568 Tuner_Frequency(MHz) = Regs / 64 569 Tuner_granularity(MHz) = Regs / 2048 570 real_Tuner_Frequency = Tuner_Frequency(MHz) - Tuner_granularity(MHz) 571 */ 572 freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) + 573 (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) + 574 stv0900_get_bits(intp, TUN_RFFREQ0); 575 576 freq = (freq * 1000) / 64; 577 578 round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) + 579 stv0900_get_bits(intp, TUN_RFRESTE0); 580 581 round = (round * 1000) / 2048; 582 583 return freq + round; 584 } 585 586 void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency, 587 u32 Bandwidth, int demod) 588 { 589 u32 tunerFrequency; 590 /* Formulat: 591 Tuner_frequency_reg= Frequency(MHz)*64 592 */ 593 tunerFrequency = (Frequency * 64) / 1000; 594 595 stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10)); 596 stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff); 597 stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03)); 598 /* Low Pass Filter = BW /2 (MHz)*/ 599 stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000); 600 /* Tuner Write trig */ 601 stv0900_write_reg(intp, TNRLD, 1); 602 } 603 604 static s32 stv0900_get_rf_level(struct stv0900_internal *intp, 605 const struct stv0900_table *lookup, 606 enum fe_stv0900_demod_num demod) 607 { 608 s32 agc_gain = 0, 609 imin, 610 imax, 611 i, 612 rf_lvl = 0; 613 614 dprintk("%s\n", __func__); 615 616 if ((lookup == NULL) || (lookup->size <= 0)) 617 return 0; 618 619 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1), 620 stv0900_get_bits(intp, AGCIQ_VALUE0)); 621 622 imin = 0; 623 imax = lookup->size - 1; 624 if (INRANGE(lookup->table[imin].regval, agc_gain, 625 lookup->table[imax].regval)) { 626 while ((imax - imin) > 1) { 627 i = (imax + imin) >> 1; 628 629 if (INRANGE(lookup->table[imin].regval, 630 agc_gain, 631 lookup->table[i].regval)) 632 imax = i; 633 else 634 imin = i; 635 } 636 637 rf_lvl = (s32)agc_gain - lookup->table[imin].regval; 638 rf_lvl *= (lookup->table[imax].realval - 639 lookup->table[imin].realval); 640 rf_lvl /= (lookup->table[imax].regval - 641 lookup->table[imin].regval); 642 rf_lvl += lookup->table[imin].realval; 643 } else if (agc_gain > lookup->table[0].regval) 644 rf_lvl = 5; 645 else if (agc_gain < lookup->table[lookup->size-1].regval) 646 rf_lvl = -100; 647 648 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl); 649 650 return rf_lvl; 651 } 652 653 static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 654 { 655 struct stv0900_state *state = fe->demodulator_priv; 656 struct stv0900_internal *internal = state->internal; 657 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf, 658 state->demod); 659 660 rflevel = (rflevel + 100) * (65535 / 70); 661 if (rflevel < 0) 662 rflevel = 0; 663 664 if (rflevel > 65535) 665 rflevel = 65535; 666 667 *strength = rflevel; 668 669 return 0; 670 } 671 672 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe, 673 const struct stv0900_table *lookup) 674 { 675 struct stv0900_state *state = fe->demodulator_priv; 676 struct stv0900_internal *intp = state->internal; 677 enum fe_stv0900_demod_num demod = state->demod; 678 679 s32 c_n = -100, 680 regval, 681 imin, 682 imax, 683 i, 684 noise_field1, 685 noise_field0; 686 687 dprintk("%s\n", __func__); 688 689 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) { 690 noise_field1 = NOSPLHT_NORMED1; 691 noise_field0 = NOSPLHT_NORMED0; 692 } else { 693 noise_field1 = NOSDATAT_NORMED1; 694 noise_field0 = NOSDATAT_NORMED0; 695 } 696 697 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) { 698 if ((lookup != NULL) && lookup->size) { 699 regval = 0; 700 msleep(5); 701 for (i = 0; i < 16; i++) { 702 regval += MAKEWORD(stv0900_get_bits(intp, 703 noise_field1), 704 stv0900_get_bits(intp, 705 noise_field0)); 706 msleep(1); 707 } 708 709 regval /= 16; 710 imin = 0; 711 imax = lookup->size - 1; 712 if (INRANGE(lookup->table[imin].regval, 713 regval, 714 lookup->table[imax].regval)) { 715 while ((imax - imin) > 1) { 716 i = (imax + imin) >> 1; 717 if (INRANGE(lookup->table[imin].regval, 718 regval, 719 lookup->table[i].regval)) 720 imax = i; 721 else 722 imin = i; 723 } 724 725 c_n = ((regval - lookup->table[imin].regval) 726 * (lookup->table[imax].realval 727 - lookup->table[imin].realval) 728 / (lookup->table[imax].regval 729 - lookup->table[imin].regval)) 730 + lookup->table[imin].realval; 731 } else if (regval < lookup->table[imin].regval) 732 c_n = 1000; 733 } 734 } 735 736 return c_n; 737 } 738 739 static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 740 { 741 struct stv0900_state *state = fe->demodulator_priv; 742 struct stv0900_internal *intp = state->internal; 743 enum fe_stv0900_demod_num demod = state->demod; 744 u8 err_val1, err_val0; 745 u32 header_err_val = 0; 746 747 *ucblocks = 0x0; 748 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) { 749 /* DVB-S2 delineator errors count */ 750 751 /* retreiving number for errnous headers */ 752 err_val1 = stv0900_read_reg(intp, BBFCRCKO1); 753 err_val0 = stv0900_read_reg(intp, BBFCRCKO0); 754 header_err_val = (err_val1 << 8) | err_val0; 755 756 /* retreiving number for errnous packets */ 757 err_val1 = stv0900_read_reg(intp, UPCRCKO1); 758 err_val0 = stv0900_read_reg(intp, UPCRCKO0); 759 *ucblocks = (err_val1 << 8) | err_val0; 760 *ucblocks += header_err_val; 761 } 762 763 return 0; 764 } 765 766 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr) 767 { 768 s32 snrlcl = stv0900_carr_get_quality(fe, 769 (const struct stv0900_table *)&stv0900_s2_cn); 770 snrlcl = (snrlcl + 30) * 384; 771 if (snrlcl < 0) 772 snrlcl = 0; 773 774 if (snrlcl > 65535) 775 snrlcl = 65535; 776 777 *snr = snrlcl; 778 779 return 0; 780 } 781 782 static u32 stv0900_get_ber(struct stv0900_internal *intp, 783 enum fe_stv0900_demod_num demod) 784 { 785 u32 ber = 10000000, i; 786 s32 demod_state; 787 788 demod_state = stv0900_get_bits(intp, HEADER_MODE); 789 790 switch (demod_state) { 791 case STV0900_SEARCH: 792 case STV0900_PLH_DETECTED: 793 default: 794 ber = 10000000; 795 break; 796 case STV0900_DVBS_FOUND: 797 ber = 0; 798 for (i = 0; i < 5; i++) { 799 msleep(5); 800 ber += stv0900_get_err_count(intp, 0, demod); 801 } 802 803 ber /= 5; 804 if (stv0900_get_bits(intp, PRFVIT)) { 805 ber *= 9766; 806 ber = ber >> 13; 807 } 808 809 break; 810 case STV0900_DVBS2_FOUND: 811 ber = 0; 812 for (i = 0; i < 5; i++) { 813 msleep(5); 814 ber += stv0900_get_err_count(intp, 0, demod); 815 } 816 817 ber /= 5; 818 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) { 819 ber *= 9766; 820 ber = ber >> 13; 821 } 822 823 break; 824 } 825 826 return ber; 827 } 828 829 static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber) 830 { 831 struct stv0900_state *state = fe->demodulator_priv; 832 struct stv0900_internal *internal = state->internal; 833 834 *ber = stv0900_get_ber(internal, state->demod); 835 836 return 0; 837 } 838 839 int stv0900_get_demod_lock(struct stv0900_internal *intp, 840 enum fe_stv0900_demod_num demod, s32 time_out) 841 { 842 s32 timer = 0, 843 lock = 0; 844 845 enum fe_stv0900_search_state dmd_state; 846 847 while ((timer < time_out) && (lock == 0)) { 848 dmd_state = stv0900_get_bits(intp, HEADER_MODE); 849 dprintk("Demod State = %d\n", dmd_state); 850 switch (dmd_state) { 851 case STV0900_SEARCH: 852 case STV0900_PLH_DETECTED: 853 default: 854 lock = 0; 855 break; 856 case STV0900_DVBS2_FOUND: 857 case STV0900_DVBS_FOUND: 858 lock = stv0900_get_bits(intp, LOCK_DEFINITIF); 859 break; 860 } 861 862 if (lock == 0) 863 msleep(10); 864 865 timer += 10; 866 } 867 868 if (lock) 869 dprintk("DEMOD LOCK OK\n"); 870 else 871 dprintk("DEMOD LOCK FAIL\n"); 872 873 return lock; 874 } 875 876 void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp, 877 enum fe_stv0900_demod_num demod) 878 { 879 s32 regflist, 880 i; 881 882 dprintk("%s\n", __func__); 883 884 regflist = MODCODLST0; 885 886 for (i = 0; i < 16; i++) 887 stv0900_write_reg(intp, regflist + i, 0xff); 888 } 889 890 void stv0900_activate_s2_modcod(struct stv0900_internal *intp, 891 enum fe_stv0900_demod_num demod) 892 { 893 u32 matype, 894 mod_code, 895 fmod, 896 reg_index, 897 field_index; 898 899 dprintk("%s\n", __func__); 900 901 if (intp->chip_id <= 0x11) { 902 msleep(5); 903 904 mod_code = stv0900_read_reg(intp, PLHMODCOD); 905 matype = mod_code & 0x3; 906 mod_code = (mod_code & 0x7f) >> 2; 907 908 reg_index = MODCODLSTF - mod_code / 2; 909 field_index = mod_code % 2; 910 911 switch (matype) { 912 case 0: 913 default: 914 fmod = 14; 915 break; 916 case 1: 917 fmod = 13; 918 break; 919 case 2: 920 fmod = 11; 921 break; 922 case 3: 923 fmod = 7; 924 break; 925 } 926 927 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910)) 928 && (matype <= 1)) { 929 if (field_index == 0) 930 stv0900_write_reg(intp, reg_index, 931 0xf0 | fmod); 932 else 933 stv0900_write_reg(intp, reg_index, 934 (fmod << 4) | 0xf); 935 } 936 937 } else if (intp->chip_id >= 0x12) { 938 for (reg_index = 0; reg_index < 7; reg_index++) 939 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff); 940 941 stv0900_write_reg(intp, MODCODLSTE, 0xff); 942 stv0900_write_reg(intp, MODCODLSTF, 0xcf); 943 for (reg_index = 0; reg_index < 8; reg_index++) 944 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc); 945 946 947 } 948 } 949 950 void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp, 951 enum fe_stv0900_demod_num demod) 952 { 953 u32 reg_index; 954 955 dprintk("%s\n", __func__); 956 957 stv0900_write_reg(intp, MODCODLST0, 0xff); 958 stv0900_write_reg(intp, MODCODLST1, 0xf0); 959 stv0900_write_reg(intp, MODCODLSTF, 0x0f); 960 for (reg_index = 0; reg_index < 13; reg_index++) 961 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0); 962 963 } 964 965 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe) 966 { 967 return DVBFE_ALGO_CUSTOM; 968 } 969 970 void stv0900_start_search(struct stv0900_internal *intp, 971 enum fe_stv0900_demod_num demod) 972 { 973 u32 freq; 974 s16 freq_s16 ; 975 976 stv0900_write_bits(intp, DEMOD_MODE, 0x1f); 977 if (intp->chip_id == 0x10) 978 stv0900_write_reg(intp, CORRELEXP, 0xaa); 979 980 if (intp->chip_id < 0x20) 981 stv0900_write_reg(intp, CARHDR, 0x55); 982 983 if (intp->chip_id <= 0x20) { 984 if (intp->symbol_rate[0] <= 5000000) { 985 stv0900_write_reg(intp, CARCFG, 0x44); 986 stv0900_write_reg(intp, CFRUP1, 0x0f); 987 stv0900_write_reg(intp, CFRUP0, 0xff); 988 stv0900_write_reg(intp, CFRLOW1, 0xf0); 989 stv0900_write_reg(intp, CFRLOW0, 0x00); 990 stv0900_write_reg(intp, RTCS2, 0x68); 991 } else { 992 stv0900_write_reg(intp, CARCFG, 0xc4); 993 stv0900_write_reg(intp, RTCS2, 0x44); 994 } 995 996 } else { /*cut 3.0 above*/ 997 if (intp->symbol_rate[demod] <= 5000000) 998 stv0900_write_reg(intp, RTCS2, 0x68); 999 else 1000 stv0900_write_reg(intp, RTCS2, 0x44); 1001 1002 stv0900_write_reg(intp, CARCFG, 0x46); 1003 if (intp->srch_algo[demod] == STV0900_WARM_START) { 1004 freq = 1000 << 16; 1005 freq /= (intp->mclk / 1000); 1006 freq_s16 = (s16)freq; 1007 } else { 1008 freq = (intp->srch_range[demod] / 2000); 1009 if (intp->symbol_rate[demod] <= 5000000) 1010 freq += 80; 1011 else 1012 freq += 600; 1013 1014 freq = freq << 16; 1015 freq /= (intp->mclk / 1000); 1016 freq_s16 = (s16)freq; 1017 } 1018 1019 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16)); 1020 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16)); 1021 freq_s16 *= (-1); 1022 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16)); 1023 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16)); 1024 } 1025 1026 stv0900_write_reg(intp, CFRINIT1, 0); 1027 stv0900_write_reg(intp, CFRINIT0, 0); 1028 1029 if (intp->chip_id >= 0x20) { 1030 stv0900_write_reg(intp, EQUALCFG, 0x41); 1031 stv0900_write_reg(intp, FFECFG, 0x41); 1032 1033 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) || 1034 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) || 1035 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) { 1036 stv0900_write_reg(intp, VITSCALE, 1037 0x82); 1038 stv0900_write_reg(intp, VAVSRVIT, 0x0); 1039 } 1040 } 1041 1042 stv0900_write_reg(intp, SFRSTEP, 0x00); 1043 stv0900_write_reg(intp, TMGTHRISE, 0xe0); 1044 stv0900_write_reg(intp, TMGTHFALL, 0xc0); 1045 stv0900_write_bits(intp, SCAN_ENABLE, 0); 1046 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); 1047 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0); 1048 stv0900_write_reg(intp, RTC, 0x88); 1049 if (intp->chip_id >= 0x20) { 1050 if (intp->symbol_rate[demod] < 2000000) { 1051 if (intp->chip_id <= 0x20) 1052 stv0900_write_reg(intp, CARFREQ, 0x39); 1053 else /*cut 3.0*/ 1054 stv0900_write_reg(intp, CARFREQ, 0x89); 1055 1056 stv0900_write_reg(intp, CARHDR, 0x40); 1057 } else if (intp->symbol_rate[demod] < 10000000) { 1058 stv0900_write_reg(intp, CARFREQ, 0x4c); 1059 stv0900_write_reg(intp, CARHDR, 0x20); 1060 } else { 1061 stv0900_write_reg(intp, CARFREQ, 0x4b); 1062 stv0900_write_reg(intp, CARHDR, 0x20); 1063 } 1064 1065 } else { 1066 if (intp->symbol_rate[demod] < 10000000) 1067 stv0900_write_reg(intp, CARFREQ, 0xef); 1068 else 1069 stv0900_write_reg(intp, CARFREQ, 0xed); 1070 } 1071 1072 switch (intp->srch_algo[demod]) { 1073 case STV0900_WARM_START: 1074 stv0900_write_reg(intp, DMDISTATE, 0x1f); 1075 stv0900_write_reg(intp, DMDISTATE, 0x18); 1076 break; 1077 case STV0900_COLD_START: 1078 stv0900_write_reg(intp, DMDISTATE, 0x1f); 1079 stv0900_write_reg(intp, DMDISTATE, 0x15); 1080 break; 1081 default: 1082 break; 1083 } 1084 } 1085 1086 u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode, 1087 s32 pilot, u8 chip_id) 1088 { 1089 u8 aclc_value = 0x29; 1090 s32 i; 1091 const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2; 1092 1093 dprintk("%s\n", __func__); 1094 1095 if (chip_id <= 0x12) { 1096 cls2 = FE_STV0900_S2CarLoop; 1097 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30; 1098 cllas2 = FE_STV0900_S2APSKCarLoopCut30; 1099 } else if (chip_id == 0x20) { 1100 cls2 = FE_STV0900_S2CarLoopCut20; 1101 cllqs2 = FE_STV0900_S2LowQPCarLoopCut20; 1102 cllas2 = FE_STV0900_S2APSKCarLoopCut20; 1103 } else { 1104 cls2 = FE_STV0900_S2CarLoopCut30; 1105 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30; 1106 cllas2 = FE_STV0900_S2APSKCarLoopCut30; 1107 } 1108 1109 if (modcode < STV0900_QPSK_12) { 1110 i = 0; 1111 while ((i < 3) && (modcode != cllqs2[i].modcode)) 1112 i++; 1113 1114 if (i >= 3) 1115 i = 2; 1116 } else { 1117 i = 0; 1118 while ((i < 14) && (modcode != cls2[i].modcode)) 1119 i++; 1120 1121 if (i >= 14) { 1122 i = 0; 1123 while ((i < 11) && (modcode != cllas2[i].modcode)) 1124 i++; 1125 1126 if (i >= 11) 1127 i = 10; 1128 } 1129 } 1130 1131 if (modcode <= STV0900_QPSK_25) { 1132 if (pilot) { 1133 if (srate <= 3000000) 1134 aclc_value = cllqs2[i].car_loop_pilots_on_2; 1135 else if (srate <= 7000000) 1136 aclc_value = cllqs2[i].car_loop_pilots_on_5; 1137 else if (srate <= 15000000) 1138 aclc_value = cllqs2[i].car_loop_pilots_on_10; 1139 else if (srate <= 25000000) 1140 aclc_value = cllqs2[i].car_loop_pilots_on_20; 1141 else 1142 aclc_value = cllqs2[i].car_loop_pilots_on_30; 1143 } else { 1144 if (srate <= 3000000) 1145 aclc_value = cllqs2[i].car_loop_pilots_off_2; 1146 else if (srate <= 7000000) 1147 aclc_value = cllqs2[i].car_loop_pilots_off_5; 1148 else if (srate <= 15000000) 1149 aclc_value = cllqs2[i].car_loop_pilots_off_10; 1150 else if (srate <= 25000000) 1151 aclc_value = cllqs2[i].car_loop_pilots_off_20; 1152 else 1153 aclc_value = cllqs2[i].car_loop_pilots_off_30; 1154 } 1155 1156 } else if (modcode <= STV0900_8PSK_910) { 1157 if (pilot) { 1158 if (srate <= 3000000) 1159 aclc_value = cls2[i].car_loop_pilots_on_2; 1160 else if (srate <= 7000000) 1161 aclc_value = cls2[i].car_loop_pilots_on_5; 1162 else if (srate <= 15000000) 1163 aclc_value = cls2[i].car_loop_pilots_on_10; 1164 else if (srate <= 25000000) 1165 aclc_value = cls2[i].car_loop_pilots_on_20; 1166 else 1167 aclc_value = cls2[i].car_loop_pilots_on_30; 1168 } else { 1169 if (srate <= 3000000) 1170 aclc_value = cls2[i].car_loop_pilots_off_2; 1171 else if (srate <= 7000000) 1172 aclc_value = cls2[i].car_loop_pilots_off_5; 1173 else if (srate <= 15000000) 1174 aclc_value = cls2[i].car_loop_pilots_off_10; 1175 else if (srate <= 25000000) 1176 aclc_value = cls2[i].car_loop_pilots_off_20; 1177 else 1178 aclc_value = cls2[i].car_loop_pilots_off_30; 1179 } 1180 1181 } else { 1182 if (srate <= 3000000) 1183 aclc_value = cllas2[i].car_loop_pilots_on_2; 1184 else if (srate <= 7000000) 1185 aclc_value = cllas2[i].car_loop_pilots_on_5; 1186 else if (srate <= 15000000) 1187 aclc_value = cllas2[i].car_loop_pilots_on_10; 1188 else if (srate <= 25000000) 1189 aclc_value = cllas2[i].car_loop_pilots_on_20; 1190 else 1191 aclc_value = cllas2[i].car_loop_pilots_on_30; 1192 } 1193 1194 return aclc_value; 1195 } 1196 1197 u8 stv0900_get_optim_short_carr_loop(s32 srate, 1198 enum fe_stv0900_modulation modulation, 1199 u8 chip_id) 1200 { 1201 const struct stv0900_short_frames_car_loop_optim *s2scl; 1202 const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30; 1203 s32 mod_index = 0; 1204 u8 aclc_value = 0x0b; 1205 1206 dprintk("%s\n", __func__); 1207 1208 s2scl = FE_STV0900_S2ShortCarLoop; 1209 s2sclc30 = FE_STV0900_S2ShortCarLoopCut30; 1210 1211 switch (modulation) { 1212 case STV0900_QPSK: 1213 default: 1214 mod_index = 0; 1215 break; 1216 case STV0900_8PSK: 1217 mod_index = 1; 1218 break; 1219 case STV0900_16APSK: 1220 mod_index = 2; 1221 break; 1222 case STV0900_32APSK: 1223 mod_index = 3; 1224 break; 1225 } 1226 1227 if (chip_id >= 0x30) { 1228 if (srate <= 3000000) 1229 aclc_value = s2sclc30[mod_index].car_loop_2; 1230 else if (srate <= 7000000) 1231 aclc_value = s2sclc30[mod_index].car_loop_5; 1232 else if (srate <= 15000000) 1233 aclc_value = s2sclc30[mod_index].car_loop_10; 1234 else if (srate <= 25000000) 1235 aclc_value = s2sclc30[mod_index].car_loop_20; 1236 else 1237 aclc_value = s2sclc30[mod_index].car_loop_30; 1238 1239 } else if (chip_id >= 0x20) { 1240 if (srate <= 3000000) 1241 aclc_value = s2scl[mod_index].car_loop_cut20_2; 1242 else if (srate <= 7000000) 1243 aclc_value = s2scl[mod_index].car_loop_cut20_5; 1244 else if (srate <= 15000000) 1245 aclc_value = s2scl[mod_index].car_loop_cut20_10; 1246 else if (srate <= 25000000) 1247 aclc_value = s2scl[mod_index].car_loop_cut20_20; 1248 else 1249 aclc_value = s2scl[mod_index].car_loop_cut20_30; 1250 1251 } else { 1252 if (srate <= 3000000) 1253 aclc_value = s2scl[mod_index].car_loop_cut12_2; 1254 else if (srate <= 7000000) 1255 aclc_value = s2scl[mod_index].car_loop_cut12_5; 1256 else if (srate <= 15000000) 1257 aclc_value = s2scl[mod_index].car_loop_cut12_10; 1258 else if (srate <= 25000000) 1259 aclc_value = s2scl[mod_index].car_loop_cut12_20; 1260 else 1261 aclc_value = s2scl[mod_index].car_loop_cut12_30; 1262 1263 } 1264 1265 return aclc_value; 1266 } 1267 1268 static 1269 enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp, 1270 enum fe_stv0900_demod_mode LDPC_Mode, 1271 enum fe_stv0900_demod_num demod) 1272 { 1273 s32 reg_ind; 1274 1275 dprintk("%s\n", __func__); 1276 1277 switch (LDPC_Mode) { 1278 case STV0900_DUAL: 1279 default: 1280 if ((intp->demod_mode != STV0900_DUAL) 1281 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) { 1282 stv0900_write_reg(intp, R0900_GENCFG, 0x1d); 1283 1284 intp->demod_mode = STV0900_DUAL; 1285 1286 stv0900_write_bits(intp, F0900_FRESFEC, 1); 1287 stv0900_write_bits(intp, F0900_FRESFEC, 0); 1288 1289 for (reg_ind = 0; reg_ind < 7; reg_ind++) 1290 stv0900_write_reg(intp, 1291 R0900_P1_MODCODLST0 + reg_ind, 1292 0xff); 1293 for (reg_ind = 0; reg_ind < 8; reg_ind++) 1294 stv0900_write_reg(intp, 1295 R0900_P1_MODCODLST7 + reg_ind, 1296 0xcc); 1297 1298 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff); 1299 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf); 1300 1301 for (reg_ind = 0; reg_ind < 7; reg_ind++) 1302 stv0900_write_reg(intp, 1303 R0900_P2_MODCODLST0 + reg_ind, 1304 0xff); 1305 for (reg_ind = 0; reg_ind < 8; reg_ind++) 1306 stv0900_write_reg(intp, 1307 R0900_P2_MODCODLST7 + reg_ind, 1308 0xcc); 1309 1310 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff); 1311 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf); 1312 } 1313 1314 break; 1315 case STV0900_SINGLE: 1316 if (demod == STV0900_DEMOD_2) { 1317 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1); 1318 stv0900_activate_s2_modcod_single(intp, 1319 STV0900_DEMOD_2); 1320 stv0900_write_reg(intp, R0900_GENCFG, 0x06); 1321 } else { 1322 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2); 1323 stv0900_activate_s2_modcod_single(intp, 1324 STV0900_DEMOD_1); 1325 stv0900_write_reg(intp, R0900_GENCFG, 0x04); 1326 } 1327 1328 intp->demod_mode = STV0900_SINGLE; 1329 1330 stv0900_write_bits(intp, F0900_FRESFEC, 1); 1331 stv0900_write_bits(intp, F0900_FRESFEC, 0); 1332 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1); 1333 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0); 1334 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1); 1335 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0); 1336 break; 1337 } 1338 1339 return STV0900_NO_ERROR; 1340 } 1341 1342 static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe, 1343 struct stv0900_init_params *p_init) 1344 { 1345 struct stv0900_state *state = fe->demodulator_priv; 1346 enum fe_stv0900_error error = STV0900_NO_ERROR; 1347 enum fe_stv0900_error demodError = STV0900_NO_ERROR; 1348 struct stv0900_internal *intp = NULL; 1349 int selosci, i; 1350 1351 struct stv0900_inode *temp_int = find_inode(state->i2c_adap, 1352 state->config->demod_address); 1353 1354 dprintk("%s\n", __func__); 1355 1356 if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) { 1357 state->internal = temp_int->internal; 1358 (state->internal->dmds_used)++; 1359 dprintk("%s: Find Internal Structure!\n", __func__); 1360 return STV0900_NO_ERROR; 1361 } else { 1362 state->internal = kmalloc(sizeof(struct stv0900_internal), 1363 GFP_KERNEL); 1364 if (state->internal == NULL) 1365 return STV0900_INVALID_HANDLE; 1366 temp_int = append_internal(state->internal); 1367 if (temp_int == NULL) { 1368 kfree(state->internal); 1369 state->internal = NULL; 1370 return STV0900_INVALID_HANDLE; 1371 } 1372 state->internal->dmds_used = 1; 1373 state->internal->i2c_adap = state->i2c_adap; 1374 state->internal->i2c_addr = state->config->demod_address; 1375 state->internal->clkmode = state->config->clkmode; 1376 state->internal->errs = STV0900_NO_ERROR; 1377 dprintk("%s: Create New Internal Structure!\n", __func__); 1378 } 1379 1380 if (state->internal == NULL) { 1381 error = STV0900_INVALID_HANDLE; 1382 return error; 1383 } 1384 1385 demodError = stv0900_initialize(state->internal); 1386 if (demodError == STV0900_NO_ERROR) { 1387 error = STV0900_NO_ERROR; 1388 } else { 1389 if (demodError == STV0900_INVALID_HANDLE) 1390 error = STV0900_INVALID_HANDLE; 1391 else 1392 error = STV0900_I2C_ERROR; 1393 1394 return error; 1395 } 1396 1397 intp = state->internal; 1398 1399 intp->demod_mode = p_init->demod_mode; 1400 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1); 1401 intp->chip_id = stv0900_read_reg(intp, R0900_MID); 1402 intp->rolloff = p_init->rolloff; 1403 intp->quartz = p_init->dmd_ref_clk; 1404 1405 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff); 1406 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff); 1407 1408 intp->ts_config = p_init->ts_config; 1409 if (intp->ts_config == NULL) 1410 stv0900_set_ts_parallel_serial(intp, 1411 p_init->path1_ts_clock, 1412 p_init->path2_ts_clock); 1413 else { 1414 for (i = 0; intp->ts_config[i].addr != 0xffff; i++) 1415 stv0900_write_reg(intp, 1416 intp->ts_config[i].addr, 1417 intp->ts_config[i].val); 1418 1419 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1); 1420 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0); 1421 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1); 1422 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0); 1423 } 1424 1425 intp->tuner_type[0] = p_init->tuner1_type; 1426 intp->tuner_type[1] = p_init->tuner2_type; 1427 /* tuner init */ 1428 switch (p_init->tuner1_type) { 1429 case 3: /*FE_AUTO_STB6100:*/ 1430 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c); 1431 stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86); 1432 stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18); 1433 stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */ 1434 stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05); 1435 stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17); 1436 stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f); 1437 stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0); 1438 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3); 1439 break; 1440 /* case FE_SW_TUNER: */ 1441 default: 1442 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6); 1443 break; 1444 } 1445 1446 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress); 1447 switch (p_init->tuner1_adc) { 1448 case 1: 1449 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26); 1450 break; 1451 default: 1452 break; 1453 } 1454 1455 stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */ 1456 1457 /* tuner init */ 1458 switch (p_init->tuner2_type) { 1459 case 3: /*FE_AUTO_STB6100:*/ 1460 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c); 1461 stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86); 1462 stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18); 1463 stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */ 1464 stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05); 1465 stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17); 1466 stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f); 1467 stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0); 1468 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3); 1469 break; 1470 /* case FE_SW_TUNER: */ 1471 default: 1472 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6); 1473 break; 1474 } 1475 1476 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress); 1477 switch (p_init->tuner2_adc) { 1478 case 1: 1479 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26); 1480 break; 1481 default: 1482 break; 1483 } 1484 1485 stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */ 1486 1487 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv); 1488 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv); 1489 stv0900_set_mclk(intp, 135000000); 1490 msleep(3); 1491 1492 switch (intp->clkmode) { 1493 case 0: 1494 case 2: 1495 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode); 1496 break; 1497 default: 1498 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL); 1499 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci); 1500 break; 1501 } 1502 msleep(3); 1503 1504 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz); 1505 if (intp->errs) 1506 error = STV0900_I2C_ERROR; 1507 1508 return error; 1509 } 1510 1511 static int stv0900_status(struct stv0900_internal *intp, 1512 enum fe_stv0900_demod_num demod) 1513 { 1514 enum fe_stv0900_search_state demod_state; 1515 int locked = FALSE; 1516 u8 tsbitrate0_val, tsbitrate1_val; 1517 s32 bitrate; 1518 1519 demod_state = stv0900_get_bits(intp, HEADER_MODE); 1520 switch (demod_state) { 1521 case STV0900_SEARCH: 1522 case STV0900_PLH_DETECTED: 1523 default: 1524 locked = FALSE; 1525 break; 1526 case STV0900_DVBS2_FOUND: 1527 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) && 1528 stv0900_get_bits(intp, PKTDELIN_LOCK) && 1529 stv0900_get_bits(intp, TSFIFO_LINEOK); 1530 break; 1531 case STV0900_DVBS_FOUND: 1532 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) && 1533 stv0900_get_bits(intp, LOCKEDVIT) && 1534 stv0900_get_bits(intp, TSFIFO_LINEOK); 1535 break; 1536 } 1537 1538 dprintk("%s: locked = %d\n", __func__, locked); 1539 1540 if (stvdebug) { 1541 /* Print TS bitrate */ 1542 tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0); 1543 tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1); 1544 /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */ 1545 bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000) 1546 * (tsbitrate1_val << 8 | tsbitrate0_val); 1547 bitrate /= 16384; 1548 dprintk("TS bitrate = %d Mbit/sec\n", bitrate); 1549 } 1550 1551 return locked; 1552 } 1553 1554 static int stv0900_set_mis(struct stv0900_internal *intp, 1555 enum fe_stv0900_demod_num demod, int mis) 1556 { 1557 dprintk("%s\n", __func__); 1558 1559 if (mis < 0 || mis > 255) { 1560 dprintk("Disable MIS filtering\n"); 1561 stv0900_write_bits(intp, FILTER_EN, 0); 1562 } else { 1563 dprintk("Enable MIS filtering - %d\n", mis); 1564 stv0900_write_bits(intp, FILTER_EN, 1); 1565 stv0900_write_reg(intp, ISIENTRY, mis); 1566 stv0900_write_reg(intp, ISIBITENA, 0xff); 1567 } 1568 1569 return STV0900_NO_ERROR; 1570 } 1571 1572 1573 static enum dvbfe_search stv0900_search(struct dvb_frontend *fe) 1574 { 1575 struct stv0900_state *state = fe->demodulator_priv; 1576 struct stv0900_internal *intp = state->internal; 1577 enum fe_stv0900_demod_num demod = state->demod; 1578 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1579 1580 struct stv0900_search_params p_search; 1581 struct stv0900_signal_info p_result = intp->result[demod]; 1582 1583 enum fe_stv0900_error error = STV0900_NO_ERROR; 1584 1585 dprintk("%s: ", __func__); 1586 1587 if (!(INRANGE(100000, c->symbol_rate, 70000000))) 1588 return DVBFE_ALGO_SEARCH_FAILED; 1589 1590 if (state->config->set_ts_params) 1591 state->config->set_ts_params(fe, 0); 1592 1593 stv0900_set_mis(intp, demod, c->stream_id); 1594 1595 p_result.locked = FALSE; 1596 p_search.path = demod; 1597 p_search.frequency = c->frequency; 1598 p_search.symbol_rate = c->symbol_rate; 1599 p_search.search_range = 10000000; 1600 p_search.fec = STV0900_FEC_UNKNOWN; 1601 p_search.standard = STV0900_AUTO_SEARCH; 1602 p_search.iq_inversion = STV0900_IQ_AUTO; 1603 p_search.search_algo = STV0900_BLIND_SEARCH; 1604 /* Speeds up DVB-S searching */ 1605 if (c->delivery_system == SYS_DVBS) 1606 p_search.standard = STV0900_SEARCH_DVBS1; 1607 1608 intp->srch_standard[demod] = p_search.standard; 1609 intp->symbol_rate[demod] = p_search.symbol_rate; 1610 intp->srch_range[demod] = p_search.search_range; 1611 intp->freq[demod] = p_search.frequency; 1612 intp->srch_algo[demod] = p_search.search_algo; 1613 intp->srch_iq_inv[demod] = p_search.iq_inversion; 1614 intp->fec[demod] = p_search.fec; 1615 if ((stv0900_algo(fe) == STV0900_RANGEOK) && 1616 (intp->errs == STV0900_NO_ERROR)) { 1617 p_result.locked = intp->result[demod].locked; 1618 p_result.standard = intp->result[demod].standard; 1619 p_result.frequency = intp->result[demod].frequency; 1620 p_result.symbol_rate = intp->result[demod].symbol_rate; 1621 p_result.fec = intp->result[demod].fec; 1622 p_result.modcode = intp->result[demod].modcode; 1623 p_result.pilot = intp->result[demod].pilot; 1624 p_result.frame_len = intp->result[demod].frame_len; 1625 p_result.spectrum = intp->result[demod].spectrum; 1626 p_result.rolloff = intp->result[demod].rolloff; 1627 p_result.modulation = intp->result[demod].modulation; 1628 } else { 1629 p_result.locked = FALSE; 1630 switch (intp->err[demod]) { 1631 case STV0900_I2C_ERROR: 1632 error = STV0900_I2C_ERROR; 1633 break; 1634 case STV0900_NO_ERROR: 1635 default: 1636 error = STV0900_SEARCH_FAILED; 1637 break; 1638 } 1639 } 1640 1641 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) { 1642 dprintk("Search Success\n"); 1643 return DVBFE_ALGO_SEARCH_SUCCESS; 1644 } else { 1645 dprintk("Search Fail\n"); 1646 return DVBFE_ALGO_SEARCH_FAILED; 1647 } 1648 1649 } 1650 1651 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status) 1652 { 1653 struct stv0900_state *state = fe->demodulator_priv; 1654 1655 dprintk("%s: ", __func__); 1656 1657 if ((stv0900_status(state->internal, state->demod)) == TRUE) { 1658 dprintk("DEMOD LOCK OK\n"); 1659 *status = FE_HAS_CARRIER 1660 | FE_HAS_VITERBI 1661 | FE_HAS_SYNC 1662 | FE_HAS_LOCK; 1663 if (state->config->set_lock_led) 1664 state->config->set_lock_led(fe, 1); 1665 } else { 1666 *status = 0; 1667 if (state->config->set_lock_led) 1668 state->config->set_lock_led(fe, 0); 1669 dprintk("DEMOD LOCK FAIL\n"); 1670 } 1671 1672 return 0; 1673 } 1674 1675 static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts) 1676 { 1677 1678 struct stv0900_state *state = fe->demodulator_priv; 1679 struct stv0900_internal *intp = state->internal; 1680 enum fe_stv0900_demod_num demod = state->demod; 1681 1682 if (stop_ts == TRUE) 1683 stv0900_write_bits(intp, RST_HWARE, 1); 1684 else 1685 stv0900_write_bits(intp, RST_HWARE, 0); 1686 1687 return 0; 1688 } 1689 1690 static int stv0900_diseqc_init(struct dvb_frontend *fe) 1691 { 1692 struct stv0900_state *state = fe->demodulator_priv; 1693 struct stv0900_internal *intp = state->internal; 1694 enum fe_stv0900_demod_num demod = state->demod; 1695 1696 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode); 1697 stv0900_write_bits(intp, DISEQC_RESET, 1); 1698 stv0900_write_bits(intp, DISEQC_RESET, 0); 1699 1700 return 0; 1701 } 1702 1703 static int stv0900_init(struct dvb_frontend *fe) 1704 { 1705 dprintk("%s\n", __func__); 1706 1707 stv0900_stop_ts(fe, 1); 1708 stv0900_diseqc_init(fe); 1709 1710 return 0; 1711 } 1712 1713 static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data, 1714 u32 NbData, enum fe_stv0900_demod_num demod) 1715 { 1716 s32 i = 0; 1717 1718 stv0900_write_bits(intp, DIS_PRECHARGE, 1); 1719 while (i < NbData) { 1720 while (stv0900_get_bits(intp, FIFO_FULL)) 1721 ;/* checkpatch complains */ 1722 stv0900_write_reg(intp, DISTXDATA, data[i]); 1723 i++; 1724 } 1725 1726 stv0900_write_bits(intp, DIS_PRECHARGE, 0); 1727 i = 0; 1728 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) { 1729 msleep(10); 1730 i++; 1731 } 1732 1733 return 0; 1734 } 1735 1736 static int stv0900_send_master_cmd(struct dvb_frontend *fe, 1737 struct dvb_diseqc_master_cmd *cmd) 1738 { 1739 struct stv0900_state *state = fe->demodulator_priv; 1740 1741 return stv0900_diseqc_send(state->internal, 1742 cmd->msg, 1743 cmd->msg_len, 1744 state->demod); 1745 } 1746 1747 static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) 1748 { 1749 struct stv0900_state *state = fe->demodulator_priv; 1750 struct stv0900_internal *intp = state->internal; 1751 enum fe_stv0900_demod_num demod = state->demod; 1752 u8 data; 1753 1754 1755 switch (burst) { 1756 case SEC_MINI_A: 1757 stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */ 1758 data = 0x00; 1759 stv0900_diseqc_send(intp, &data, 1, state->demod); 1760 break; 1761 case SEC_MINI_B: 1762 stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */ 1763 data = 0xff; 1764 stv0900_diseqc_send(intp, &data, 1, state->demod); 1765 break; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int stv0900_recv_slave_reply(struct dvb_frontend *fe, 1772 struct dvb_diseqc_slave_reply *reply) 1773 { 1774 struct stv0900_state *state = fe->demodulator_priv; 1775 struct stv0900_internal *intp = state->internal; 1776 enum fe_stv0900_demod_num demod = state->demod; 1777 s32 i = 0; 1778 1779 reply->msg_len = 0; 1780 1781 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) { 1782 msleep(10); 1783 i++; 1784 } 1785 1786 if (stv0900_get_bits(intp, RX_END)) { 1787 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR); 1788 1789 for (i = 0; i < reply->msg_len; i++) 1790 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA); 1791 } 1792 1793 return 0; 1794 } 1795 1796 static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff) 1797 { 1798 struct stv0900_state *state = fe->demodulator_priv; 1799 struct stv0900_internal *intp = state->internal; 1800 enum fe_stv0900_demod_num demod = state->demod; 1801 1802 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off")); 1803 1804 switch (toneoff) { 1805 case SEC_TONE_ON: 1806 /*Set the DiseqC mode to 22Khz _continues_ tone*/ 1807 stv0900_write_bits(intp, DISTX_MODE, 0); 1808 stv0900_write_bits(intp, DISEQC_RESET, 1); 1809 /*release DiseqC reset to enable the 22KHz tone*/ 1810 stv0900_write_bits(intp, DISEQC_RESET, 0); 1811 break; 1812 case SEC_TONE_OFF: 1813 /*return diseqc mode to config->diseqc_mode. 1814 Usually it's without _continues_ tone */ 1815 stv0900_write_bits(intp, DISTX_MODE, 1816 state->config->diseqc_mode); 1817 /*maintain the DiseqC reset to disable the 22KHz tone*/ 1818 stv0900_write_bits(intp, DISEQC_RESET, 1); 1819 stv0900_write_bits(intp, DISEQC_RESET, 0); 1820 break; 1821 default: 1822 return -EINVAL; 1823 } 1824 1825 return 0; 1826 } 1827 1828 static void stv0900_release(struct dvb_frontend *fe) 1829 { 1830 struct stv0900_state *state = fe->demodulator_priv; 1831 1832 dprintk("%s\n", __func__); 1833 1834 if (state->config->set_lock_led) 1835 state->config->set_lock_led(fe, 0); 1836 1837 if ((--(state->internal->dmds_used)) <= 0) { 1838 1839 dprintk("%s: Actually removing\n", __func__); 1840 1841 remove_inode(state->internal); 1842 kfree(state->internal); 1843 } 1844 1845 kfree(state); 1846 } 1847 1848 static int stv0900_sleep(struct dvb_frontend *fe) 1849 { 1850 struct stv0900_state *state = fe->demodulator_priv; 1851 1852 dprintk("%s\n", __func__); 1853 1854 if (state->config->set_lock_led) 1855 state->config->set_lock_led(fe, 0); 1856 1857 return 0; 1858 } 1859 1860 static int stv0900_get_frontend(struct dvb_frontend *fe) 1861 { 1862 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1863 struct stv0900_state *state = fe->demodulator_priv; 1864 struct stv0900_internal *intp = state->internal; 1865 enum fe_stv0900_demod_num demod = state->demod; 1866 struct stv0900_signal_info p_result = intp->result[demod]; 1867 1868 p->frequency = p_result.locked ? p_result.frequency : 0; 1869 p->symbol_rate = p_result.locked ? p_result.symbol_rate : 0; 1870 return 0; 1871 } 1872 1873 static struct dvb_frontend_ops stv0900_ops = { 1874 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, 1875 .info = { 1876 .name = "STV0900 frontend", 1877 .frequency_min = 950000, 1878 .frequency_max = 2150000, 1879 .frequency_stepsize = 125, 1880 .frequency_tolerance = 0, 1881 .symbol_rate_min = 1000000, 1882 .symbol_rate_max = 45000000, 1883 .symbol_rate_tolerance = 500, 1884 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 1885 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | 1886 FE_CAN_FEC_7_8 | FE_CAN_QPSK | 1887 FE_CAN_2G_MODULATION | 1888 FE_CAN_FEC_AUTO 1889 }, 1890 .release = stv0900_release, 1891 .init = stv0900_init, 1892 .get_frontend = stv0900_get_frontend, 1893 .sleep = stv0900_sleep, 1894 .get_frontend_algo = stv0900_frontend_algo, 1895 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl, 1896 .diseqc_send_master_cmd = stv0900_send_master_cmd, 1897 .diseqc_send_burst = stv0900_send_burst, 1898 .diseqc_recv_slave_reply = stv0900_recv_slave_reply, 1899 .set_tone = stv0900_set_tone, 1900 .search = stv0900_search, 1901 .read_status = stv0900_read_status, 1902 .read_ber = stv0900_read_ber, 1903 .read_signal_strength = stv0900_read_signal_strength, 1904 .read_snr = stv0900_read_snr, 1905 .read_ucblocks = stv0900_read_ucblocks, 1906 }; 1907 1908 struct dvb_frontend *stv0900_attach(const struct stv0900_config *config, 1909 struct i2c_adapter *i2c, 1910 int demod) 1911 { 1912 struct stv0900_state *state = NULL; 1913 struct stv0900_init_params init_params; 1914 enum fe_stv0900_error err_stv0900; 1915 1916 state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL); 1917 if (state == NULL) 1918 goto error; 1919 1920 state->demod = demod; 1921 state->config = config; 1922 state->i2c_adap = i2c; 1923 1924 memcpy(&state->frontend.ops, &stv0900_ops, 1925 sizeof(struct dvb_frontend_ops)); 1926 state->frontend.demodulator_priv = state; 1927 1928 switch (demod) { 1929 case 0: 1930 case 1: 1931 init_params.dmd_ref_clk = config->xtal; 1932 init_params.demod_mode = config->demod_mode; 1933 init_params.rolloff = STV0900_35; 1934 init_params.path1_ts_clock = config->path1_mode; 1935 init_params.tun1_maddress = config->tun1_maddress; 1936 init_params.tun1_iq_inv = STV0900_IQ_NORMAL; 1937 init_params.tuner1_adc = config->tun1_adc; 1938 init_params.tuner1_type = config->tun1_type; 1939 init_params.path2_ts_clock = config->path2_mode; 1940 init_params.ts_config = config->ts_config_regs; 1941 init_params.tun2_maddress = config->tun2_maddress; 1942 init_params.tuner2_adc = config->tun2_adc; 1943 init_params.tuner2_type = config->tun2_type; 1944 init_params.tun2_iq_inv = STV0900_IQ_SWAPPED; 1945 1946 err_stv0900 = stv0900_init_internal(&state->frontend, 1947 &init_params); 1948 1949 if (err_stv0900) 1950 goto error; 1951 1952 if (state->internal->chip_id >= 0x30) 1953 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM; 1954 1955 break; 1956 default: 1957 goto error; 1958 break; 1959 } 1960 1961 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod); 1962 return &state->frontend; 1963 1964 error: 1965 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n", 1966 __func__, demod); 1967 kfree(state); 1968 return NULL; 1969 } 1970 EXPORT_SYMBOL(stv0900_attach); 1971 1972 MODULE_PARM_DESC(debug, "Set debug"); 1973 1974 MODULE_AUTHOR("Igor M. Liplianin"); 1975 MODULE_DESCRIPTION("ST STV0900 frontend"); 1976 MODULE_LICENSE("GPL"); 1977