1 /*
2  * Driver for
3  *    Samsung S5H1420 and
4  *    PnpNetwork PN1010 QPSK Demodulator
5  *
6  * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
7  * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *
18  * GNU General Public License for more details.
19  */
20 
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/string.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/jiffies.h>
28 #include <asm/div64.h>
29 
30 #include <linux/i2c.h>
31 
32 
33 #include <media/dvb_frontend.h>
34 #include "s5h1420.h"
35 #include "s5h1420_priv.h"
36 
37 #define TONE_FREQ 22000
38 
39 struct s5h1420_state {
40 	struct i2c_adapter* i2c;
41 	const struct s5h1420_config* config;
42 
43 	struct dvb_frontend frontend;
44 	struct i2c_adapter tuner_i2c_adapter;
45 
46 	u8 CON_1_val;
47 
48 	u8 postlocked:1;
49 	u32 fclk;
50 	u32 tunedfreq;
51 	enum fe_code_rate fec_inner;
52 	u32 symbol_rate;
53 
54 	/* FIXME: ugly workaround for flexcop's incapable i2c-controller
55 	 * it does not support repeated-start, workaround: write addr-1
56 	 * and then read
57 	 */
58 	u8 shadow[256];
59 };
60 
61 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
62 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
63 				     struct dvb_frontend_tune_settings* fesettings);
64 
65 
66 static int debug;
67 module_param(debug, int, 0644);
68 MODULE_PARM_DESC(debug, "enable debugging");
69 
70 #define dprintk(x...) do { \
71 	if (debug) \
72 		printk(KERN_DEBUG "S5H1420: " x); \
73 } while (0)
74 
75 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
76 {
77 	int ret;
78 	u8 b[2];
79 	struct i2c_msg msg[] = {
80 		{ .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
81 		{ .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
82 		{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
83 	};
84 
85 	b[0] = (reg - 1) & 0xff;
86 	b[1] = state->shadow[(reg - 1) & 0xff];
87 
88 	if (state->config->repeated_start_workaround) {
89 		ret = i2c_transfer(state->i2c, msg, 3);
90 		if (ret != 3)
91 			return ret;
92 	} else {
93 		ret = i2c_transfer(state->i2c, &msg[1], 1);
94 		if (ret != 1)
95 			return ret;
96 		ret = i2c_transfer(state->i2c, &msg[2], 1);
97 		if (ret != 1)
98 			return ret;
99 	}
100 
101 	/* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
102 
103 	return b[0];
104 }
105 
106 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
107 {
108 	u8 buf[] = { reg, data };
109 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
110 	int err;
111 
112 	/* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
113 	err = i2c_transfer(state->i2c, &msg, 1);
114 	if (err != 1) {
115 		dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
116 		return -EREMOTEIO;
117 	}
118 	state->shadow[reg] = data;
119 
120 	return 0;
121 }
122 
123 static int s5h1420_set_voltage(struct dvb_frontend *fe,
124 			       enum fe_sec_voltage voltage)
125 {
126 	struct s5h1420_state* state = fe->demodulator_priv;
127 
128 	dprintk("enter %s\n", __func__);
129 
130 	switch(voltage) {
131 	case SEC_VOLTAGE_13:
132 		s5h1420_writereg(state, 0x3c,
133 				 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
134 		break;
135 
136 	case SEC_VOLTAGE_18:
137 		s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
138 		break;
139 
140 	case SEC_VOLTAGE_OFF:
141 		s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
142 		break;
143 	}
144 
145 	dprintk("leave %s\n", __func__);
146 	return 0;
147 }
148 
149 static int s5h1420_set_tone(struct dvb_frontend *fe,
150 			    enum fe_sec_tone_mode tone)
151 {
152 	struct s5h1420_state* state = fe->demodulator_priv;
153 
154 	dprintk("enter %s\n", __func__);
155 	switch(tone) {
156 	case SEC_TONE_ON:
157 		s5h1420_writereg(state, 0x3b,
158 				 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
159 		break;
160 
161 	case SEC_TONE_OFF:
162 		s5h1420_writereg(state, 0x3b,
163 				 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
164 		break;
165 	}
166 	dprintk("leave %s\n", __func__);
167 
168 	return 0;
169 }
170 
171 static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
172 				    struct dvb_diseqc_master_cmd* cmd)
173 {
174 	struct s5h1420_state* state = fe->demodulator_priv;
175 	u8 val;
176 	int i;
177 	unsigned long timeout;
178 	int result = 0;
179 
180 	dprintk("enter %s\n", __func__);
181 	if (cmd->msg_len > sizeof(cmd->msg))
182 		return -EINVAL;
183 
184 	/* setup for DISEQC */
185 	val = s5h1420_readreg(state, 0x3b);
186 	s5h1420_writereg(state, 0x3b, 0x02);
187 	msleep(15);
188 
189 	/* write the DISEQC command bytes */
190 	for(i=0; i< cmd->msg_len; i++) {
191 		s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
192 	}
193 
194 	/* kick off transmission */
195 	s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
196 				      ((cmd->msg_len-1) << 4) | 0x08);
197 
198 	/* wait for transmission to complete */
199 	timeout = jiffies + ((100*HZ) / 1000);
200 	while(time_before(jiffies, timeout)) {
201 		if (!(s5h1420_readreg(state, 0x3b) & 0x08))
202 			break;
203 
204 		msleep(5);
205 	}
206 	if (time_after(jiffies, timeout))
207 		result = -ETIMEDOUT;
208 
209 	/* restore original settings */
210 	s5h1420_writereg(state, 0x3b, val);
211 	msleep(15);
212 	dprintk("leave %s\n", __func__);
213 	return result;
214 }
215 
216 static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
217 				     struct dvb_diseqc_slave_reply* reply)
218 {
219 	struct s5h1420_state* state = fe->demodulator_priv;
220 	u8 val;
221 	int i;
222 	int length;
223 	unsigned long timeout;
224 	int result = 0;
225 
226 	/* setup for DISEQC receive */
227 	val = s5h1420_readreg(state, 0x3b);
228 	s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
229 	msleep(15);
230 
231 	/* wait for reception to complete */
232 	timeout = jiffies + ((reply->timeout*HZ) / 1000);
233 	while(time_before(jiffies, timeout)) {
234 		if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
235 			break;
236 
237 		msleep(5);
238 	}
239 	if (time_after(jiffies, timeout)) {
240 		result = -ETIMEDOUT;
241 		goto exit;
242 	}
243 
244 	/* check error flag - FIXME: not sure what this does - docs do not describe
245 	 * beyond "error flag for diseqc receive data :( */
246 	if (s5h1420_readreg(state, 0x49)) {
247 		result = -EIO;
248 		goto exit;
249 	}
250 
251 	/* check length */
252 	length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
253 	if (length > sizeof(reply->msg)) {
254 		result = -EOVERFLOW;
255 		goto exit;
256 	}
257 	reply->msg_len = length;
258 
259 	/* extract data */
260 	for(i=0; i< length; i++) {
261 		reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
262 	}
263 
264 exit:
265 	/* restore original settings */
266 	s5h1420_writereg(state, 0x3b, val);
267 	msleep(15);
268 	return result;
269 }
270 
271 static int s5h1420_send_burst(struct dvb_frontend *fe,
272 			      enum fe_sec_mini_cmd minicmd)
273 {
274 	struct s5h1420_state* state = fe->demodulator_priv;
275 	u8 val;
276 	int result = 0;
277 	unsigned long timeout;
278 
279 	/* setup for tone burst */
280 	val = s5h1420_readreg(state, 0x3b);
281 	s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
282 
283 	/* set value for B position if requested */
284 	if (minicmd == SEC_MINI_B) {
285 		s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
286 	}
287 	msleep(15);
288 
289 	/* start transmission */
290 	s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
291 
292 	/* wait for transmission to complete */
293 	timeout = jiffies + ((100*HZ) / 1000);
294 	while(time_before(jiffies, timeout)) {
295 		if (!(s5h1420_readreg(state, 0x3b) & 0x08))
296 			break;
297 
298 		msleep(5);
299 	}
300 	if (time_after(jiffies, timeout))
301 		result = -ETIMEDOUT;
302 
303 	/* restore original settings */
304 	s5h1420_writereg(state, 0x3b, val);
305 	msleep(15);
306 	return result;
307 }
308 
309 static enum fe_status s5h1420_get_status_bits(struct s5h1420_state *state)
310 {
311 	u8 val;
312 	enum fe_status status = 0;
313 
314 	val = s5h1420_readreg(state, 0x14);
315 	if (val & 0x02)
316 		status |=  FE_HAS_SIGNAL;
317 	if (val & 0x01)
318 		status |=  FE_HAS_CARRIER;
319 	val = s5h1420_readreg(state, 0x36);
320 	if (val & 0x01)
321 		status |=  FE_HAS_VITERBI;
322 	if (val & 0x20)
323 		status |=  FE_HAS_SYNC;
324 	if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
325 		status |=  FE_HAS_LOCK;
326 
327 	return status;
328 }
329 
330 static int s5h1420_read_status(struct dvb_frontend *fe,
331 			       enum fe_status *status)
332 {
333 	struct s5h1420_state* state = fe->demodulator_priv;
334 	u8 val;
335 
336 	dprintk("enter %s\n", __func__);
337 
338 	if (status == NULL)
339 		return -EINVAL;
340 
341 	/* determine lock state */
342 	*status = s5h1420_get_status_bits(state);
343 
344 	/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
345 	the inversion, wait a bit and check again */
346 	if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
347 		val = s5h1420_readreg(state, Vit10);
348 		if ((val & 0x07) == 0x03) {
349 			if (val & 0x08)
350 				s5h1420_writereg(state, Vit09, 0x13);
351 			else
352 				s5h1420_writereg(state, Vit09, 0x1b);
353 
354 			/* wait a bit then update lock status */
355 			mdelay(200);
356 			*status = s5h1420_get_status_bits(state);
357 		}
358 	}
359 
360 	/* perform post lock setup */
361 	if ((*status & FE_HAS_LOCK) && !state->postlocked) {
362 
363 		/* calculate the data rate */
364 		u32 tmp = s5h1420_getsymbolrate(state);
365 		switch (s5h1420_readreg(state, Vit10) & 0x07) {
366 		case 0: tmp = (tmp * 2 * 1) / 2; break;
367 		case 1: tmp = (tmp * 2 * 2) / 3; break;
368 		case 2: tmp = (tmp * 2 * 3) / 4; break;
369 		case 3: tmp = (tmp * 2 * 5) / 6; break;
370 		case 4: tmp = (tmp * 2 * 6) / 7; break;
371 		case 5: tmp = (tmp * 2 * 7) / 8; break;
372 		}
373 
374 		if (tmp == 0) {
375 			printk(KERN_ERR "s5h1420: avoided division by 0\n");
376 			tmp = 1;
377 		}
378 		tmp = state->fclk / tmp;
379 
380 
381 		/* set the MPEG_CLK_INTL for the calculated data rate */
382 		if (tmp < 2)
383 			val = 0x00;
384 		else if (tmp < 5)
385 			val = 0x01;
386 		else if (tmp < 9)
387 			val = 0x02;
388 		else if (tmp < 13)
389 			val = 0x03;
390 		else if (tmp < 17)
391 			val = 0x04;
392 		else if (tmp < 25)
393 			val = 0x05;
394 		else if (tmp < 33)
395 			val = 0x06;
396 		else
397 			val = 0x07;
398 		dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
399 
400 		s5h1420_writereg(state, FEC01, 0x18);
401 		s5h1420_writereg(state, FEC01, 0x10);
402 		s5h1420_writereg(state, FEC01, val);
403 
404 		/* Enable "MPEG_Out" */
405 		val = s5h1420_readreg(state, Mpeg02);
406 		s5h1420_writereg(state, Mpeg02, val | (1 << 6));
407 
408 		/* kicker disable */
409 		val = s5h1420_readreg(state, QPSK01) & 0x7f;
410 		s5h1420_writereg(state, QPSK01, val);
411 
412 		/* DC freeze TODO it was never activated by default or it can stay activated */
413 
414 		if (s5h1420_getsymbolrate(state) >= 20000000) {
415 			s5h1420_writereg(state, Loop04, 0x8a);
416 			s5h1420_writereg(state, Loop05, 0x6a);
417 		} else {
418 			s5h1420_writereg(state, Loop04, 0x58);
419 			s5h1420_writereg(state, Loop05, 0x27);
420 		}
421 
422 		/* post-lock processing has been done! */
423 		state->postlocked = 1;
424 	}
425 
426 	dprintk("leave %s\n", __func__);
427 
428 	return 0;
429 }
430 
431 static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
432 {
433 	struct s5h1420_state* state = fe->demodulator_priv;
434 
435 	s5h1420_writereg(state, 0x46, 0x1d);
436 	mdelay(25);
437 
438 	*ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
439 
440 	return 0;
441 }
442 
443 static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
444 {
445 	struct s5h1420_state* state = fe->demodulator_priv;
446 
447 	u8 val = s5h1420_readreg(state, 0x15);
448 
449 	*strength =  (u16) ((val << 8) | val);
450 
451 	return 0;
452 }
453 
454 static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
455 {
456 	struct s5h1420_state* state = fe->demodulator_priv;
457 
458 	s5h1420_writereg(state, 0x46, 0x1f);
459 	mdelay(25);
460 
461 	*ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
462 
463 	return 0;
464 }
465 
466 static void s5h1420_reset(struct s5h1420_state* state)
467 {
468 	dprintk("%s\n", __func__);
469 	s5h1420_writereg (state, 0x01, 0x08);
470 	s5h1420_writereg (state, 0x01, 0x00);
471 	udelay(10);
472 }
473 
474 static void s5h1420_setsymbolrate(struct s5h1420_state* state,
475 				  struct dtv_frontend_properties *p)
476 {
477 	u8 v;
478 	u64 val;
479 
480 	dprintk("enter %s\n", __func__);
481 
482 	val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24);
483 	if (p->symbol_rate < 29000000)
484 		val *= 2;
485 	do_div(val, (state->fclk / 1000));
486 
487 	dprintk("symbol rate register: %06llx\n", (unsigned long long)val);
488 
489 	v = s5h1420_readreg(state, Loop01);
490 	s5h1420_writereg(state, Loop01, v & 0x7f);
491 	s5h1420_writereg(state, Tnco01, val >> 16);
492 	s5h1420_writereg(state, Tnco02, val >> 8);
493 	s5h1420_writereg(state, Tnco03, val & 0xff);
494 	s5h1420_writereg(state, Loop01,  v | 0x80);
495 	dprintk("leave %s\n", __func__);
496 }
497 
498 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
499 {
500 	return state->symbol_rate;
501 }
502 
503 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
504 {
505 	int val;
506 	u8 v;
507 
508 	dprintk("enter %s\n", __func__);
509 
510 	/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
511 	 * divide fclk by 1000000 to get the correct value. */
512 	val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
513 
514 	dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
515 
516 	v = s5h1420_readreg(state, Loop01);
517 	s5h1420_writereg(state, Loop01, v & 0xbf);
518 	s5h1420_writereg(state, Pnco01, val >> 16);
519 	s5h1420_writereg(state, Pnco02, val >> 8);
520 	s5h1420_writereg(state, Pnco03, val & 0xff);
521 	s5h1420_writereg(state, Loop01, v | 0x40);
522 	dprintk("leave %s\n", __func__);
523 }
524 
525 static int s5h1420_getfreqoffset(struct s5h1420_state* state)
526 {
527 	int val;
528 
529 	s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
530 	val  = s5h1420_readreg(state, 0x0e) << 16;
531 	val |= s5h1420_readreg(state, 0x0f) << 8;
532 	val |= s5h1420_readreg(state, 0x10);
533 	s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
534 
535 	if (val & 0x800000)
536 		val |= 0xff000000;
537 
538 	/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
539 	 * divide fclk by 1000000 to get the correct value. */
540 	val = (((-val) * (state->fclk/1000000)) / (1<<24));
541 
542 	return val;
543 }
544 
545 static void s5h1420_setfec_inversion(struct s5h1420_state* state,
546 				     struct dtv_frontend_properties *p)
547 {
548 	u8 inversion = 0;
549 	u8 vit08, vit09;
550 
551 	dprintk("enter %s\n", __func__);
552 
553 	if (p->inversion == INVERSION_OFF)
554 		inversion = state->config->invert ? 0x08 : 0;
555 	else if (p->inversion == INVERSION_ON)
556 		inversion = state->config->invert ? 0 : 0x08;
557 
558 	if ((p->fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
559 		vit08 = 0x3f;
560 		vit09 = 0;
561 	} else {
562 		switch (p->fec_inner) {
563 		case FEC_1_2:
564 			vit08 = 0x01;
565 			vit09 = 0x10;
566 			break;
567 
568 		case FEC_2_3:
569 			vit08 = 0x02;
570 			vit09 = 0x11;
571 			break;
572 
573 		case FEC_3_4:
574 			vit08 = 0x04;
575 			vit09 = 0x12;
576 			break;
577 
578 		case FEC_5_6:
579 			vit08 = 0x08;
580 			vit09 = 0x13;
581 			break;
582 
583 		case FEC_6_7:
584 			vit08 = 0x10;
585 			vit09 = 0x14;
586 			break;
587 
588 		case FEC_7_8:
589 			vit08 = 0x20;
590 			vit09 = 0x15;
591 			break;
592 
593 		default:
594 			return;
595 		}
596 	}
597 	vit09 |= inversion;
598 	dprintk("fec: %02x %02x\n", vit08, vit09);
599 	s5h1420_writereg(state, Vit08, vit08);
600 	s5h1420_writereg(state, Vit09, vit09);
601 	dprintk("leave %s\n", __func__);
602 }
603 
604 static enum fe_code_rate s5h1420_getfec(struct s5h1420_state *state)
605 {
606 	switch(s5h1420_readreg(state, 0x32) & 0x07) {
607 	case 0:
608 		return FEC_1_2;
609 
610 	case 1:
611 		return FEC_2_3;
612 
613 	case 2:
614 		return FEC_3_4;
615 
616 	case 3:
617 		return FEC_5_6;
618 
619 	case 4:
620 		return FEC_6_7;
621 
622 	case 5:
623 		return FEC_7_8;
624 	}
625 
626 	return FEC_NONE;
627 }
628 
629 static enum fe_spectral_inversion
630 s5h1420_getinversion(struct s5h1420_state *state)
631 {
632 	if (s5h1420_readreg(state, 0x32) & 0x08)
633 		return INVERSION_ON;
634 
635 	return INVERSION_OFF;
636 }
637 
638 static int s5h1420_set_frontend(struct dvb_frontend *fe)
639 {
640 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
641 	struct s5h1420_state* state = fe->demodulator_priv;
642 	int frequency_delta;
643 	struct dvb_frontend_tune_settings fesettings;
644 
645 	dprintk("enter %s\n", __func__);
646 
647 	/* check if we should do a fast-tune */
648 	s5h1420_get_tune_settings(fe, &fesettings);
649 	frequency_delta = p->frequency - state->tunedfreq;
650 	if ((frequency_delta > -fesettings.max_drift) &&
651 			(frequency_delta < fesettings.max_drift) &&
652 			(frequency_delta != 0) &&
653 			(state->fec_inner == p->fec_inner) &&
654 			(state->symbol_rate == p->symbol_rate)) {
655 
656 		if (fe->ops.tuner_ops.set_params) {
657 			fe->ops.tuner_ops.set_params(fe);
658 			if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
659 		}
660 		if (fe->ops.tuner_ops.get_frequency) {
661 			u32 tmp;
662 			fe->ops.tuner_ops.get_frequency(fe, &tmp);
663 			if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
664 			s5h1420_setfreqoffset(state, p->frequency - tmp);
665 		} else {
666 			s5h1420_setfreqoffset(state, 0);
667 		}
668 		dprintk("simple tune\n");
669 		return 0;
670 	}
671 	dprintk("tuning demod\n");
672 
673 	/* first of all, software reset */
674 	s5h1420_reset(state);
675 
676 	/* set s5h1420 fclk PLL according to desired symbol rate */
677 	if (p->symbol_rate > 33000000)
678 		state->fclk = 80000000;
679 	else if (p->symbol_rate > 28500000)
680 		state->fclk = 59000000;
681 	else if (p->symbol_rate > 25000000)
682 		state->fclk = 86000000;
683 	else if (p->symbol_rate > 1900000)
684 		state->fclk = 88000000;
685 	else
686 		state->fclk = 44000000;
687 
688 	dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
689 	s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
690 	s5h1420_writereg(state, PLL02, 0x40);
691 	s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
692 
693 	/* TODO DC offset removal, config parameter ? */
694 	if (p->symbol_rate > 29000000)
695 		s5h1420_writereg(state, QPSK01, 0xae | 0x10);
696 	else
697 		s5h1420_writereg(state, QPSK01, 0xac | 0x10);
698 
699 	/* set misc registers */
700 	s5h1420_writereg(state, CON_1, 0x00);
701 	s5h1420_writereg(state, QPSK02, 0x00);
702 	s5h1420_writereg(state, Pre01, 0xb0);
703 
704 	s5h1420_writereg(state, Loop01, 0xF0);
705 	s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
706 	s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
707 	if (p->symbol_rate > 20000000)
708 		s5h1420_writereg(state, Loop04, 0x79);
709 	else
710 		s5h1420_writereg(state, Loop04, 0x58);
711 	s5h1420_writereg(state, Loop05, 0x6b);
712 
713 	if (p->symbol_rate >= 8000000)
714 		s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
715 	else if (p->symbol_rate >= 4000000)
716 		s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
717 	else
718 		s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
719 
720 	s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
721 
722 	s5h1420_writereg(state, Sync01, 0x33);
723 	s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
724 	s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
725 	s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
726 
727 	s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
728 	s5h1420_writereg(state, DiS03, 0x00);
729 	s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
730 
731 	/* set tuner PLL */
732 	if (fe->ops.tuner_ops.set_params) {
733 		fe->ops.tuner_ops.set_params(fe);
734 		if (fe->ops.i2c_gate_ctrl)
735 			fe->ops.i2c_gate_ctrl(fe, 0);
736 		s5h1420_setfreqoffset(state, 0);
737 	}
738 
739 	/* set the reset of the parameters */
740 	s5h1420_setsymbolrate(state, p);
741 	s5h1420_setfec_inversion(state, p);
742 
743 	/* start QPSK */
744 	s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
745 
746 	state->fec_inner = p->fec_inner;
747 	state->symbol_rate = p->symbol_rate;
748 	state->postlocked = 0;
749 	state->tunedfreq = p->frequency;
750 
751 	dprintk("leave %s\n", __func__);
752 	return 0;
753 }
754 
755 static int s5h1420_get_frontend(struct dvb_frontend* fe,
756 				struct dtv_frontend_properties *p)
757 {
758 	struct s5h1420_state* state = fe->demodulator_priv;
759 
760 	p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
761 	p->inversion = s5h1420_getinversion(state);
762 	p->symbol_rate = s5h1420_getsymbolrate(state);
763 	p->fec_inner = s5h1420_getfec(state);
764 
765 	return 0;
766 }
767 
768 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
769 				     struct dvb_frontend_tune_settings* fesettings)
770 {
771 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
772 	if (p->symbol_rate > 20000000) {
773 		fesettings->min_delay_ms = 50;
774 		fesettings->step_size = 2000;
775 		fesettings->max_drift = 8000;
776 	} else if (p->symbol_rate > 12000000) {
777 		fesettings->min_delay_ms = 100;
778 		fesettings->step_size = 1500;
779 		fesettings->max_drift = 9000;
780 	} else if (p->symbol_rate > 8000000) {
781 		fesettings->min_delay_ms = 100;
782 		fesettings->step_size = 1000;
783 		fesettings->max_drift = 8000;
784 	} else if (p->symbol_rate > 4000000) {
785 		fesettings->min_delay_ms = 100;
786 		fesettings->step_size = 500;
787 		fesettings->max_drift = 7000;
788 	} else if (p->symbol_rate > 2000000) {
789 		fesettings->min_delay_ms = 200;
790 		fesettings->step_size = (p->symbol_rate / 8000);
791 		fesettings->max_drift = 14 * fesettings->step_size;
792 	} else {
793 		fesettings->min_delay_ms = 200;
794 		fesettings->step_size = (p->symbol_rate / 8000);
795 		fesettings->max_drift = 18 * fesettings->step_size;
796 	}
797 
798 	return 0;
799 }
800 
801 static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
802 {
803 	struct s5h1420_state* state = fe->demodulator_priv;
804 
805 	if (enable)
806 		return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
807 	else
808 		return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
809 }
810 
811 static int s5h1420_init (struct dvb_frontend* fe)
812 {
813 	struct s5h1420_state* state = fe->demodulator_priv;
814 
815 	/* disable power down and do reset */
816 	state->CON_1_val = state->config->serial_mpeg << 4;
817 	s5h1420_writereg(state, 0x02, state->CON_1_val);
818 	msleep(10);
819 	s5h1420_reset(state);
820 
821 	return 0;
822 }
823 
824 static int s5h1420_sleep(struct dvb_frontend* fe)
825 {
826 	struct s5h1420_state* state = fe->demodulator_priv;
827 	state->CON_1_val = 0x12;
828 	return s5h1420_writereg(state, 0x02, state->CON_1_val);
829 }
830 
831 static void s5h1420_release(struct dvb_frontend* fe)
832 {
833 	struct s5h1420_state* state = fe->demodulator_priv;
834 	i2c_del_adapter(&state->tuner_i2c_adapter);
835 	kfree(state);
836 }
837 
838 static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
839 {
840 	return I2C_FUNC_I2C;
841 }
842 
843 static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
844 {
845 	struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
846 	struct i2c_msg m[3];
847 	u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
848 
849 	if (1 + num > ARRAY_SIZE(m)) {
850 		printk(KERN_WARNING
851 		       "%s: i2c xfer: num=%d is too big!\n",
852 		       KBUILD_MODNAME, num);
853 		return  -EOPNOTSUPP;
854 	}
855 
856 	memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
857 
858 	m[0].addr = state->config->demod_address;
859 	m[0].buf  = tx_open;
860 	m[0].len  = 2;
861 
862 	memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
863 
864 	return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO;
865 }
866 
867 static const struct i2c_algorithm s5h1420_tuner_i2c_algo = {
868 	.master_xfer   = s5h1420_tuner_i2c_tuner_xfer,
869 	.functionality = s5h1420_tuner_i2c_func,
870 };
871 
872 struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
873 {
874 	struct s5h1420_state *state = fe->demodulator_priv;
875 	return &state->tuner_i2c_adapter;
876 }
877 EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
878 
879 static const struct dvb_frontend_ops s5h1420_ops;
880 
881 struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
882 				    struct i2c_adapter *i2c)
883 {
884 	/* allocate memory for the internal state */
885 	struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
886 	u8 i;
887 
888 	if (state == NULL)
889 		goto error;
890 
891 	/* setup the state */
892 	state->config = config;
893 	state->i2c = i2c;
894 	state->postlocked = 0;
895 	state->fclk = 88000000;
896 	state->tunedfreq = 0;
897 	state->fec_inner = FEC_NONE;
898 	state->symbol_rate = 0;
899 
900 	/* check if the demod is there + identify it */
901 	i = s5h1420_readreg(state, ID01);
902 	if (i != 0x03)
903 		goto error;
904 
905 	memset(state->shadow, 0xff, sizeof(state->shadow));
906 
907 	for (i = 0; i < 0x50; i++)
908 		state->shadow[i] = s5h1420_readreg(state, i);
909 
910 	/* create dvb_frontend */
911 	memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
912 	state->frontend.demodulator_priv = state;
913 
914 	/* create tuner i2c adapter */
915 	strlcpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
916 		sizeof(state->tuner_i2c_adapter.name));
917 	state->tuner_i2c_adapter.algo      = &s5h1420_tuner_i2c_algo;
918 	state->tuner_i2c_adapter.algo_data = NULL;
919 	i2c_set_adapdata(&state->tuner_i2c_adapter, state);
920 	if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
921 		printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
922 		goto error;
923 	}
924 
925 	return &state->frontend;
926 
927 error:
928 	kfree(state);
929 	return NULL;
930 }
931 EXPORT_SYMBOL(s5h1420_attach);
932 
933 static const struct dvb_frontend_ops s5h1420_ops = {
934 	.delsys = { SYS_DVBS },
935 	.info = {
936 		.name     = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
937 		.frequency_min_hz    =  950 * MHz,
938 		.frequency_max_hz    = 2150 * MHz,
939 		.frequency_stepsize_hz = 125 * kHz,
940 		.frequency_tolerance_hz  = 29500 * kHz,
941 		.symbol_rate_min  = 1000000,
942 		.symbol_rate_max  = 45000000,
943 		/*  .symbol_rate_tolerance  = ???,*/
944 		.caps = FE_CAN_INVERSION_AUTO |
945 		FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
946 		FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
947 		FE_CAN_QPSK
948 	},
949 
950 	.release = s5h1420_release,
951 
952 	.init = s5h1420_init,
953 	.sleep = s5h1420_sleep,
954 	.i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,
955 
956 	.set_frontend = s5h1420_set_frontend,
957 	.get_frontend = s5h1420_get_frontend,
958 	.get_tune_settings = s5h1420_get_tune_settings,
959 
960 	.read_status = s5h1420_read_status,
961 	.read_ber = s5h1420_read_ber,
962 	.read_signal_strength = s5h1420_read_signal_strength,
963 	.read_ucblocks = s5h1420_read_ucblocks,
964 
965 	.diseqc_send_master_cmd = s5h1420_send_master_cmd,
966 	.diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
967 	.diseqc_send_burst = s5h1420_send_burst,
968 	.set_tone = s5h1420_set_tone,
969 	.set_voltage = s5h1420_set_voltage,
970 };
971 
972 MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
973 MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
974 MODULE_LICENSE("GPL");
975