1 /* 2 Samsung S5H1411 VSB/QAM demodulator driver 3 4 Copyright (C) 2008 Steven Toth <stoth@linuxtv.org> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/module.h> 25 #include <linux/string.h> 26 #include <linux/slab.h> 27 #include <linux/delay.h> 28 #include <media/dvb_frontend.h> 29 #include "s5h1411.h" 30 31 struct s5h1411_state { 32 33 struct i2c_adapter *i2c; 34 35 /* configuration settings */ 36 const struct s5h1411_config *config; 37 38 struct dvb_frontend frontend; 39 40 enum fe_modulation current_modulation; 41 unsigned int first_tune:1; 42 43 u32 current_frequency; 44 int if_freq; 45 46 u8 inversion; 47 }; 48 49 static int debug; 50 51 #define dprintk(arg...) do { \ 52 if (debug) \ 53 printk(arg); \ 54 } while (0) 55 56 /* Register values to initialise the demod, defaults to VSB */ 57 static struct init_tab { 58 u8 addr; 59 u8 reg; 60 u16 data; 61 } init_tab[] = { 62 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, }, 63 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, }, 64 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, }, 65 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, }, 66 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, }, 67 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, }, 68 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, }, 69 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, }, 70 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, }, 71 { S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, }, 72 { S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, }, 73 { S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, }, 74 { S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, }, 75 { S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, }, 76 { S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, }, 77 { S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, }, 78 { S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, }, 79 { S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, }, 80 { S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, }, 81 { S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, }, 82 { S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, }, 83 { S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, }, 84 { S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, }, 85 { S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, }, 86 { S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, }, 87 { S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, }, 88 { S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, }, 89 { S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, }, 90 { S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, }, 91 { S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, }, 92 { S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, }, 93 { S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, }, 94 { S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, }, 95 { S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, }, 96 { S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, }, 97 { S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, }, 98 { S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, }, 99 { S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, }, 100 { S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, }, 101 { S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, }, 102 { S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, }, 103 { S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, }, 104 { S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, }, 105 { S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, }, 106 { S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, }, 107 { S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, }, 108 { S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, }, 109 { S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, }, 110 { S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, }, 111 { S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, }, 112 { S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, }, 113 { S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, }, 114 { S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, }, 115 { S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, }, 116 { S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, }, 117 { S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, }, 118 { S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, }, 119 { S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, }, 120 { S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, }, 121 { S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, }, 122 { S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, }, 123 { S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, }, 124 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, }, 125 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, }, 126 { S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, }, 127 { S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, }, 128 { S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, }, 129 { S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, }, 130 { S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, }, 131 { S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, }, 132 { S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, }, 133 { S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, }, 134 { S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, }, 135 { S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, }, 136 { S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, }, 137 { S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, }, 138 { S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, }, 139 { S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, }, 140 { S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, }, 141 { S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, }, 142 }; 143 144 /* VSB SNR lookup table */ 145 static struct vsb_snr_tab { 146 u16 val; 147 u16 data; 148 } vsb_snr_tab[] = { 149 { 0x39f, 300, }, 150 { 0x39b, 295, }, 151 { 0x397, 290, }, 152 { 0x394, 285, }, 153 { 0x38f, 280, }, 154 { 0x38b, 275, }, 155 { 0x387, 270, }, 156 { 0x382, 265, }, 157 { 0x37d, 260, }, 158 { 0x377, 255, }, 159 { 0x370, 250, }, 160 { 0x36a, 245, }, 161 { 0x364, 240, }, 162 { 0x35b, 235, }, 163 { 0x353, 230, }, 164 { 0x349, 225, }, 165 { 0x340, 320, }, 166 { 0x337, 215, }, 167 { 0x327, 210, }, 168 { 0x31b, 205, }, 169 { 0x310, 200, }, 170 { 0x302, 195, }, 171 { 0x2f3, 190, }, 172 { 0x2e4, 185, }, 173 { 0x2d7, 180, }, 174 { 0x2cd, 175, }, 175 { 0x2bb, 170, }, 176 { 0x2a9, 165, }, 177 { 0x29e, 160, }, 178 { 0x284, 155, }, 179 { 0x27a, 150, }, 180 { 0x260, 145, }, 181 { 0x23a, 140, }, 182 { 0x224, 135, }, 183 { 0x213, 130, }, 184 { 0x204, 125, }, 185 { 0x1fe, 120, }, 186 { 0, 0, }, 187 }; 188 189 /* QAM64 SNR lookup table */ 190 static struct qam64_snr_tab { 191 u16 val; 192 u16 data; 193 } qam64_snr_tab[] = { 194 { 0x0001, 0, }, 195 { 0x0af0, 300, }, 196 { 0x0d80, 290, }, 197 { 0x10a0, 280, }, 198 { 0x14b5, 270, }, 199 { 0x1590, 268, }, 200 { 0x1680, 266, }, 201 { 0x17b0, 264, }, 202 { 0x18c0, 262, }, 203 { 0x19b0, 260, }, 204 { 0x1ad0, 258, }, 205 { 0x1d00, 256, }, 206 { 0x1da0, 254, }, 207 { 0x1ef0, 252, }, 208 { 0x2050, 250, }, 209 { 0x20f0, 249, }, 210 { 0x21d0, 248, }, 211 { 0x22b0, 247, }, 212 { 0x23a0, 246, }, 213 { 0x2470, 245, }, 214 { 0x24f0, 244, }, 215 { 0x25a0, 243, }, 216 { 0x26c0, 242, }, 217 { 0x27b0, 241, }, 218 { 0x28d0, 240, }, 219 { 0x29b0, 239, }, 220 { 0x2ad0, 238, }, 221 { 0x2ba0, 237, }, 222 { 0x2c80, 236, }, 223 { 0x2d20, 235, }, 224 { 0x2e00, 234, }, 225 { 0x2f10, 233, }, 226 { 0x3050, 232, }, 227 { 0x3190, 231, }, 228 { 0x3300, 230, }, 229 { 0x3340, 229, }, 230 { 0x3200, 228, }, 231 { 0x3550, 227, }, 232 { 0x3610, 226, }, 233 { 0x3600, 225, }, 234 { 0x3700, 224, }, 235 { 0x3800, 223, }, 236 { 0x3920, 222, }, 237 { 0x3a20, 221, }, 238 { 0x3b30, 220, }, 239 { 0x3d00, 219, }, 240 { 0x3e00, 218, }, 241 { 0x4000, 217, }, 242 { 0x4100, 216, }, 243 { 0x4300, 215, }, 244 { 0x4400, 214, }, 245 { 0x4600, 213, }, 246 { 0x4700, 212, }, 247 { 0x4800, 211, }, 248 { 0x4a00, 210, }, 249 { 0x4b00, 209, }, 250 { 0x4d00, 208, }, 251 { 0x4f00, 207, }, 252 { 0x5050, 206, }, 253 { 0x5200, 205, }, 254 { 0x53c0, 204, }, 255 { 0x5450, 203, }, 256 { 0x5650, 202, }, 257 { 0x5820, 201, }, 258 { 0x6000, 200, }, 259 { 0xffff, 0, }, 260 }; 261 262 /* QAM256 SNR lookup table */ 263 static struct qam256_snr_tab { 264 u16 val; 265 u16 data; 266 } qam256_snr_tab[] = { 267 { 0x0001, 0, }, 268 { 0x0970, 400, }, 269 { 0x0a90, 390, }, 270 { 0x0b90, 380, }, 271 { 0x0d90, 370, }, 272 { 0x0ff0, 360, }, 273 { 0x1240, 350, }, 274 { 0x1345, 348, }, 275 { 0x13c0, 346, }, 276 { 0x14c0, 344, }, 277 { 0x1500, 342, }, 278 { 0x1610, 340, }, 279 { 0x1700, 338, }, 280 { 0x1800, 336, }, 281 { 0x18b0, 334, }, 282 { 0x1900, 332, }, 283 { 0x1ab0, 330, }, 284 { 0x1bc0, 328, }, 285 { 0x1cb0, 326, }, 286 { 0x1db0, 324, }, 287 { 0x1eb0, 322, }, 288 { 0x2030, 320, }, 289 { 0x2200, 318, }, 290 { 0x2280, 316, }, 291 { 0x2410, 314, }, 292 { 0x25b0, 312, }, 293 { 0x27a0, 310, }, 294 { 0x2840, 308, }, 295 { 0x29d0, 306, }, 296 { 0x2b10, 304, }, 297 { 0x2d30, 302, }, 298 { 0x2f20, 300, }, 299 { 0x30c0, 298, }, 300 { 0x3260, 297, }, 301 { 0x32c0, 296, }, 302 { 0x3300, 295, }, 303 { 0x33b0, 294, }, 304 { 0x34b0, 293, }, 305 { 0x35a0, 292, }, 306 { 0x3650, 291, }, 307 { 0x3800, 290, }, 308 { 0x3900, 289, }, 309 { 0x3a50, 288, }, 310 { 0x3b30, 287, }, 311 { 0x3cb0, 286, }, 312 { 0x3e20, 285, }, 313 { 0x3fa0, 284, }, 314 { 0x40a0, 283, }, 315 { 0x41c0, 282, }, 316 { 0x42f0, 281, }, 317 { 0x44a0, 280, }, 318 { 0x4600, 279, }, 319 { 0x47b0, 278, }, 320 { 0x4900, 277, }, 321 { 0x4a00, 276, }, 322 { 0x4ba0, 275, }, 323 { 0x4d00, 274, }, 324 { 0x4f00, 273, }, 325 { 0x5000, 272, }, 326 { 0x51f0, 272, }, 327 { 0x53a0, 270, }, 328 { 0x5520, 269, }, 329 { 0x5700, 268, }, 330 { 0x5800, 267, }, 331 { 0x5a00, 266, }, 332 { 0x5c00, 265, }, 333 { 0x5d00, 264, }, 334 { 0x5f00, 263, }, 335 { 0x6000, 262, }, 336 { 0x6200, 261, }, 337 { 0x6400, 260, }, 338 { 0xffff, 0, }, 339 }; 340 341 /* 8 bit registers, 16 bit values */ 342 static int s5h1411_writereg(struct s5h1411_state *state, 343 u8 addr, u8 reg, u16 data) 344 { 345 int ret; 346 u8 buf[] = { reg, data >> 8, data & 0xff }; 347 348 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 }; 349 350 ret = i2c_transfer(state->i2c, &msg, 1); 351 352 if (ret != 1) 353 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n", 354 __func__, addr, reg, data, ret); 355 356 return (ret != 1) ? -1 : 0; 357 } 358 359 static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg) 360 { 361 int ret; 362 u8 b0[] = { reg }; 363 u8 b1[] = { 0, 0 }; 364 365 struct i2c_msg msg[] = { 366 { .addr = addr, .flags = 0, .buf = b0, .len = 1 }, 367 { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } }; 368 369 ret = i2c_transfer(state->i2c, msg, 2); 370 371 if (ret != 2) 372 printk(KERN_ERR "%s: readreg error (ret == %i)\n", 373 __func__, ret); 374 return (b1[0] << 8) | b1[1]; 375 } 376 377 static int s5h1411_softreset(struct dvb_frontend *fe) 378 { 379 struct s5h1411_state *state = fe->demodulator_priv; 380 381 dprintk("%s()\n", __func__); 382 383 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0); 384 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1); 385 return 0; 386 } 387 388 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz) 389 { 390 struct s5h1411_state *state = fe->demodulator_priv; 391 392 dprintk("%s(%d KHz)\n", __func__, KHz); 393 394 switch (KHz) { 395 case 3250: 396 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5); 397 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342); 398 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9); 399 break; 400 case 3500: 401 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225); 402 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96); 403 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225); 404 break; 405 case 4000: 406 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc); 407 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e); 408 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd); 409 break; 410 default: 411 dprintk("%s(%d KHz) Invalid, defaulting to 5380\n", 412 __func__, KHz); 413 /* fall through */ 414 case 5380: 415 case 44000: 416 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4); 417 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655); 418 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4); 419 break; 420 } 421 422 state->if_freq = KHz; 423 424 return 0; 425 } 426 427 static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode) 428 { 429 struct s5h1411_state *state = fe->demodulator_priv; 430 u16 val; 431 432 dprintk("%s(%d)\n", __func__, mode); 433 434 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff; 435 switch (mode) { 436 case S5H1411_MPEGTIMING_CONTINOUS_INVERTING_CLOCK: 437 val |= 0x0000; 438 break; 439 case S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK: 440 dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode); 441 val |= 0x1000; 442 break; 443 case S5H1411_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK: 444 val |= 0x2000; 445 break; 446 case S5H1411_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK: 447 val |= 0x3000; 448 break; 449 default: 450 return -EINVAL; 451 } 452 453 /* Configure MPEG Signal Timing charactistics */ 454 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val); 455 } 456 457 static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion) 458 { 459 struct s5h1411_state *state = fe->demodulator_priv; 460 u16 val; 461 462 dprintk("%s(%d)\n", __func__, inversion); 463 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000; 464 465 if (inversion == 1) 466 val |= 0x1000; /* Inverted */ 467 468 state->inversion = inversion; 469 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val); 470 } 471 472 static int s5h1411_set_serialmode(struct dvb_frontend *fe, int serial) 473 { 474 struct s5h1411_state *state = fe->demodulator_priv; 475 u16 val; 476 477 dprintk("%s(%d)\n", __func__, serial); 478 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100; 479 480 if (serial == 1) 481 val |= 0x100; 482 483 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val); 484 } 485 486 static int s5h1411_enable_modulation(struct dvb_frontend *fe, 487 enum fe_modulation m) 488 { 489 struct s5h1411_state *state = fe->demodulator_priv; 490 491 dprintk("%s(0x%08x)\n", __func__, m); 492 493 if ((state->first_tune == 0) && (m == state->current_modulation)) { 494 dprintk("%s() Already at desired modulation. Skipping...\n", 495 __func__); 496 return 0; 497 } 498 499 switch (m) { 500 case VSB_8: 501 dprintk("%s() VSB_8\n", __func__); 502 s5h1411_set_if_freq(fe, state->config->vsb_if); 503 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71); 504 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00); 505 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1); 506 break; 507 case QAM_64: 508 case QAM_256: 509 case QAM_AUTO: 510 dprintk("%s() QAM_AUTO (64/256)\n", __func__); 511 s5h1411_set_if_freq(fe, state->config->qam_if); 512 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171); 513 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001); 514 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101); 515 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0); 516 break; 517 default: 518 dprintk("%s() Invalid modulation\n", __func__); 519 return -EINVAL; 520 } 521 522 state->current_modulation = m; 523 state->first_tune = 0; 524 s5h1411_softreset(fe); 525 526 return 0; 527 } 528 529 static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 530 { 531 struct s5h1411_state *state = fe->demodulator_priv; 532 533 dprintk("%s(%d)\n", __func__, enable); 534 535 if (enable) 536 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); 537 else 538 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0); 539 } 540 541 static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable) 542 { 543 struct s5h1411_state *state = fe->demodulator_priv; 544 u16 val; 545 546 dprintk("%s(%d)\n", __func__, enable); 547 548 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02; 549 550 if (enable) 551 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, 552 val | 0x02); 553 else 554 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val); 555 } 556 557 static int s5h1411_set_powerstate(struct dvb_frontend *fe, int enable) 558 { 559 struct s5h1411_state *state = fe->demodulator_priv; 560 561 dprintk("%s(%d)\n", __func__, enable); 562 563 if (enable) 564 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1); 565 else { 566 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0); 567 s5h1411_softreset(fe); 568 } 569 570 return 0; 571 } 572 573 static int s5h1411_sleep(struct dvb_frontend *fe) 574 { 575 return s5h1411_set_powerstate(fe, 1); 576 } 577 578 static int s5h1411_register_reset(struct dvb_frontend *fe) 579 { 580 struct s5h1411_state *state = fe->demodulator_priv; 581 582 dprintk("%s()\n", __func__); 583 584 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0); 585 } 586 587 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 588 static int s5h1411_set_frontend(struct dvb_frontend *fe) 589 { 590 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 591 struct s5h1411_state *state = fe->demodulator_priv; 592 593 dprintk("%s(frequency=%d)\n", __func__, p->frequency); 594 595 s5h1411_softreset(fe); 596 597 state->current_frequency = p->frequency; 598 599 s5h1411_enable_modulation(fe, p->modulation); 600 601 if (fe->ops.tuner_ops.set_params) { 602 if (fe->ops.i2c_gate_ctrl) 603 fe->ops.i2c_gate_ctrl(fe, 1); 604 605 fe->ops.tuner_ops.set_params(fe); 606 607 if (fe->ops.i2c_gate_ctrl) 608 fe->ops.i2c_gate_ctrl(fe, 0); 609 } 610 611 /* Issue a reset to the demod so it knows to resync against the 612 newly tuned frequency */ 613 s5h1411_softreset(fe); 614 615 return 0; 616 } 617 618 /* Reset the demod hardware and reset all of the configuration registers 619 to a default state. */ 620 static int s5h1411_init(struct dvb_frontend *fe) 621 { 622 struct s5h1411_state *state = fe->demodulator_priv; 623 int i; 624 625 dprintk("%s()\n", __func__); 626 627 s5h1411_set_powerstate(fe, 0); 628 s5h1411_register_reset(fe); 629 630 for (i = 0; i < ARRAY_SIZE(init_tab); i++) 631 s5h1411_writereg(state, init_tab[i].addr, 632 init_tab[i].reg, 633 init_tab[i].data); 634 635 /* The datasheet says that after initialisation, VSB is default */ 636 state->current_modulation = VSB_8; 637 638 /* Although the datasheet says it's in VSB, empirical evidence 639 shows problems getting lock on the first tuning request. Make 640 sure we call enable_modulation the first time around */ 641 state->first_tune = 1; 642 643 if (state->config->output_mode == S5H1411_SERIAL_OUTPUT) 644 /* Serial */ 645 s5h1411_set_serialmode(fe, 1); 646 else 647 /* Parallel */ 648 s5h1411_set_serialmode(fe, 0); 649 650 s5h1411_set_spectralinversion(fe, state->config->inversion); 651 s5h1411_set_if_freq(fe, state->config->vsb_if); 652 s5h1411_set_gpio(fe, state->config->gpio); 653 s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing); 654 s5h1411_softreset(fe); 655 656 /* Note: Leaving the I2C gate closed. */ 657 s5h1411_i2c_gate_ctrl(fe, 0); 658 659 return 0; 660 } 661 662 static int s5h1411_read_status(struct dvb_frontend *fe, enum fe_status *status) 663 { 664 struct s5h1411_state *state = fe->demodulator_priv; 665 u16 reg; 666 u32 tuner_status = 0; 667 668 *status = 0; 669 670 /* Register F2 bit 15 = Master Lock, removed */ 671 672 switch (state->current_modulation) { 673 case QAM_64: 674 case QAM_256: 675 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0); 676 if (reg & 0x10) /* QAM FEC Lock */ 677 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 678 if (reg & 0x100) /* QAM EQ Lock */ 679 *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL; 680 681 break; 682 case VSB_8: 683 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2); 684 if (reg & 0x1000) /* FEC Lock */ 685 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 686 if (reg & 0x2000) /* EQ Lock */ 687 *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL; 688 689 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53); 690 if (reg & 0x1) /* AFC Lock */ 691 *status |= FE_HAS_SIGNAL; 692 693 break; 694 default: 695 return -EINVAL; 696 } 697 698 switch (state->config->status_mode) { 699 case S5H1411_DEMODLOCKING: 700 if (*status & FE_HAS_VITERBI) 701 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; 702 break; 703 case S5H1411_TUNERLOCKING: 704 /* Get the tuner status */ 705 if (fe->ops.tuner_ops.get_status) { 706 if (fe->ops.i2c_gate_ctrl) 707 fe->ops.i2c_gate_ctrl(fe, 1); 708 709 fe->ops.tuner_ops.get_status(fe, &tuner_status); 710 711 if (fe->ops.i2c_gate_ctrl) 712 fe->ops.i2c_gate_ctrl(fe, 0); 713 } 714 if (tuner_status) 715 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; 716 break; 717 } 718 719 dprintk("%s() status 0x%08x\n", __func__, *status); 720 721 return 0; 722 } 723 724 static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v) 725 { 726 int i, ret = -EINVAL; 727 dprintk("%s()\n", __func__); 728 729 for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) { 730 if (v < qam256_snr_tab[i].val) { 731 *snr = qam256_snr_tab[i].data; 732 ret = 0; 733 break; 734 } 735 } 736 return ret; 737 } 738 739 static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v) 740 { 741 int i, ret = -EINVAL; 742 dprintk("%s()\n", __func__); 743 744 for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) { 745 if (v < qam64_snr_tab[i].val) { 746 *snr = qam64_snr_tab[i].data; 747 ret = 0; 748 break; 749 } 750 } 751 return ret; 752 } 753 754 static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v) 755 { 756 int i, ret = -EINVAL; 757 dprintk("%s()\n", __func__); 758 759 for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) { 760 if (v > vsb_snr_tab[i].val) { 761 *snr = vsb_snr_tab[i].data; 762 ret = 0; 763 break; 764 } 765 } 766 dprintk("%s() snr=%d\n", __func__, *snr); 767 return ret; 768 } 769 770 static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr) 771 { 772 struct s5h1411_state *state = fe->demodulator_priv; 773 u16 reg; 774 dprintk("%s()\n", __func__); 775 776 switch (state->current_modulation) { 777 case QAM_64: 778 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); 779 return s5h1411_qam64_lookup_snr(fe, snr, reg); 780 case QAM_256: 781 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); 782 return s5h1411_qam256_lookup_snr(fe, snr, reg); 783 case VSB_8: 784 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 785 0xf2) & 0x3ff; 786 return s5h1411_vsb_lookup_snr(fe, snr, reg); 787 default: 788 break; 789 } 790 791 return -EINVAL; 792 } 793 794 static int s5h1411_read_signal_strength(struct dvb_frontend *fe, 795 u16 *signal_strength) 796 { 797 /* borrowed from lgdt330x.c 798 * 799 * Calculate strength from SNR up to 35dB 800 * Even though the SNR can go higher than 35dB, 801 * there is some comfort factor in having a range of 802 * strong signals that can show at 100% 803 */ 804 u16 snr; 805 u32 tmp; 806 int ret = s5h1411_read_snr(fe, &snr); 807 808 *signal_strength = 0; 809 810 if (0 == ret) { 811 /* The following calculation method was chosen 812 * purely for the sake of code re-use from the 813 * other demod drivers that use this method */ 814 815 /* Convert from SNR in dB * 10 to 8.24 fixed-point */ 816 tmp = (snr * ((1 << 24) / 10)); 817 818 /* Convert from 8.24 fixed-point to 819 * scale the range 0 - 35*2^24 into 0 - 65535*/ 820 if (tmp >= 8960 * 0x10000) 821 *signal_strength = 0xffff; 822 else 823 *signal_strength = tmp / 8960; 824 } 825 826 return ret; 827 } 828 829 static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 830 { 831 struct s5h1411_state *state = fe->demodulator_priv; 832 833 *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9); 834 835 return 0; 836 } 837 838 static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber) 839 { 840 return s5h1411_read_ucblocks(fe, ber); 841 } 842 843 static int s5h1411_get_frontend(struct dvb_frontend *fe, 844 struct dtv_frontend_properties *p) 845 { 846 struct s5h1411_state *state = fe->demodulator_priv; 847 848 p->frequency = state->current_frequency; 849 p->modulation = state->current_modulation; 850 851 return 0; 852 } 853 854 static int s5h1411_get_tune_settings(struct dvb_frontend *fe, 855 struct dvb_frontend_tune_settings *tune) 856 { 857 tune->min_delay_ms = 1000; 858 return 0; 859 } 860 861 static void s5h1411_release(struct dvb_frontend *fe) 862 { 863 struct s5h1411_state *state = fe->demodulator_priv; 864 kfree(state); 865 } 866 867 static const struct dvb_frontend_ops s5h1411_ops; 868 869 struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config, 870 struct i2c_adapter *i2c) 871 { 872 struct s5h1411_state *state = NULL; 873 u16 reg; 874 875 /* allocate memory for the internal state */ 876 state = kzalloc(sizeof(struct s5h1411_state), GFP_KERNEL); 877 if (state == NULL) 878 goto error; 879 880 /* setup the state */ 881 state->config = config; 882 state->i2c = i2c; 883 state->current_modulation = VSB_8; 884 state->inversion = state->config->inversion; 885 886 /* check if the demod exists */ 887 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05); 888 if (reg != 0x0066) 889 goto error; 890 891 /* create dvb_frontend */ 892 memcpy(&state->frontend.ops, &s5h1411_ops, 893 sizeof(struct dvb_frontend_ops)); 894 895 state->frontend.demodulator_priv = state; 896 897 if (s5h1411_init(&state->frontend) != 0) { 898 printk(KERN_ERR "%s: Failed to initialize correctly\n", 899 __func__); 900 goto error; 901 } 902 903 /* Note: Leaving the I2C gate open here. */ 904 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); 905 906 /* Put the device into low-power mode until first use */ 907 s5h1411_set_powerstate(&state->frontend, 1); 908 909 return &state->frontend; 910 911 error: 912 kfree(state); 913 return NULL; 914 } 915 EXPORT_SYMBOL(s5h1411_attach); 916 917 static const struct dvb_frontend_ops s5h1411_ops = { 918 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 919 .info = { 920 .name = "Samsung S5H1411 QAM/8VSB Frontend", 921 .frequency_min = 54000000, 922 .frequency_max = 858000000, 923 .frequency_stepsize = 62500, 924 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 925 }, 926 927 .init = s5h1411_init, 928 .sleep = s5h1411_sleep, 929 .i2c_gate_ctrl = s5h1411_i2c_gate_ctrl, 930 .set_frontend = s5h1411_set_frontend, 931 .get_frontend = s5h1411_get_frontend, 932 .get_tune_settings = s5h1411_get_tune_settings, 933 .read_status = s5h1411_read_status, 934 .read_ber = s5h1411_read_ber, 935 .read_signal_strength = s5h1411_read_signal_strength, 936 .read_snr = s5h1411_read_snr, 937 .read_ucblocks = s5h1411_read_ucblocks, 938 .release = s5h1411_release, 939 }; 940 941 module_param(debug, int, 0644); 942 MODULE_PARM_DESC(debug, "Enable verbose debug messages"); 943 944 MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver"); 945 MODULE_AUTHOR("Steven Toth"); 946 MODULE_LICENSE("GPL"); 947