1 /* 2 * Realtek RTL2832 DVB-T demodulator driver 3 * 4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef RTL2832_PRIV_H 22 #define RTL2832_PRIV_H 23 24 #include "dvb_frontend.h" 25 #include "rtl2832.h" 26 #include <linux/i2c-mux.h> 27 28 struct rtl2832_priv { 29 struct i2c_adapter *i2c; 30 struct i2c_adapter *i2c_adapter; 31 struct i2c_adapter *i2c_adapter_tuner; 32 struct dvb_frontend fe; 33 struct rtl2832_config cfg; 34 35 bool i2c_gate_state; 36 bool sleeping; 37 38 u8 tuner; 39 u8 page; /* active register page */ 40 struct delayed_work i2c_gate_work; 41 }; 42 43 struct rtl2832_reg_entry { 44 u8 page; 45 u8 start_address; 46 u8 msb; 47 u8 lsb; 48 }; 49 50 struct rtl2832_reg_value { 51 int reg; 52 u32 value; 53 }; 54 55 56 /* Demod register bit names */ 57 enum DVBT_REG_BIT_NAME { 58 DVBT_SOFT_RST, 59 DVBT_IIC_REPEAT, 60 DVBT_TR_WAIT_MIN_8K, 61 DVBT_RSD_BER_FAIL_VAL, 62 DVBT_EN_BK_TRK, 63 DVBT_REG_PI, 64 DVBT_REG_PFREQ_1_0, 65 DVBT_PD_DA8, 66 DVBT_LOCK_TH, 67 DVBT_BER_PASS_SCAL, 68 DVBT_CE_FFSM_BYPASS, 69 DVBT_ALPHAIIR_N, 70 DVBT_ALPHAIIR_DIF, 71 DVBT_EN_TRK_SPAN, 72 DVBT_LOCK_TH_LEN, 73 DVBT_CCI_THRE, 74 DVBT_CCI_MON_SCAL, 75 DVBT_CCI_M0, 76 DVBT_CCI_M1, 77 DVBT_CCI_M2, 78 DVBT_CCI_M3, 79 DVBT_SPEC_INIT_0, 80 DVBT_SPEC_INIT_1, 81 DVBT_SPEC_INIT_2, 82 DVBT_AD_EN_REG, 83 DVBT_AD_EN_REG1, 84 DVBT_EN_BBIN, 85 DVBT_MGD_THD0, 86 DVBT_MGD_THD1, 87 DVBT_MGD_THD2, 88 DVBT_MGD_THD3, 89 DVBT_MGD_THD4, 90 DVBT_MGD_THD5, 91 DVBT_MGD_THD6, 92 DVBT_MGD_THD7, 93 DVBT_EN_CACQ_NOTCH, 94 DVBT_AD_AV_REF, 95 DVBT_PIP_ON, 96 DVBT_SCALE1_B92, 97 DVBT_SCALE1_B93, 98 DVBT_SCALE1_BA7, 99 DVBT_SCALE1_BA9, 100 DVBT_SCALE1_BAA, 101 DVBT_SCALE1_BAB, 102 DVBT_SCALE1_BAC, 103 DVBT_SCALE1_BB0, 104 DVBT_SCALE1_BB1, 105 DVBT_KB_P1, 106 DVBT_KB_P2, 107 DVBT_KB_P3, 108 DVBT_OPT_ADC_IQ, 109 DVBT_AD_AVI, 110 DVBT_AD_AVQ, 111 DVBT_K1_CR_STEP12, 112 DVBT_TRK_KS_P2, 113 DVBT_TRK_KS_I2, 114 DVBT_TR_THD_SET2, 115 DVBT_TRK_KC_P2, 116 DVBT_TRK_KC_I2, 117 DVBT_CR_THD_SET2, 118 DVBT_PSET_IFFREQ, 119 DVBT_SPEC_INV, 120 DVBT_BW_INDEX, 121 DVBT_RSAMP_RATIO, 122 DVBT_CFREQ_OFF_RATIO, 123 DVBT_FSM_STAGE, 124 DVBT_RX_CONSTEL, 125 DVBT_RX_HIER, 126 DVBT_RX_C_RATE_LP, 127 DVBT_RX_C_RATE_HP, 128 DVBT_GI_IDX, 129 DVBT_FFT_MODE_IDX, 130 DVBT_RSD_BER_EST, 131 DVBT_CE_EST_EVM, 132 DVBT_RF_AGC_VAL, 133 DVBT_IF_AGC_VAL, 134 DVBT_DAGC_VAL, 135 DVBT_SFREQ_OFF, 136 DVBT_CFREQ_OFF, 137 DVBT_POLAR_RF_AGC, 138 DVBT_POLAR_IF_AGC, 139 DVBT_AAGC_HOLD, 140 DVBT_EN_RF_AGC, 141 DVBT_EN_IF_AGC, 142 DVBT_IF_AGC_MIN, 143 DVBT_IF_AGC_MAX, 144 DVBT_RF_AGC_MIN, 145 DVBT_RF_AGC_MAX, 146 DVBT_IF_AGC_MAN, 147 DVBT_IF_AGC_MAN_VAL, 148 DVBT_RF_AGC_MAN, 149 DVBT_RF_AGC_MAN_VAL, 150 DVBT_DAGC_TRG_VAL, 151 DVBT_AGC_TARG_VAL, 152 DVBT_LOOP_GAIN_3_0, 153 DVBT_LOOP_GAIN_4, 154 DVBT_VTOP, 155 DVBT_KRF, 156 DVBT_AGC_TARG_VAL_0, 157 DVBT_AGC_TARG_VAL_8_1, 158 DVBT_AAGC_LOOP_GAIN, 159 DVBT_LOOP_GAIN2_3_0, 160 DVBT_LOOP_GAIN2_4, 161 DVBT_LOOP_GAIN3, 162 DVBT_VTOP1, 163 DVBT_VTOP2, 164 DVBT_VTOP3, 165 DVBT_KRF1, 166 DVBT_KRF2, 167 DVBT_KRF3, 168 DVBT_KRF4, 169 DVBT_EN_GI_PGA, 170 DVBT_THD_LOCK_UP, 171 DVBT_THD_LOCK_DW, 172 DVBT_THD_UP1, 173 DVBT_THD_DW1, 174 DVBT_INTER_CNT_LEN, 175 DVBT_GI_PGA_STATE, 176 DVBT_EN_AGC_PGA, 177 DVBT_CKOUTPAR, 178 DVBT_CKOUT_PWR, 179 DVBT_SYNC_DUR, 180 DVBT_ERR_DUR, 181 DVBT_SYNC_LVL, 182 DVBT_ERR_LVL, 183 DVBT_VAL_LVL, 184 DVBT_SERIAL, 185 DVBT_SER_LSB, 186 DVBT_CDIV_PH0, 187 DVBT_CDIV_PH1, 188 DVBT_MPEG_IO_OPT_2_2, 189 DVBT_MPEG_IO_OPT_1_0, 190 DVBT_CKOUTPAR_PIP, 191 DVBT_CKOUT_PWR_PIP, 192 DVBT_SYNC_LVL_PIP, 193 DVBT_ERR_LVL_PIP, 194 DVBT_VAL_LVL_PIP, 195 DVBT_CKOUTPAR_PID, 196 DVBT_CKOUT_PWR_PID, 197 DVBT_SYNC_LVL_PID, 198 DVBT_ERR_LVL_PID, 199 DVBT_VAL_LVL_PID, 200 DVBT_SM_PASS, 201 DVBT_UPDATE_REG_2, 202 DVBT_BTHD_P3, 203 DVBT_BTHD_D3, 204 DVBT_FUNC4_REG0, 205 DVBT_FUNC4_REG1, 206 DVBT_FUNC4_REG2, 207 DVBT_FUNC4_REG3, 208 DVBT_FUNC4_REG4, 209 DVBT_FUNC4_REG5, 210 DVBT_FUNC4_REG6, 211 DVBT_FUNC4_REG7, 212 DVBT_FUNC4_REG8, 213 DVBT_FUNC4_REG9, 214 DVBT_FUNC4_REG10, 215 DVBT_FUNC5_REG0, 216 DVBT_FUNC5_REG1, 217 DVBT_FUNC5_REG2, 218 DVBT_FUNC5_REG3, 219 DVBT_FUNC5_REG4, 220 DVBT_FUNC5_REG5, 221 DVBT_FUNC5_REG6, 222 DVBT_FUNC5_REG7, 223 DVBT_FUNC5_REG8, 224 DVBT_FUNC5_REG9, 225 DVBT_FUNC5_REG10, 226 DVBT_FUNC5_REG11, 227 DVBT_FUNC5_REG12, 228 DVBT_FUNC5_REG13, 229 DVBT_FUNC5_REG14, 230 DVBT_FUNC5_REG15, 231 DVBT_FUNC5_REG16, 232 DVBT_FUNC5_REG17, 233 DVBT_FUNC5_REG18, 234 DVBT_AD7_SETTING, 235 DVBT_RSSI_R, 236 DVBT_ACI_DET_IND, 237 DVBT_REG_MON, 238 DVBT_REG_MONSEL, 239 DVBT_REG_GPE, 240 DVBT_REG_GPO, 241 DVBT_REG_4MSEL, 242 DVBT_TEST_REG_1, 243 DVBT_TEST_REG_2, 244 DVBT_TEST_REG_3, 245 DVBT_TEST_REG_4, 246 DVBT_REG_BIT_NAME_ITEM_TERMINATOR, 247 }; 248 249 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = { 250 {DVBT_DAGC_TRG_VAL, 0x39}, 251 {DVBT_AGC_TARG_VAL_0, 0x0}, 252 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 253 {DVBT_AAGC_LOOP_GAIN, 0x16}, 254 {DVBT_LOOP_GAIN2_3_0, 0x6}, 255 {DVBT_LOOP_GAIN2_4, 0x1}, 256 {DVBT_LOOP_GAIN3, 0x16}, 257 {DVBT_VTOP1, 0x35}, 258 {DVBT_VTOP2, 0x21}, 259 {DVBT_VTOP3, 0x21}, 260 {DVBT_KRF1, 0x0}, 261 {DVBT_KRF2, 0x40}, 262 {DVBT_KRF3, 0x10}, 263 {DVBT_KRF4, 0x10}, 264 {DVBT_IF_AGC_MIN, 0x80}, 265 {DVBT_IF_AGC_MAX, 0x7f}, 266 {DVBT_RF_AGC_MIN, 0x9c}, 267 {DVBT_RF_AGC_MAX, 0x7f}, 268 {DVBT_POLAR_RF_AGC, 0x0}, 269 {DVBT_POLAR_IF_AGC, 0x0}, 270 {DVBT_AD7_SETTING, 0xe9f4}, 271 {DVBT_OPT_ADC_IQ, 0x1}, 272 {DVBT_AD_AVI, 0x0}, 273 {DVBT_AD_AVQ, 0x0}, 274 {DVBT_SPEC_INV, 0x0}, 275 }; 276 277 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { 278 {DVBT_DAGC_TRG_VAL, 0x5a}, 279 {DVBT_AGC_TARG_VAL_0, 0x0}, 280 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 281 {DVBT_AAGC_LOOP_GAIN, 0x16}, 282 {DVBT_LOOP_GAIN2_3_0, 0x6}, 283 {DVBT_LOOP_GAIN2_4, 0x1}, 284 {DVBT_LOOP_GAIN3, 0x16}, 285 {DVBT_VTOP1, 0x35}, 286 {DVBT_VTOP2, 0x21}, 287 {DVBT_VTOP3, 0x21}, 288 {DVBT_KRF1, 0x0}, 289 {DVBT_KRF2, 0x40}, 290 {DVBT_KRF3, 0x10}, 291 {DVBT_KRF4, 0x10}, 292 {DVBT_IF_AGC_MIN, 0x80}, 293 {DVBT_IF_AGC_MAX, 0x7f}, 294 {DVBT_RF_AGC_MIN, 0x80}, 295 {DVBT_RF_AGC_MAX, 0x7f}, 296 {DVBT_POLAR_RF_AGC, 0x0}, 297 {DVBT_POLAR_IF_AGC, 0x0}, 298 {DVBT_AD7_SETTING, 0xe9bf}, 299 {DVBT_EN_GI_PGA, 0x0}, 300 {DVBT_THD_LOCK_UP, 0x0}, 301 {DVBT_THD_LOCK_DW, 0x0}, 302 {DVBT_THD_UP1, 0x11}, 303 {DVBT_THD_DW1, 0xef}, 304 {DVBT_INTER_CNT_LEN, 0xc}, 305 {DVBT_GI_PGA_STATE, 0x0}, 306 {DVBT_EN_AGC_PGA, 0x1}, 307 {DVBT_IF_AGC_MAN, 0x0}, 308 {DVBT_SPEC_INV, 0x0}, 309 }; 310 311 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { 312 {DVBT_DAGC_TRG_VAL, 0x5a}, 313 {DVBT_AGC_TARG_VAL_0, 0x0}, 314 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 315 {DVBT_AAGC_LOOP_GAIN, 0x18}, 316 {DVBT_LOOP_GAIN2_3_0, 0x8}, 317 {DVBT_LOOP_GAIN2_4, 0x1}, 318 {DVBT_LOOP_GAIN3, 0x18}, 319 {DVBT_VTOP1, 0x35}, 320 {DVBT_VTOP2, 0x21}, 321 {DVBT_VTOP3, 0x21}, 322 {DVBT_KRF1, 0x0}, 323 {DVBT_KRF2, 0x40}, 324 {DVBT_KRF3, 0x10}, 325 {DVBT_KRF4, 0x10}, 326 {DVBT_IF_AGC_MIN, 0x80}, 327 {DVBT_IF_AGC_MAX, 0x7f}, 328 {DVBT_RF_AGC_MIN, 0x80}, 329 {DVBT_RF_AGC_MAX, 0x7f}, 330 {DVBT_POLAR_RF_AGC, 0x0}, 331 {DVBT_POLAR_IF_AGC, 0x0}, 332 {DVBT_AD7_SETTING, 0xe9d4}, 333 {DVBT_EN_GI_PGA, 0x0}, 334 {DVBT_THD_LOCK_UP, 0x0}, 335 {DVBT_THD_LOCK_DW, 0x0}, 336 {DVBT_THD_UP1, 0x14}, 337 {DVBT_THD_DW1, 0xec}, 338 {DVBT_INTER_CNT_LEN, 0xc}, 339 {DVBT_GI_PGA_STATE, 0x0}, 340 {DVBT_EN_AGC_PGA, 0x1}, 341 {DVBT_REG_GPE, 0x1}, 342 {DVBT_REG_GPO, 0x1}, 343 {DVBT_REG_MONSEL, 0x1}, 344 {DVBT_REG_MON, 0x1}, 345 {DVBT_REG_4MSEL, 0x0}, 346 {DVBT_SPEC_INV, 0x0}, 347 }; 348 349 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = { 350 {DVBT_DAGC_TRG_VAL, 0x39}, 351 {DVBT_AGC_TARG_VAL_0, 0x0}, 352 {DVBT_AGC_TARG_VAL_8_1, 0x40}, 353 {DVBT_AAGC_LOOP_GAIN, 0x16}, 354 {DVBT_LOOP_GAIN2_3_0, 0x8}, 355 {DVBT_LOOP_GAIN2_4, 0x1}, 356 {DVBT_LOOP_GAIN3, 0x18}, 357 {DVBT_VTOP1, 0x35}, 358 {DVBT_VTOP2, 0x21}, 359 {DVBT_VTOP3, 0x21}, 360 {DVBT_KRF1, 0x0}, 361 {DVBT_KRF2, 0x40}, 362 {DVBT_KRF3, 0x10}, 363 {DVBT_KRF4, 0x10}, 364 {DVBT_IF_AGC_MIN, 0x80}, 365 {DVBT_IF_AGC_MAX, 0x7f}, 366 {DVBT_RF_AGC_MIN, 0x80}, 367 {DVBT_RF_AGC_MAX, 0x7f}, 368 {DVBT_POLAR_RF_AGC, 0x0}, 369 {DVBT_POLAR_IF_AGC, 0x0}, 370 {DVBT_AD7_SETTING, 0xe9f4}, 371 {DVBT_SPEC_INV, 0x1}, 372 }; 373 374 #endif /* RTL2832_PRIV_H */ 375