1 /*
2  * Realtek RTL2832 DVB-T demodulator driver
3  *
4  * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5  * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
6  *
7  *	This program is free software; you can redistribute it and/or modify
8  *	it under the terms of the GNU General Public License as published by
9  *	the Free Software Foundation; either version 2 of the License, or
10  *	(at your option) any later version.
11  *
12  *	This program is distributed in the hope that it will be useful,
13  *	but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *	GNU General Public License for more details.
16  *
17  *	You should have received a copy of the GNU General Public License along
18  *	with this program; if not, write to the Free Software Foundation, Inc.,
19  *	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20  */
21 
22 #ifndef RTL2832_PRIV_H
23 #define RTL2832_PRIV_H
24 
25 #include <linux/regmap.h>
26 #include <linux/math64.h>
27 #include <linux/bitops.h>
28 
29 #include <media/dvb_frontend.h>
30 #include <media/dvb_math.h>
31 #include "rtl2832.h"
32 
33 struct rtl2832_dev {
34 	struct rtl2832_platform_data *pdata;
35 	struct i2c_client *client;
36 	struct regmap_config regmap_config;
37 	struct regmap *regmap;
38 	struct i2c_mux_core *muxc;
39 	struct dvb_frontend fe;
40 	enum fe_status fe_status;
41 	u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
42 	u64 post_bit_error;
43 	u64 post_bit_count;
44 	bool sleeping;
45 	struct delayed_work i2c_gate_work;
46 	unsigned long filters; /* PID filter */
47 	bool slave_ts;
48 };
49 
50 struct rtl2832_reg_entry {
51 	u16 start_address;
52 	u8 msb;
53 	u8 lsb;
54 };
55 
56 struct rtl2832_reg_value {
57 	int reg;
58 	u32 value;
59 };
60 
61 /* Demod register bit names */
62 enum DVBT_REG_BIT_NAME {
63 	DVBT_SOFT_RST,
64 	DVBT_IIC_REPEAT,
65 	DVBT_TR_WAIT_MIN_8K,
66 	DVBT_RSD_BER_FAIL_VAL,
67 	DVBT_EN_BK_TRK,
68 	DVBT_REG_PI,
69 	DVBT_REG_PFREQ_1_0,
70 	DVBT_PD_DA8,
71 	DVBT_LOCK_TH,
72 	DVBT_BER_PASS_SCAL,
73 	DVBT_CE_FFSM_BYPASS,
74 	DVBT_ALPHAIIR_N,
75 	DVBT_ALPHAIIR_DIF,
76 	DVBT_EN_TRK_SPAN,
77 	DVBT_LOCK_TH_LEN,
78 	DVBT_CCI_THRE,
79 	DVBT_CCI_MON_SCAL,
80 	DVBT_CCI_M0,
81 	DVBT_CCI_M1,
82 	DVBT_CCI_M2,
83 	DVBT_CCI_M3,
84 	DVBT_SPEC_INIT_0,
85 	DVBT_SPEC_INIT_1,
86 	DVBT_SPEC_INIT_2,
87 	DVBT_AD_EN_REG,
88 	DVBT_AD_EN_REG1,
89 	DVBT_EN_BBIN,
90 	DVBT_MGD_THD0,
91 	DVBT_MGD_THD1,
92 	DVBT_MGD_THD2,
93 	DVBT_MGD_THD3,
94 	DVBT_MGD_THD4,
95 	DVBT_MGD_THD5,
96 	DVBT_MGD_THD6,
97 	DVBT_MGD_THD7,
98 	DVBT_EN_CACQ_NOTCH,
99 	DVBT_AD_AV_REF,
100 	DVBT_PIP_ON,
101 	DVBT_SCALE1_B92,
102 	DVBT_SCALE1_B93,
103 	DVBT_SCALE1_BA7,
104 	DVBT_SCALE1_BA9,
105 	DVBT_SCALE1_BAA,
106 	DVBT_SCALE1_BAB,
107 	DVBT_SCALE1_BAC,
108 	DVBT_SCALE1_BB0,
109 	DVBT_SCALE1_BB1,
110 	DVBT_KB_P1,
111 	DVBT_KB_P2,
112 	DVBT_KB_P3,
113 	DVBT_OPT_ADC_IQ,
114 	DVBT_AD_AVI,
115 	DVBT_AD_AVQ,
116 	DVBT_K1_CR_STEP12,
117 	DVBT_TRK_KS_P2,
118 	DVBT_TRK_KS_I2,
119 	DVBT_TR_THD_SET2,
120 	DVBT_TRK_KC_P2,
121 	DVBT_TRK_KC_I2,
122 	DVBT_CR_THD_SET2,
123 	DVBT_PSET_IFFREQ,
124 	DVBT_SPEC_INV,
125 	DVBT_BW_INDEX,
126 	DVBT_RSAMP_RATIO,
127 	DVBT_CFREQ_OFF_RATIO,
128 	DVBT_FSM_STAGE,
129 	DVBT_RX_CONSTEL,
130 	DVBT_RX_HIER,
131 	DVBT_RX_C_RATE_LP,
132 	DVBT_RX_C_RATE_HP,
133 	DVBT_GI_IDX,
134 	DVBT_FFT_MODE_IDX,
135 	DVBT_RSD_BER_EST,
136 	DVBT_CE_EST_EVM,
137 	DVBT_RF_AGC_VAL,
138 	DVBT_IF_AGC_VAL,
139 	DVBT_DAGC_VAL,
140 	DVBT_SFREQ_OFF,
141 	DVBT_CFREQ_OFF,
142 	DVBT_POLAR_RF_AGC,
143 	DVBT_POLAR_IF_AGC,
144 	DVBT_AAGC_HOLD,
145 	DVBT_EN_RF_AGC,
146 	DVBT_EN_IF_AGC,
147 	DVBT_IF_AGC_MIN,
148 	DVBT_IF_AGC_MAX,
149 	DVBT_RF_AGC_MIN,
150 	DVBT_RF_AGC_MAX,
151 	DVBT_IF_AGC_MAN,
152 	DVBT_IF_AGC_MAN_VAL,
153 	DVBT_RF_AGC_MAN,
154 	DVBT_RF_AGC_MAN_VAL,
155 	DVBT_DAGC_TRG_VAL,
156 	DVBT_AGC_TARG_VAL,
157 	DVBT_LOOP_GAIN_3_0,
158 	DVBT_LOOP_GAIN_4,
159 	DVBT_VTOP,
160 	DVBT_KRF,
161 	DVBT_AGC_TARG_VAL_0,
162 	DVBT_AGC_TARG_VAL_8_1,
163 	DVBT_AAGC_LOOP_GAIN,
164 	DVBT_LOOP_GAIN2_3_0,
165 	DVBT_LOOP_GAIN2_4,
166 	DVBT_LOOP_GAIN3,
167 	DVBT_VTOP1,
168 	DVBT_VTOP2,
169 	DVBT_VTOP3,
170 	DVBT_KRF1,
171 	DVBT_KRF2,
172 	DVBT_KRF3,
173 	DVBT_KRF4,
174 	DVBT_EN_GI_PGA,
175 	DVBT_THD_LOCK_UP,
176 	DVBT_THD_LOCK_DW,
177 	DVBT_THD_UP1,
178 	DVBT_THD_DW1,
179 	DVBT_INTER_CNT_LEN,
180 	DVBT_GI_PGA_STATE,
181 	DVBT_EN_AGC_PGA,
182 	DVBT_CKOUTPAR,
183 	DVBT_CKOUT_PWR,
184 	DVBT_SYNC_DUR,
185 	DVBT_ERR_DUR,
186 	DVBT_SYNC_LVL,
187 	DVBT_ERR_LVL,
188 	DVBT_VAL_LVL,
189 	DVBT_SERIAL,
190 	DVBT_SER_LSB,
191 	DVBT_CDIV_PH0,
192 	DVBT_CDIV_PH1,
193 	DVBT_MPEG_IO_OPT_2_2,
194 	DVBT_MPEG_IO_OPT_1_0,
195 	DVBT_CKOUTPAR_PIP,
196 	DVBT_CKOUT_PWR_PIP,
197 	DVBT_SYNC_LVL_PIP,
198 	DVBT_ERR_LVL_PIP,
199 	DVBT_VAL_LVL_PIP,
200 	DVBT_CKOUTPAR_PID,
201 	DVBT_CKOUT_PWR_PID,
202 	DVBT_SYNC_LVL_PID,
203 	DVBT_ERR_LVL_PID,
204 	DVBT_VAL_LVL_PID,
205 	DVBT_SM_PASS,
206 	DVBT_UPDATE_REG_2,
207 	DVBT_BTHD_P3,
208 	DVBT_BTHD_D3,
209 	DVBT_FUNC4_REG0,
210 	DVBT_FUNC4_REG1,
211 	DVBT_FUNC4_REG2,
212 	DVBT_FUNC4_REG3,
213 	DVBT_FUNC4_REG4,
214 	DVBT_FUNC4_REG5,
215 	DVBT_FUNC4_REG6,
216 	DVBT_FUNC4_REG7,
217 	DVBT_FUNC4_REG8,
218 	DVBT_FUNC4_REG9,
219 	DVBT_FUNC4_REG10,
220 	DVBT_FUNC5_REG0,
221 	DVBT_FUNC5_REG1,
222 	DVBT_FUNC5_REG2,
223 	DVBT_FUNC5_REG3,
224 	DVBT_FUNC5_REG4,
225 	DVBT_FUNC5_REG5,
226 	DVBT_FUNC5_REG6,
227 	DVBT_FUNC5_REG7,
228 	DVBT_FUNC5_REG8,
229 	DVBT_FUNC5_REG9,
230 	DVBT_FUNC5_REG10,
231 	DVBT_FUNC5_REG11,
232 	DVBT_FUNC5_REG12,
233 	DVBT_FUNC5_REG13,
234 	DVBT_FUNC5_REG14,
235 	DVBT_FUNC5_REG15,
236 	DVBT_FUNC5_REG16,
237 	DVBT_FUNC5_REG17,
238 	DVBT_FUNC5_REG18,
239 	DVBT_AD7_SETTING,
240 	DVBT_RSSI_R,
241 	DVBT_ACI_DET_IND,
242 	DVBT_REG_MON,
243 	DVBT_REG_MONSEL,
244 	DVBT_REG_GPE,
245 	DVBT_REG_GPO,
246 	DVBT_REG_4MSEL,
247 	DVBT_TEST_REG_1,
248 	DVBT_TEST_REG_2,
249 	DVBT_TEST_REG_3,
250 	DVBT_TEST_REG_4,
251 	DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
252 };
253 
254 static const struct rtl2832_reg_value rtl2832_tuner_init_fc2580[] = {
255 	{DVBT_DAGC_TRG_VAL,             0x39},
256 	{DVBT_AGC_TARG_VAL_0,            0x0},
257 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
258 	{DVBT_AAGC_LOOP_GAIN,           0x16},
259 	{DVBT_LOOP_GAIN2_3_0,            0x6},
260 	{DVBT_LOOP_GAIN2_4,              0x1},
261 	{DVBT_LOOP_GAIN3,               0x16},
262 	{DVBT_VTOP1,                    0x35},
263 	{DVBT_VTOP2,                    0x21},
264 	{DVBT_VTOP3,                    0x21},
265 	{DVBT_KRF1,                      0x0},
266 	{DVBT_KRF2,                     0x40},
267 	{DVBT_KRF3,                     0x10},
268 	{DVBT_KRF4,                     0x10},
269 	{DVBT_IF_AGC_MIN,               0x80},
270 	{DVBT_IF_AGC_MAX,               0x7f},
271 	{DVBT_RF_AGC_MIN,               0x9c},
272 	{DVBT_RF_AGC_MAX,               0x7f},
273 	{DVBT_POLAR_RF_AGC,              0x0},
274 	{DVBT_POLAR_IF_AGC,              0x0},
275 	{DVBT_AD7_SETTING,            0xe9f4},
276 };
277 
278 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
279 	{DVBT_DAGC_TRG_VAL,             0x39},
280 	{DVBT_AGC_TARG_VAL_0,            0x0},
281 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
282 	{DVBT_AAGC_LOOP_GAIN,           0x16},
283 	{DVBT_LOOP_GAIN2_3_0,            0x6},
284 	{DVBT_LOOP_GAIN2_4,              0x1},
285 	{DVBT_LOOP_GAIN3,               0x16},
286 	{DVBT_VTOP1,                    0x35},
287 	{DVBT_VTOP2,                    0x21},
288 	{DVBT_VTOP3,                    0x21},
289 	{DVBT_KRF1,                      0x0},
290 	{DVBT_KRF2,                     0x40},
291 	{DVBT_KRF3,                     0x10},
292 	{DVBT_KRF4,                     0x10},
293 	{DVBT_IF_AGC_MIN,               0x80},
294 	{DVBT_IF_AGC_MAX,               0x7f},
295 	{DVBT_RF_AGC_MIN,               0x9c},
296 	{DVBT_RF_AGC_MAX,               0x7f},
297 	{DVBT_POLAR_RF_AGC,              0x0},
298 	{DVBT_POLAR_IF_AGC,              0x0},
299 	{DVBT_AD7_SETTING,            0xe9f4},
300 	{DVBT_OPT_ADC_IQ,                0x1},
301 	{DVBT_AD_AVI,                    0x0},
302 	{DVBT_AD_AVQ,                    0x0},
303 	{DVBT_SPEC_INV,                  0x0},
304 };
305 
306 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
307 	{DVBT_DAGC_TRG_VAL,             0x5a},
308 	{DVBT_AGC_TARG_VAL_0,            0x0},
309 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
310 	{DVBT_AAGC_LOOP_GAIN,           0x16},
311 	{DVBT_LOOP_GAIN2_3_0,            0x6},
312 	{DVBT_LOOP_GAIN2_4,              0x1},
313 	{DVBT_LOOP_GAIN3,               0x16},
314 	{DVBT_VTOP1,                    0x35},
315 	{DVBT_VTOP2,                    0x21},
316 	{DVBT_VTOP3,                    0x21},
317 	{DVBT_KRF1,                      0x0},
318 	{DVBT_KRF2,                     0x40},
319 	{DVBT_KRF3,                     0x10},
320 	{DVBT_KRF4,                     0x10},
321 	{DVBT_IF_AGC_MIN,               0x80},
322 	{DVBT_IF_AGC_MAX,               0x7f},
323 	{DVBT_RF_AGC_MIN,               0x80},
324 	{DVBT_RF_AGC_MAX,               0x7f},
325 	{DVBT_POLAR_RF_AGC,              0x0},
326 	{DVBT_POLAR_IF_AGC,              0x0},
327 	{DVBT_AD7_SETTING,            0xe9bf},
328 	{DVBT_EN_GI_PGA,                 0x0},
329 	{DVBT_THD_LOCK_UP,               0x0},
330 	{DVBT_THD_LOCK_DW,               0x0},
331 	{DVBT_THD_UP1,                  0x11},
332 	{DVBT_THD_DW1,                  0xef},
333 	{DVBT_INTER_CNT_LEN,             0xc},
334 	{DVBT_GI_PGA_STATE,              0x0},
335 	{DVBT_EN_AGC_PGA,                0x1},
336 	{DVBT_IF_AGC_MAN,                0x0},
337 	{DVBT_SPEC_INV,                  0x0},
338 };
339 
340 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
341 	{DVBT_DAGC_TRG_VAL,             0x5a},
342 	{DVBT_AGC_TARG_VAL_0,            0x0},
343 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
344 	{DVBT_AAGC_LOOP_GAIN,           0x18},
345 	{DVBT_LOOP_GAIN2_3_0,            0x8},
346 	{DVBT_LOOP_GAIN2_4,              0x1},
347 	{DVBT_LOOP_GAIN3,               0x18},
348 	{DVBT_VTOP1,                    0x35},
349 	{DVBT_VTOP2,                    0x21},
350 	{DVBT_VTOP3,                    0x21},
351 	{DVBT_KRF1,                      0x0},
352 	{DVBT_KRF2,                     0x40},
353 	{DVBT_KRF3,                     0x10},
354 	{DVBT_KRF4,                     0x10},
355 	{DVBT_IF_AGC_MIN,               0x80},
356 	{DVBT_IF_AGC_MAX,               0x7f},
357 	{DVBT_RF_AGC_MIN,               0x80},
358 	{DVBT_RF_AGC_MAX,               0x7f},
359 	{DVBT_POLAR_RF_AGC,              0x0},
360 	{DVBT_POLAR_IF_AGC,              0x0},
361 	{DVBT_AD7_SETTING,            0xe9d4},
362 	{DVBT_EN_GI_PGA,                 0x0},
363 	{DVBT_THD_LOCK_UP,               0x0},
364 	{DVBT_THD_LOCK_DW,               0x0},
365 	{DVBT_THD_UP1,                  0x14},
366 	{DVBT_THD_DW1,                  0xec},
367 	{DVBT_INTER_CNT_LEN,             0xc},
368 	{DVBT_GI_PGA_STATE,              0x0},
369 	{DVBT_EN_AGC_PGA,                0x1},
370 	{DVBT_REG_GPE,                   0x1},
371 	{DVBT_REG_GPO,                   0x1},
372 	{DVBT_REG_MONSEL,                0x1},
373 	{DVBT_REG_MON,                   0x1},
374 	{DVBT_REG_4MSEL,                 0x0},
375 	{DVBT_SPEC_INV,                  0x0},
376 };
377 
378 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
379 	{DVBT_DAGC_TRG_VAL,             0x39},
380 	{DVBT_AGC_TARG_VAL_0,            0x0},
381 	{DVBT_AGC_TARG_VAL_8_1,         0x40},
382 	{DVBT_AAGC_LOOP_GAIN,           0x16},
383 	{DVBT_LOOP_GAIN2_3_0,            0x8},
384 	{DVBT_LOOP_GAIN2_4,              0x1},
385 	{DVBT_LOOP_GAIN3,               0x18},
386 	{DVBT_VTOP1,                    0x35},
387 	{DVBT_VTOP2,                    0x21},
388 	{DVBT_VTOP3,                    0x21},
389 	{DVBT_KRF1,                      0x0},
390 	{DVBT_KRF2,                     0x40},
391 	{DVBT_KRF3,                     0x10},
392 	{DVBT_KRF4,                     0x10},
393 	{DVBT_IF_AGC_MIN,               0x80},
394 	{DVBT_IF_AGC_MAX,               0x7f},
395 	{DVBT_RF_AGC_MIN,               0x80},
396 	{DVBT_RF_AGC_MAX,               0x7f},
397 	{DVBT_POLAR_RF_AGC,              0x0},
398 	{DVBT_POLAR_IF_AGC,              0x0},
399 	{DVBT_AD7_SETTING,            0xe9f4},
400 	{DVBT_SPEC_INV,                  0x1},
401 };
402 
403 static const struct rtl2832_reg_value rtl2832_tuner_init_si2157[] = {
404 	{DVBT_DAGC_TRG_VAL,             0x39},
405 	{DVBT_AGC_TARG_VAL_0,            0x0},
406 	{DVBT_AGC_TARG_VAL_8_1,         0x40},
407 	{DVBT_AAGC_LOOP_GAIN,           0x16},
408 	{DVBT_LOOP_GAIN2_3_0,            0x8},
409 	{DVBT_LOOP_GAIN2_4,              0x1},
410 	{DVBT_LOOP_GAIN3,               0x18},
411 	{DVBT_VTOP1,                    0x35},
412 	{DVBT_VTOP2,                    0x21},
413 	{DVBT_VTOP3,                    0x21},
414 	{DVBT_KRF1,                      0x0},
415 	{DVBT_KRF2,                     0x40},
416 	{DVBT_KRF3,                     0x10},
417 	{DVBT_KRF4,                     0x10},
418 	{DVBT_IF_AGC_MIN,               0x80},
419 	{DVBT_IF_AGC_MAX,               0x7f},
420 	{DVBT_RF_AGC_MIN,               0x80},
421 	{DVBT_RF_AGC_MAX,               0x7f},
422 	{DVBT_POLAR_RF_AGC,              0x0},
423 	{DVBT_POLAR_IF_AGC,              0x0},
424 	{DVBT_AD7_SETTING,            0xe9f4},
425 	{DVBT_SPEC_INV,                  0x0},
426 };
427 
428 #endif /* RTL2832_PRIV_H */
429