1 /* 2 * Realtek RTL2832 DVB-T demodulator driver 3 * 4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com> 5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #ifndef RTL2832_PRIV_H 23 #define RTL2832_PRIV_H 24 25 #include <linux/regmap.h> 26 #include <linux/math64.h> 27 #include <linux/bitops.h> 28 29 #include "dvb_frontend.h" 30 #include "dvb_math.h" 31 #include "rtl2832.h" 32 33 struct rtl2832_dev { 34 struct rtl2832_platform_data *pdata; 35 struct i2c_client *client; 36 struct mutex regmap_mutex; 37 struct regmap_config regmap_config; 38 struct regmap *regmap; 39 struct i2c_adapter *i2c_adapter_tuner; 40 struct dvb_frontend fe; 41 struct delayed_work stat_work; 42 enum fe_status fe_status; 43 u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */ 44 u64 post_bit_error; 45 u64 post_bit_count; 46 bool sleeping; 47 struct delayed_work i2c_gate_work; 48 unsigned long filters; /* PID filter */ 49 }; 50 51 struct rtl2832_reg_entry { 52 u16 start_address; 53 u8 msb; 54 u8 lsb; 55 }; 56 57 struct rtl2832_reg_value { 58 int reg; 59 u32 value; 60 }; 61 62 /* Demod register bit names */ 63 enum DVBT_REG_BIT_NAME { 64 DVBT_SOFT_RST, 65 DVBT_IIC_REPEAT, 66 DVBT_TR_WAIT_MIN_8K, 67 DVBT_RSD_BER_FAIL_VAL, 68 DVBT_EN_BK_TRK, 69 DVBT_REG_PI, 70 DVBT_REG_PFREQ_1_0, 71 DVBT_PD_DA8, 72 DVBT_LOCK_TH, 73 DVBT_BER_PASS_SCAL, 74 DVBT_CE_FFSM_BYPASS, 75 DVBT_ALPHAIIR_N, 76 DVBT_ALPHAIIR_DIF, 77 DVBT_EN_TRK_SPAN, 78 DVBT_LOCK_TH_LEN, 79 DVBT_CCI_THRE, 80 DVBT_CCI_MON_SCAL, 81 DVBT_CCI_M0, 82 DVBT_CCI_M1, 83 DVBT_CCI_M2, 84 DVBT_CCI_M3, 85 DVBT_SPEC_INIT_0, 86 DVBT_SPEC_INIT_1, 87 DVBT_SPEC_INIT_2, 88 DVBT_AD_EN_REG, 89 DVBT_AD_EN_REG1, 90 DVBT_EN_BBIN, 91 DVBT_MGD_THD0, 92 DVBT_MGD_THD1, 93 DVBT_MGD_THD2, 94 DVBT_MGD_THD3, 95 DVBT_MGD_THD4, 96 DVBT_MGD_THD5, 97 DVBT_MGD_THD6, 98 DVBT_MGD_THD7, 99 DVBT_EN_CACQ_NOTCH, 100 DVBT_AD_AV_REF, 101 DVBT_PIP_ON, 102 DVBT_SCALE1_B92, 103 DVBT_SCALE1_B93, 104 DVBT_SCALE1_BA7, 105 DVBT_SCALE1_BA9, 106 DVBT_SCALE1_BAA, 107 DVBT_SCALE1_BAB, 108 DVBT_SCALE1_BAC, 109 DVBT_SCALE1_BB0, 110 DVBT_SCALE1_BB1, 111 DVBT_KB_P1, 112 DVBT_KB_P2, 113 DVBT_KB_P3, 114 DVBT_OPT_ADC_IQ, 115 DVBT_AD_AVI, 116 DVBT_AD_AVQ, 117 DVBT_K1_CR_STEP12, 118 DVBT_TRK_KS_P2, 119 DVBT_TRK_KS_I2, 120 DVBT_TR_THD_SET2, 121 DVBT_TRK_KC_P2, 122 DVBT_TRK_KC_I2, 123 DVBT_CR_THD_SET2, 124 DVBT_PSET_IFFREQ, 125 DVBT_SPEC_INV, 126 DVBT_BW_INDEX, 127 DVBT_RSAMP_RATIO, 128 DVBT_CFREQ_OFF_RATIO, 129 DVBT_FSM_STAGE, 130 DVBT_RX_CONSTEL, 131 DVBT_RX_HIER, 132 DVBT_RX_C_RATE_LP, 133 DVBT_RX_C_RATE_HP, 134 DVBT_GI_IDX, 135 DVBT_FFT_MODE_IDX, 136 DVBT_RSD_BER_EST, 137 DVBT_CE_EST_EVM, 138 DVBT_RF_AGC_VAL, 139 DVBT_IF_AGC_VAL, 140 DVBT_DAGC_VAL, 141 DVBT_SFREQ_OFF, 142 DVBT_CFREQ_OFF, 143 DVBT_POLAR_RF_AGC, 144 DVBT_POLAR_IF_AGC, 145 DVBT_AAGC_HOLD, 146 DVBT_EN_RF_AGC, 147 DVBT_EN_IF_AGC, 148 DVBT_IF_AGC_MIN, 149 DVBT_IF_AGC_MAX, 150 DVBT_RF_AGC_MIN, 151 DVBT_RF_AGC_MAX, 152 DVBT_IF_AGC_MAN, 153 DVBT_IF_AGC_MAN_VAL, 154 DVBT_RF_AGC_MAN, 155 DVBT_RF_AGC_MAN_VAL, 156 DVBT_DAGC_TRG_VAL, 157 DVBT_AGC_TARG_VAL, 158 DVBT_LOOP_GAIN_3_0, 159 DVBT_LOOP_GAIN_4, 160 DVBT_VTOP, 161 DVBT_KRF, 162 DVBT_AGC_TARG_VAL_0, 163 DVBT_AGC_TARG_VAL_8_1, 164 DVBT_AAGC_LOOP_GAIN, 165 DVBT_LOOP_GAIN2_3_0, 166 DVBT_LOOP_GAIN2_4, 167 DVBT_LOOP_GAIN3, 168 DVBT_VTOP1, 169 DVBT_VTOP2, 170 DVBT_VTOP3, 171 DVBT_KRF1, 172 DVBT_KRF2, 173 DVBT_KRF3, 174 DVBT_KRF4, 175 DVBT_EN_GI_PGA, 176 DVBT_THD_LOCK_UP, 177 DVBT_THD_LOCK_DW, 178 DVBT_THD_UP1, 179 DVBT_THD_DW1, 180 DVBT_INTER_CNT_LEN, 181 DVBT_GI_PGA_STATE, 182 DVBT_EN_AGC_PGA, 183 DVBT_CKOUTPAR, 184 DVBT_CKOUT_PWR, 185 DVBT_SYNC_DUR, 186 DVBT_ERR_DUR, 187 DVBT_SYNC_LVL, 188 DVBT_ERR_LVL, 189 DVBT_VAL_LVL, 190 DVBT_SERIAL, 191 DVBT_SER_LSB, 192 DVBT_CDIV_PH0, 193 DVBT_CDIV_PH1, 194 DVBT_MPEG_IO_OPT_2_2, 195 DVBT_MPEG_IO_OPT_1_0, 196 DVBT_CKOUTPAR_PIP, 197 DVBT_CKOUT_PWR_PIP, 198 DVBT_SYNC_LVL_PIP, 199 DVBT_ERR_LVL_PIP, 200 DVBT_VAL_LVL_PIP, 201 DVBT_CKOUTPAR_PID, 202 DVBT_CKOUT_PWR_PID, 203 DVBT_SYNC_LVL_PID, 204 DVBT_ERR_LVL_PID, 205 DVBT_VAL_LVL_PID, 206 DVBT_SM_PASS, 207 DVBT_UPDATE_REG_2, 208 DVBT_BTHD_P3, 209 DVBT_BTHD_D3, 210 DVBT_FUNC4_REG0, 211 DVBT_FUNC4_REG1, 212 DVBT_FUNC4_REG2, 213 DVBT_FUNC4_REG3, 214 DVBT_FUNC4_REG4, 215 DVBT_FUNC4_REG5, 216 DVBT_FUNC4_REG6, 217 DVBT_FUNC4_REG7, 218 DVBT_FUNC4_REG8, 219 DVBT_FUNC4_REG9, 220 DVBT_FUNC4_REG10, 221 DVBT_FUNC5_REG0, 222 DVBT_FUNC5_REG1, 223 DVBT_FUNC5_REG2, 224 DVBT_FUNC5_REG3, 225 DVBT_FUNC5_REG4, 226 DVBT_FUNC5_REG5, 227 DVBT_FUNC5_REG6, 228 DVBT_FUNC5_REG7, 229 DVBT_FUNC5_REG8, 230 DVBT_FUNC5_REG9, 231 DVBT_FUNC5_REG10, 232 DVBT_FUNC5_REG11, 233 DVBT_FUNC5_REG12, 234 DVBT_FUNC5_REG13, 235 DVBT_FUNC5_REG14, 236 DVBT_FUNC5_REG15, 237 DVBT_FUNC5_REG16, 238 DVBT_FUNC5_REG17, 239 DVBT_FUNC5_REG18, 240 DVBT_AD7_SETTING, 241 DVBT_RSSI_R, 242 DVBT_ACI_DET_IND, 243 DVBT_REG_MON, 244 DVBT_REG_MONSEL, 245 DVBT_REG_GPE, 246 DVBT_REG_GPO, 247 DVBT_REG_4MSEL, 248 DVBT_TEST_REG_1, 249 DVBT_TEST_REG_2, 250 DVBT_TEST_REG_3, 251 DVBT_TEST_REG_4, 252 DVBT_REG_BIT_NAME_ITEM_TERMINATOR, 253 }; 254 255 static const struct rtl2832_reg_value rtl2832_tuner_init_fc2580[] = { 256 {DVBT_DAGC_TRG_VAL, 0x39}, 257 {DVBT_AGC_TARG_VAL_0, 0x0}, 258 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 259 {DVBT_AAGC_LOOP_GAIN, 0x16}, 260 {DVBT_LOOP_GAIN2_3_0, 0x6}, 261 {DVBT_LOOP_GAIN2_4, 0x1}, 262 {DVBT_LOOP_GAIN3, 0x16}, 263 {DVBT_VTOP1, 0x35}, 264 {DVBT_VTOP2, 0x21}, 265 {DVBT_VTOP3, 0x21}, 266 {DVBT_KRF1, 0x0}, 267 {DVBT_KRF2, 0x40}, 268 {DVBT_KRF3, 0x10}, 269 {DVBT_KRF4, 0x10}, 270 {DVBT_IF_AGC_MIN, 0x80}, 271 {DVBT_IF_AGC_MAX, 0x7f}, 272 {DVBT_RF_AGC_MIN, 0x9c}, 273 {DVBT_RF_AGC_MAX, 0x7f}, 274 {DVBT_POLAR_RF_AGC, 0x0}, 275 {DVBT_POLAR_IF_AGC, 0x0}, 276 {DVBT_AD7_SETTING, 0xe9f4}, 277 }; 278 279 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = { 280 {DVBT_DAGC_TRG_VAL, 0x39}, 281 {DVBT_AGC_TARG_VAL_0, 0x0}, 282 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 283 {DVBT_AAGC_LOOP_GAIN, 0x16}, 284 {DVBT_LOOP_GAIN2_3_0, 0x6}, 285 {DVBT_LOOP_GAIN2_4, 0x1}, 286 {DVBT_LOOP_GAIN3, 0x16}, 287 {DVBT_VTOP1, 0x35}, 288 {DVBT_VTOP2, 0x21}, 289 {DVBT_VTOP3, 0x21}, 290 {DVBT_KRF1, 0x0}, 291 {DVBT_KRF2, 0x40}, 292 {DVBT_KRF3, 0x10}, 293 {DVBT_KRF4, 0x10}, 294 {DVBT_IF_AGC_MIN, 0x80}, 295 {DVBT_IF_AGC_MAX, 0x7f}, 296 {DVBT_RF_AGC_MIN, 0x9c}, 297 {DVBT_RF_AGC_MAX, 0x7f}, 298 {DVBT_POLAR_RF_AGC, 0x0}, 299 {DVBT_POLAR_IF_AGC, 0x0}, 300 {DVBT_AD7_SETTING, 0xe9f4}, 301 {DVBT_OPT_ADC_IQ, 0x1}, 302 {DVBT_AD_AVI, 0x0}, 303 {DVBT_AD_AVQ, 0x0}, 304 {DVBT_SPEC_INV, 0x0}, 305 }; 306 307 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { 308 {DVBT_DAGC_TRG_VAL, 0x5a}, 309 {DVBT_AGC_TARG_VAL_0, 0x0}, 310 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 311 {DVBT_AAGC_LOOP_GAIN, 0x16}, 312 {DVBT_LOOP_GAIN2_3_0, 0x6}, 313 {DVBT_LOOP_GAIN2_4, 0x1}, 314 {DVBT_LOOP_GAIN3, 0x16}, 315 {DVBT_VTOP1, 0x35}, 316 {DVBT_VTOP2, 0x21}, 317 {DVBT_VTOP3, 0x21}, 318 {DVBT_KRF1, 0x0}, 319 {DVBT_KRF2, 0x40}, 320 {DVBT_KRF3, 0x10}, 321 {DVBT_KRF4, 0x10}, 322 {DVBT_IF_AGC_MIN, 0x80}, 323 {DVBT_IF_AGC_MAX, 0x7f}, 324 {DVBT_RF_AGC_MIN, 0x80}, 325 {DVBT_RF_AGC_MAX, 0x7f}, 326 {DVBT_POLAR_RF_AGC, 0x0}, 327 {DVBT_POLAR_IF_AGC, 0x0}, 328 {DVBT_AD7_SETTING, 0xe9bf}, 329 {DVBT_EN_GI_PGA, 0x0}, 330 {DVBT_THD_LOCK_UP, 0x0}, 331 {DVBT_THD_LOCK_DW, 0x0}, 332 {DVBT_THD_UP1, 0x11}, 333 {DVBT_THD_DW1, 0xef}, 334 {DVBT_INTER_CNT_LEN, 0xc}, 335 {DVBT_GI_PGA_STATE, 0x0}, 336 {DVBT_EN_AGC_PGA, 0x1}, 337 {DVBT_IF_AGC_MAN, 0x0}, 338 {DVBT_SPEC_INV, 0x0}, 339 }; 340 341 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { 342 {DVBT_DAGC_TRG_VAL, 0x5a}, 343 {DVBT_AGC_TARG_VAL_0, 0x0}, 344 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 345 {DVBT_AAGC_LOOP_GAIN, 0x18}, 346 {DVBT_LOOP_GAIN2_3_0, 0x8}, 347 {DVBT_LOOP_GAIN2_4, 0x1}, 348 {DVBT_LOOP_GAIN3, 0x18}, 349 {DVBT_VTOP1, 0x35}, 350 {DVBT_VTOP2, 0x21}, 351 {DVBT_VTOP3, 0x21}, 352 {DVBT_KRF1, 0x0}, 353 {DVBT_KRF2, 0x40}, 354 {DVBT_KRF3, 0x10}, 355 {DVBT_KRF4, 0x10}, 356 {DVBT_IF_AGC_MIN, 0x80}, 357 {DVBT_IF_AGC_MAX, 0x7f}, 358 {DVBT_RF_AGC_MIN, 0x80}, 359 {DVBT_RF_AGC_MAX, 0x7f}, 360 {DVBT_POLAR_RF_AGC, 0x0}, 361 {DVBT_POLAR_IF_AGC, 0x0}, 362 {DVBT_AD7_SETTING, 0xe9d4}, 363 {DVBT_EN_GI_PGA, 0x0}, 364 {DVBT_THD_LOCK_UP, 0x0}, 365 {DVBT_THD_LOCK_DW, 0x0}, 366 {DVBT_THD_UP1, 0x14}, 367 {DVBT_THD_DW1, 0xec}, 368 {DVBT_INTER_CNT_LEN, 0xc}, 369 {DVBT_GI_PGA_STATE, 0x0}, 370 {DVBT_EN_AGC_PGA, 0x1}, 371 {DVBT_REG_GPE, 0x1}, 372 {DVBT_REG_GPO, 0x1}, 373 {DVBT_REG_MONSEL, 0x1}, 374 {DVBT_REG_MON, 0x1}, 375 {DVBT_REG_4MSEL, 0x0}, 376 {DVBT_SPEC_INV, 0x0}, 377 }; 378 379 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = { 380 {DVBT_DAGC_TRG_VAL, 0x39}, 381 {DVBT_AGC_TARG_VAL_0, 0x0}, 382 {DVBT_AGC_TARG_VAL_8_1, 0x40}, 383 {DVBT_AAGC_LOOP_GAIN, 0x16}, 384 {DVBT_LOOP_GAIN2_3_0, 0x8}, 385 {DVBT_LOOP_GAIN2_4, 0x1}, 386 {DVBT_LOOP_GAIN3, 0x18}, 387 {DVBT_VTOP1, 0x35}, 388 {DVBT_VTOP2, 0x21}, 389 {DVBT_VTOP3, 0x21}, 390 {DVBT_KRF1, 0x0}, 391 {DVBT_KRF2, 0x40}, 392 {DVBT_KRF3, 0x10}, 393 {DVBT_KRF4, 0x10}, 394 {DVBT_IF_AGC_MIN, 0x80}, 395 {DVBT_IF_AGC_MAX, 0x7f}, 396 {DVBT_RF_AGC_MIN, 0x80}, 397 {DVBT_RF_AGC_MAX, 0x7f}, 398 {DVBT_POLAR_RF_AGC, 0x0}, 399 {DVBT_POLAR_IF_AGC, 0x0}, 400 {DVBT_AD7_SETTING, 0xe9f4}, 401 {DVBT_SPEC_INV, 0x1}, 402 }; 403 404 static const struct rtl2832_reg_value rtl2832_tuner_init_si2157[] = { 405 {DVBT_DAGC_TRG_VAL, 0x39}, 406 {DVBT_AGC_TARG_VAL_0, 0x0}, 407 {DVBT_AGC_TARG_VAL_8_1, 0x40}, 408 {DVBT_AAGC_LOOP_GAIN, 0x16}, 409 {DVBT_LOOP_GAIN2_3_0, 0x8}, 410 {DVBT_LOOP_GAIN2_4, 0x1}, 411 {DVBT_LOOP_GAIN3, 0x18}, 412 {DVBT_VTOP1, 0x35}, 413 {DVBT_VTOP2, 0x21}, 414 {DVBT_VTOP3, 0x21}, 415 {DVBT_KRF1, 0x0}, 416 {DVBT_KRF2, 0x40}, 417 {DVBT_KRF3, 0x10}, 418 {DVBT_KRF4, 0x10}, 419 {DVBT_IF_AGC_MIN, 0x80}, 420 {DVBT_IF_AGC_MAX, 0x7f}, 421 {DVBT_RF_AGC_MIN, 0x80}, 422 {DVBT_RF_AGC_MAX, 0x7f}, 423 {DVBT_POLAR_RF_AGC, 0x0}, 424 {DVBT_POLAR_IF_AGC, 0x0}, 425 {DVBT_AD7_SETTING, 0xe9f4}, 426 {DVBT_SPEC_INV, 0x0}, 427 }; 428 429 #endif /* RTL2832_PRIV_H */ 430