1 /* 2 * Realtek RTL2832 DVB-T demodulator driver 3 * 4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef RTL2832_PRIV_H 22 #define RTL2832_PRIV_H 23 24 #include "dvb_frontend.h" 25 #include "rtl2832.h" 26 27 struct rtl2832_priv { 28 struct i2c_adapter *i2c; 29 struct dvb_frontend fe; 30 struct rtl2832_config cfg; 31 32 bool i2c_gate_state; 33 bool sleeping; 34 35 u8 tuner; 36 u8 page; /* active register page */ 37 }; 38 39 struct rtl2832_reg_entry { 40 u8 page; 41 u8 start_address; 42 u8 msb; 43 u8 lsb; 44 }; 45 46 struct rtl2832_reg_value { 47 int reg; 48 u32 value; 49 }; 50 51 52 /* Demod register bit names */ 53 enum DVBT_REG_BIT_NAME { 54 DVBT_SOFT_RST, 55 DVBT_IIC_REPEAT, 56 DVBT_TR_WAIT_MIN_8K, 57 DVBT_RSD_BER_FAIL_VAL, 58 DVBT_EN_BK_TRK, 59 DVBT_REG_PI, 60 DVBT_REG_PFREQ_1_0, 61 DVBT_PD_DA8, 62 DVBT_LOCK_TH, 63 DVBT_BER_PASS_SCAL, 64 DVBT_CE_FFSM_BYPASS, 65 DVBT_ALPHAIIR_N, 66 DVBT_ALPHAIIR_DIF, 67 DVBT_EN_TRK_SPAN, 68 DVBT_LOCK_TH_LEN, 69 DVBT_CCI_THRE, 70 DVBT_CCI_MON_SCAL, 71 DVBT_CCI_M0, 72 DVBT_CCI_M1, 73 DVBT_CCI_M2, 74 DVBT_CCI_M3, 75 DVBT_SPEC_INIT_0, 76 DVBT_SPEC_INIT_1, 77 DVBT_SPEC_INIT_2, 78 DVBT_AD_EN_REG, 79 DVBT_AD_EN_REG1, 80 DVBT_EN_BBIN, 81 DVBT_MGD_THD0, 82 DVBT_MGD_THD1, 83 DVBT_MGD_THD2, 84 DVBT_MGD_THD3, 85 DVBT_MGD_THD4, 86 DVBT_MGD_THD5, 87 DVBT_MGD_THD6, 88 DVBT_MGD_THD7, 89 DVBT_EN_CACQ_NOTCH, 90 DVBT_AD_AV_REF, 91 DVBT_PIP_ON, 92 DVBT_SCALE1_B92, 93 DVBT_SCALE1_B93, 94 DVBT_SCALE1_BA7, 95 DVBT_SCALE1_BA9, 96 DVBT_SCALE1_BAA, 97 DVBT_SCALE1_BAB, 98 DVBT_SCALE1_BAC, 99 DVBT_SCALE1_BB0, 100 DVBT_SCALE1_BB1, 101 DVBT_KB_P1, 102 DVBT_KB_P2, 103 DVBT_KB_P3, 104 DVBT_OPT_ADC_IQ, 105 DVBT_AD_AVI, 106 DVBT_AD_AVQ, 107 DVBT_K1_CR_STEP12, 108 DVBT_TRK_KS_P2, 109 DVBT_TRK_KS_I2, 110 DVBT_TR_THD_SET2, 111 DVBT_TRK_KC_P2, 112 DVBT_TRK_KC_I2, 113 DVBT_CR_THD_SET2, 114 DVBT_PSET_IFFREQ, 115 DVBT_SPEC_INV, 116 DVBT_BW_INDEX, 117 DVBT_RSAMP_RATIO, 118 DVBT_CFREQ_OFF_RATIO, 119 DVBT_FSM_STAGE, 120 DVBT_RX_CONSTEL, 121 DVBT_RX_HIER, 122 DVBT_RX_C_RATE_LP, 123 DVBT_RX_C_RATE_HP, 124 DVBT_GI_IDX, 125 DVBT_FFT_MODE_IDX, 126 DVBT_RSD_BER_EST, 127 DVBT_CE_EST_EVM, 128 DVBT_RF_AGC_VAL, 129 DVBT_IF_AGC_VAL, 130 DVBT_DAGC_VAL, 131 DVBT_SFREQ_OFF, 132 DVBT_CFREQ_OFF, 133 DVBT_POLAR_RF_AGC, 134 DVBT_POLAR_IF_AGC, 135 DVBT_AAGC_HOLD, 136 DVBT_EN_RF_AGC, 137 DVBT_EN_IF_AGC, 138 DVBT_IF_AGC_MIN, 139 DVBT_IF_AGC_MAX, 140 DVBT_RF_AGC_MIN, 141 DVBT_RF_AGC_MAX, 142 DVBT_IF_AGC_MAN, 143 DVBT_IF_AGC_MAN_VAL, 144 DVBT_RF_AGC_MAN, 145 DVBT_RF_AGC_MAN_VAL, 146 DVBT_DAGC_TRG_VAL, 147 DVBT_AGC_TARG_VAL, 148 DVBT_LOOP_GAIN_3_0, 149 DVBT_LOOP_GAIN_4, 150 DVBT_VTOP, 151 DVBT_KRF, 152 DVBT_AGC_TARG_VAL_0, 153 DVBT_AGC_TARG_VAL_8_1, 154 DVBT_AAGC_LOOP_GAIN, 155 DVBT_LOOP_GAIN2_3_0, 156 DVBT_LOOP_GAIN2_4, 157 DVBT_LOOP_GAIN3, 158 DVBT_VTOP1, 159 DVBT_VTOP2, 160 DVBT_VTOP3, 161 DVBT_KRF1, 162 DVBT_KRF2, 163 DVBT_KRF3, 164 DVBT_KRF4, 165 DVBT_EN_GI_PGA, 166 DVBT_THD_LOCK_UP, 167 DVBT_THD_LOCK_DW, 168 DVBT_THD_UP1, 169 DVBT_THD_DW1, 170 DVBT_INTER_CNT_LEN, 171 DVBT_GI_PGA_STATE, 172 DVBT_EN_AGC_PGA, 173 DVBT_CKOUTPAR, 174 DVBT_CKOUT_PWR, 175 DVBT_SYNC_DUR, 176 DVBT_ERR_DUR, 177 DVBT_SYNC_LVL, 178 DVBT_ERR_LVL, 179 DVBT_VAL_LVL, 180 DVBT_SERIAL, 181 DVBT_SER_LSB, 182 DVBT_CDIV_PH0, 183 DVBT_CDIV_PH1, 184 DVBT_MPEG_IO_OPT_2_2, 185 DVBT_MPEG_IO_OPT_1_0, 186 DVBT_CKOUTPAR_PIP, 187 DVBT_CKOUT_PWR_PIP, 188 DVBT_SYNC_LVL_PIP, 189 DVBT_ERR_LVL_PIP, 190 DVBT_VAL_LVL_PIP, 191 DVBT_CKOUTPAR_PID, 192 DVBT_CKOUT_PWR_PID, 193 DVBT_SYNC_LVL_PID, 194 DVBT_ERR_LVL_PID, 195 DVBT_VAL_LVL_PID, 196 DVBT_SM_PASS, 197 DVBT_UPDATE_REG_2, 198 DVBT_BTHD_P3, 199 DVBT_BTHD_D3, 200 DVBT_FUNC4_REG0, 201 DVBT_FUNC4_REG1, 202 DVBT_FUNC4_REG2, 203 DVBT_FUNC4_REG3, 204 DVBT_FUNC4_REG4, 205 DVBT_FUNC4_REG5, 206 DVBT_FUNC4_REG6, 207 DVBT_FUNC4_REG7, 208 DVBT_FUNC4_REG8, 209 DVBT_FUNC4_REG9, 210 DVBT_FUNC4_REG10, 211 DVBT_FUNC5_REG0, 212 DVBT_FUNC5_REG1, 213 DVBT_FUNC5_REG2, 214 DVBT_FUNC5_REG3, 215 DVBT_FUNC5_REG4, 216 DVBT_FUNC5_REG5, 217 DVBT_FUNC5_REG6, 218 DVBT_FUNC5_REG7, 219 DVBT_FUNC5_REG8, 220 DVBT_FUNC5_REG9, 221 DVBT_FUNC5_REG10, 222 DVBT_FUNC5_REG11, 223 DVBT_FUNC5_REG12, 224 DVBT_FUNC5_REG13, 225 DVBT_FUNC5_REG14, 226 DVBT_FUNC5_REG15, 227 DVBT_FUNC5_REG16, 228 DVBT_FUNC5_REG17, 229 DVBT_FUNC5_REG18, 230 DVBT_AD7_SETTING, 231 DVBT_RSSI_R, 232 DVBT_ACI_DET_IND, 233 DVBT_REG_MON, 234 DVBT_REG_MONSEL, 235 DVBT_REG_GPE, 236 DVBT_REG_GPO, 237 DVBT_REG_4MSEL, 238 DVBT_TEST_REG_1, 239 DVBT_TEST_REG_2, 240 DVBT_TEST_REG_3, 241 DVBT_TEST_REG_4, 242 DVBT_REG_BIT_NAME_ITEM_TERMINATOR, 243 }; 244 245 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = { 246 {DVBT_DAGC_TRG_VAL, 0x39}, 247 {DVBT_AGC_TARG_VAL_0, 0x0}, 248 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 249 {DVBT_AAGC_LOOP_GAIN, 0x16}, 250 {DVBT_LOOP_GAIN2_3_0, 0x6}, 251 {DVBT_LOOP_GAIN2_4, 0x1}, 252 {DVBT_LOOP_GAIN3, 0x16}, 253 {DVBT_VTOP1, 0x35}, 254 {DVBT_VTOP2, 0x21}, 255 {DVBT_VTOP3, 0x21}, 256 {DVBT_KRF1, 0x0}, 257 {DVBT_KRF2, 0x40}, 258 {DVBT_KRF3, 0x10}, 259 {DVBT_KRF4, 0x10}, 260 {DVBT_IF_AGC_MIN, 0x80}, 261 {DVBT_IF_AGC_MAX, 0x7f}, 262 {DVBT_RF_AGC_MIN, 0x9c}, 263 {DVBT_RF_AGC_MAX, 0x7f}, 264 {DVBT_POLAR_RF_AGC, 0x0}, 265 {DVBT_POLAR_IF_AGC, 0x0}, 266 {DVBT_AD7_SETTING, 0xe9f4}, 267 {DVBT_OPT_ADC_IQ, 0x1}, 268 {DVBT_AD_AVI, 0x0}, 269 {DVBT_AD_AVQ, 0x0}, 270 {DVBT_SPEC_INV, 0x0}, 271 }; 272 273 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { 274 {DVBT_DAGC_TRG_VAL, 0x5a}, 275 {DVBT_AGC_TARG_VAL_0, 0x0}, 276 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 277 {DVBT_AAGC_LOOP_GAIN, 0x16}, 278 {DVBT_LOOP_GAIN2_3_0, 0x6}, 279 {DVBT_LOOP_GAIN2_4, 0x1}, 280 {DVBT_LOOP_GAIN3, 0x16}, 281 {DVBT_VTOP1, 0x35}, 282 {DVBT_VTOP2, 0x21}, 283 {DVBT_VTOP3, 0x21}, 284 {DVBT_KRF1, 0x0}, 285 {DVBT_KRF2, 0x40}, 286 {DVBT_KRF3, 0x10}, 287 {DVBT_KRF4, 0x10}, 288 {DVBT_IF_AGC_MIN, 0x80}, 289 {DVBT_IF_AGC_MAX, 0x7f}, 290 {DVBT_RF_AGC_MIN, 0x80}, 291 {DVBT_RF_AGC_MAX, 0x7f}, 292 {DVBT_POLAR_RF_AGC, 0x0}, 293 {DVBT_POLAR_IF_AGC, 0x0}, 294 {DVBT_AD7_SETTING, 0xe9bf}, 295 {DVBT_EN_GI_PGA, 0x0}, 296 {DVBT_THD_LOCK_UP, 0x0}, 297 {DVBT_THD_LOCK_DW, 0x0}, 298 {DVBT_THD_UP1, 0x11}, 299 {DVBT_THD_DW1, 0xef}, 300 {DVBT_INTER_CNT_LEN, 0xc}, 301 {DVBT_GI_PGA_STATE, 0x0}, 302 {DVBT_EN_AGC_PGA, 0x1}, 303 {DVBT_IF_AGC_MAN, 0x0}, 304 {DVBT_SPEC_INV, 0x0}, 305 }; 306 307 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { 308 {DVBT_DAGC_TRG_VAL, 0x5a}, 309 {DVBT_AGC_TARG_VAL_0, 0x0}, 310 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 311 {DVBT_AAGC_LOOP_GAIN, 0x18}, 312 {DVBT_LOOP_GAIN2_3_0, 0x8}, 313 {DVBT_LOOP_GAIN2_4, 0x1}, 314 {DVBT_LOOP_GAIN3, 0x18}, 315 {DVBT_VTOP1, 0x35}, 316 {DVBT_VTOP2, 0x21}, 317 {DVBT_VTOP3, 0x21}, 318 {DVBT_KRF1, 0x0}, 319 {DVBT_KRF2, 0x40}, 320 {DVBT_KRF3, 0x10}, 321 {DVBT_KRF4, 0x10}, 322 {DVBT_IF_AGC_MIN, 0x80}, 323 {DVBT_IF_AGC_MAX, 0x7f}, 324 {DVBT_RF_AGC_MIN, 0x80}, 325 {DVBT_RF_AGC_MAX, 0x7f}, 326 {DVBT_POLAR_RF_AGC, 0x0}, 327 {DVBT_POLAR_IF_AGC, 0x0}, 328 {DVBT_AD7_SETTING, 0xe9d4}, 329 {DVBT_EN_GI_PGA, 0x0}, 330 {DVBT_THD_LOCK_UP, 0x0}, 331 {DVBT_THD_LOCK_DW, 0x0}, 332 {DVBT_THD_UP1, 0x14}, 333 {DVBT_THD_DW1, 0xec}, 334 {DVBT_INTER_CNT_LEN, 0xc}, 335 {DVBT_GI_PGA_STATE, 0x0}, 336 {DVBT_EN_AGC_PGA, 0x1}, 337 {DVBT_REG_GPE, 0x1}, 338 {DVBT_REG_GPO, 0x1}, 339 {DVBT_REG_MONSEL, 0x1}, 340 {DVBT_REG_MON, 0x1}, 341 {DVBT_REG_4MSEL, 0x0}, 342 {DVBT_SPEC_INV, 0x0}, 343 }; 344 345 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = { 346 {DVBT_DAGC_TRG_VAL, 0x39}, 347 {DVBT_AGC_TARG_VAL_0, 0x0}, 348 {DVBT_AGC_TARG_VAL_8_1, 0x40}, 349 {DVBT_AAGC_LOOP_GAIN, 0x16}, 350 {DVBT_LOOP_GAIN2_3_0, 0x8}, 351 {DVBT_LOOP_GAIN2_4, 0x1}, 352 {DVBT_LOOP_GAIN3, 0x18}, 353 {DVBT_VTOP1, 0x35}, 354 {DVBT_VTOP2, 0x21}, 355 {DVBT_VTOP3, 0x21}, 356 {DVBT_KRF1, 0x0}, 357 {DVBT_KRF2, 0x40}, 358 {DVBT_KRF3, 0x10}, 359 {DVBT_KRF4, 0x10}, 360 {DVBT_IF_AGC_MIN, 0x80}, 361 {DVBT_IF_AGC_MAX, 0x7f}, 362 {DVBT_RF_AGC_MIN, 0x80}, 363 {DVBT_RF_AGC_MAX, 0x7f}, 364 {DVBT_POLAR_RF_AGC, 0x0}, 365 {DVBT_POLAR_IF_AGC, 0x0}, 366 {DVBT_AD7_SETTING, 0xe9f4}, 367 {DVBT_SPEC_INV, 0x1}, 368 }; 369 370 #endif /* RTL2832_PRIV_H */ 371