1 /*
2  * Realtek RTL2832 DVB-T demodulator driver
3  *
4  * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5  * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
6  *
7  *	This program is free software; you can redistribute it and/or modify
8  *	it under the terms of the GNU General Public License as published by
9  *	the Free Software Foundation; either version 2 of the License, or
10  *	(at your option) any later version.
11  *
12  *	This program is distributed in the hope that it will be useful,
13  *	but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *	GNU General Public License for more details.
16  *
17  *	You should have received a copy of the GNU General Public License along
18  *	with this program; if not, write to the Free Software Foundation, Inc.,
19  *	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20  */
21 
22 #ifndef RTL2832_PRIV_H
23 #define RTL2832_PRIV_H
24 
25 #include <linux/regmap.h>
26 #include <linux/math64.h>
27 #include <linux/bitops.h>
28 
29 #include "dvb_frontend.h"
30 #include "dvb_math.h"
31 #include "rtl2832.h"
32 
33 struct rtl2832_dev {
34 	struct rtl2832_platform_data *pdata;
35 	struct i2c_client *client;
36 	struct regmap_config regmap_config;
37 	struct regmap *regmap;
38 	struct i2c_mux_core *muxc;
39 	struct dvb_frontend fe;
40 	enum fe_status fe_status;
41 	u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
42 	u64 post_bit_error;
43 	u64 post_bit_count;
44 	bool sleeping;
45 	struct delayed_work i2c_gate_work;
46 	unsigned long filters; /* PID filter */
47 };
48 
49 struct rtl2832_reg_entry {
50 	u16 start_address;
51 	u8 msb;
52 	u8 lsb;
53 };
54 
55 struct rtl2832_reg_value {
56 	int reg;
57 	u32 value;
58 };
59 
60 /* Demod register bit names */
61 enum DVBT_REG_BIT_NAME {
62 	DVBT_SOFT_RST,
63 	DVBT_IIC_REPEAT,
64 	DVBT_TR_WAIT_MIN_8K,
65 	DVBT_RSD_BER_FAIL_VAL,
66 	DVBT_EN_BK_TRK,
67 	DVBT_REG_PI,
68 	DVBT_REG_PFREQ_1_0,
69 	DVBT_PD_DA8,
70 	DVBT_LOCK_TH,
71 	DVBT_BER_PASS_SCAL,
72 	DVBT_CE_FFSM_BYPASS,
73 	DVBT_ALPHAIIR_N,
74 	DVBT_ALPHAIIR_DIF,
75 	DVBT_EN_TRK_SPAN,
76 	DVBT_LOCK_TH_LEN,
77 	DVBT_CCI_THRE,
78 	DVBT_CCI_MON_SCAL,
79 	DVBT_CCI_M0,
80 	DVBT_CCI_M1,
81 	DVBT_CCI_M2,
82 	DVBT_CCI_M3,
83 	DVBT_SPEC_INIT_0,
84 	DVBT_SPEC_INIT_1,
85 	DVBT_SPEC_INIT_2,
86 	DVBT_AD_EN_REG,
87 	DVBT_AD_EN_REG1,
88 	DVBT_EN_BBIN,
89 	DVBT_MGD_THD0,
90 	DVBT_MGD_THD1,
91 	DVBT_MGD_THD2,
92 	DVBT_MGD_THD3,
93 	DVBT_MGD_THD4,
94 	DVBT_MGD_THD5,
95 	DVBT_MGD_THD6,
96 	DVBT_MGD_THD7,
97 	DVBT_EN_CACQ_NOTCH,
98 	DVBT_AD_AV_REF,
99 	DVBT_PIP_ON,
100 	DVBT_SCALE1_B92,
101 	DVBT_SCALE1_B93,
102 	DVBT_SCALE1_BA7,
103 	DVBT_SCALE1_BA9,
104 	DVBT_SCALE1_BAA,
105 	DVBT_SCALE1_BAB,
106 	DVBT_SCALE1_BAC,
107 	DVBT_SCALE1_BB0,
108 	DVBT_SCALE1_BB1,
109 	DVBT_KB_P1,
110 	DVBT_KB_P2,
111 	DVBT_KB_P3,
112 	DVBT_OPT_ADC_IQ,
113 	DVBT_AD_AVI,
114 	DVBT_AD_AVQ,
115 	DVBT_K1_CR_STEP12,
116 	DVBT_TRK_KS_P2,
117 	DVBT_TRK_KS_I2,
118 	DVBT_TR_THD_SET2,
119 	DVBT_TRK_KC_P2,
120 	DVBT_TRK_KC_I2,
121 	DVBT_CR_THD_SET2,
122 	DVBT_PSET_IFFREQ,
123 	DVBT_SPEC_INV,
124 	DVBT_BW_INDEX,
125 	DVBT_RSAMP_RATIO,
126 	DVBT_CFREQ_OFF_RATIO,
127 	DVBT_FSM_STAGE,
128 	DVBT_RX_CONSTEL,
129 	DVBT_RX_HIER,
130 	DVBT_RX_C_RATE_LP,
131 	DVBT_RX_C_RATE_HP,
132 	DVBT_GI_IDX,
133 	DVBT_FFT_MODE_IDX,
134 	DVBT_RSD_BER_EST,
135 	DVBT_CE_EST_EVM,
136 	DVBT_RF_AGC_VAL,
137 	DVBT_IF_AGC_VAL,
138 	DVBT_DAGC_VAL,
139 	DVBT_SFREQ_OFF,
140 	DVBT_CFREQ_OFF,
141 	DVBT_POLAR_RF_AGC,
142 	DVBT_POLAR_IF_AGC,
143 	DVBT_AAGC_HOLD,
144 	DVBT_EN_RF_AGC,
145 	DVBT_EN_IF_AGC,
146 	DVBT_IF_AGC_MIN,
147 	DVBT_IF_AGC_MAX,
148 	DVBT_RF_AGC_MIN,
149 	DVBT_RF_AGC_MAX,
150 	DVBT_IF_AGC_MAN,
151 	DVBT_IF_AGC_MAN_VAL,
152 	DVBT_RF_AGC_MAN,
153 	DVBT_RF_AGC_MAN_VAL,
154 	DVBT_DAGC_TRG_VAL,
155 	DVBT_AGC_TARG_VAL,
156 	DVBT_LOOP_GAIN_3_0,
157 	DVBT_LOOP_GAIN_4,
158 	DVBT_VTOP,
159 	DVBT_KRF,
160 	DVBT_AGC_TARG_VAL_0,
161 	DVBT_AGC_TARG_VAL_8_1,
162 	DVBT_AAGC_LOOP_GAIN,
163 	DVBT_LOOP_GAIN2_3_0,
164 	DVBT_LOOP_GAIN2_4,
165 	DVBT_LOOP_GAIN3,
166 	DVBT_VTOP1,
167 	DVBT_VTOP2,
168 	DVBT_VTOP3,
169 	DVBT_KRF1,
170 	DVBT_KRF2,
171 	DVBT_KRF3,
172 	DVBT_KRF4,
173 	DVBT_EN_GI_PGA,
174 	DVBT_THD_LOCK_UP,
175 	DVBT_THD_LOCK_DW,
176 	DVBT_THD_UP1,
177 	DVBT_THD_DW1,
178 	DVBT_INTER_CNT_LEN,
179 	DVBT_GI_PGA_STATE,
180 	DVBT_EN_AGC_PGA,
181 	DVBT_CKOUTPAR,
182 	DVBT_CKOUT_PWR,
183 	DVBT_SYNC_DUR,
184 	DVBT_ERR_DUR,
185 	DVBT_SYNC_LVL,
186 	DVBT_ERR_LVL,
187 	DVBT_VAL_LVL,
188 	DVBT_SERIAL,
189 	DVBT_SER_LSB,
190 	DVBT_CDIV_PH0,
191 	DVBT_CDIV_PH1,
192 	DVBT_MPEG_IO_OPT_2_2,
193 	DVBT_MPEG_IO_OPT_1_0,
194 	DVBT_CKOUTPAR_PIP,
195 	DVBT_CKOUT_PWR_PIP,
196 	DVBT_SYNC_LVL_PIP,
197 	DVBT_ERR_LVL_PIP,
198 	DVBT_VAL_LVL_PIP,
199 	DVBT_CKOUTPAR_PID,
200 	DVBT_CKOUT_PWR_PID,
201 	DVBT_SYNC_LVL_PID,
202 	DVBT_ERR_LVL_PID,
203 	DVBT_VAL_LVL_PID,
204 	DVBT_SM_PASS,
205 	DVBT_UPDATE_REG_2,
206 	DVBT_BTHD_P3,
207 	DVBT_BTHD_D3,
208 	DVBT_FUNC4_REG0,
209 	DVBT_FUNC4_REG1,
210 	DVBT_FUNC4_REG2,
211 	DVBT_FUNC4_REG3,
212 	DVBT_FUNC4_REG4,
213 	DVBT_FUNC4_REG5,
214 	DVBT_FUNC4_REG6,
215 	DVBT_FUNC4_REG7,
216 	DVBT_FUNC4_REG8,
217 	DVBT_FUNC4_REG9,
218 	DVBT_FUNC4_REG10,
219 	DVBT_FUNC5_REG0,
220 	DVBT_FUNC5_REG1,
221 	DVBT_FUNC5_REG2,
222 	DVBT_FUNC5_REG3,
223 	DVBT_FUNC5_REG4,
224 	DVBT_FUNC5_REG5,
225 	DVBT_FUNC5_REG6,
226 	DVBT_FUNC5_REG7,
227 	DVBT_FUNC5_REG8,
228 	DVBT_FUNC5_REG9,
229 	DVBT_FUNC5_REG10,
230 	DVBT_FUNC5_REG11,
231 	DVBT_FUNC5_REG12,
232 	DVBT_FUNC5_REG13,
233 	DVBT_FUNC5_REG14,
234 	DVBT_FUNC5_REG15,
235 	DVBT_FUNC5_REG16,
236 	DVBT_FUNC5_REG17,
237 	DVBT_FUNC5_REG18,
238 	DVBT_AD7_SETTING,
239 	DVBT_RSSI_R,
240 	DVBT_ACI_DET_IND,
241 	DVBT_REG_MON,
242 	DVBT_REG_MONSEL,
243 	DVBT_REG_GPE,
244 	DVBT_REG_GPO,
245 	DVBT_REG_4MSEL,
246 	DVBT_TEST_REG_1,
247 	DVBT_TEST_REG_2,
248 	DVBT_TEST_REG_3,
249 	DVBT_TEST_REG_4,
250 	DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
251 };
252 
253 static const struct rtl2832_reg_value rtl2832_tuner_init_fc2580[] = {
254 	{DVBT_DAGC_TRG_VAL,             0x39},
255 	{DVBT_AGC_TARG_VAL_0,            0x0},
256 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
257 	{DVBT_AAGC_LOOP_GAIN,           0x16},
258 	{DVBT_LOOP_GAIN2_3_0,            0x6},
259 	{DVBT_LOOP_GAIN2_4,              0x1},
260 	{DVBT_LOOP_GAIN3,               0x16},
261 	{DVBT_VTOP1,                    0x35},
262 	{DVBT_VTOP2,                    0x21},
263 	{DVBT_VTOP3,                    0x21},
264 	{DVBT_KRF1,                      0x0},
265 	{DVBT_KRF2,                     0x40},
266 	{DVBT_KRF3,                     0x10},
267 	{DVBT_KRF4,                     0x10},
268 	{DVBT_IF_AGC_MIN,               0x80},
269 	{DVBT_IF_AGC_MAX,               0x7f},
270 	{DVBT_RF_AGC_MIN,               0x9c},
271 	{DVBT_RF_AGC_MAX,               0x7f},
272 	{DVBT_POLAR_RF_AGC,              0x0},
273 	{DVBT_POLAR_IF_AGC,              0x0},
274 	{DVBT_AD7_SETTING,            0xe9f4},
275 };
276 
277 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
278 	{DVBT_DAGC_TRG_VAL,             0x39},
279 	{DVBT_AGC_TARG_VAL_0,            0x0},
280 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
281 	{DVBT_AAGC_LOOP_GAIN,           0x16},
282 	{DVBT_LOOP_GAIN2_3_0,            0x6},
283 	{DVBT_LOOP_GAIN2_4,              0x1},
284 	{DVBT_LOOP_GAIN3,               0x16},
285 	{DVBT_VTOP1,                    0x35},
286 	{DVBT_VTOP2,                    0x21},
287 	{DVBT_VTOP3,                    0x21},
288 	{DVBT_KRF1,                      0x0},
289 	{DVBT_KRF2,                     0x40},
290 	{DVBT_KRF3,                     0x10},
291 	{DVBT_KRF4,                     0x10},
292 	{DVBT_IF_AGC_MIN,               0x80},
293 	{DVBT_IF_AGC_MAX,               0x7f},
294 	{DVBT_RF_AGC_MIN,               0x9c},
295 	{DVBT_RF_AGC_MAX,               0x7f},
296 	{DVBT_POLAR_RF_AGC,              0x0},
297 	{DVBT_POLAR_IF_AGC,              0x0},
298 	{DVBT_AD7_SETTING,            0xe9f4},
299 	{DVBT_OPT_ADC_IQ,                0x1},
300 	{DVBT_AD_AVI,                    0x0},
301 	{DVBT_AD_AVQ,                    0x0},
302 	{DVBT_SPEC_INV,                  0x0},
303 };
304 
305 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
306 	{DVBT_DAGC_TRG_VAL,             0x5a},
307 	{DVBT_AGC_TARG_VAL_0,            0x0},
308 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
309 	{DVBT_AAGC_LOOP_GAIN,           0x16},
310 	{DVBT_LOOP_GAIN2_3_0,            0x6},
311 	{DVBT_LOOP_GAIN2_4,              0x1},
312 	{DVBT_LOOP_GAIN3,               0x16},
313 	{DVBT_VTOP1,                    0x35},
314 	{DVBT_VTOP2,                    0x21},
315 	{DVBT_VTOP3,                    0x21},
316 	{DVBT_KRF1,                      0x0},
317 	{DVBT_KRF2,                     0x40},
318 	{DVBT_KRF3,                     0x10},
319 	{DVBT_KRF4,                     0x10},
320 	{DVBT_IF_AGC_MIN,               0x80},
321 	{DVBT_IF_AGC_MAX,               0x7f},
322 	{DVBT_RF_AGC_MIN,               0x80},
323 	{DVBT_RF_AGC_MAX,               0x7f},
324 	{DVBT_POLAR_RF_AGC,              0x0},
325 	{DVBT_POLAR_IF_AGC,              0x0},
326 	{DVBT_AD7_SETTING,            0xe9bf},
327 	{DVBT_EN_GI_PGA,                 0x0},
328 	{DVBT_THD_LOCK_UP,               0x0},
329 	{DVBT_THD_LOCK_DW,               0x0},
330 	{DVBT_THD_UP1,                  0x11},
331 	{DVBT_THD_DW1,                  0xef},
332 	{DVBT_INTER_CNT_LEN,             0xc},
333 	{DVBT_GI_PGA_STATE,              0x0},
334 	{DVBT_EN_AGC_PGA,                0x1},
335 	{DVBT_IF_AGC_MAN,                0x0},
336 	{DVBT_SPEC_INV,                  0x0},
337 };
338 
339 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
340 	{DVBT_DAGC_TRG_VAL,             0x5a},
341 	{DVBT_AGC_TARG_VAL_0,            0x0},
342 	{DVBT_AGC_TARG_VAL_8_1,         0x5a},
343 	{DVBT_AAGC_LOOP_GAIN,           0x18},
344 	{DVBT_LOOP_GAIN2_3_0,            0x8},
345 	{DVBT_LOOP_GAIN2_4,              0x1},
346 	{DVBT_LOOP_GAIN3,               0x18},
347 	{DVBT_VTOP1,                    0x35},
348 	{DVBT_VTOP2,                    0x21},
349 	{DVBT_VTOP3,                    0x21},
350 	{DVBT_KRF1,                      0x0},
351 	{DVBT_KRF2,                     0x40},
352 	{DVBT_KRF3,                     0x10},
353 	{DVBT_KRF4,                     0x10},
354 	{DVBT_IF_AGC_MIN,               0x80},
355 	{DVBT_IF_AGC_MAX,               0x7f},
356 	{DVBT_RF_AGC_MIN,               0x80},
357 	{DVBT_RF_AGC_MAX,               0x7f},
358 	{DVBT_POLAR_RF_AGC,              0x0},
359 	{DVBT_POLAR_IF_AGC,              0x0},
360 	{DVBT_AD7_SETTING,            0xe9d4},
361 	{DVBT_EN_GI_PGA,                 0x0},
362 	{DVBT_THD_LOCK_UP,               0x0},
363 	{DVBT_THD_LOCK_DW,               0x0},
364 	{DVBT_THD_UP1,                  0x14},
365 	{DVBT_THD_DW1,                  0xec},
366 	{DVBT_INTER_CNT_LEN,             0xc},
367 	{DVBT_GI_PGA_STATE,              0x0},
368 	{DVBT_EN_AGC_PGA,                0x1},
369 	{DVBT_REG_GPE,                   0x1},
370 	{DVBT_REG_GPO,                   0x1},
371 	{DVBT_REG_MONSEL,                0x1},
372 	{DVBT_REG_MON,                   0x1},
373 	{DVBT_REG_4MSEL,                 0x0},
374 	{DVBT_SPEC_INV,                  0x0},
375 };
376 
377 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
378 	{DVBT_DAGC_TRG_VAL,             0x39},
379 	{DVBT_AGC_TARG_VAL_0,            0x0},
380 	{DVBT_AGC_TARG_VAL_8_1,         0x40},
381 	{DVBT_AAGC_LOOP_GAIN,           0x16},
382 	{DVBT_LOOP_GAIN2_3_0,            0x8},
383 	{DVBT_LOOP_GAIN2_4,              0x1},
384 	{DVBT_LOOP_GAIN3,               0x18},
385 	{DVBT_VTOP1,                    0x35},
386 	{DVBT_VTOP2,                    0x21},
387 	{DVBT_VTOP3,                    0x21},
388 	{DVBT_KRF1,                      0x0},
389 	{DVBT_KRF2,                     0x40},
390 	{DVBT_KRF3,                     0x10},
391 	{DVBT_KRF4,                     0x10},
392 	{DVBT_IF_AGC_MIN,               0x80},
393 	{DVBT_IF_AGC_MAX,               0x7f},
394 	{DVBT_RF_AGC_MIN,               0x80},
395 	{DVBT_RF_AGC_MAX,               0x7f},
396 	{DVBT_POLAR_RF_AGC,              0x0},
397 	{DVBT_POLAR_IF_AGC,              0x0},
398 	{DVBT_AD7_SETTING,            0xe9f4},
399 	{DVBT_SPEC_INV,                  0x1},
400 };
401 
402 static const struct rtl2832_reg_value rtl2832_tuner_init_si2157[] = {
403 	{DVBT_DAGC_TRG_VAL,             0x39},
404 	{DVBT_AGC_TARG_VAL_0,            0x0},
405 	{DVBT_AGC_TARG_VAL_8_1,         0x40},
406 	{DVBT_AAGC_LOOP_GAIN,           0x16},
407 	{DVBT_LOOP_GAIN2_3_0,            0x8},
408 	{DVBT_LOOP_GAIN2_4,              0x1},
409 	{DVBT_LOOP_GAIN3,               0x18},
410 	{DVBT_VTOP1,                    0x35},
411 	{DVBT_VTOP2,                    0x21},
412 	{DVBT_VTOP3,                    0x21},
413 	{DVBT_KRF1,                      0x0},
414 	{DVBT_KRF2,                     0x40},
415 	{DVBT_KRF3,                     0x10},
416 	{DVBT_KRF4,                     0x10},
417 	{DVBT_IF_AGC_MIN,               0x80},
418 	{DVBT_IF_AGC_MAX,               0x7f},
419 	{DVBT_RF_AGC_MIN,               0x80},
420 	{DVBT_RF_AGC_MAX,               0x7f},
421 	{DVBT_POLAR_RF_AGC,              0x0},
422 	{DVBT_POLAR_IF_AGC,              0x0},
423 	{DVBT_AD7_SETTING,            0xe9f4},
424 	{DVBT_SPEC_INV,                  0x0},
425 };
426 
427 #endif /* RTL2832_PRIV_H */
428