1 /* 2 * Support for NXT2002 and NXT2004 - VSB/QAM 3 * 4 * Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com> 5 * Copyright (C) 2006-2014 Michael Krufky <mkrufky@linuxtv.org> 6 * based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net> 7 * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 /* 22 * NOTES ABOUT THIS DRIVER 23 * 24 * This Linux driver supports: 25 * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002) 26 * AverTVHD MCE A180 (NXT2004) 27 * ATI HDTV Wonder (NXT2004) 28 * 29 * This driver needs external firmware. Please use the command 30 * "<kerneldir>/scripts/get_dvb_firmware nxt2002" or 31 * "<kerneldir>/scripts/get_dvb_firmware nxt2004" to 32 * download/extract the appropriate firmware, and then copy it to 33 * /usr/lib/hotplug/firmware/ or /lib/firmware/ 34 * (depending on configuration of firmware hotplug). 35 */ 36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 37 38 /* Max transfer size done by I2C transfer functions */ 39 #define MAX_XFER_SIZE 256 40 41 #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw" 42 #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw" 43 #define CRC_CCIT_MASK 0x1021 44 45 #include <linux/kernel.h> 46 #include <linux/init.h> 47 #include <linux/module.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 51 #include <media/dvb_frontend.h> 52 #include "nxt200x.h" 53 54 struct nxt200x_state { 55 56 struct i2c_adapter* i2c; 57 const struct nxt200x_config* config; 58 struct dvb_frontend frontend; 59 60 /* demodulator private data */ 61 nxt_chip_type demod_chip; 62 u8 initialised:1; 63 }; 64 65 static int debug; 66 #define dprintk(args...) do { if (debug) pr_debug(args); } while (0) 67 68 static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len) 69 { 70 int err; 71 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len }; 72 73 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 74 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", 75 __func__, addr, err); 76 return -EREMOTEIO; 77 } 78 return 0; 79 } 80 81 static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len) 82 { 83 int err; 84 struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len }; 85 86 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 87 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", 88 __func__, addr, err); 89 return -EREMOTEIO; 90 } 91 return 0; 92 } 93 94 static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg, 95 const u8 *buf, u8 len) 96 { 97 u8 buf2[MAX_XFER_SIZE]; 98 int err; 99 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 }; 100 101 if (1 + len > sizeof(buf2)) { 102 pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n", 103 __func__, reg, len); 104 return -EINVAL; 105 } 106 107 buf2[0] = reg; 108 memcpy(&buf2[1], buf, len); 109 110 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 111 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", 112 __func__, state->config->demod_address, err); 113 return -EREMOTEIO; 114 } 115 return 0; 116 } 117 118 static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len) 119 { 120 u8 reg2 [] = { reg }; 121 122 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 }, 123 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } }; 124 125 int err; 126 127 if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) { 128 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", 129 __func__, state->config->demod_address, err); 130 return -EREMOTEIO; 131 } 132 return 0; 133 } 134 135 static u16 nxt200x_crc(u16 crc, u8 c) 136 { 137 u8 i; 138 u16 input = (u16) c & 0xFF; 139 140 input<<=8; 141 for(i=0; i<8; i++) { 142 if((crc^input) & 0x8000) 143 crc=(crc<<1)^CRC_CCIT_MASK; 144 else 145 crc<<=1; 146 input<<=1; 147 } 148 return crc; 149 } 150 151 static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) 152 { 153 u8 attr, len2, buf; 154 dprintk("%s\n", __func__); 155 156 /* set multi register register */ 157 nxt200x_writebytes(state, 0x35, ®, 1); 158 159 /* send the actual data */ 160 nxt200x_writebytes(state, 0x36, data, len); 161 162 switch (state->demod_chip) { 163 case NXT2002: 164 len2 = len; 165 buf = 0x02; 166 break; 167 case NXT2004: 168 /* probably not right, but gives correct values */ 169 attr = 0x02; 170 if (reg & 0x80) { 171 attr = attr << 1; 172 if (reg & 0x04) 173 attr = attr >> 1; 174 } 175 /* set write bit */ 176 len2 = ((attr << 4) | 0x10) | len; 177 buf = 0x80; 178 break; 179 default: 180 return -EINVAL; 181 break; 182 } 183 184 /* set multi register length */ 185 nxt200x_writebytes(state, 0x34, &len2, 1); 186 187 /* toggle the multireg write bit */ 188 nxt200x_writebytes(state, 0x21, &buf, 1); 189 190 nxt200x_readbytes(state, 0x21, &buf, 1); 191 192 switch (state->demod_chip) { 193 case NXT2002: 194 if ((buf & 0x02) == 0) 195 return 0; 196 break; 197 case NXT2004: 198 if (buf == 0) 199 return 0; 200 break; 201 default: 202 return -EINVAL; 203 break; 204 } 205 206 pr_warn("Error writing multireg register 0x%02X\n", reg); 207 208 return 0; 209 } 210 211 static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) 212 { 213 int i; 214 u8 buf, len2, attr; 215 dprintk("%s\n", __func__); 216 217 /* set multi register register */ 218 nxt200x_writebytes(state, 0x35, ®, 1); 219 220 switch (state->demod_chip) { 221 case NXT2002: 222 /* set multi register length */ 223 len2 = len & 0x80; 224 nxt200x_writebytes(state, 0x34, &len2, 1); 225 226 /* read the actual data */ 227 nxt200x_readbytes(state, reg, data, len); 228 return 0; 229 break; 230 case NXT2004: 231 /* probably not right, but gives correct values */ 232 attr = 0x02; 233 if (reg & 0x80) { 234 attr = attr << 1; 235 if (reg & 0x04) 236 attr = attr >> 1; 237 } 238 239 /* set multi register length */ 240 len2 = (attr << 4) | len; 241 nxt200x_writebytes(state, 0x34, &len2, 1); 242 243 /* toggle the multireg bit*/ 244 buf = 0x80; 245 nxt200x_writebytes(state, 0x21, &buf, 1); 246 247 /* read the actual data */ 248 for(i = 0; i < len; i++) { 249 nxt200x_readbytes(state, 0x36 + i, &data[i], 1); 250 } 251 return 0; 252 break; 253 default: 254 return -EINVAL; 255 break; 256 } 257 } 258 259 static void nxt200x_microcontroller_stop (struct nxt200x_state* state) 260 { 261 u8 buf, stopval, counter = 0; 262 dprintk("%s\n", __func__); 263 264 /* set correct stop value */ 265 switch (state->demod_chip) { 266 case NXT2002: 267 stopval = 0x40; 268 break; 269 case NXT2004: 270 stopval = 0x10; 271 break; 272 default: 273 stopval = 0; 274 break; 275 } 276 277 buf = 0x80; 278 nxt200x_writebytes(state, 0x22, &buf, 1); 279 280 while (counter < 20) { 281 nxt200x_readbytes(state, 0x31, &buf, 1); 282 if (buf & stopval) 283 return; 284 msleep(10); 285 counter++; 286 } 287 288 pr_warn("Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n"); 289 return; 290 } 291 292 static void nxt200x_microcontroller_start (struct nxt200x_state* state) 293 { 294 u8 buf; 295 dprintk("%s\n", __func__); 296 297 buf = 0x00; 298 nxt200x_writebytes(state, 0x22, &buf, 1); 299 } 300 301 static void nxt2004_microcontroller_init (struct nxt200x_state* state) 302 { 303 u8 buf[9]; 304 u8 counter = 0; 305 dprintk("%s\n", __func__); 306 307 buf[0] = 0x00; 308 nxt200x_writebytes(state, 0x2b, buf, 1); 309 buf[0] = 0x70; 310 nxt200x_writebytes(state, 0x34, buf, 1); 311 buf[0] = 0x04; 312 nxt200x_writebytes(state, 0x35, buf, 1); 313 buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89; 314 buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0; 315 nxt200x_writebytes(state, 0x36, buf, 9); 316 buf[0] = 0x80; 317 nxt200x_writebytes(state, 0x21, buf, 1); 318 319 while (counter < 20) { 320 nxt200x_readbytes(state, 0x21, buf, 1); 321 if (buf[0] == 0) 322 return; 323 msleep(10); 324 counter++; 325 } 326 327 pr_warn("Timeout waiting for nxt2004 to init.\n"); 328 329 return; 330 } 331 332 static int nxt200x_writetuner (struct nxt200x_state* state, u8* data) 333 { 334 u8 buf, count = 0; 335 336 dprintk("%s\n", __func__); 337 338 dprintk("Tuner Bytes: %*ph\n", 4, data + 1); 339 340 /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip. 341 * direct write is required for Philips TUV1236D and ALPS TDHU2 */ 342 switch (state->demod_chip) { 343 case NXT2004: 344 if (i2c_writebytes(state, data[0], data+1, 4)) 345 pr_warn("error writing to tuner\n"); 346 /* wait until we have a lock */ 347 while (count < 20) { 348 i2c_readbytes(state, data[0], &buf, 1); 349 if (buf & 0x40) 350 return 0; 351 msleep(100); 352 count++; 353 } 354 pr_warn("timeout waiting for tuner lock\n"); 355 break; 356 case NXT2002: 357 /* set the i2c transfer speed to the tuner */ 358 buf = 0x03; 359 nxt200x_writebytes(state, 0x20, &buf, 1); 360 361 /* setup to transfer 4 bytes via i2c */ 362 buf = 0x04; 363 nxt200x_writebytes(state, 0x34, &buf, 1); 364 365 /* write actual tuner bytes */ 366 nxt200x_writebytes(state, 0x36, data+1, 4); 367 368 /* set tuner i2c address */ 369 buf = data[0] << 1; 370 nxt200x_writebytes(state, 0x35, &buf, 1); 371 372 /* write UC Opmode to begin transfer */ 373 buf = 0x80; 374 nxt200x_writebytes(state, 0x21, &buf, 1); 375 376 while (count < 20) { 377 nxt200x_readbytes(state, 0x21, &buf, 1); 378 if ((buf & 0x80)== 0x00) 379 return 0; 380 msleep(100); 381 count++; 382 } 383 pr_warn("timeout error writing to tuner\n"); 384 break; 385 default: 386 return -EINVAL; 387 break; 388 } 389 return 0; 390 } 391 392 static void nxt200x_agc_reset(struct nxt200x_state* state) 393 { 394 u8 buf; 395 dprintk("%s\n", __func__); 396 397 switch (state->demod_chip) { 398 case NXT2002: 399 buf = 0x08; 400 nxt200x_writebytes(state, 0x08, &buf, 1); 401 buf = 0x00; 402 nxt200x_writebytes(state, 0x08, &buf, 1); 403 break; 404 case NXT2004: 405 nxt200x_readreg_multibyte(state, 0x08, &buf, 1); 406 buf = 0x08; 407 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); 408 buf = 0x00; 409 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); 410 break; 411 default: 412 break; 413 } 414 return; 415 } 416 417 static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) 418 { 419 420 struct nxt200x_state* state = fe->demodulator_priv; 421 u8 buf[3], written = 0, chunkpos = 0; 422 u16 rambase, position, crc = 0; 423 424 dprintk("%s\n", __func__); 425 dprintk("Firmware is %zu bytes\n", fw->size); 426 427 /* Get the RAM base for this nxt2002 */ 428 nxt200x_readbytes(state, 0x10, buf, 1); 429 430 if (buf[0] & 0x10) 431 rambase = 0x1000; 432 else 433 rambase = 0x0000; 434 435 dprintk("rambase on this nxt2002 is %04X\n", rambase); 436 437 /* Hold the micro in reset while loading firmware */ 438 buf[0] = 0x80; 439 nxt200x_writebytes(state, 0x2B, buf, 1); 440 441 for (position = 0; position < fw->size; position++) { 442 if (written == 0) { 443 crc = 0; 444 chunkpos = 0x28; 445 buf[0] = ((rambase + position) >> 8); 446 buf[1] = (rambase + position) & 0xFF; 447 buf[2] = 0x81; 448 /* write starting address */ 449 nxt200x_writebytes(state, 0x29, buf, 3); 450 } 451 written++; 452 chunkpos++; 453 454 if ((written % 4) == 0) 455 nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4); 456 457 crc = nxt200x_crc(crc, fw->data[position]); 458 459 if ((written == 255) || (position+1 == fw->size)) { 460 /* write remaining bytes of firmware */ 461 nxt200x_writebytes(state, chunkpos+4-(written %4), 462 &fw->data[position-(written %4) + 1], 463 written %4); 464 buf[0] = crc << 8; 465 buf[1] = crc & 0xFF; 466 467 /* write crc */ 468 nxt200x_writebytes(state, 0x2C, buf, 2); 469 470 /* do a read to stop things */ 471 nxt200x_readbytes(state, 0x2A, buf, 1); 472 473 /* set transfer mode to complete */ 474 buf[0] = 0x80; 475 nxt200x_writebytes(state, 0x2B, buf, 1); 476 477 written = 0; 478 } 479 } 480 481 return 0; 482 }; 483 484 static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) 485 { 486 487 struct nxt200x_state* state = fe->demodulator_priv; 488 u8 buf[3]; 489 u16 rambase, position, crc=0; 490 491 dprintk("%s\n", __func__); 492 dprintk("Firmware is %zu bytes\n", fw->size); 493 494 /* set rambase */ 495 rambase = 0x1000; 496 497 /* hold the micro in reset while loading firmware */ 498 buf[0] = 0x80; 499 nxt200x_writebytes(state, 0x2B, buf,1); 500 501 /* calculate firmware CRC */ 502 for (position = 0; position < fw->size; position++) { 503 crc = nxt200x_crc(crc, fw->data[position]); 504 } 505 506 buf[0] = rambase >> 8; 507 buf[1] = rambase & 0xFF; 508 buf[2] = 0x81; 509 /* write starting address */ 510 nxt200x_writebytes(state,0x29,buf,3); 511 512 for (position = 0; position < fw->size;) { 513 nxt200x_writebytes(state, 0x2C, &fw->data[position], 514 fw->size-position > 255 ? 255 : fw->size-position); 515 position += (fw->size-position > 255 ? 255 : fw->size-position); 516 } 517 buf[0] = crc >> 8; 518 buf[1] = crc & 0xFF; 519 520 dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]); 521 522 /* write crc */ 523 nxt200x_writebytes(state, 0x2C, buf,2); 524 525 /* do a read to stop things */ 526 nxt200x_readbytes(state, 0x2C, buf, 1); 527 528 /* set transfer mode to complete */ 529 buf[0] = 0x80; 530 nxt200x_writebytes(state, 0x2B, buf,1); 531 532 return 0; 533 }; 534 535 static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe) 536 { 537 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 538 struct nxt200x_state* state = fe->demodulator_priv; 539 u8 buf[5]; 540 541 /* stop the micro first */ 542 nxt200x_microcontroller_stop(state); 543 544 if (state->demod_chip == NXT2004) { 545 /* make sure demod is set to digital */ 546 buf[0] = 0x04; 547 nxt200x_writebytes(state, 0x14, buf, 1); 548 buf[0] = 0x00; 549 nxt200x_writebytes(state, 0x17, buf, 1); 550 } 551 552 /* set additional params */ 553 switch (p->modulation) { 554 case QAM_64: 555 case QAM_256: 556 /* Set punctured clock for QAM */ 557 /* This is just a guess since I am unable to test it */ 558 if (state->config->set_ts_params) 559 state->config->set_ts_params(fe, 1); 560 break; 561 case VSB_8: 562 /* Set non-punctured clock for VSB */ 563 if (state->config->set_ts_params) 564 state->config->set_ts_params(fe, 0); 565 break; 566 default: 567 return -EINVAL; 568 break; 569 } 570 571 if (fe->ops.tuner_ops.calc_regs) { 572 /* get tuning information */ 573 fe->ops.tuner_ops.calc_regs(fe, buf, 5); 574 575 /* write frequency information */ 576 nxt200x_writetuner(state, buf); 577 } 578 579 /* reset the agc now that tuning has been completed */ 580 nxt200x_agc_reset(state); 581 582 /* set target power level */ 583 switch (p->modulation) { 584 case QAM_64: 585 case QAM_256: 586 buf[0] = 0x74; 587 break; 588 case VSB_8: 589 buf[0] = 0x70; 590 break; 591 default: 592 return -EINVAL; 593 break; 594 } 595 nxt200x_writebytes(state, 0x42, buf, 1); 596 597 /* configure sdm */ 598 switch (state->demod_chip) { 599 case NXT2002: 600 buf[0] = 0x87; 601 break; 602 case NXT2004: 603 buf[0] = 0x07; 604 break; 605 default: 606 return -EINVAL; 607 break; 608 } 609 nxt200x_writebytes(state, 0x57, buf, 1); 610 611 /* write sdm1 input */ 612 buf[0] = 0x10; 613 buf[1] = 0x00; 614 switch (state->demod_chip) { 615 case NXT2002: 616 nxt200x_writereg_multibyte(state, 0x58, buf, 2); 617 break; 618 case NXT2004: 619 nxt200x_writebytes(state, 0x58, buf, 2); 620 break; 621 default: 622 return -EINVAL; 623 break; 624 } 625 626 /* write sdmx input */ 627 switch (p->modulation) { 628 case QAM_64: 629 buf[0] = 0x68; 630 break; 631 case QAM_256: 632 buf[0] = 0x64; 633 break; 634 case VSB_8: 635 buf[0] = 0x60; 636 break; 637 default: 638 return -EINVAL; 639 break; 640 } 641 buf[1] = 0x00; 642 switch (state->demod_chip) { 643 case NXT2002: 644 nxt200x_writereg_multibyte(state, 0x5C, buf, 2); 645 break; 646 case NXT2004: 647 nxt200x_writebytes(state, 0x5C, buf, 2); 648 break; 649 default: 650 return -EINVAL; 651 break; 652 } 653 654 /* write adc power lpf fc */ 655 buf[0] = 0x05; 656 nxt200x_writebytes(state, 0x43, buf, 1); 657 658 if (state->demod_chip == NXT2004) { 659 /* write ??? */ 660 buf[0] = 0x00; 661 buf[1] = 0x00; 662 nxt200x_writebytes(state, 0x46, buf, 2); 663 } 664 665 /* write accumulator2 input */ 666 buf[0] = 0x80; 667 buf[1] = 0x00; 668 switch (state->demod_chip) { 669 case NXT2002: 670 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); 671 break; 672 case NXT2004: 673 nxt200x_writebytes(state, 0x4B, buf, 2); 674 break; 675 default: 676 return -EINVAL; 677 break; 678 } 679 680 /* write kg1 */ 681 buf[0] = 0x00; 682 nxt200x_writebytes(state, 0x4D, buf, 1); 683 684 /* write sdm12 lpf fc */ 685 buf[0] = 0x44; 686 nxt200x_writebytes(state, 0x55, buf, 1); 687 688 /* write agc control reg */ 689 buf[0] = 0x04; 690 nxt200x_writebytes(state, 0x41, buf, 1); 691 692 if (state->demod_chip == NXT2004) { 693 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 694 buf[0] = 0x24; 695 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 696 697 /* soft reset? */ 698 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 699 buf[0] = 0x10; 700 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 701 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 702 buf[0] = 0x00; 703 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 704 705 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 706 buf[0] = 0x04; 707 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 708 buf[0] = 0x00; 709 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 710 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; 711 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 712 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 713 buf[0] = 0x11; 714 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 715 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 716 buf[0] = 0x44; 717 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 718 } 719 720 /* write agc ucgp0 */ 721 switch (p->modulation) { 722 case QAM_64: 723 buf[0] = 0x02; 724 break; 725 case QAM_256: 726 buf[0] = 0x03; 727 break; 728 case VSB_8: 729 buf[0] = 0x00; 730 break; 731 default: 732 return -EINVAL; 733 break; 734 } 735 nxt200x_writebytes(state, 0x30, buf, 1); 736 737 /* write agc control reg */ 738 buf[0] = 0x00; 739 nxt200x_writebytes(state, 0x41, buf, 1); 740 741 /* write accumulator2 input */ 742 buf[0] = 0x80; 743 buf[1] = 0x00; 744 switch (state->demod_chip) { 745 case NXT2002: 746 nxt200x_writereg_multibyte(state, 0x49, buf, 2); 747 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); 748 break; 749 case NXT2004: 750 nxt200x_writebytes(state, 0x49, buf, 2); 751 nxt200x_writebytes(state, 0x4B, buf, 2); 752 break; 753 default: 754 return -EINVAL; 755 break; 756 } 757 758 /* write agc control reg */ 759 buf[0] = 0x04; 760 nxt200x_writebytes(state, 0x41, buf, 1); 761 762 nxt200x_microcontroller_start(state); 763 764 if (state->demod_chip == NXT2004) { 765 nxt2004_microcontroller_init(state); 766 767 /* ???? */ 768 buf[0] = 0xF0; 769 buf[1] = 0x00; 770 nxt200x_writebytes(state, 0x5C, buf, 2); 771 } 772 773 /* adjacent channel detection should be done here, but I don't 774 have any stations with this need so I cannot test it */ 775 776 return 0; 777 } 778 779 static int nxt200x_read_status(struct dvb_frontend *fe, enum fe_status *status) 780 { 781 struct nxt200x_state* state = fe->demodulator_priv; 782 u8 lock; 783 nxt200x_readbytes(state, 0x31, &lock, 1); 784 785 *status = 0; 786 if (lock & 0x20) { 787 *status |= FE_HAS_SIGNAL; 788 *status |= FE_HAS_CARRIER; 789 *status |= FE_HAS_VITERBI; 790 *status |= FE_HAS_SYNC; 791 *status |= FE_HAS_LOCK; 792 } 793 return 0; 794 } 795 796 static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber) 797 { 798 struct nxt200x_state* state = fe->demodulator_priv; 799 u8 b[3]; 800 801 nxt200x_readreg_multibyte(state, 0xE6, b, 3); 802 803 *ber = ((b[0] << 8) + b[1]) * 8; 804 805 return 0; 806 } 807 808 static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength) 809 { 810 struct nxt200x_state* state = fe->demodulator_priv; 811 u8 b[2]; 812 u16 temp = 0; 813 814 /* setup to read cluster variance */ 815 b[0] = 0x00; 816 nxt200x_writebytes(state, 0xA1, b, 1); 817 818 /* get multreg val */ 819 nxt200x_readreg_multibyte(state, 0xA6, b, 2); 820 821 temp = (b[0] << 8) | b[1]; 822 *strength = ((0x7FFF - temp) & 0x0FFF) * 16; 823 824 return 0; 825 } 826 827 static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr) 828 { 829 830 struct nxt200x_state* state = fe->demodulator_priv; 831 u8 b[2]; 832 u16 temp = 0, temp2; 833 u32 snrdb = 0; 834 835 /* setup to read cluster variance */ 836 b[0] = 0x00; 837 nxt200x_writebytes(state, 0xA1, b, 1); 838 839 /* get multreg val from 0xA6 */ 840 nxt200x_readreg_multibyte(state, 0xA6, b, 2); 841 842 temp = (b[0] << 8) | b[1]; 843 temp2 = 0x7FFF - temp; 844 845 /* snr will be in db */ 846 if (temp2 > 0x7F00) 847 snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) ); 848 else if (temp2 > 0x7EC0) 849 snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) ); 850 else if (temp2 > 0x7C00) 851 snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) ); 852 else 853 snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) ); 854 855 /* the value reported back from the frontend will be FFFF=32db 0000=0db */ 856 *snr = snrdb * (0xFFFF/32000); 857 858 return 0; 859 } 860 861 static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 862 { 863 struct nxt200x_state* state = fe->demodulator_priv; 864 u8 b[3]; 865 866 nxt200x_readreg_multibyte(state, 0xE6, b, 3); 867 *ucblocks = b[2]; 868 869 return 0; 870 } 871 872 static int nxt200x_sleep(struct dvb_frontend* fe) 873 { 874 return 0; 875 } 876 877 static int nxt2002_init(struct dvb_frontend* fe) 878 { 879 struct nxt200x_state* state = fe->demodulator_priv; 880 const struct firmware *fw; 881 int ret; 882 u8 buf[2]; 883 884 /* request the firmware, this will block until someone uploads it */ 885 pr_debug("%s: Waiting for firmware upload (%s)...\n", 886 __func__, NXT2002_DEFAULT_FIRMWARE); 887 ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE, 888 state->i2c->dev.parent); 889 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__); 890 if (ret) { 891 pr_err("%s: No firmware uploaded (timeout or file not found?)\n", 892 __func__); 893 return ret; 894 } 895 896 ret = nxt2002_load_firmware(fe, fw); 897 release_firmware(fw); 898 if (ret) { 899 pr_err("%s: Writing firmware to device failed\n", __func__); 900 return ret; 901 } 902 pr_info("%s: Firmware upload complete\n", __func__); 903 904 /* Put the micro into reset */ 905 nxt200x_microcontroller_stop(state); 906 907 /* ensure transfer is complete */ 908 buf[0]=0x00; 909 nxt200x_writebytes(state, 0x2B, buf, 1); 910 911 /* Put the micro into reset for real this time */ 912 nxt200x_microcontroller_stop(state); 913 914 /* soft reset everything (agc,frontend,eq,fec)*/ 915 buf[0] = 0x0F; 916 nxt200x_writebytes(state, 0x08, buf, 1); 917 buf[0] = 0x00; 918 nxt200x_writebytes(state, 0x08, buf, 1); 919 920 /* write agc sdm configure */ 921 buf[0] = 0xF1; 922 nxt200x_writebytes(state, 0x57, buf, 1); 923 924 /* write mod output format */ 925 buf[0] = 0x20; 926 nxt200x_writebytes(state, 0x09, buf, 1); 927 928 /* write fec mpeg mode */ 929 buf[0] = 0x7E; 930 buf[1] = 0x00; 931 nxt200x_writebytes(state, 0xE9, buf, 2); 932 933 /* write mux selection */ 934 buf[0] = 0x00; 935 nxt200x_writebytes(state, 0xCC, buf, 1); 936 937 return 0; 938 } 939 940 static int nxt2004_init(struct dvb_frontend* fe) 941 { 942 struct nxt200x_state* state = fe->demodulator_priv; 943 const struct firmware *fw; 944 int ret; 945 u8 buf[3]; 946 947 /* ??? */ 948 buf[0]=0x00; 949 nxt200x_writebytes(state, 0x1E, buf, 1); 950 951 /* request the firmware, this will block until someone uploads it */ 952 pr_debug("%s: Waiting for firmware upload (%s)...\n", 953 __func__, NXT2004_DEFAULT_FIRMWARE); 954 ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE, 955 state->i2c->dev.parent); 956 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__); 957 if (ret) { 958 pr_err("%s: No firmware uploaded (timeout or file not found?)\n", 959 __func__); 960 return ret; 961 } 962 963 ret = nxt2004_load_firmware(fe, fw); 964 release_firmware(fw); 965 if (ret) { 966 pr_err("%s: Writing firmware to device failed\n", __func__); 967 return ret; 968 } 969 pr_info("%s: Firmware upload complete\n", __func__); 970 971 /* ensure transfer is complete */ 972 buf[0] = 0x01; 973 nxt200x_writebytes(state, 0x19, buf, 1); 974 975 nxt2004_microcontroller_init(state); 976 nxt200x_microcontroller_stop(state); 977 nxt200x_microcontroller_stop(state); 978 nxt2004_microcontroller_init(state); 979 nxt200x_microcontroller_stop(state); 980 981 /* soft reset everything (agc,frontend,eq,fec)*/ 982 buf[0] = 0xFF; 983 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 984 buf[0] = 0x00; 985 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 986 987 /* write agc sdm configure */ 988 buf[0] = 0xD7; 989 nxt200x_writebytes(state, 0x57, buf, 1); 990 991 /* ???*/ 992 buf[0] = 0x07; 993 buf[1] = 0xfe; 994 nxt200x_writebytes(state, 0x35, buf, 2); 995 buf[0] = 0x12; 996 nxt200x_writebytes(state, 0x34, buf, 1); 997 buf[0] = 0x80; 998 nxt200x_writebytes(state, 0x21, buf, 1); 999 1000 /* ???*/ 1001 buf[0] = 0x21; 1002 nxt200x_writebytes(state, 0x0A, buf, 1); 1003 1004 /* ???*/ 1005 buf[0] = 0x01; 1006 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1007 1008 /* write fec mpeg mode */ 1009 buf[0] = 0x7E; 1010 buf[1] = 0x00; 1011 nxt200x_writebytes(state, 0xE9, buf, 2); 1012 1013 /* write mux selection */ 1014 buf[0] = 0x00; 1015 nxt200x_writebytes(state, 0xCC, buf, 1); 1016 1017 /* ???*/ 1018 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1019 buf[0] = 0x00; 1020 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1021 1022 /* soft reset? */ 1023 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1024 buf[0] = 0x10; 1025 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1026 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1027 buf[0] = 0x00; 1028 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1029 1030 /* ???*/ 1031 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1032 buf[0] = 0x01; 1033 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1034 buf[0] = 0x70; 1035 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 1036 buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66; 1037 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 1038 1039 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 1040 buf[0] = 0x11; 1041 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 1042 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1043 buf[0] = 0x40; 1044 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1045 1046 nxt200x_readbytes(state, 0x10, buf, 1); 1047 buf[0] = 0x10; 1048 nxt200x_writebytes(state, 0x10, buf, 1); 1049 nxt200x_readbytes(state, 0x0A, buf, 1); 1050 buf[0] = 0x21; 1051 nxt200x_writebytes(state, 0x0A, buf, 1); 1052 1053 nxt2004_microcontroller_init(state); 1054 1055 buf[0] = 0x21; 1056 nxt200x_writebytes(state, 0x0A, buf, 1); 1057 buf[0] = 0x7E; 1058 nxt200x_writebytes(state, 0xE9, buf, 1); 1059 buf[0] = 0x00; 1060 nxt200x_writebytes(state, 0xEA, buf, 1); 1061 1062 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1063 buf[0] = 0x00; 1064 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1065 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1066 buf[0] = 0x00; 1067 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1068 1069 /* soft reset? */ 1070 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1071 buf[0] = 0x10; 1072 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1073 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1074 buf[0] = 0x00; 1075 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1076 1077 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1078 buf[0] = 0x04; 1079 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1080 buf[0] = 0x00; 1081 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 1082 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; 1083 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 1084 1085 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 1086 buf[0] = 0x11; 1087 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 1088 1089 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1090 buf[0] = 0x44; 1091 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1092 1093 /* initialize tuner */ 1094 nxt200x_readbytes(state, 0x10, buf, 1); 1095 buf[0] = 0x12; 1096 nxt200x_writebytes(state, 0x10, buf, 1); 1097 buf[0] = 0x04; 1098 nxt200x_writebytes(state, 0x13, buf, 1); 1099 buf[0] = 0x00; 1100 nxt200x_writebytes(state, 0x16, buf, 1); 1101 buf[0] = 0x04; 1102 nxt200x_writebytes(state, 0x14, buf, 1); 1103 buf[0] = 0x00; 1104 nxt200x_writebytes(state, 0x14, buf, 1); 1105 nxt200x_writebytes(state, 0x17, buf, 1); 1106 nxt200x_writebytes(state, 0x14, buf, 1); 1107 nxt200x_writebytes(state, 0x17, buf, 1); 1108 1109 return 0; 1110 } 1111 1112 static int nxt200x_init(struct dvb_frontend* fe) 1113 { 1114 struct nxt200x_state* state = fe->demodulator_priv; 1115 int ret = 0; 1116 1117 if (!state->initialised) { 1118 switch (state->demod_chip) { 1119 case NXT2002: 1120 ret = nxt2002_init(fe); 1121 break; 1122 case NXT2004: 1123 ret = nxt2004_init(fe); 1124 break; 1125 default: 1126 return -EINVAL; 1127 break; 1128 } 1129 state->initialised = 1; 1130 } 1131 return ret; 1132 } 1133 1134 static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) 1135 { 1136 fesettings->min_delay_ms = 500; 1137 fesettings->step_size = 0; 1138 fesettings->max_drift = 0; 1139 return 0; 1140 } 1141 1142 static void nxt200x_release(struct dvb_frontend* fe) 1143 { 1144 struct nxt200x_state* state = fe->demodulator_priv; 1145 kfree(state); 1146 } 1147 1148 static const struct dvb_frontend_ops nxt200x_ops; 1149 1150 struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config, 1151 struct i2c_adapter* i2c) 1152 { 1153 struct nxt200x_state* state = NULL; 1154 u8 buf [] = {0,0,0,0,0}; 1155 1156 /* allocate memory for the internal state */ 1157 state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL); 1158 if (state == NULL) 1159 goto error; 1160 1161 /* setup the state */ 1162 state->config = config; 1163 state->i2c = i2c; 1164 state->initialised = 0; 1165 1166 /* read card id */ 1167 nxt200x_readbytes(state, 0x00, buf, 5); 1168 dprintk("NXT info: %*ph\n", 5, buf); 1169 1170 /* set demod chip */ 1171 switch (buf[0]) { 1172 case 0x04: 1173 state->demod_chip = NXT2002; 1174 pr_info("NXT2002 Detected\n"); 1175 break; 1176 case 0x05: 1177 state->demod_chip = NXT2004; 1178 pr_info("NXT2004 Detected\n"); 1179 break; 1180 default: 1181 goto error; 1182 } 1183 1184 /* make sure demod chip is supported */ 1185 switch (state->demod_chip) { 1186 case NXT2002: 1187 if (buf[0] != 0x04) goto error; /* device id */ 1188 if (buf[1] != 0x02) goto error; /* fab id */ 1189 if (buf[2] != 0x11) goto error; /* month */ 1190 if (buf[3] != 0x20) goto error; /* year msb */ 1191 if (buf[4] != 0x00) goto error; /* year lsb */ 1192 break; 1193 case NXT2004: 1194 if (buf[0] != 0x05) goto error; /* device id */ 1195 break; 1196 default: 1197 goto error; 1198 } 1199 1200 /* create dvb_frontend */ 1201 memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops)); 1202 state->frontend.demodulator_priv = state; 1203 return &state->frontend; 1204 1205 error: 1206 kfree(state); 1207 pr_err("Unknown/Unsupported NXT chip: %*ph\n", 5, buf); 1208 return NULL; 1209 } 1210 1211 static const struct dvb_frontend_ops nxt200x_ops = { 1212 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 1213 .info = { 1214 .name = "Nextwave NXT200X VSB/QAM frontend", 1215 .frequency_min_hz = 54 * MHz, 1216 .frequency_max_hz = 860 * MHz, 1217 .frequency_stepsize_hz = 166666, /* stepsize is just a guess */ 1218 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1219 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1220 FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256 1221 }, 1222 1223 .release = nxt200x_release, 1224 1225 .init = nxt200x_init, 1226 .sleep = nxt200x_sleep, 1227 1228 .set_frontend = nxt200x_setup_frontend_parameters, 1229 .get_tune_settings = nxt200x_get_tune_settings, 1230 1231 .read_status = nxt200x_read_status, 1232 .read_ber = nxt200x_read_ber, 1233 .read_signal_strength = nxt200x_read_signal_strength, 1234 .read_snr = nxt200x_read_snr, 1235 .read_ucblocks = nxt200x_read_ucblocks, 1236 }; 1237 1238 module_param(debug, int, 0644); 1239 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 1240 1241 MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); 1242 MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob"); 1243 MODULE_LICENSE("GPL"); 1244 1245 EXPORT_SYMBOL(nxt200x_attach); 1246 1247