1 /* 2 * Support for NXT2002 and NXT2004 - VSB/QAM 3 * 4 * Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com> 5 * Copyright (C) 2006-2014 Michael Krufky <mkrufky@linuxtv.org> 6 * based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net> 7 * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 * 23 */ 24 25 /* 26 * NOTES ABOUT THIS DRIVER 27 * 28 * This Linux driver supports: 29 * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002) 30 * AverTVHD MCE A180 (NXT2004) 31 * ATI HDTV Wonder (NXT2004) 32 * 33 * This driver needs external firmware. Please use the command 34 * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2002" or 35 * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2004" to 36 * download/extract the appropriate firmware, and then copy it to 37 * /usr/lib/hotplug/firmware/ or /lib/firmware/ 38 * (depending on configuration of firmware hotplug). 39 */ 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 /* Max transfer size done by I2C transfer functions */ 43 #define MAX_XFER_SIZE 256 44 45 #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw" 46 #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw" 47 #define CRC_CCIT_MASK 0x1021 48 49 #include <linux/kernel.h> 50 #include <linux/init.h> 51 #include <linux/module.h> 52 #include <linux/slab.h> 53 #include <linux/string.h> 54 55 #include "dvb_frontend.h" 56 #include "nxt200x.h" 57 58 struct nxt200x_state { 59 60 struct i2c_adapter* i2c; 61 const struct nxt200x_config* config; 62 struct dvb_frontend frontend; 63 64 /* demodulator private data */ 65 nxt_chip_type demod_chip; 66 u8 initialised:1; 67 }; 68 69 static int debug; 70 #define dprintk(args...) do { if (debug) pr_debug(args); } while (0) 71 72 static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len) 73 { 74 int err; 75 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len }; 76 77 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 78 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", 79 __func__, addr, err); 80 return -EREMOTEIO; 81 } 82 return 0; 83 } 84 85 static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len) 86 { 87 int err; 88 struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len }; 89 90 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 91 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", 92 __func__, addr, err); 93 return -EREMOTEIO; 94 } 95 return 0; 96 } 97 98 static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg, 99 const u8 *buf, u8 len) 100 { 101 u8 buf2[MAX_XFER_SIZE]; 102 int err; 103 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 }; 104 105 if (1 + len > sizeof(buf2)) { 106 pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n", 107 __func__, reg, len); 108 return -EINVAL; 109 } 110 111 buf2[0] = reg; 112 memcpy(&buf2[1], buf, len); 113 114 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 115 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", 116 __func__, state->config->demod_address, err); 117 return -EREMOTEIO; 118 } 119 return 0; 120 } 121 122 static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len) 123 { 124 u8 reg2 [] = { reg }; 125 126 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 }, 127 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } }; 128 129 int err; 130 131 if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) { 132 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", 133 __func__, state->config->demod_address, err); 134 return -EREMOTEIO; 135 } 136 return 0; 137 } 138 139 static u16 nxt200x_crc(u16 crc, u8 c) 140 { 141 u8 i; 142 u16 input = (u16) c & 0xFF; 143 144 input<<=8; 145 for(i=0; i<8; i++) { 146 if((crc^input) & 0x8000) 147 crc=(crc<<1)^CRC_CCIT_MASK; 148 else 149 crc<<=1; 150 input<<=1; 151 } 152 return crc; 153 } 154 155 static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) 156 { 157 u8 attr, len2, buf; 158 dprintk("%s\n", __func__); 159 160 /* set mutli register register */ 161 nxt200x_writebytes(state, 0x35, ®, 1); 162 163 /* send the actual data */ 164 nxt200x_writebytes(state, 0x36, data, len); 165 166 switch (state->demod_chip) { 167 case NXT2002: 168 len2 = len; 169 buf = 0x02; 170 break; 171 case NXT2004: 172 /* probably not right, but gives correct values */ 173 attr = 0x02; 174 if (reg & 0x80) { 175 attr = attr << 1; 176 if (reg & 0x04) 177 attr = attr >> 1; 178 } 179 /* set write bit */ 180 len2 = ((attr << 4) | 0x10) | len; 181 buf = 0x80; 182 break; 183 default: 184 return -EINVAL; 185 break; 186 } 187 188 /* set multi register length */ 189 nxt200x_writebytes(state, 0x34, &len2, 1); 190 191 /* toggle the multireg write bit */ 192 nxt200x_writebytes(state, 0x21, &buf, 1); 193 194 nxt200x_readbytes(state, 0x21, &buf, 1); 195 196 switch (state->demod_chip) { 197 case NXT2002: 198 if ((buf & 0x02) == 0) 199 return 0; 200 break; 201 case NXT2004: 202 if (buf == 0) 203 return 0; 204 break; 205 default: 206 return -EINVAL; 207 break; 208 } 209 210 pr_warn("Error writing multireg register 0x%02X\n", reg); 211 212 return 0; 213 } 214 215 static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) 216 { 217 int i; 218 u8 buf, len2, attr; 219 dprintk("%s\n", __func__); 220 221 /* set mutli register register */ 222 nxt200x_writebytes(state, 0x35, ®, 1); 223 224 switch (state->demod_chip) { 225 case NXT2002: 226 /* set multi register length */ 227 len2 = len & 0x80; 228 nxt200x_writebytes(state, 0x34, &len2, 1); 229 230 /* read the actual data */ 231 nxt200x_readbytes(state, reg, data, len); 232 return 0; 233 break; 234 case NXT2004: 235 /* probably not right, but gives correct values */ 236 attr = 0x02; 237 if (reg & 0x80) { 238 attr = attr << 1; 239 if (reg & 0x04) 240 attr = attr >> 1; 241 } 242 243 /* set multi register length */ 244 len2 = (attr << 4) | len; 245 nxt200x_writebytes(state, 0x34, &len2, 1); 246 247 /* toggle the multireg bit*/ 248 buf = 0x80; 249 nxt200x_writebytes(state, 0x21, &buf, 1); 250 251 /* read the actual data */ 252 for(i = 0; i < len; i++) { 253 nxt200x_readbytes(state, 0x36 + i, &data[i], 1); 254 } 255 return 0; 256 break; 257 default: 258 return -EINVAL; 259 break; 260 } 261 } 262 263 static void nxt200x_microcontroller_stop (struct nxt200x_state* state) 264 { 265 u8 buf, stopval, counter = 0; 266 dprintk("%s\n", __func__); 267 268 /* set correct stop value */ 269 switch (state->demod_chip) { 270 case NXT2002: 271 stopval = 0x40; 272 break; 273 case NXT2004: 274 stopval = 0x10; 275 break; 276 default: 277 stopval = 0; 278 break; 279 } 280 281 buf = 0x80; 282 nxt200x_writebytes(state, 0x22, &buf, 1); 283 284 while (counter < 20) { 285 nxt200x_readbytes(state, 0x31, &buf, 1); 286 if (buf & stopval) 287 return; 288 msleep(10); 289 counter++; 290 } 291 292 pr_warn("Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n"); 293 return; 294 } 295 296 static void nxt200x_microcontroller_start (struct nxt200x_state* state) 297 { 298 u8 buf; 299 dprintk("%s\n", __func__); 300 301 buf = 0x00; 302 nxt200x_writebytes(state, 0x22, &buf, 1); 303 } 304 305 static void nxt2004_microcontroller_init (struct nxt200x_state* state) 306 { 307 u8 buf[9]; 308 u8 counter = 0; 309 dprintk("%s\n", __func__); 310 311 buf[0] = 0x00; 312 nxt200x_writebytes(state, 0x2b, buf, 1); 313 buf[0] = 0x70; 314 nxt200x_writebytes(state, 0x34, buf, 1); 315 buf[0] = 0x04; 316 nxt200x_writebytes(state, 0x35, buf, 1); 317 buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89; 318 buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0; 319 nxt200x_writebytes(state, 0x36, buf, 9); 320 buf[0] = 0x80; 321 nxt200x_writebytes(state, 0x21, buf, 1); 322 323 while (counter < 20) { 324 nxt200x_readbytes(state, 0x21, buf, 1); 325 if (buf[0] == 0) 326 return; 327 msleep(10); 328 counter++; 329 } 330 331 pr_warn("Timeout waiting for nxt2004 to init.\n"); 332 333 return; 334 } 335 336 static int nxt200x_writetuner (struct nxt200x_state* state, u8* data) 337 { 338 u8 buf, count = 0; 339 340 dprintk("%s\n", __func__); 341 342 dprintk("Tuner Bytes: %*ph\n", 4, data + 1); 343 344 /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip. 345 * direct write is required for Philips TUV1236D and ALPS TDHU2 */ 346 switch (state->demod_chip) { 347 case NXT2004: 348 if (i2c_writebytes(state, data[0], data+1, 4)) 349 pr_warn("error writing to tuner\n"); 350 /* wait until we have a lock */ 351 while (count < 20) { 352 i2c_readbytes(state, data[0], &buf, 1); 353 if (buf & 0x40) 354 return 0; 355 msleep(100); 356 count++; 357 } 358 pr_warn("timeout waiting for tuner lock\n"); 359 break; 360 case NXT2002: 361 /* set the i2c transfer speed to the tuner */ 362 buf = 0x03; 363 nxt200x_writebytes(state, 0x20, &buf, 1); 364 365 /* setup to transfer 4 bytes via i2c */ 366 buf = 0x04; 367 nxt200x_writebytes(state, 0x34, &buf, 1); 368 369 /* write actual tuner bytes */ 370 nxt200x_writebytes(state, 0x36, data+1, 4); 371 372 /* set tuner i2c address */ 373 buf = data[0] << 1; 374 nxt200x_writebytes(state, 0x35, &buf, 1); 375 376 /* write UC Opmode to begin transfer */ 377 buf = 0x80; 378 nxt200x_writebytes(state, 0x21, &buf, 1); 379 380 while (count < 20) { 381 nxt200x_readbytes(state, 0x21, &buf, 1); 382 if ((buf & 0x80)== 0x00) 383 return 0; 384 msleep(100); 385 count++; 386 } 387 pr_warn("timeout error writing to tuner\n"); 388 break; 389 default: 390 return -EINVAL; 391 break; 392 } 393 return 0; 394 } 395 396 static void nxt200x_agc_reset(struct nxt200x_state* state) 397 { 398 u8 buf; 399 dprintk("%s\n", __func__); 400 401 switch (state->demod_chip) { 402 case NXT2002: 403 buf = 0x08; 404 nxt200x_writebytes(state, 0x08, &buf, 1); 405 buf = 0x00; 406 nxt200x_writebytes(state, 0x08, &buf, 1); 407 break; 408 case NXT2004: 409 nxt200x_readreg_multibyte(state, 0x08, &buf, 1); 410 buf = 0x08; 411 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); 412 buf = 0x00; 413 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); 414 break; 415 default: 416 break; 417 } 418 return; 419 } 420 421 static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) 422 { 423 424 struct nxt200x_state* state = fe->demodulator_priv; 425 u8 buf[3], written = 0, chunkpos = 0; 426 u16 rambase, position, crc = 0; 427 428 dprintk("%s\n", __func__); 429 dprintk("Firmware is %zu bytes\n", fw->size); 430 431 /* Get the RAM base for this nxt2002 */ 432 nxt200x_readbytes(state, 0x10, buf, 1); 433 434 if (buf[0] & 0x10) 435 rambase = 0x1000; 436 else 437 rambase = 0x0000; 438 439 dprintk("rambase on this nxt2002 is %04X\n", rambase); 440 441 /* Hold the micro in reset while loading firmware */ 442 buf[0] = 0x80; 443 nxt200x_writebytes(state, 0x2B, buf, 1); 444 445 for (position = 0; position < fw->size; position++) { 446 if (written == 0) { 447 crc = 0; 448 chunkpos = 0x28; 449 buf[0] = ((rambase + position) >> 8); 450 buf[1] = (rambase + position) & 0xFF; 451 buf[2] = 0x81; 452 /* write starting address */ 453 nxt200x_writebytes(state, 0x29, buf, 3); 454 } 455 written++; 456 chunkpos++; 457 458 if ((written % 4) == 0) 459 nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4); 460 461 crc = nxt200x_crc(crc, fw->data[position]); 462 463 if ((written == 255) || (position+1 == fw->size)) { 464 /* write remaining bytes of firmware */ 465 nxt200x_writebytes(state, chunkpos+4-(written %4), 466 &fw->data[position-(written %4) + 1], 467 written %4); 468 buf[0] = crc << 8; 469 buf[1] = crc & 0xFF; 470 471 /* write crc */ 472 nxt200x_writebytes(state, 0x2C, buf, 2); 473 474 /* do a read to stop things */ 475 nxt200x_readbytes(state, 0x2A, buf, 1); 476 477 /* set transfer mode to complete */ 478 buf[0] = 0x80; 479 nxt200x_writebytes(state, 0x2B, buf, 1); 480 481 written = 0; 482 } 483 } 484 485 return 0; 486 }; 487 488 static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) 489 { 490 491 struct nxt200x_state* state = fe->demodulator_priv; 492 u8 buf[3]; 493 u16 rambase, position, crc=0; 494 495 dprintk("%s\n", __func__); 496 dprintk("Firmware is %zu bytes\n", fw->size); 497 498 /* set rambase */ 499 rambase = 0x1000; 500 501 /* hold the micro in reset while loading firmware */ 502 buf[0] = 0x80; 503 nxt200x_writebytes(state, 0x2B, buf,1); 504 505 /* calculate firmware CRC */ 506 for (position = 0; position < fw->size; position++) { 507 crc = nxt200x_crc(crc, fw->data[position]); 508 } 509 510 buf[0] = rambase >> 8; 511 buf[1] = rambase & 0xFF; 512 buf[2] = 0x81; 513 /* write starting address */ 514 nxt200x_writebytes(state,0x29,buf,3); 515 516 for (position = 0; position < fw->size;) { 517 nxt200x_writebytes(state, 0x2C, &fw->data[position], 518 fw->size-position > 255 ? 255 : fw->size-position); 519 position += (fw->size-position > 255 ? 255 : fw->size-position); 520 } 521 buf[0] = crc >> 8; 522 buf[1] = crc & 0xFF; 523 524 dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]); 525 526 /* write crc */ 527 nxt200x_writebytes(state, 0x2C, buf,2); 528 529 /* do a read to stop things */ 530 nxt200x_readbytes(state, 0x2C, buf, 1); 531 532 /* set transfer mode to complete */ 533 buf[0] = 0x80; 534 nxt200x_writebytes(state, 0x2B, buf,1); 535 536 return 0; 537 }; 538 539 static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe) 540 { 541 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 542 struct nxt200x_state* state = fe->demodulator_priv; 543 u8 buf[5]; 544 545 /* stop the micro first */ 546 nxt200x_microcontroller_stop(state); 547 548 if (state->demod_chip == NXT2004) { 549 /* make sure demod is set to digital */ 550 buf[0] = 0x04; 551 nxt200x_writebytes(state, 0x14, buf, 1); 552 buf[0] = 0x00; 553 nxt200x_writebytes(state, 0x17, buf, 1); 554 } 555 556 /* set additional params */ 557 switch (p->modulation) { 558 case QAM_64: 559 case QAM_256: 560 /* Set punctured clock for QAM */ 561 /* This is just a guess since I am unable to test it */ 562 if (state->config->set_ts_params) 563 state->config->set_ts_params(fe, 1); 564 break; 565 case VSB_8: 566 /* Set non-punctured clock for VSB */ 567 if (state->config->set_ts_params) 568 state->config->set_ts_params(fe, 0); 569 break; 570 default: 571 return -EINVAL; 572 break; 573 } 574 575 if (fe->ops.tuner_ops.calc_regs) { 576 /* get tuning information */ 577 fe->ops.tuner_ops.calc_regs(fe, buf, 5); 578 579 /* write frequency information */ 580 nxt200x_writetuner(state, buf); 581 } 582 583 /* reset the agc now that tuning has been completed */ 584 nxt200x_agc_reset(state); 585 586 /* set target power level */ 587 switch (p->modulation) { 588 case QAM_64: 589 case QAM_256: 590 buf[0] = 0x74; 591 break; 592 case VSB_8: 593 buf[0] = 0x70; 594 break; 595 default: 596 return -EINVAL; 597 break; 598 } 599 nxt200x_writebytes(state, 0x42, buf, 1); 600 601 /* configure sdm */ 602 switch (state->demod_chip) { 603 case NXT2002: 604 buf[0] = 0x87; 605 break; 606 case NXT2004: 607 buf[0] = 0x07; 608 break; 609 default: 610 return -EINVAL; 611 break; 612 } 613 nxt200x_writebytes(state, 0x57, buf, 1); 614 615 /* write sdm1 input */ 616 buf[0] = 0x10; 617 buf[1] = 0x00; 618 switch (state->demod_chip) { 619 case NXT2002: 620 nxt200x_writereg_multibyte(state, 0x58, buf, 2); 621 break; 622 case NXT2004: 623 nxt200x_writebytes(state, 0x58, buf, 2); 624 break; 625 default: 626 return -EINVAL; 627 break; 628 } 629 630 /* write sdmx input */ 631 switch (p->modulation) { 632 case QAM_64: 633 buf[0] = 0x68; 634 break; 635 case QAM_256: 636 buf[0] = 0x64; 637 break; 638 case VSB_8: 639 buf[0] = 0x60; 640 break; 641 default: 642 return -EINVAL; 643 break; 644 } 645 buf[1] = 0x00; 646 switch (state->demod_chip) { 647 case NXT2002: 648 nxt200x_writereg_multibyte(state, 0x5C, buf, 2); 649 break; 650 case NXT2004: 651 nxt200x_writebytes(state, 0x5C, buf, 2); 652 break; 653 default: 654 return -EINVAL; 655 break; 656 } 657 658 /* write adc power lpf fc */ 659 buf[0] = 0x05; 660 nxt200x_writebytes(state, 0x43, buf, 1); 661 662 if (state->demod_chip == NXT2004) { 663 /* write ??? */ 664 buf[0] = 0x00; 665 buf[1] = 0x00; 666 nxt200x_writebytes(state, 0x46, buf, 2); 667 } 668 669 /* write accumulator2 input */ 670 buf[0] = 0x80; 671 buf[1] = 0x00; 672 switch (state->demod_chip) { 673 case NXT2002: 674 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); 675 break; 676 case NXT2004: 677 nxt200x_writebytes(state, 0x4B, buf, 2); 678 break; 679 default: 680 return -EINVAL; 681 break; 682 } 683 684 /* write kg1 */ 685 buf[0] = 0x00; 686 nxt200x_writebytes(state, 0x4D, buf, 1); 687 688 /* write sdm12 lpf fc */ 689 buf[0] = 0x44; 690 nxt200x_writebytes(state, 0x55, buf, 1); 691 692 /* write agc control reg */ 693 buf[0] = 0x04; 694 nxt200x_writebytes(state, 0x41, buf, 1); 695 696 if (state->demod_chip == NXT2004) { 697 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 698 buf[0] = 0x24; 699 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 700 701 /* soft reset? */ 702 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 703 buf[0] = 0x10; 704 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 705 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 706 buf[0] = 0x00; 707 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 708 709 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 710 buf[0] = 0x04; 711 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 712 buf[0] = 0x00; 713 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 714 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; 715 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 716 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 717 buf[0] = 0x11; 718 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 719 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 720 buf[0] = 0x44; 721 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 722 } 723 724 /* write agc ucgp0 */ 725 switch (p->modulation) { 726 case QAM_64: 727 buf[0] = 0x02; 728 break; 729 case QAM_256: 730 buf[0] = 0x03; 731 break; 732 case VSB_8: 733 buf[0] = 0x00; 734 break; 735 default: 736 return -EINVAL; 737 break; 738 } 739 nxt200x_writebytes(state, 0x30, buf, 1); 740 741 /* write agc control reg */ 742 buf[0] = 0x00; 743 nxt200x_writebytes(state, 0x41, buf, 1); 744 745 /* write accumulator2 input */ 746 buf[0] = 0x80; 747 buf[1] = 0x00; 748 switch (state->demod_chip) { 749 case NXT2002: 750 nxt200x_writereg_multibyte(state, 0x49, buf, 2); 751 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); 752 break; 753 case NXT2004: 754 nxt200x_writebytes(state, 0x49, buf, 2); 755 nxt200x_writebytes(state, 0x4B, buf, 2); 756 break; 757 default: 758 return -EINVAL; 759 break; 760 } 761 762 /* write agc control reg */ 763 buf[0] = 0x04; 764 nxt200x_writebytes(state, 0x41, buf, 1); 765 766 nxt200x_microcontroller_start(state); 767 768 if (state->demod_chip == NXT2004) { 769 nxt2004_microcontroller_init(state); 770 771 /* ???? */ 772 buf[0] = 0xF0; 773 buf[1] = 0x00; 774 nxt200x_writebytes(state, 0x5C, buf, 2); 775 } 776 777 /* adjacent channel detection should be done here, but I don't 778 have any stations with this need so I cannot test it */ 779 780 return 0; 781 } 782 783 static int nxt200x_read_status(struct dvb_frontend *fe, enum fe_status *status) 784 { 785 struct nxt200x_state* state = fe->demodulator_priv; 786 u8 lock; 787 nxt200x_readbytes(state, 0x31, &lock, 1); 788 789 *status = 0; 790 if (lock & 0x20) { 791 *status |= FE_HAS_SIGNAL; 792 *status |= FE_HAS_CARRIER; 793 *status |= FE_HAS_VITERBI; 794 *status |= FE_HAS_SYNC; 795 *status |= FE_HAS_LOCK; 796 } 797 return 0; 798 } 799 800 static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber) 801 { 802 struct nxt200x_state* state = fe->demodulator_priv; 803 u8 b[3]; 804 805 nxt200x_readreg_multibyte(state, 0xE6, b, 3); 806 807 *ber = ((b[0] << 8) + b[1]) * 8; 808 809 return 0; 810 } 811 812 static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength) 813 { 814 struct nxt200x_state* state = fe->demodulator_priv; 815 u8 b[2]; 816 u16 temp = 0; 817 818 /* setup to read cluster variance */ 819 b[0] = 0x00; 820 nxt200x_writebytes(state, 0xA1, b, 1); 821 822 /* get multreg val */ 823 nxt200x_readreg_multibyte(state, 0xA6, b, 2); 824 825 temp = (b[0] << 8) | b[1]; 826 *strength = ((0x7FFF - temp) & 0x0FFF) * 16; 827 828 return 0; 829 } 830 831 static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr) 832 { 833 834 struct nxt200x_state* state = fe->demodulator_priv; 835 u8 b[2]; 836 u16 temp = 0, temp2; 837 u32 snrdb = 0; 838 839 /* setup to read cluster variance */ 840 b[0] = 0x00; 841 nxt200x_writebytes(state, 0xA1, b, 1); 842 843 /* get multreg val from 0xA6 */ 844 nxt200x_readreg_multibyte(state, 0xA6, b, 2); 845 846 temp = (b[0] << 8) | b[1]; 847 temp2 = 0x7FFF - temp; 848 849 /* snr will be in db */ 850 if (temp2 > 0x7F00) 851 snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) ); 852 else if (temp2 > 0x7EC0) 853 snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) ); 854 else if (temp2 > 0x7C00) 855 snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) ); 856 else 857 snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) ); 858 859 /* the value reported back from the frontend will be FFFF=32db 0000=0db */ 860 *snr = snrdb * (0xFFFF/32000); 861 862 return 0; 863 } 864 865 static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 866 { 867 struct nxt200x_state* state = fe->demodulator_priv; 868 u8 b[3]; 869 870 nxt200x_readreg_multibyte(state, 0xE6, b, 3); 871 *ucblocks = b[2]; 872 873 return 0; 874 } 875 876 static int nxt200x_sleep(struct dvb_frontend* fe) 877 { 878 return 0; 879 } 880 881 static int nxt2002_init(struct dvb_frontend* fe) 882 { 883 struct nxt200x_state* state = fe->demodulator_priv; 884 const struct firmware *fw; 885 int ret; 886 u8 buf[2]; 887 888 /* request the firmware, this will block until someone uploads it */ 889 pr_debug("%s: Waiting for firmware upload (%s)...\n", 890 __func__, NXT2002_DEFAULT_FIRMWARE); 891 ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE, 892 state->i2c->dev.parent); 893 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__); 894 if (ret) { 895 pr_err("%s: No firmware uploaded (timeout or file not found?)\n", 896 __func__); 897 return ret; 898 } 899 900 ret = nxt2002_load_firmware(fe, fw); 901 release_firmware(fw); 902 if (ret) { 903 pr_err("%s: Writing firmware to device failed\n", __func__); 904 return ret; 905 } 906 pr_info("%s: Firmware upload complete\n", __func__); 907 908 /* Put the micro into reset */ 909 nxt200x_microcontroller_stop(state); 910 911 /* ensure transfer is complete */ 912 buf[0]=0x00; 913 nxt200x_writebytes(state, 0x2B, buf, 1); 914 915 /* Put the micro into reset for real this time */ 916 nxt200x_microcontroller_stop(state); 917 918 /* soft reset everything (agc,frontend,eq,fec)*/ 919 buf[0] = 0x0F; 920 nxt200x_writebytes(state, 0x08, buf, 1); 921 buf[0] = 0x00; 922 nxt200x_writebytes(state, 0x08, buf, 1); 923 924 /* write agc sdm configure */ 925 buf[0] = 0xF1; 926 nxt200x_writebytes(state, 0x57, buf, 1); 927 928 /* write mod output format */ 929 buf[0] = 0x20; 930 nxt200x_writebytes(state, 0x09, buf, 1); 931 932 /* write fec mpeg mode */ 933 buf[0] = 0x7E; 934 buf[1] = 0x00; 935 nxt200x_writebytes(state, 0xE9, buf, 2); 936 937 /* write mux selection */ 938 buf[0] = 0x00; 939 nxt200x_writebytes(state, 0xCC, buf, 1); 940 941 return 0; 942 } 943 944 static int nxt2004_init(struct dvb_frontend* fe) 945 { 946 struct nxt200x_state* state = fe->demodulator_priv; 947 const struct firmware *fw; 948 int ret; 949 u8 buf[3]; 950 951 /* ??? */ 952 buf[0]=0x00; 953 nxt200x_writebytes(state, 0x1E, buf, 1); 954 955 /* request the firmware, this will block until someone uploads it */ 956 pr_debug("%s: Waiting for firmware upload (%s)...\n", 957 __func__, NXT2004_DEFAULT_FIRMWARE); 958 ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE, 959 state->i2c->dev.parent); 960 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__); 961 if (ret) { 962 pr_err("%s: No firmware uploaded (timeout or file not found?)\n", 963 __func__); 964 return ret; 965 } 966 967 ret = nxt2004_load_firmware(fe, fw); 968 release_firmware(fw); 969 if (ret) { 970 pr_err("%s: Writing firmware to device failed\n", __func__); 971 return ret; 972 } 973 pr_info("%s: Firmware upload complete\n", __func__); 974 975 /* ensure transfer is complete */ 976 buf[0] = 0x01; 977 nxt200x_writebytes(state, 0x19, buf, 1); 978 979 nxt2004_microcontroller_init(state); 980 nxt200x_microcontroller_stop(state); 981 nxt200x_microcontroller_stop(state); 982 nxt2004_microcontroller_init(state); 983 nxt200x_microcontroller_stop(state); 984 985 /* soft reset everything (agc,frontend,eq,fec)*/ 986 buf[0] = 0xFF; 987 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 988 buf[0] = 0x00; 989 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 990 991 /* write agc sdm configure */ 992 buf[0] = 0xD7; 993 nxt200x_writebytes(state, 0x57, buf, 1); 994 995 /* ???*/ 996 buf[0] = 0x07; 997 buf[1] = 0xfe; 998 nxt200x_writebytes(state, 0x35, buf, 2); 999 buf[0] = 0x12; 1000 nxt200x_writebytes(state, 0x34, buf, 1); 1001 buf[0] = 0x80; 1002 nxt200x_writebytes(state, 0x21, buf, 1); 1003 1004 /* ???*/ 1005 buf[0] = 0x21; 1006 nxt200x_writebytes(state, 0x0A, buf, 1); 1007 1008 /* ???*/ 1009 buf[0] = 0x01; 1010 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1011 1012 /* write fec mpeg mode */ 1013 buf[0] = 0x7E; 1014 buf[1] = 0x00; 1015 nxt200x_writebytes(state, 0xE9, buf, 2); 1016 1017 /* write mux selection */ 1018 buf[0] = 0x00; 1019 nxt200x_writebytes(state, 0xCC, buf, 1); 1020 1021 /* ???*/ 1022 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1023 buf[0] = 0x00; 1024 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1025 1026 /* soft reset? */ 1027 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1028 buf[0] = 0x10; 1029 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1030 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1031 buf[0] = 0x00; 1032 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1033 1034 /* ???*/ 1035 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1036 buf[0] = 0x01; 1037 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1038 buf[0] = 0x70; 1039 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 1040 buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66; 1041 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 1042 1043 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 1044 buf[0] = 0x11; 1045 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 1046 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1047 buf[0] = 0x40; 1048 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1049 1050 nxt200x_readbytes(state, 0x10, buf, 1); 1051 buf[0] = 0x10; 1052 nxt200x_writebytes(state, 0x10, buf, 1); 1053 nxt200x_readbytes(state, 0x0A, buf, 1); 1054 buf[0] = 0x21; 1055 nxt200x_writebytes(state, 0x0A, buf, 1); 1056 1057 nxt2004_microcontroller_init(state); 1058 1059 buf[0] = 0x21; 1060 nxt200x_writebytes(state, 0x0A, buf, 1); 1061 buf[0] = 0x7E; 1062 nxt200x_writebytes(state, 0xE9, buf, 1); 1063 buf[0] = 0x00; 1064 nxt200x_writebytes(state, 0xEA, buf, 1); 1065 1066 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1067 buf[0] = 0x00; 1068 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1069 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1070 buf[0] = 0x00; 1071 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1072 1073 /* soft reset? */ 1074 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1075 buf[0] = 0x10; 1076 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1077 nxt200x_readreg_multibyte(state, 0x08, buf, 1); 1078 buf[0] = 0x00; 1079 nxt200x_writereg_multibyte(state, 0x08, buf, 1); 1080 1081 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1082 buf[0] = 0x04; 1083 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1084 buf[0] = 0x00; 1085 nxt200x_writereg_multibyte(state, 0x81, buf, 1); 1086 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; 1087 nxt200x_writereg_multibyte(state, 0x82, buf, 3); 1088 1089 nxt200x_readreg_multibyte(state, 0x88, buf, 1); 1090 buf[0] = 0x11; 1091 nxt200x_writereg_multibyte(state, 0x88, buf, 1); 1092 1093 nxt200x_readreg_multibyte(state, 0x80, buf, 1); 1094 buf[0] = 0x44; 1095 nxt200x_writereg_multibyte(state, 0x80, buf, 1); 1096 1097 /* initialize tuner */ 1098 nxt200x_readbytes(state, 0x10, buf, 1); 1099 buf[0] = 0x12; 1100 nxt200x_writebytes(state, 0x10, buf, 1); 1101 buf[0] = 0x04; 1102 nxt200x_writebytes(state, 0x13, buf, 1); 1103 buf[0] = 0x00; 1104 nxt200x_writebytes(state, 0x16, buf, 1); 1105 buf[0] = 0x04; 1106 nxt200x_writebytes(state, 0x14, buf, 1); 1107 buf[0] = 0x00; 1108 nxt200x_writebytes(state, 0x14, buf, 1); 1109 nxt200x_writebytes(state, 0x17, buf, 1); 1110 nxt200x_writebytes(state, 0x14, buf, 1); 1111 nxt200x_writebytes(state, 0x17, buf, 1); 1112 1113 return 0; 1114 } 1115 1116 static int nxt200x_init(struct dvb_frontend* fe) 1117 { 1118 struct nxt200x_state* state = fe->demodulator_priv; 1119 int ret = 0; 1120 1121 if (!state->initialised) { 1122 switch (state->demod_chip) { 1123 case NXT2002: 1124 ret = nxt2002_init(fe); 1125 break; 1126 case NXT2004: 1127 ret = nxt2004_init(fe); 1128 break; 1129 default: 1130 return -EINVAL; 1131 break; 1132 } 1133 state->initialised = 1; 1134 } 1135 return ret; 1136 } 1137 1138 static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) 1139 { 1140 fesettings->min_delay_ms = 500; 1141 fesettings->step_size = 0; 1142 fesettings->max_drift = 0; 1143 return 0; 1144 } 1145 1146 static void nxt200x_release(struct dvb_frontend* fe) 1147 { 1148 struct nxt200x_state* state = fe->demodulator_priv; 1149 kfree(state); 1150 } 1151 1152 static struct dvb_frontend_ops nxt200x_ops; 1153 1154 struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config, 1155 struct i2c_adapter* i2c) 1156 { 1157 struct nxt200x_state* state = NULL; 1158 u8 buf [] = {0,0,0,0,0}; 1159 1160 /* allocate memory for the internal state */ 1161 state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL); 1162 if (state == NULL) 1163 goto error; 1164 1165 /* setup the state */ 1166 state->config = config; 1167 state->i2c = i2c; 1168 state->initialised = 0; 1169 1170 /* read card id */ 1171 nxt200x_readbytes(state, 0x00, buf, 5); 1172 dprintk("NXT info: %*ph\n", 5, buf); 1173 1174 /* set demod chip */ 1175 switch (buf[0]) { 1176 case 0x04: 1177 state->demod_chip = NXT2002; 1178 pr_info("NXT2002 Detected\n"); 1179 break; 1180 case 0x05: 1181 state->demod_chip = NXT2004; 1182 pr_info("NXT2004 Detected\n"); 1183 break; 1184 default: 1185 goto error; 1186 } 1187 1188 /* make sure demod chip is supported */ 1189 switch (state->demod_chip) { 1190 case NXT2002: 1191 if (buf[0] != 0x04) goto error; /* device id */ 1192 if (buf[1] != 0x02) goto error; /* fab id */ 1193 if (buf[2] != 0x11) goto error; /* month */ 1194 if (buf[3] != 0x20) goto error; /* year msb */ 1195 if (buf[4] != 0x00) goto error; /* year lsb */ 1196 break; 1197 case NXT2004: 1198 if (buf[0] != 0x05) goto error; /* device id */ 1199 break; 1200 default: 1201 goto error; 1202 } 1203 1204 /* create dvb_frontend */ 1205 memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops)); 1206 state->frontend.demodulator_priv = state; 1207 return &state->frontend; 1208 1209 error: 1210 kfree(state); 1211 pr_err("Unknown/Unsupported NXT chip: %*ph\n", 5, buf); 1212 return NULL; 1213 } 1214 1215 static struct dvb_frontend_ops nxt200x_ops = { 1216 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 1217 .info = { 1218 .name = "Nextwave NXT200X VSB/QAM frontend", 1219 .frequency_min = 54000000, 1220 .frequency_max = 860000000, 1221 .frequency_stepsize = 166666, /* stepsize is just a guess */ 1222 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1223 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1224 FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256 1225 }, 1226 1227 .release = nxt200x_release, 1228 1229 .init = nxt200x_init, 1230 .sleep = nxt200x_sleep, 1231 1232 .set_frontend = nxt200x_setup_frontend_parameters, 1233 .get_tune_settings = nxt200x_get_tune_settings, 1234 1235 .read_status = nxt200x_read_status, 1236 .read_ber = nxt200x_read_ber, 1237 .read_signal_strength = nxt200x_read_signal_strength, 1238 .read_snr = nxt200x_read_snr, 1239 .read_ucblocks = nxt200x_read_ucblocks, 1240 }; 1241 1242 module_param(debug, int, 0644); 1243 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 1244 1245 MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); 1246 MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob"); 1247 MODULE_LICENSE("GPL"); 1248 1249 EXPORT_SYMBOL(nxt200x_attach); 1250 1251