1 /*
2  * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
3  *
4  * License type: GPLv2
5  *
6  * This program is free software; you can redistribute it and/or modify it under
7  * the terms of the GNU General Public License as published by the Free Software
8  * Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
12  * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
13  *
14  * This program may alternatively be licensed under a proprietary license from
15  * MaxLinear, Inc.
16  *
17  */
18 
19 #ifndef __MXL58X_REGISTERS_H__
20 #define __MXL58X_REGISTERS_H__
21 
22 #define HYDRA_INTR_STATUS_REG               0x80030008
23 #define HYDRA_INTR_MASK_REG                 0x8003000C
24 
25 #define HYDRA_CRYSTAL_SETTING               0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
26 #define HYDRA_CRYSTAL_CAP                   0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
27 
28 #define HYDRA_CPU_RESET_REG                 0x8003003C
29 #define HYDRA_CPU_RESET_DATA                0x00000400
30 
31 #define HYDRA_RESET_TRANSPORT_FIFO_REG      0x80030028
32 #define HYDRA_RESET_TRANSPORT_FIFO_DATA     0x00000000
33 
34 #define HYDRA_RESET_BBAND_REG               0x80030024
35 #define HYDRA_RESET_BBAND_DATA              0x00000000
36 
37 #define HYDRA_RESET_XBAR_REG                0x80030020
38 #define HYDRA_RESET_XBAR_DATA               0x00000000
39 
40 #define HYDRA_MODULES_CLK_1_REG             0x80030014
41 #define HYDRA_DISABLE_CLK_1                 0x00000000
42 
43 #define HYDRA_MODULES_CLK_2_REG             0x8003001C
44 #define HYDRA_DISABLE_CLK_2                 0x0000000B
45 
46 #define HYDRA_PRCM_ROOT_CLK_REG             0x80030018
47 #define HYDRA_PRCM_ROOT_CLK_DISABLE         0x00000000
48 
49 #define HYDRA_CPU_RESET_CHECK_REG           0x80030008
50 #define HYDRA_CPU_RESET_CHECK_OFFSET        0x40000000  /* <bit 30> */
51 
52 #define HYDRA_SKU_ID_REG                    0x90000190
53 
54 #define FW_DL_SIGN_ADDR                     0x3FFFEAE0
55 
56 /* Register to check if FW is running or not */
57 #define HYDRA_HEAR_BEAT                     0x3FFFEDDC
58 
59 /* Firmware version */
60 #define HYDRA_FIRMWARE_VERSION              0x3FFFEDB8
61 #define HYDRA_FW_RC_VERSION                 0x3FFFCFAC
62 
63 /* Firmware patch version */
64 #define HYDRA_FIRMWARE_PATCH_VERSION        0x3FFFEDC2
65 
66 /* SOC operating temperature in C */
67 #define HYDRA_TEMPARATURE                   0x3FFFEDB4
68 
69 /* Demod & Tuner status registers */
70 /* Demod 0 status base address */
71 #define HYDRA_DEMOD_0_BASE_ADDR             0x3FFFC64C
72 
73 /* Tuner 0 status base address */
74 #define HYDRA_TUNER_0_BASE_ADDR             0x3FFFCE4C
75 
76 #define POWER_FROM_ADCRSSI_READBACK         0x3FFFEB6C
77 
78 /* Macros to determine base address of respective demod or tuner */
79 #define HYDRA_DMD_STATUS_OFFSET(demodID)        ((demodID) * 0x100)
80 #define HYDRA_TUNER_STATUS_OFFSET(tunerID)      ((tunerID) * 0x40)
81 
82 /* Demod status address offset from respective demod's base address */
83 #define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET               0x3FFFC64C
84 #define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET                 0x3FFFC650
85 #define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET                  0x3FFFC654
86 
87 #define HYDRA_DMD_STANDARD_ADDR_OFFSET                    0x3FFFC658
88 #define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET          0x3FFFC65C
89 #define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET           0x3FFFC660
90 #define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET                 0x3FFFC664
91 #define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET           0x3FFFC668
92 #define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET               0x3FFFC66C
93 
94 #define HYDRA_DMD_SNR_ADDR_OFFSET                         0x3FFFC670
95 #define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET                 0x3FFFC674
96 #define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET             0x3FFFC678
97 #define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET             0x3FFFC67C
98 #define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET             0x3FFFC680
99 #define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET           0x3FFFC684
100 #define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET            0x3FFFC688
101 
102 #define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET                   0x3FFFC68C
103 #define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET                   0x3FFFC68E
104 
105 #define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET            0x3FFFC690
106 #define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET             0x3FFFC694
107 #define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET            0x3FFFC698
108 
109 #define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET         0x3FFFC69C
110 #define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET       0x3FFFC6A0
111 #define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET              0x3FFFC6A4
112 #define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET             0x3FFFC6A8
113 
114 /* Debug-purpose DVB-S DMD 0 */
115 #define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET     0x3FFFC6C8  /* corrected RS Errors: 1st iteration */
116 #define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET   0x3FFFC6CC  /* uncorrected RS Errors: 1st iteration */
117 #define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET          0x3FFFC6D0
118 #define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET         0x3FFFC6D4
119 
120 #define HYDRA_DMD_TUNER_ID_ADDR_OFFSET                    0x3FFFC6AC
121 #define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET          0x3FFFC6B0
122 #define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET       0x3FFFC6B4
123 #define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET                 0x3FFFC6B8
124 #define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR          0x3FFFC704
125 #define HYDRA_DMD_STATUS_INPUT_POWER_ADDR                 0x3FFFC708
126 
127 /* DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" */
128 #define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR        0x3FFFC710 /* DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */
129 #define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR            0x3FFFC714 /* DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */
130 
131 #define DMD0_SPECTRUM_MIN_GAIN_STATUS                     0x3FFFC73C
132 #define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE              0x3FFFC740
133 #define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE              0x3FFFC744
134 
135 #define HYDRA_DMD_STATUS_END_ADDR_OFFSET                  0x3FFFC748
136 
137 /* Tuner status address offset from respective tuners's base address */
138 #define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET                  0x3FFFCE4C
139 #define HYDRA_TUNER_AGC_LOCK_OFFSET                       0x3FFFCE50
140 #define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET                0x3FFFCE54
141 #define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET              0x3FFFCE58
142 #define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET               0x3FFFCE5C
143 #define HYDRA_TUNER_ENABLE_COMPLETE                       0x3FFFEB78
144 
145 #define HYDRA_DEMOD_STATUS_LOCK(devId, demodId)   write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES)
146 #define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO)
147 
148 #define HYDRA_VERSION                                     0x3FFFEDB8
149 #define HYDRA_DEMOD0_VERSION                              0x3FFFEDBC
150 #define HYDRA_DEMOD1_VERSION                              0x3FFFEDC0
151 #define HYDRA_DEMOD2_VERSION                              0x3FFFEDC4
152 #define HYDRA_DEMOD3_VERSION                              0x3FFFEDC8
153 #define HYDRA_DEMOD4_VERSION                              0x3FFFEDCC
154 #define HYDRA_DEMOD5_VERSION                              0x3FFFEDD0
155 #define HYDRA_DEMOD6_VERSION                              0x3FFFEDD4
156 #define HYDRA_DEMOD7_VERSION                              0x3FFFEDD8
157 #define HYDRA_HEAR_BEAT                                   0x3FFFEDDC
158 #define HYDRA_SKU_MGMT                                    0x3FFFEBC0
159 
160 #define MXL_HYDRA_FPGA_A_ADDRESS                          0x91C00000
161 #define MXL_HYDRA_FPGA_B_ADDRESS                          0x91D00000
162 
163 /* TS control base address */
164 #define HYDRA_TS_CTRL_BASE_ADDR                           0x90700000
165 
166 #define MPEG_MUX_MODE_SLICE0_REG            (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
167 
168 #define MPEG_MUX_MODE_SLICE1_REG            (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
169 
170 #define PID_BANK_SEL_SLICE0_REG             (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
171 #define PID_BANK_SEL_SLICE1_REG             (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
172 
173 #define MPEG_CLK_GATED_REG                  (HYDRA_TS_CTRL_BASE_ADDR + 0x20)
174 
175 #define MPEG_CLK_ALWAYS_ON_REG              (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4)
176 
177 #define HYDRA_REGULAR_PID_BANK_A_REG        (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
178 
179 #define HYDRA_FIXED_PID_BANK_A_REG          (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
180 
181 #define HYDRA_REGULAR_PID_BANK_B_REG        (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
182 
183 #define HYDRA_FIXED_PID_BANK_B_REG          (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
184 
185 #define FIXED_PID_TBL_REG_ADDRESS_0         (HYDRA_TS_CTRL_BASE_ADDR + 0x9000)
186 #define FIXED_PID_TBL_REG_ADDRESS_1         (HYDRA_TS_CTRL_BASE_ADDR + 0x9100)
187 #define FIXED_PID_TBL_REG_ADDRESS_2         (HYDRA_TS_CTRL_BASE_ADDR + 0x9200)
188 #define FIXED_PID_TBL_REG_ADDRESS_3         (HYDRA_TS_CTRL_BASE_ADDR + 0x9300)
189 
190 #define FIXED_PID_TBL_REG_ADDRESS_4         (HYDRA_TS_CTRL_BASE_ADDR + 0xB000)
191 #define FIXED_PID_TBL_REG_ADDRESS_5         (HYDRA_TS_CTRL_BASE_ADDR + 0xB100)
192 #define FIXED_PID_TBL_REG_ADDRESS_6         (HYDRA_TS_CTRL_BASE_ADDR + 0xB200)
193 #define FIXED_PID_TBL_REG_ADDRESS_7         (HYDRA_TS_CTRL_BASE_ADDR + 0xB300)
194 
195 #define REGULAR_PID_TBL_REG_ADDRESS_0       (HYDRA_TS_CTRL_BASE_ADDR + 0x8000)
196 #define REGULAR_PID_TBL_REG_ADDRESS_1       (HYDRA_TS_CTRL_BASE_ADDR + 0x8200)
197 #define REGULAR_PID_TBL_REG_ADDRESS_2       (HYDRA_TS_CTRL_BASE_ADDR + 0x8400)
198 #define REGULAR_PID_TBL_REG_ADDRESS_3       (HYDRA_TS_CTRL_BASE_ADDR + 0x8600)
199 
200 #define REGULAR_PID_TBL_REG_ADDRESS_4       (HYDRA_TS_CTRL_BASE_ADDR + 0xA000)
201 #define REGULAR_PID_TBL_REG_ADDRESS_5       (HYDRA_TS_CTRL_BASE_ADDR + 0xA200)
202 #define REGULAR_PID_TBL_REG_ADDRESS_6       (HYDRA_TS_CTRL_BASE_ADDR + 0xA400)
203 #define REGULAR_PID_TBL_REG_ADDRESS_7       (HYDRA_TS_CTRL_BASE_ADDR + 0xA600)
204 
205 /***************************************************************************/
206 
207 #define PAD_MUX_GPIO_00_SYNC_BASEADDR                          0x90000188
208 
209 
210 #define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C
211 
212 #define   XPT_PACKET_GAP_MIN_BASEADDR                            0x90700044
213 #define   XPT_NCO_COUNT_BASEADDR                                 0x90700238
214 
215 #define   XPT_NCO_COUNT_BASEADDR1                                0x9070023C
216 
217 /* V2 DigRF status register */
218 
219 #define   XPT_PID_BASEADDR                                       0x90708000
220 
221 #define   XPT_PID_REMAP_BASEADDR                                 0x90708004
222 
223 #define   XPT_KNOWN_PID_BASEADDR                                 0x90709000
224 
225 #define   XPT_PID_BASEADDR1                                      0x9070A000
226 
227 #define   XPT_PID_REMAP_BASEADDR1                                0x9070A004
228 
229 #define   XPT_KNOWN_PID_BASEADDR1                                0x9070B000
230 
231 #define   XPT_BERT_LOCK_BASEADDR                                 0x907000B8
232 
233 #define   XPT_BERT_BASEADDR                                      0x907000BC
234 
235 #define   XPT_BERT_INVERT_BASEADDR                               0x907000C0
236 
237 #define   XPT_BERT_HEADER_BASEADDR                               0x907000C4
238 
239 #define   XPT_BERT_BASEADDR1                                     0x907000C8
240 
241 #define   XPT_BERT_BIT_COUNT0_BASEADDR                           0x907000CC
242 
243 #define   XPT_BERT_BIT_COUNT0_BASEADDR1                          0x907000D0
244 
245 #define   XPT_BERT_BIT_COUNT1_BASEADDR                           0x907000D4
246 
247 #define   XPT_BERT_BIT_COUNT1_BASEADDR1                          0x907000D8
248 
249 #define   XPT_BERT_BIT_COUNT2_BASEADDR                           0x907000DC
250 
251 #define   XPT_BERT_BIT_COUNT2_BASEADDR1                          0x907000E0
252 
253 #define   XPT_BERT_BIT_COUNT3_BASEADDR                           0x907000E4
254 
255 #define   XPT_BERT_BIT_COUNT3_BASEADDR1                          0x907000E8
256 
257 #define   XPT_BERT_BIT_COUNT4_BASEADDR                           0x907000EC
258 
259 #define   XPT_BERT_BIT_COUNT4_BASEADDR1                          0x907000F0
260 
261 #define   XPT_BERT_BIT_COUNT5_BASEADDR                           0x907000F4
262 
263 #define   XPT_BERT_BIT_COUNT5_BASEADDR1                          0x907000F8
264 
265 #define   XPT_BERT_BIT_COUNT6_BASEADDR                           0x907000FC
266 
267 #define   XPT_BERT_BIT_COUNT6_BASEADDR1                          0x90700100
268 
269 #define   XPT_BERT_BIT_COUNT7_BASEADDR                           0x90700104
270 
271 #define   XPT_BERT_BIT_COUNT7_BASEADDR1                          0x90700108
272 
273 #define   XPT_BERT_ERR_COUNT0_BASEADDR                           0x9070010C
274 
275 #define   XPT_BERT_ERR_COUNT0_BASEADDR1                          0x90700110
276 
277 #define   XPT_BERT_ERR_COUNT1_BASEADDR                           0x90700114
278 
279 #define   XPT_BERT_ERR_COUNT1_BASEADDR1                          0x90700118
280 
281 #define   XPT_BERT_ERR_COUNT2_BASEADDR                           0x9070011C
282 
283 #define   XPT_BERT_ERR_COUNT2_BASEADDR1                          0x90700120
284 
285 #define   XPT_BERT_ERR_COUNT3_BASEADDR                           0x90700124
286 
287 #define   XPT_BERT_ERR_COUNT3_BASEADDR1                          0x90700128
288 
289 #define   XPT_BERT_ERR_COUNT4_BASEADDR                           0x9070012C
290 
291 #define   XPT_BERT_ERR_COUNT4_BASEADDR1                          0x90700130
292 
293 #define   XPT_BERT_ERR_COUNT5_BASEADDR                           0x90700134
294 
295 #define   XPT_BERT_ERR_COUNT5_BASEADDR1                          0x90700138
296 
297 #define   XPT_BERT_ERR_COUNT6_BASEADDR                           0x9070013C
298 
299 #define   XPT_BERT_ERR_COUNT6_BASEADDR1                          0x90700140
300 
301 #define   XPT_BERT_ERR_COUNT7_BASEADDR                           0x90700144
302 
303 #define   XPT_BERT_ERR_COUNT7_BASEADDR1                          0x90700148
304 
305 #define   XPT_BERT_ERROR_BASEADDR                                0x9070014C
306 
307 #define   XPT_BERT_ANALYZER_BASEADDR                             0x90700150
308 
309 #define   XPT_BERT_ANALYZER_BASEADDR1                            0x90700154
310 
311 #define   XPT_BERT_ANALYZER_BASEADDR2                            0x90700158
312 
313 #define   XPT_BERT_ANALYZER_BASEADDR3                            0x9070015C
314 
315 #define   XPT_BERT_ANALYZER_BASEADDR4                            0x90700160
316 
317 #define   XPT_BERT_ANALYZER_BASEADDR5                            0x90700164
318 
319 #define   XPT_BERT_ANALYZER_BASEADDR6                            0x90700168
320 
321 #define   XPT_BERT_ANALYZER_BASEADDR7                            0x9070016C
322 
323 #define   XPT_BERT_ANALYZER_BASEADDR8                            0x90700170
324 
325 #define   XPT_BERT_ANALYZER_BASEADDR9                            0x90700174
326 
327 #define   XPT_DMD0_BASEADDR                                      0x9070024C
328 
329 /* V2 AGC Gain Freeze & step */
330 #define   DBG_ENABLE_DISABLE_AGC                                 (0x3FFFCF60) /* 1: DISABLE, 0:ENABLE */
331 #define   WB_DFE0_DFE_FB_RF1_BASEADDR                            0x903004A4
332 
333 #define   WB_DFE1_DFE_FB_RF1_BASEADDR                            0x904004A4
334 
335 #define   WB_DFE2_DFE_FB_RF1_BASEADDR                            0x905004A4
336 
337 #define   WB_DFE3_DFE_FB_RF1_BASEADDR                            0x906004A4
338 
339 #define   AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR                0x90200104
340 
341 #define   AFE_REG_AFE_REG_SPARE_BASEADDR                         0x902000A0
342 
343 #define   AFE_REG_AFE_REG_SPARE_BASEADDR1                        0x902000B4
344 
345 #define   AFE_REG_AFE_REG_SPARE_BASEADDR2                        0x902000C4
346 
347 #define   AFE_REG_AFE_REG_SPARE_BASEADDR3                        0x902000D4
348 
349 #define   WB_DFE0_DFE_FB_AGC_BASEADDR                            0x90300498
350 
351 #define   WB_DFE1_DFE_FB_AGC_BASEADDR                            0x90400498
352 
353 #define   WB_DFE2_DFE_FB_AGC_BASEADDR                            0x90500498
354 
355 #define   WB_DFE3_DFE_FB_AGC_BASEADDR                            0x90600498
356 
357 #define   WDT_WD_INT_BASEADDR                                    0x8002000C
358 
359 #define   FSK_TX_FTM_BASEADDR                                    0x80090000
360 
361 #define   FSK_TX_FTM_TX_CNT_BASEADDR                             0x80090018
362 
363 #define   AFE_REG_D2A_FSK_BIAS_BASEADDR                          0x90200040
364 
365 #define   DMD_TEI_BASEADDR                                       0x3FFFEBE0
366 
367 #endif /* __MXL58X_REGISTERS_H__ */
368