1 /* 2 * Defines for the Maxlinear MX58x family of tuners/demods 3 * 4 * Copyright (C) 2014 Digital Devices GmbH 5 * 6 * based on code: 7 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved 8 * which was released under GPL V2 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * version 2, as published by the Free Software Foundation. 13 */ 14 15 enum MXL_BOOL_E { 16 MXL_DISABLE = 0, 17 MXL_ENABLE = 1, 18 19 MXL_FALSE = 0, 20 MXL_TRUE = 1, 21 22 MXL_INVALID = 0, 23 MXL_VALID = 1, 24 25 MXL_NO = 0, 26 MXL_YES = 1, 27 28 MXL_OFF = 0, 29 MXL_ON = 1 30 }; 31 32 /* Firmware-Host Command IDs */ 33 enum MXL_HYDRA_HOST_CMD_ID_E { 34 /* --Device command IDs-- */ 35 MXL_HYDRA_DEV_NO_OP_CMD = 0, /* No OP */ 36 37 MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1, 38 MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2, 39 40 /* Host-used CMD, not used by firmware */ 41 MXL_HYDRA_DEV_FIRMWARE_DOWNLOAD_CMD = 3, 42 43 /* Additional CONTROL types from DTV */ 44 MXL_HYDRA_DEV_SET_BROADCAST_PID_STB_ID_CMD = 4, 45 MXL_HYDRA_DEV_GET_PMM_SLEEP_CMD = 5, 46 47 /* --Tuner command IDs-- */ 48 MXL_HYDRA_TUNER_TUNE_CMD = 6, 49 MXL_HYDRA_TUNER_GET_STATUS_CMD = 7, 50 51 /* --Demod command IDs-- */ 52 MXL_HYDRA_DEMOD_SET_PARAM_CMD = 8, 53 MXL_HYDRA_DEMOD_GET_STATUS_CMD = 9, 54 55 MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD = 10, 56 57 MXL_HYDRA_DEMOD_SET_PKT_NUM_CMD = 11, 58 59 MXL_HYDRA_DEMOD_SET_IQ_SOURCE_CMD = 12, 60 MXL_HYDRA_DEMOD_GET_IQ_DATA_CMD = 13, 61 62 MXL_HYDRA_DEMOD_GET_M68HC05_VER_CMD = 14, 63 64 MXL_HYDRA_DEMOD_SET_ERROR_COUNTER_MODE_CMD = 15, 65 66 /* --- ABORT channel tune */ 67 MXL_HYDRA_ABORT_TUNE_CMD = 16, /* Abort current tune command. */ 68 69 /* --SWM/FSK command IDs-- */ 70 MXL_HYDRA_FSK_RESET_CMD = 17, 71 MXL_HYDRA_FSK_MSG_CMD = 18, 72 MXL_HYDRA_FSK_SET_OP_MODE_CMD = 19, 73 74 /* --DiSeqC command IDs-- */ 75 MXL_HYDRA_DISEQC_MSG_CMD = 20, 76 MXL_HYDRA_DISEQC_COPY_MSG_TO_MAILBOX = 21, 77 MXL_HYDRA_DISEQC_CFG_MSG_CMD = 22, 78 79 /* --- FFT Debug Command IDs-- */ 80 MXL_HYDRA_REQ_FFT_SPECTRUM_CMD = 23, 81 82 /* -- Demod scramblle code */ 83 MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD = 24, 84 85 /* ---For host to know how many commands in total */ 86 MXL_HYDRA_LAST_HOST_CMD = 25, 87 88 MXL_HYDRA_DEMOD_INTR_TYPE_CMD = 47, 89 MXL_HYDRA_DEV_INTR_CLEAR_CMD = 48, 90 MXL_HYDRA_TUNER_SPECTRUM_REQ_CMD = 53, 91 MXL_HYDRA_TUNER_ACTIVATE_CMD = 55, 92 MXL_HYDRA_DEV_CFG_POWER_MODE_CMD = 56, 93 MXL_HYDRA_DEV_XTAL_CAP_CMD = 57, 94 MXL_HYDRA_DEV_CFG_SKU_CMD = 58, 95 MXL_HYDRA_TUNER_SPECTRUM_MIN_GAIN_CMD = 59, 96 MXL_HYDRA_DISEQC_CONT_TONE_CFG = 60, 97 MXL_HYDRA_DEV_RF_WAKE_UP_CMD = 61, 98 MXL_HYDRA_DEMOD_CFG_EQ_CTRL_PARAM_CMD = 62, 99 MXL_HYDRA_DEMOD_FREQ_OFFSET_SEARCH_RANGE_CMD = 63, 100 MXL_HYDRA_DEV_REQ_PWR_FROM_ADCRSSI_CMD = 64, 101 102 MXL_XCPU_PID_FLT_CFG_CMD = 65, 103 MXL_XCPU_SHMEM_TEST_CMD = 66, 104 MXL_XCPU_ABORT_TUNE_CMD = 67, 105 MXL_XCPU_CHAN_TUNE_CMD = 68, 106 MXL_XCPU_FLT_BOND_HDRS_CMD = 69, 107 108 MXL_HYDRA_DEV_BROADCAST_WAKE_UP_CMD = 70, 109 MXL_HYDRA_FSK_CFG_FSK_FREQ_CMD = 71, 110 MXL_HYDRA_FSK_POWER_DOWN_CMD = 72, 111 MXL_XCPU_CLEAR_CB_STATS_CMD = 73, 112 MXL_XCPU_CHAN_BOND_RESTART_CMD = 74 113 }; 114 115 #define MXL_ENABLE_BIG_ENDIAN (0) 116 117 #define MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH 248 118 119 #define MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN (248) 120 121 #define MXL_HYDRA_CAP_MIN 10 122 #define MXL_HYDRA_CAP_MAX 33 123 124 #define MXL_HYDRA_PLID_REG_READ 0xFB /* Read register PLID */ 125 #define MXL_HYDRA_PLID_REG_WRITE 0xFC /* Write register PLID */ 126 127 #define MXL_HYDRA_PLID_CMD_READ 0xFD /* Command Read PLID */ 128 #define MXL_HYDRA_PLID_CMD_WRITE 0xFE /* Command Write PLID */ 129 130 #define MXL_HYDRA_REG_SIZE_IN_BYTES 4 /* Hydra register size in bytes */ 131 #define MXL_HYDRA_I2C_HDR_SIZE (2 * sizeof(u8)) /* PLID + LEN(0xFF) */ 132 #define MXL_HYDRA_CMD_HEADER_SIZE (MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE) 133 134 #define MXL_HYDRA_SKU_ID_581 0 135 #define MXL_HYDRA_SKU_ID_584 1 136 #define MXL_HYDRA_SKU_ID_585 2 137 #define MXL_HYDRA_SKU_ID_544 3 138 #define MXL_HYDRA_SKU_ID_561 4 139 #define MXL_HYDRA_SKU_ID_582 5 140 #define MXL_HYDRA_SKU_ID_568 6 141 142 /* macro for register write data buffer size 143 * (PLID + LEN (0xFF) + RegAddr + RegData) 144 */ 145 #define MXL_HYDRA_REG_WRITE_LEN (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES)) 146 147 /* macro to extract a single byte from 4-byte(32-bit) data */ 148 #define GET_BYTE(x, n) (((x) >> (8*(n))) & 0xFF) 149 150 #define MAX_CMD_DATA 512 151 152 #define MXL_GET_REG_MASK_32(lsb_loc, num_of_bits) ((0xFFFFFFFF >> (32 - (num_of_bits))) << (lsb_loc)) 153 154 #define FW_DL_SIGN (0xDEADBEEF) 155 156 #define MBIN_FORMAT_VERSION '1' 157 #define MBIN_FILE_HEADER_ID 'M' 158 #define MBIN_SEGMENT_HEADER_ID 'S' 159 #define MBIN_MAX_FILE_LENGTH (1<<23) 160 161 struct MBIN_FILE_HEADER_T { 162 u8 id; 163 u8 fmt_version; 164 u8 header_len; 165 u8 num_segments; 166 u8 entry_address[4]; 167 u8 image_size24[3]; 168 u8 image_checksum; 169 u8 reserved[4]; 170 }; 171 172 struct MBIN_FILE_T { 173 struct MBIN_FILE_HEADER_T header; 174 u8 data[1]; 175 }; 176 177 struct MBIN_SEGMENT_HEADER_T { 178 u8 id; 179 u8 len24[3]; 180 u8 address[4]; 181 }; 182 183 struct MBIN_SEGMENT_T { 184 struct MBIN_SEGMENT_HEADER_T header; 185 u8 data[1]; 186 }; 187 188 enum MXL_CMD_TYPE_E { MXL_CMD_WRITE = 0, MXL_CMD_READ }; 189 190 #define BUILD_HYDRA_CMD(cmd_id, req_type, size, data_ptr, cmd_buff) \ 191 do { \ 192 cmd_buff[0] = ((req_type == MXL_CMD_WRITE) ? MXL_HYDRA_PLID_CMD_WRITE : MXL_HYDRA_PLID_CMD_READ); \ 193 cmd_buff[1] = (size > 251) ? 0xff : (u8) (size + 4); \ 194 cmd_buff[2] = size; \ 195 cmd_buff[3] = cmd_id; \ 196 cmd_buff[4] = 0x00; \ 197 cmd_buff[5] = 0x00; \ 198 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, (u8 *)data_ptr); \ 199 memcpy((void *)&cmd_buff[6], data_ptr, size); \ 200 } while (0) 201 202 struct MXL_REG_FIELD_T { 203 u32 reg_addr; 204 u8 lsb_pos; 205 u8 num_of_bits; 206 }; 207 208 struct MXL_DEV_CMD_DATA_T { 209 u32 data_size; 210 u8 data[MAX_CMD_DATA]; 211 }; 212 213 enum MXL_HYDRA_SKU_TYPE_E { 214 MXL_HYDRA_SKU_TYPE_MIN = 0x00, 215 MXL_HYDRA_SKU_TYPE_581 = 0x00, 216 MXL_HYDRA_SKU_TYPE_584 = 0x01, 217 MXL_HYDRA_SKU_TYPE_585 = 0x02, 218 MXL_HYDRA_SKU_TYPE_544 = 0x03, 219 MXL_HYDRA_SKU_TYPE_561 = 0x04, 220 MXL_HYDRA_SKU_TYPE_5XX = 0x05, 221 MXL_HYDRA_SKU_TYPE_5YY = 0x06, 222 MXL_HYDRA_SKU_TYPE_511 = 0x07, 223 MXL_HYDRA_SKU_TYPE_561_DE = 0x08, 224 MXL_HYDRA_SKU_TYPE_582 = 0x09, 225 MXL_HYDRA_SKU_TYPE_541 = 0x0A, 226 MXL_HYDRA_SKU_TYPE_568 = 0x0B, 227 MXL_HYDRA_SKU_TYPE_542 = 0x0C, 228 MXL_HYDRA_SKU_TYPE_MAX = 0x0D, 229 }; 230 231 struct MXL_HYDRA_SKU_COMMAND_T { 232 enum MXL_HYDRA_SKU_TYPE_E sku_type; 233 }; 234 235 enum MXL_HYDRA_DEMOD_ID_E { 236 MXL_HYDRA_DEMOD_ID_0 = 0, 237 MXL_HYDRA_DEMOD_ID_1, 238 MXL_HYDRA_DEMOD_ID_2, 239 MXL_HYDRA_DEMOD_ID_3, 240 MXL_HYDRA_DEMOD_ID_4, 241 MXL_HYDRA_DEMOD_ID_5, 242 MXL_HYDRA_DEMOD_ID_6, 243 MXL_HYDRA_DEMOD_ID_7, 244 MXL_HYDRA_DEMOD_MAX 245 }; 246 247 #define MXL_DEMOD_SCRAMBLE_SEQ_LEN 12 248 249 #define MAX_STEP_SIZE_24_XTAL_102_05_KHZ 195 250 #define MAX_STEP_SIZE_24_XTAL_204_10_KHZ 215 251 #define MAX_STEP_SIZE_24_XTAL_306_15_KHZ 203 252 #define MAX_STEP_SIZE_24_XTAL_408_20_KHZ 177 253 254 #define MAX_STEP_SIZE_27_XTAL_102_05_KHZ 195 255 #define MAX_STEP_SIZE_27_XTAL_204_10_KHZ 215 256 #define MAX_STEP_SIZE_27_XTAL_306_15_KHZ 203 257 #define MAX_STEP_SIZE_27_XTAL_408_20_KHZ 177 258 259 #define MXL_HYDRA_SPECTRUM_MIN_FREQ_KHZ 300000 260 #define MXL_HYDRA_SPECTRUM_MAX_FREQ_KHZ 2350000 261 262 enum MXL_DEMOD_CHAN_PARAMS_OFFSET_E { 263 DMD_STANDARD_ADDR = 0, 264 DMD_SPECTRUM_INVERSION_ADDR, 265 DMD_SPECTRUM_ROLL_OFF_ADDR, 266 DMD_SYMBOL_RATE_ADDR, 267 DMD_MODULATION_SCHEME_ADDR, 268 DMD_FEC_CODE_RATE_ADDR, 269 DMD_SNR_ADDR, 270 DMD_FREQ_OFFSET_ADDR, 271 DMD_CTL_FREQ_OFFSET_ADDR, 272 DMD_STR_FREQ_OFFSET_ADDR, 273 DMD_FTL_FREQ_OFFSET_ADDR, 274 DMD_STR_NBC_SYNC_LOCK_ADDR, 275 DMD_CYCLE_SLIP_COUNT_ADDR, 276 DMD_DISPLAY_IQ_ADDR, 277 DMD_DVBS2_CRC_ERRORS_ADDR, 278 DMD_DVBS2_PER_COUNT_ADDR, 279 DMD_DVBS2_PER_WINDOW_ADDR, 280 DMD_DVBS_CORR_RS_ERRORS_ADDR, 281 DMD_DVBS_UNCORR_RS_ERRORS_ADDR, 282 DMD_DVBS_BER_COUNT_ADDR, 283 DMD_DVBS_BER_WINDOW_ADDR, 284 DMD_TUNER_ID_ADDR, 285 DMD_DVBS2_PILOT_ON_OFF_ADDR, 286 DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR, 287 288 MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE, 289 }; 290 291 enum MXL_HYDRA_TUNER_ID_E { 292 MXL_HYDRA_TUNER_ID_0 = 0, 293 MXL_HYDRA_TUNER_ID_1, 294 MXL_HYDRA_TUNER_ID_2, 295 MXL_HYDRA_TUNER_ID_3, 296 MXL_HYDRA_TUNER_MAX 297 }; 298 299 enum MXL_HYDRA_BCAST_STD_E { 300 MXL_HYDRA_DSS = 0, 301 MXL_HYDRA_DVBS, 302 MXL_HYDRA_DVBS2, 303 }; 304 305 enum MXL_HYDRA_FEC_E { 306 MXL_HYDRA_FEC_AUTO = 0, 307 MXL_HYDRA_FEC_1_2, 308 MXL_HYDRA_FEC_3_5, 309 MXL_HYDRA_FEC_2_3, 310 MXL_HYDRA_FEC_3_4, 311 MXL_HYDRA_FEC_4_5, 312 MXL_HYDRA_FEC_5_6, 313 MXL_HYDRA_FEC_6_7, 314 MXL_HYDRA_FEC_7_8, 315 MXL_HYDRA_FEC_8_9, 316 MXL_HYDRA_FEC_9_10, 317 }; 318 319 enum MXL_HYDRA_MODULATION_E { 320 MXL_HYDRA_MOD_AUTO = 0, 321 MXL_HYDRA_MOD_QPSK, 322 MXL_HYDRA_MOD_8PSK 323 }; 324 325 enum MXL_HYDRA_SPECTRUM_E { 326 MXL_HYDRA_SPECTRUM_AUTO = 0, 327 MXL_HYDRA_SPECTRUM_INVERTED, 328 MXL_HYDRA_SPECTRUM_NON_INVERTED, 329 }; 330 331 enum MXL_HYDRA_ROLLOFF_E { 332 MXL_HYDRA_ROLLOFF_AUTO = 0, 333 MXL_HYDRA_ROLLOFF_0_20, 334 MXL_HYDRA_ROLLOFF_0_25, 335 MXL_HYDRA_ROLLOFF_0_35 336 }; 337 338 enum MXL_HYDRA_PILOTS_E { 339 MXL_HYDRA_PILOTS_OFF = 0, 340 MXL_HYDRA_PILOTS_ON, 341 MXL_HYDRA_PILOTS_AUTO 342 }; 343 344 enum MXL_HYDRA_CONSTELLATION_SRC_E { 345 MXL_HYDRA_FORMATTER = 0, 346 MXL_HYDRA_LEGACY_FEC, 347 MXL_HYDRA_FREQ_RECOVERY, 348 MXL_HYDRA_NBC, 349 MXL_HYDRA_CTL, 350 MXL_HYDRA_EQ, 351 }; 352 353 struct MXL_HYDRA_DEMOD_LOCK_T { 354 int agc_lock; /* AGC lock info */ 355 int fec_lock; /* Demod FEC block lock info */ 356 }; 357 358 struct MXL_HYDRA_DEMOD_STATUS_DVBS_T { 359 u32 rs_errors; /* RS decoder err counter */ 360 u32 ber_window; /* Ber Windows */ 361 u32 ber_count; /* BER count */ 362 u32 ber_window_iter1; /* Ber Windows - post viterbi */ 363 u32 ber_count_iter1; /* BER count - post viterbi */ 364 }; 365 366 struct MXL_HYDRA_DEMOD_STATUS_DSS_T { 367 u32 rs_errors; /* RS decoder err counter */ 368 u32 ber_window; /* Ber Windows */ 369 u32 ber_count; /* BER count */ 370 }; 371 372 struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T { 373 u32 crc_errors; /* CRC error counter */ 374 u32 packet_error_count; /* Number of packet errors */ 375 u32 total_packets; /* Total packets */ 376 }; 377 378 struct MXL_HYDRA_DEMOD_STATUS_T { 379 enum MXL_HYDRA_BCAST_STD_E standard_mask; /* Standard DVB-S, DVB-S2 or DSS */ 380 381 union { 382 struct MXL_HYDRA_DEMOD_STATUS_DVBS_T demod_status_dvbs; /* DVB-S demod status */ 383 struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T demod_status_dvbs2; /* DVB-S2 demod status */ 384 struct MXL_HYDRA_DEMOD_STATUS_DSS_T demod_status_dss; /* DSS demod status */ 385 } u; 386 }; 387 388 struct MXL_HYDRA_DEMOD_SIG_OFFSET_INFO_T { 389 s32 carrier_offset_in_hz; /* CRL offset info */ 390 s32 symbol_offset_in_symbol; /* SRL offset info */ 391 }; 392 393 struct MXL_HYDRA_DEMOD_SCRAMBLE_INFO_T { 394 u8 scramble_sequence[MXL_DEMOD_SCRAMBLE_SEQ_LEN]; /* scramble sequence */ 395 u32 scramble_code; /* scramble gold code */ 396 }; 397 398 enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E { 399 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */ 400 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */ 401 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */ 402 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */ 403 404 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */ 405 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */ 406 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */ 407 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */ 408 }; 409 410 enum MXL_HYDRA_SPECTRUM_RESOLUTION_E { 411 MXL_HYDRA_SPECTRUM_RESOLUTION_00_1_DB, /* 0.1 dB */ 412 MXL_HYDRA_SPECTRUM_RESOLUTION_01_0_DB, /* 1.0 dB */ 413 MXL_HYDRA_SPECTRUM_RESOLUTION_05_0_DB, /* 5.0 dB */ 414 MXL_HYDRA_SPECTRUM_RESOLUTION_10_0_DB, /* 10 dB */ 415 }; 416 417 enum MXL_HYDRA_SPECTRUM_ERROR_CODE_E { 418 MXL_SPECTRUM_NO_ERROR, 419 MXL_SPECTRUM_INVALID_PARAMETER, 420 MXL_SPECTRUM_INVALID_STEP_SIZE, 421 MXL_SPECTRUM_BW_CANNOT_BE_COVERED, 422 MXL_SPECTRUM_DEMOD_BUSY, 423 MXL_SPECTRUM_TUNER_NOT_ENABLED, 424 }; 425 426 struct MXL_HYDRA_SPECTRUM_REQ_T { 427 u32 tuner_index; /* TUNER Ctrl: one of MXL58x_TUNER_ID_E */ 428 u32 demod_index; /* DEMOD Ctrl: one of MXL58x_DEMOD_ID_E */ 429 enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E step_size_in_khz; 430 u32 starting_freq_ink_hz; 431 u32 total_steps; 432 enum MXL_HYDRA_SPECTRUM_RESOLUTION_E spectrum_division; 433 }; 434 435 enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E { 436 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */ 437 MXL_HYDRA_SEARCH_BW_PLUS_ROLLOFF, /* DMD searches for BW + ROLLOFF/2 */ 438 }; 439 440 struct MXL58X_CFG_FREQ_OFF_SEARCH_RANGE_T { 441 u32 demod_index; 442 enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E search_type; 443 }; 444 445 /* there are two slices 446 * slice0 - TS0, TS1, TS2 & TS3 447 * slice1 - TS4, TS5, TS6 & TS7 448 */ 449 #define MXL_HYDRA_TS_SLICE_MAX 2 450 451 #define MAX_FIXED_PID_NUM 32 452 453 #define MXL_HYDRA_NCO_CLK 418 /* 418 MHz */ 454 455 #define MXL_HYDRA_MAX_TS_CLOCK 139 /* 139 MHz */ 456 457 #define MXL_HYDRA_TS_FIXED_PID_FILT_SIZE 32 458 459 #define MXL_HYDRA_SHARED_PID_FILT_SIZE_DEFAULT 33 /* Shared PID filter size in 1-1 mux mode */ 460 #define MXL_HYDRA_SHARED_PID_FILT_SIZE_2_TO_1 66 /* Shared PID filter size in 2-1 mux mode */ 461 #define MXL_HYDRA_SHARED_PID_FILT_SIZE_4_TO_1 132 /* Shared PID filter size in 4-1 mux mode */ 462 463 enum MXL_HYDRA_PID_BANK_TYPE_E { 464 MXL_HYDRA_SOFTWARE_PID_BANK = 0, 465 MXL_HYDRA_HARDWARE_PID_BANK, 466 }; 467 468 enum MXL_HYDRA_TS_MUX_MODE_E { 469 MXL_HYDRA_TS_MUX_PID_REMAP = 0, 470 MXL_HYDRA_TS_MUX_PREFIX_EXTRA_HEADER = 1, 471 }; 472 473 enum MXL_HYDRA_TS_MUX_TYPE_E { 474 MXL_HYDRA_TS_MUX_DISABLE = 0, /* No Mux ( 1 TSIF to 1 TSIF) */ 475 MXL_HYDRA_TS_MUX_2_TO_1, /* Mux 2 TSIF to 1 TSIF */ 476 MXL_HYDRA_TS_MUX_4_TO_1, /* Mux 4 TSIF to 1 TSIF */ 477 }; 478 479 enum MXL_HYDRA_TS_GROUP_E { 480 MXL_HYDRA_TS_GROUP_0_3 = 0, /* TS group 0 to 3 (TS0, TS1, TS2 & TS3) */ 481 MXL_HYDRA_TS_GROUP_4_7, /* TS group 0 to 3 (TS4, TS5, TS6 & TS7) */ 482 }; 483 484 enum MXL_HYDRA_TS_PID_FLT_CTRL_E { 485 MXL_HYDRA_TS_PIDS_ALLOW_ALL = 0, /* Allow all pids */ 486 MXL_HYDRA_TS_PIDS_DROP_ALL, /* Drop all pids */ 487 MXL_HYDRA_TS_INVALIDATE_PID_FILTER, /* Delete current PD filter in the device */ 488 }; 489 490 enum MXL_HYDRA_TS_PID_TYPE_E { 491 MXL_HYDRA_TS_PID_FIXED = 0, 492 MXL_HYDRA_TS_PID_REGULAR, 493 }; 494 495 struct MXL_HYDRA_TS_PID_T { 496 u16 original_pid; /* pid from TS */ 497 u16 remapped_pid; /* remapped pid */ 498 enum MXL_BOOL_E enable; /* enable or disable pid */ 499 enum MXL_BOOL_E allow_or_drop; /* allow or drop pid */ 500 enum MXL_BOOL_E enable_pid_remap; /* enable or disable pid remap */ 501 u8 bond_id; /* Bond ID in A0 always 0 - Only for 568 Sku */ 502 u8 dest_id; /* Output port ID for the PID - Only for 568 Sku */ 503 }; 504 505 struct MXL_HYDRA_TS_MUX_PREFIX_HEADER_T { 506 enum MXL_BOOL_E enable; 507 u8 num_byte; 508 u8 header[12]; 509 }; 510 511 enum MXL_HYDRA_PID_FILTER_BANK_E { 512 MXL_HYDRA_PID_BANK_A = 0, 513 MXL_HYDRA_PID_BANK_B, 514 }; 515 516 enum MXL_HYDRA_MPEG_DATA_FMT_E { 517 MXL_HYDRA_MPEG_SERIAL_MSB_1ST = 0, 518 MXL_HYDRA_MPEG_SERIAL_LSB_1ST, 519 520 MXL_HYDRA_MPEG_SYNC_WIDTH_BIT = 0, 521 MXL_HYDRA_MPEG_SYNC_WIDTH_BYTE 522 }; 523 524 enum MXL_HYDRA_MPEG_MODE_E { 525 MXL_HYDRA_MPEG_MODE_SERIAL_4_WIRE = 0, /* MPEG 4 Wire serial mode */ 526 MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE, /* MPEG 3 Wire serial mode */ 527 MXL_HYDRA_MPEG_MODE_SERIAL_2_WIRE, /* MPEG 2 Wire serial mode */ 528 MXL_HYDRA_MPEG_MODE_PARALLEL /* MPEG parallel mode - valid only for MxL581 */ 529 }; 530 531 enum MXL_HYDRA_MPEG_CLK_TYPE_E { 532 MXL_HYDRA_MPEG_CLK_CONTINUOUS = 0, /* Continuous MPEG clock */ 533 MXL_HYDRA_MPEG_CLK_GAPPED, /* Gapped (gated) MPEG clock */ 534 }; 535 536 enum MXL_HYDRA_MPEG_CLK_FMT_E { 537 MXL_HYDRA_MPEG_ACTIVE_LOW = 0, 538 MXL_HYDRA_MPEG_ACTIVE_HIGH, 539 540 MXL_HYDRA_MPEG_CLK_NEGATIVE = 0, 541 MXL_HYDRA_MPEG_CLK_POSITIVE, 542 543 MXL_HYDRA_MPEG_CLK_IN_PHASE = 0, 544 MXL_HYDRA_MPEG_CLK_INVERTED, 545 }; 546 547 enum MXL_HYDRA_MPEG_CLK_PHASE_E { 548 MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG = 0, 549 MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_90_DEG, 550 MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_180_DEG, 551 MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_270_DEG 552 }; 553 554 enum MXL_HYDRA_MPEG_ERR_INDICATION_E { 555 MXL_HYDRA_MPEG_ERR_REPLACE_SYNC = 0, 556 MXL_HYDRA_MPEG_ERR_REPLACE_VALID, 557 MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED 558 }; 559 560 struct MXL_HYDRA_MPEGOUT_PARAM_T { 561 int enable; /* Enable or Disable MPEG OUT */ 562 enum MXL_HYDRA_MPEG_CLK_TYPE_E mpeg_clk_type; /* Continuous or gapped */ 563 enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_clk_pol; /* MPEG Clk polarity */ 564 u8 max_mpeg_clk_rate; /* Max MPEG Clk rate (0 - 104 MHz, 139 MHz) */ 565 enum MXL_HYDRA_MPEG_CLK_PHASE_E mpeg_clk_phase; /* MPEG Clk phase */ 566 enum MXL_HYDRA_MPEG_DATA_FMT_E lsb_or_msb_first; /* LSB first or MSB first in TS transmission */ 567 enum MXL_HYDRA_MPEG_DATA_FMT_E mpeg_sync_pulse_width; /* MPEG SYNC pulse width (1-bit or 1-byte) */ 568 enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_valid_pol; /* MPEG VALID polarity */ 569 enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_sync_pol; /* MPEG SYNC polarity */ 570 enum MXL_HYDRA_MPEG_MODE_E mpeg_mode; /* config 4/3/2-wire serial or parallel TS out */ 571 enum MXL_HYDRA_MPEG_ERR_INDICATION_E mpeg_error_indication; /* Enable or Disable MPEG error indication */ 572 }; 573 574 enum MXL_HYDRA_EXT_TS_IN_ID_E { 575 MXL_HYDRA_EXT_TS_IN_0 = 0, 576 MXL_HYDRA_EXT_TS_IN_1, 577 MXL_HYDRA_EXT_TS_IN_2, 578 MXL_HYDRA_EXT_TS_IN_3, 579 MXL_HYDRA_EXT_TS_IN_MAX 580 }; 581 582 enum MXL_HYDRA_TS_OUT_ID_E { 583 MXL_HYDRA_TS_OUT_0 = 0, 584 MXL_HYDRA_TS_OUT_1, 585 MXL_HYDRA_TS_OUT_2, 586 MXL_HYDRA_TS_OUT_3, 587 MXL_HYDRA_TS_OUT_4, 588 MXL_HYDRA_TS_OUT_5, 589 MXL_HYDRA_TS_OUT_6, 590 MXL_HYDRA_TS_OUT_7, 591 MXL_HYDRA_TS_OUT_MAX 592 }; 593 594 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E { 595 MXL_HYDRA_TS_DRIVE_STRENGTH_1X = 0, 596 MXL_HYDRA_TS_DRIVE_STRENGTH_2X, 597 MXL_HYDRA_TS_DRIVE_STRENGTH_3X, 598 MXL_HYDRA_TS_DRIVE_STRENGTH_4X, 599 MXL_HYDRA_TS_DRIVE_STRENGTH_5X, 600 MXL_HYDRA_TS_DRIVE_STRENGTH_6X, 601 MXL_HYDRA_TS_DRIVE_STRENGTH_7X, 602 MXL_HYDRA_TS_DRIVE_STRENGTH_8X 603 }; 604 605 enum MXL_HYDRA_DEVICE_E { 606 MXL_HYDRA_DEVICE_581 = 0, 607 MXL_HYDRA_DEVICE_584, 608 MXL_HYDRA_DEVICE_585, 609 MXL_HYDRA_DEVICE_544, 610 MXL_HYDRA_DEVICE_561, 611 MXL_HYDRA_DEVICE_TEST, 612 MXL_HYDRA_DEVICE_582, 613 MXL_HYDRA_DEVICE_541, 614 MXL_HYDRA_DEVICE_568, 615 MXL_HYDRA_DEVICE_542, 616 MXL_HYDRA_DEVICE_541S, 617 MXL_HYDRA_DEVICE_561S, 618 MXL_HYDRA_DEVICE_581S, 619 MXL_HYDRA_DEVICE_MAX 620 }; 621 622 /* Demod IQ data */ 623 struct MXL_HYDRA_DEMOD_IQ_SRC_T { 624 u32 demod_id; 625 u32 source_of_iq; /* == 0, it means I/Q comes from Formatter 626 * == 1, Legacy FEC 627 * == 2, Frequency Recovery 628 * == 3, NBC 629 * == 4, CTL 630 * == 5, EQ 631 * == 6, FPGA 632 */ 633 }; 634 635 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T { 636 u32 demod_id; 637 }; 638 639 struct MXL_HYDRA_TUNER_CMD { 640 u8 tuner_id; 641 u8 enable; 642 }; 643 644 /* Demod Para for Channel Tune */ 645 struct MXL_HYDRA_DEMOD_PARAM_T { 646 u32 tuner_index; 647 u32 demod_index; 648 u32 frequency_in_hz; /* Frequency */ 649 u32 standard; /* one of MXL_HYDRA_BCAST_STD_E */ 650 u32 spectrum_inversion; /* Input : Spectrum inversion. */ 651 u32 roll_off; /* rollOff (alpha) factor */ 652 u32 symbol_rate_in_hz; /* Symbol rate */ 653 u32 pilots; /* TRUE = pilots enabled */ 654 u32 modulation_scheme; /* Input : Modulation Scheme is one of MXL_HYDRA_MODULATION_E */ 655 u32 fec_code_rate; /* Input : Forward error correction rate. Is one of MXL_HYDRA_FEC_E */ 656 u32 max_carrier_offset_in_mhz; /* Maximum carrier freq offset in MHz. Same as freqSearchRangeKHz, but in unit of MHz. */ 657 }; 658 659 struct MXL_HYDRA_DEMOD_SCRAMBLE_CODE_T { 660 u32 demod_index; 661 u8 scramble_sequence[12]; /* scramble sequence */ 662 u32 scramble_code; /* scramble gold code */ 663 }; 664 665 struct MXL_INTR_CFG_T { 666 u32 intr_type; 667 u32 intr_duration_in_nano_secs; 668 u32 intr_mask; 669 }; 670 671 struct MXL_HYDRA_POWER_MODE_CMD { 672 u8 power_mode; /* enumeration values are defined in MXL_HYDRA_PWR_MODE_E (device API.h) */ 673 }; 674 675 struct MXL_HYDRA_RF_WAKEUP_PARAM_T { 676 u32 time_interval_in_seconds; /* in seconds */ 677 u32 tuner_index; 678 s32 rssi_threshold; 679 }; 680 681 struct MXL_HYDRA_RF_WAKEUP_CFG_T { 682 u32 tuner_count; 683 struct MXL_HYDRA_RF_WAKEUP_PARAM_T params; 684 }; 685 686 enum MXL_HYDRA_AUX_CTRL_MODE_E { 687 MXL_HYDRA_AUX_CTRL_MODE_FSK = 0, /* Select FSK controller */ 688 MXL_HYDRA_AUX_CTRL_MODE_DISEQC, /* Select DiSEqC controller */ 689 }; 690 691 enum MXL_HYDRA_DISEQC_OPMODE_E { 692 MXL_HYDRA_DISEQC_ENVELOPE_MODE = 0, 693 MXL_HYDRA_DISEQC_TONE_MODE, 694 }; 695 696 enum MXL_HYDRA_DISEQC_VER_E { 697 MXL_HYDRA_DISEQC_1_X = 0, /* Config DiSEqC 1.x mode */ 698 MXL_HYDRA_DISEQC_2_X, /* Config DiSEqC 2.x mode */ 699 MXL_HYDRA_DISEQC_DISABLE /* Disable DiSEqC */ 700 }; 701 702 enum MXL_HYDRA_DISEQC_CARRIER_FREQ_E { 703 MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ = 0, /* DiSEqC signal frequency of 22 KHz */ 704 MXL_HYDRA_DISEQC_CARRIER_FREQ_33KHZ, /* DiSEqC signal frequency of 33 KHz */ 705 MXL_HYDRA_DISEQC_CARRIER_FREQ_44KHZ /* DiSEqC signal frequency of 44 KHz */ 706 }; 707 708 enum MXL_HYDRA_DISEQC_ID_E { 709 MXL_HYDRA_DISEQC_ID_0 = 0, 710 MXL_HYDRA_DISEQC_ID_1, 711 MXL_HYDRA_DISEQC_ID_2, 712 MXL_HYDRA_DISEQC_ID_3 713 }; 714 715 enum MXL_HYDRA_FSK_OP_MODE_E { 716 MXL_HYDRA_FSK_CFG_TYPE_39KPBS = 0, /* 39.0kbps */ 717 MXL_HYDRA_FSK_CFG_TYPE_39_017KPBS, /* 39.017kbps */ 718 MXL_HYDRA_FSK_CFG_TYPE_115_2KPBS /* 115.2kbps */ 719 }; 720 721 struct MXL58X_DSQ_OP_MODE_T { 722 u32 diseqc_id; /* DSQ 0, 1, 2 or 3 */ 723 u32 op_mode; /* Envelope mode (0) or internal tone mode (1) */ 724 u32 version; /* 0: 1.0, 1: 1.1, 2: Disable */ 725 u32 center_freq; /* 0: 22KHz, 1: 33KHz and 2: 44 KHz */ 726 }; 727 728 struct MXL_HYDRA_DISEQC_CFG_CONT_TONE_T { 729 u32 diseqc_id; 730 u32 cont_tone_flag; /* 1: Enable , 0: Disable */ 731 }; 732