1 /*
2  *   Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
3  *
4  *   Copyright (C) 2010-2013 Mauro Carvalho Chehab
5  *   Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
6  *
7  *   This program is free software; you can redistribute it and/or
8  *   modify it under the terms of the GNU General Public License as
9  *   published by the Free Software Foundation version 2.
10  *
11  *   This program is distributed in the hope that it will be useful,
12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  *   General Public License for more details.
15  */
16 
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
19 
20 #include "dvb_frontend.h"
21 #include "mb86a20s.h"
22 
23 #define NUM_LAYERS 3
24 
25 static int debug = 1;
26 module_param(debug, int, 0644);
27 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
28 
29 enum mb86a20s_bandwidth {
30 	MB86A20S_13SEG = 0,
31 	MB86A20S_13SEG_PARTIAL = 1,
32 	MB86A20S_1SEG = 2,
33 	MB86A20S_3SEG = 3,
34 };
35 
36 static u8 mb86a20s_subchannel[] = {
37 	0xb0, 0xc0, 0xd0, 0xe0,
38 	0xf0, 0x00, 0x10, 0x20,
39 };
40 
41 struct mb86a20s_state {
42 	struct i2c_adapter *i2c;
43 	const struct mb86a20s_config *config;
44 	u32 last_frequency;
45 
46 	struct dvb_frontend frontend;
47 
48 	u32 if_freq;
49 	enum mb86a20s_bandwidth bw;
50 	bool inversion;
51 	u32 subchannel;
52 
53 	u32 estimated_rate[NUM_LAYERS];
54 	unsigned long get_strength_time;
55 
56 	bool need_init;
57 };
58 
59 struct regdata {
60 	u8 reg;
61 	u8 data;
62 };
63 
64 #define BER_SAMPLING_RATE	1	/* Seconds */
65 
66 /*
67  * Initialization sequence: Use whatevere default values that PV SBTVD
68  * does on its initialisation, obtained via USB snoop
69  */
70 static struct regdata mb86a20s_init1[] = {
71 	{ 0x70, 0x0f },
72 	{ 0x70, 0xff },
73 	{ 0x08, 0x01 },
74 	{ 0x50, 0xd1 }, { 0x51, 0x20 },
75 };
76 
77 static struct regdata mb86a20s_init2[] = {
78 	{ 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
79 	{ 0x3b, 0x21 },
80 	{ 0x3c, 0x38 },
81 	{ 0x01, 0x0d },
82 	{ 0x04, 0x08 }, { 0x05, 0x03 },
83 	{ 0x04, 0x0e }, { 0x05, 0x00 },
84 	{ 0x04, 0x0f }, { 0x05, 0x37 },
85 	{ 0x04, 0x0b }, { 0x05, 0x78 },
86 	{ 0x04, 0x00 }, { 0x05, 0x00 },
87 	{ 0x04, 0x01 }, { 0x05, 0x1e },
88 	{ 0x04, 0x02 }, { 0x05, 0x07 },
89 	{ 0x04, 0x03 }, { 0x05, 0xd0 },
90 	{ 0x04, 0x09 }, { 0x05, 0x00 },
91 	{ 0x04, 0x0a }, { 0x05, 0xff },
92 	{ 0x04, 0x27 }, { 0x05, 0x00 },
93 	{ 0x04, 0x28 }, { 0x05, 0x00 },
94 	{ 0x04, 0x1e }, { 0x05, 0x00 },
95 	{ 0x04, 0x29 }, { 0x05, 0x64 },
96 	{ 0x04, 0x32 }, { 0x05, 0x02 },
97 	{ 0x04, 0x14 }, { 0x05, 0x02 },
98 	{ 0x04, 0x04 }, { 0x05, 0x00 },
99 	{ 0x04, 0x05 }, { 0x05, 0x22 },
100 	{ 0x04, 0x06 }, { 0x05, 0x0e },
101 	{ 0x04, 0x07 }, { 0x05, 0xd8 },
102 	{ 0x04, 0x12 }, { 0x05, 0x00 },
103 	{ 0x04, 0x13 }, { 0x05, 0xff },
104 	{ 0x04, 0x15 }, { 0x05, 0x4e },
105 	{ 0x04, 0x16 }, { 0x05, 0x20 },
106 
107 	/*
108 	 * On this demod, when the bit count reaches the count below,
109 	 * it collects the bit error count. The bit counters are initialized
110 	 * to 65535 here. This warrants that all of them will be quickly
111 	 * calculated when device gets locked. As TMCC is parsed, the values
112 	 * will be adjusted later in the driver's code.
113 	 */
114 	{ 0x52, 0x01 },				/* Turn on BER before Viterbi */
115 	{ 0x50, 0xa7 }, { 0x51, 0x00 },
116 	{ 0x50, 0xa8 }, { 0x51, 0xff },
117 	{ 0x50, 0xa9 }, { 0x51, 0xff },
118 	{ 0x50, 0xaa }, { 0x51, 0x00 },
119 	{ 0x50, 0xab }, { 0x51, 0xff },
120 	{ 0x50, 0xac }, { 0x51, 0xff },
121 	{ 0x50, 0xad }, { 0x51, 0x00 },
122 	{ 0x50, 0xae }, { 0x51, 0xff },
123 	{ 0x50, 0xaf }, { 0x51, 0xff },
124 
125 	/*
126 	 * On this demod, post BER counts blocks. When the count reaches the
127 	 * value below, it collects the block error count. The block counters
128 	 * are initialized to 127 here. This warrants that all of them will be
129 	 * quickly calculated when device gets locked. As TMCC is parsed, the
130 	 * values will be adjusted later in the driver's code.
131 	 */
132 	{ 0x5e, 0x07 },				/* Turn on BER after Viterbi */
133 	{ 0x50, 0xdc }, { 0x51, 0x00 },
134 	{ 0x50, 0xdd }, { 0x51, 0x7f },
135 	{ 0x50, 0xde }, { 0x51, 0x00 },
136 	{ 0x50, 0xdf }, { 0x51, 0x7f },
137 	{ 0x50, 0xe0 }, { 0x51, 0x00 },
138 	{ 0x50, 0xe1 }, { 0x51, 0x7f },
139 
140 	/*
141 	 * On this demod, when the block count reaches the count below,
142 	 * it collects the block error count. The block counters are initialized
143 	 * to 127 here. This warrants that all of them will be quickly
144 	 * calculated when device gets locked. As TMCC is parsed, the values
145 	 * will be adjusted later in the driver's code.
146 	 */
147 	{ 0x50, 0xb0 }, { 0x51, 0x07 },		/* Enable PER */
148 	{ 0x50, 0xb2 }, { 0x51, 0x00 },
149 	{ 0x50, 0xb3 }, { 0x51, 0x7f },
150 	{ 0x50, 0xb4 }, { 0x51, 0x00 },
151 	{ 0x50, 0xb5 }, { 0x51, 0x7f },
152 	{ 0x50, 0xb6 }, { 0x51, 0x00 },
153 	{ 0x50, 0xb7 }, { 0x51, 0x7f },
154 
155 	{ 0x50, 0x50 }, { 0x51, 0x02 },		/* MER manual mode */
156 	{ 0x50, 0x51 }, { 0x51, 0x04 },		/* MER symbol 4 */
157 	{ 0x45, 0x04 },				/* CN symbol 4 */
158 	{ 0x48, 0x04 },				/* CN manual mode */
159 
160 	{ 0x50, 0xd6 }, { 0x51, 0x1f },
161 	{ 0x50, 0xd2 }, { 0x51, 0x03 },
162 	{ 0x50, 0xd7 }, { 0x51, 0xbf },
163 	{ 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
164 	{ 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
165 
166 	{ 0x04, 0x40 }, { 0x05, 0x00 },
167 	{ 0x28, 0x00 }, { 0x2b, 0x08 },
168 	{ 0x28, 0x05 }, { 0x2b, 0x00 },
169 	{ 0x1c, 0x01 },
170 	{ 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
171 	{ 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
172 	{ 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
173 	{ 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
174 	{ 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
175 	{ 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
176 	{ 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
177 	{ 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
178 	{ 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
179 	{ 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
180 	{ 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
181 	{ 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
182 	{ 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
183 	{ 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
184 	{ 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
185 	{ 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
186 	{ 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
187 	{ 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
188 	{ 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
189 	{ 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
190 	{ 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
191 	{ 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
192 	{ 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
193 	{ 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
194 	{ 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
195 	{ 0x50, 0x1e }, { 0x51, 0x5d },
196 	{ 0x50, 0x22 }, { 0x51, 0x00 },
197 	{ 0x50, 0x23 }, { 0x51, 0xc8 },
198 	{ 0x50, 0x24 }, { 0x51, 0x00 },
199 	{ 0x50, 0x25 }, { 0x51, 0xf0 },
200 	{ 0x50, 0x26 }, { 0x51, 0x00 },
201 	{ 0x50, 0x27 }, { 0x51, 0xc3 },
202 	{ 0x50, 0x39 }, { 0x51, 0x02 },
203 	{ 0xec, 0x0f },
204 	{ 0xeb, 0x1f },
205 	{ 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
206 	{ 0xd0, 0x00 },
207 };
208 
209 static struct regdata mb86a20s_reset_reception[] = {
210 	{ 0x70, 0xf0 },
211 	{ 0x70, 0xff },
212 	{ 0x08, 0x01 },
213 	{ 0x08, 0x00 },
214 };
215 
216 static struct regdata mb86a20s_per_ber_reset[] = {
217 	{ 0x53, 0x00 },	/* pre BER Counter reset */
218 	{ 0x53, 0x07 },
219 
220 	{ 0x5f, 0x00 },	/* post BER Counter reset */
221 	{ 0x5f, 0x07 },
222 
223 	{ 0x50, 0xb1 },	/* PER Counter reset */
224 	{ 0x51, 0x07 },
225 	{ 0x51, 0x00 },
226 };
227 
228 /*
229  * I2C read/write functions and macros
230  */
231 
232 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
233 			     u8 i2c_addr, u8 reg, u8 data)
234 {
235 	u8 buf[] = { reg, data };
236 	struct i2c_msg msg = {
237 		.addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
238 	};
239 	int rc;
240 
241 	rc = i2c_transfer(state->i2c, &msg, 1);
242 	if (rc != 1) {
243 		dev_err(&state->i2c->dev,
244 			"%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
245 			__func__, rc, reg, data);
246 		return rc;
247 	}
248 
249 	return 0;
250 }
251 
252 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
253 				     u8 i2c_addr, struct regdata *rd, int size)
254 {
255 	int i, rc;
256 
257 	for (i = 0; i < size; i++) {
258 		rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
259 					   rd[i].data);
260 		if (rc < 0)
261 			return rc;
262 	}
263 	return 0;
264 }
265 
266 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
267 				u8 i2c_addr, u8 reg)
268 {
269 	u8 val;
270 	int rc;
271 	struct i2c_msg msg[] = {
272 		{ .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
273 		{ .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
274 	};
275 
276 	rc = i2c_transfer(state->i2c, msg, 2);
277 
278 	if (rc != 2) {
279 		dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
280 			__func__, reg, rc);
281 		return (rc < 0) ? rc : -EIO;
282 	}
283 
284 	return val;
285 }
286 
287 #define mb86a20s_readreg(state, reg) \
288 	mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
289 #define mb86a20s_writereg(state, reg, val) \
290 	mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
291 #define mb86a20s_writeregdata(state, regdata) \
292 	mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
293 	regdata, ARRAY_SIZE(regdata))
294 
295 /*
296  * Ancillary internal routines (likely compiled inlined)
297  *
298  * The functions below assume that gateway lock has already obtained
299  */
300 
301 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
302 {
303 	struct mb86a20s_state *state = fe->demodulator_priv;
304 	int val;
305 
306 	*status = 0;
307 
308 	val = mb86a20s_readreg(state, 0x0a) & 0xf;
309 	if (val < 0)
310 		return val;
311 
312 	if (val >= 2)
313 		*status |= FE_HAS_SIGNAL;
314 
315 	if (val >= 4)
316 		*status |= FE_HAS_CARRIER;
317 
318 	if (val >= 5)
319 		*status |= FE_HAS_VITERBI;
320 
321 	if (val >= 7)
322 		*status |= FE_HAS_SYNC;
323 
324 	if (val >= 8)				/* Maybe 9? */
325 		*status |= FE_HAS_LOCK;
326 
327 	dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
328 		 __func__, *status, val);
329 
330 	return val;
331 }
332 
333 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
334 {
335 	struct mb86a20s_state *state = fe->demodulator_priv;
336 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
337 	int rc;
338 	unsigned rf_max, rf_min, rf;
339 
340 	if (state->get_strength_time &&
341 	   (!time_after(jiffies, state->get_strength_time)))
342 		return c->strength.stat[0].uvalue;
343 
344 	/* Reset its value if an error happen */
345 	c->strength.stat[0].uvalue = 0;
346 
347 	/* Does a binary search to get RF strength */
348 	rf_max = 0xfff;
349 	rf_min = 0;
350 	do {
351 		rf = (rf_max + rf_min) / 2;
352 		rc = mb86a20s_writereg(state, 0x04, 0x1f);
353 		if (rc < 0)
354 			return rc;
355 		rc = mb86a20s_writereg(state, 0x05, rf >> 8);
356 		if (rc < 0)
357 			return rc;
358 		rc = mb86a20s_writereg(state, 0x04, 0x20);
359 		if (rc < 0)
360 			return rc;
361 		rc = mb86a20s_writereg(state, 0x05, rf);
362 		if (rc < 0)
363 			return rc;
364 
365 		rc = mb86a20s_readreg(state, 0x02);
366 		if (rc < 0)
367 			return rc;
368 		if (rc & 0x08)
369 			rf_min = (rf_max + rf_min) / 2;
370 		else
371 			rf_max = (rf_max + rf_min) / 2;
372 		if (rf_max - rf_min < 4) {
373 			rf = (rf_max + rf_min) / 2;
374 
375 			/* Rescale it from 2^12 (4096) to 2^16 */
376 			rf = rf << (16 - 12);
377 			if (rf)
378 				rf |= (1 << 12) - 1;
379 
380 			dev_dbg(&state->i2c->dev,
381 				"%s: signal strength = %d (%d < RF=%d < %d)\n",
382 				__func__, rf, rf_min, rf >> 4, rf_max);
383 			c->strength.stat[0].uvalue = rf;
384 			state->get_strength_time = jiffies +
385 						   msecs_to_jiffies(1000);
386 			return 0;
387 		}
388 	} while (1);
389 }
390 
391 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
392 				   unsigned layer)
393 {
394 	int rc;
395 	static unsigned char reg[] = {
396 		[0] = 0x86,	/* Layer A */
397 		[1] = 0x8a,	/* Layer B */
398 		[2] = 0x8e,	/* Layer C */
399 	};
400 
401 	if (layer >= ARRAY_SIZE(reg))
402 		return -EINVAL;
403 	rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
404 	if (rc < 0)
405 		return rc;
406 	rc = mb86a20s_readreg(state, 0x6e);
407 	if (rc < 0)
408 		return rc;
409 	switch ((rc >> 4) & 0x07) {
410 	case 0:
411 		return DQPSK;
412 	case 1:
413 		return QPSK;
414 	case 2:
415 		return QAM_16;
416 	case 3:
417 		return QAM_64;
418 	default:
419 		return QAM_AUTO;
420 	}
421 }
422 
423 static int mb86a20s_get_fec(struct mb86a20s_state *state,
424 			    unsigned layer)
425 {
426 	int rc;
427 
428 	static unsigned char reg[] = {
429 		[0] = 0x87,	/* Layer A */
430 		[1] = 0x8b,	/* Layer B */
431 		[2] = 0x8f,	/* Layer C */
432 	};
433 
434 	if (layer >= ARRAY_SIZE(reg))
435 		return -EINVAL;
436 	rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
437 	if (rc < 0)
438 		return rc;
439 	rc = mb86a20s_readreg(state, 0x6e);
440 	if (rc < 0)
441 		return rc;
442 	switch ((rc >> 4) & 0x07) {
443 	case 0:
444 		return FEC_1_2;
445 	case 1:
446 		return FEC_2_3;
447 	case 2:
448 		return FEC_3_4;
449 	case 3:
450 		return FEC_5_6;
451 	case 4:
452 		return FEC_7_8;
453 	default:
454 		return FEC_AUTO;
455 	}
456 }
457 
458 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
459 				     unsigned layer)
460 {
461 	int rc;
462 	int interleaving[] = {
463 		0, 1, 2, 4, 8
464 	};
465 
466 	static unsigned char reg[] = {
467 		[0] = 0x88,	/* Layer A */
468 		[1] = 0x8c,	/* Layer B */
469 		[2] = 0x90,	/* Layer C */
470 	};
471 
472 	if (layer >= ARRAY_SIZE(reg))
473 		return -EINVAL;
474 	rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
475 	if (rc < 0)
476 		return rc;
477 	rc = mb86a20s_readreg(state, 0x6e);
478 	if (rc < 0)
479 		return rc;
480 
481 	return interleaving[(rc >> 4) & 0x07];
482 }
483 
484 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
485 				      unsigned layer)
486 {
487 	int rc, count;
488 	static unsigned char reg[] = {
489 		[0] = 0x89,	/* Layer A */
490 		[1] = 0x8d,	/* Layer B */
491 		[2] = 0x91,	/* Layer C */
492 	};
493 
494 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
495 
496 	if (layer >= ARRAY_SIZE(reg))
497 		return -EINVAL;
498 
499 	rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
500 	if (rc < 0)
501 		return rc;
502 	rc = mb86a20s_readreg(state, 0x6e);
503 	if (rc < 0)
504 		return rc;
505 	count = (rc >> 4) & 0x0f;
506 
507 	dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
508 
509 	return count;
510 }
511 
512 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
513 {
514 	struct mb86a20s_state *state = fe->demodulator_priv;
515 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
516 
517 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
518 
519 	/* Fixed parameters */
520 	c->delivery_system = SYS_ISDBT;
521 	c->bandwidth_hz = 6000000;
522 
523 	/* Initialize values that will be later autodetected */
524 	c->isdbt_layer_enabled = 0;
525 	c->transmission_mode = TRANSMISSION_MODE_AUTO;
526 	c->guard_interval = GUARD_INTERVAL_AUTO;
527 	c->isdbt_sb_mode = 0;
528 	c->isdbt_sb_segment_count = 0;
529 }
530 
531 /*
532  * Estimates the bit rate using the per-segment bit rate given by
533  * ABNT/NBR 15601 spec (table 4).
534  */
535 static u32 isdbt_rate[3][5][4] = {
536 	{	/* DQPSK/QPSK */
537 		{  280850,  312060,  330420,  340430 },	/* 1/2 */
538 		{  374470,  416080,  440560,  453910 },	/* 2/3 */
539 		{  421280,  468090,  495630,  510650 },	/* 3/4 */
540 		{  468090,  520100,  550700,  567390 },	/* 5/6 */
541 		{  491500,  546110,  578230,  595760 },	/* 7/8 */
542 	}, {	/* QAM16 */
543 		{  561710,  624130,  660840,  680870 },	/* 1/2 */
544 		{  748950,  832170,  881120,  907820 },	/* 2/3 */
545 		{  842570,  936190,  991260, 1021300 },	/* 3/4 */
546 		{  936190, 1040210, 1101400, 1134780 },	/* 5/6 */
547 		{  983000, 1092220, 1156470, 1191520 },	/* 7/8 */
548 	}, {	/* QAM64 */
549 		{  842570,  936190,  991260, 1021300 },	/* 1/2 */
550 		{ 1123430, 1248260, 1321680, 1361740 },	/* 2/3 */
551 		{ 1263860, 1404290, 1486900, 1531950 },	/* 3/4 */
552 		{ 1404290, 1560320, 1652110, 1702170 },	/* 5/6 */
553 		{ 1474500, 1638340, 1734710, 1787280 },	/* 7/8 */
554 	}
555 };
556 
557 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
558 				   u32 modulation, u32 forward_error_correction,
559 				   u32 guard_interval,
560 				   u32 segment)
561 {
562 	struct mb86a20s_state *state = fe->demodulator_priv;
563 	u32 rate;
564 	int mod, fec, guard;
565 
566 	/*
567 	 * If modulation/fec/guard is not detected, the default is
568 	 * to consider the lowest bit rate, to avoid taking too long time
569 	 * to get BER.
570 	 */
571 	switch (modulation) {
572 	case DQPSK:
573 	case QPSK:
574 	default:
575 		mod = 0;
576 		break;
577 	case QAM_16:
578 		mod = 1;
579 		break;
580 	case QAM_64:
581 		mod = 2;
582 		break;
583 	}
584 
585 	switch (forward_error_correction) {
586 	default:
587 	case FEC_1_2:
588 	case FEC_AUTO:
589 		fec = 0;
590 		break;
591 	case FEC_2_3:
592 		fec = 1;
593 		break;
594 	case FEC_3_4:
595 		fec = 2;
596 		break;
597 	case FEC_5_6:
598 		fec = 3;
599 		break;
600 	case FEC_7_8:
601 		fec = 4;
602 		break;
603 	}
604 
605 	switch (guard_interval) {
606 	default:
607 	case GUARD_INTERVAL_1_4:
608 		guard = 0;
609 		break;
610 	case GUARD_INTERVAL_1_8:
611 		guard = 1;
612 		break;
613 	case GUARD_INTERVAL_1_16:
614 		guard = 2;
615 		break;
616 	case GUARD_INTERVAL_1_32:
617 		guard = 3;
618 		break;
619 	}
620 
621 	/* Samples BER at BER_SAMPLING_RATE seconds */
622 	rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
623 
624 	/* Avoids sampling too quickly or to overflow the register */
625 	if (rate < 256)
626 		rate = 256;
627 	else if (rate > (1 << 24) - 1)
628 		rate = (1 << 24) - 1;
629 
630 	dev_dbg(&state->i2c->dev,
631 		"%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
632 		__func__, 'A' + layer,
633 		segment * isdbt_rate[mod][fec][guard]/1000,
634 		rate, rate);
635 
636 	state->estimated_rate[layer] = rate;
637 }
638 
639 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
640 {
641 	struct mb86a20s_state *state = fe->demodulator_priv;
642 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
643 	int layer, rc;
644 
645 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
646 
647 	/* Reset frontend cache to default values */
648 	mb86a20s_reset_frontend_cache(fe);
649 
650 	/* Check for partial reception */
651 	rc = mb86a20s_writereg(state, 0x6d, 0x85);
652 	if (rc < 0)
653 		return rc;
654 	rc = mb86a20s_readreg(state, 0x6e);
655 	if (rc < 0)
656 		return rc;
657 	c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
658 
659 	/* Get per-layer data */
660 
661 	for (layer = 0; layer < NUM_LAYERS; layer++) {
662 		dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
663 			__func__, 'A' + layer);
664 
665 		rc = mb86a20s_get_segment_count(state, layer);
666 		if (rc < 0)
667 			goto noperlayer_error;
668 		if (rc >= 0 && rc < 14) {
669 			c->layer[layer].segment_count = rc;
670 		} else {
671 			c->layer[layer].segment_count = 0;
672 			state->estimated_rate[layer] = 0;
673 			continue;
674 		}
675 		c->isdbt_layer_enabled |= 1 << layer;
676 		rc = mb86a20s_get_modulation(state, layer);
677 		if (rc < 0)
678 			goto noperlayer_error;
679 		dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
680 			__func__, rc);
681 		c->layer[layer].modulation = rc;
682 		rc = mb86a20s_get_fec(state, layer);
683 		if (rc < 0)
684 			goto noperlayer_error;
685 		dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
686 			__func__, rc);
687 		c->layer[layer].fec = rc;
688 		rc = mb86a20s_get_interleaving(state, layer);
689 		if (rc < 0)
690 			goto noperlayer_error;
691 		dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
692 			__func__, rc);
693 		c->layer[layer].interleaving = rc;
694 		mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
695 				       c->layer[layer].fec,
696 				       c->guard_interval,
697 				       c->layer[layer].segment_count);
698 	}
699 
700 	rc = mb86a20s_writereg(state, 0x6d, 0x84);
701 	if (rc < 0)
702 		return rc;
703 	if ((rc & 0x60) == 0x20) {
704 		c->isdbt_sb_mode = 1;
705 		/* At least, one segment should exist */
706 		if (!c->isdbt_sb_segment_count)
707 			c->isdbt_sb_segment_count = 1;
708 	}
709 
710 	/* Get transmission mode and guard interval */
711 	rc = mb86a20s_readreg(state, 0x07);
712 	if (rc < 0)
713 		return rc;
714 	c->transmission_mode = TRANSMISSION_MODE_AUTO;
715 	if ((rc & 0x60) == 0x20) {
716 		/* Only modes 2 and 3 are supported */
717 		switch ((rc >> 2) & 0x03) {
718 		case 1:
719 			c->transmission_mode = TRANSMISSION_MODE_4K;
720 			break;
721 		case 2:
722 			c->transmission_mode = TRANSMISSION_MODE_8K;
723 			break;
724 		}
725 	}
726 	c->guard_interval = GUARD_INTERVAL_AUTO;
727 	if (!(rc & 0x10)) {
728 		/* Guard interval 1/32 is not supported */
729 		switch (rc & 0x3) {
730 		case 0:
731 			c->guard_interval = GUARD_INTERVAL_1_4;
732 			break;
733 		case 1:
734 			c->guard_interval = GUARD_INTERVAL_1_8;
735 			break;
736 		case 2:
737 			c->guard_interval = GUARD_INTERVAL_1_16;
738 			break;
739 		}
740 	}
741 	return 0;
742 
743 noperlayer_error:
744 
745 	/* per-layer info is incomplete; discard all per-layer */
746 	c->isdbt_layer_enabled = 0;
747 
748 	return rc;
749 }
750 
751 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
752 {
753 	struct mb86a20s_state *state = fe->demodulator_priv;
754 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
755 	int rc, val;
756 
757 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
758 
759 	/* Reset the counters, if the channel changed */
760 	if (state->last_frequency != c->frequency) {
761 		memset(&c->cnr, 0, sizeof(c->cnr));
762 		memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
763 		memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
764 		memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
765 		memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
766 		memset(&c->block_error, 0, sizeof(c->block_error));
767 		memset(&c->block_count, 0, sizeof(c->block_count));
768 
769 		state->last_frequency = c->frequency;
770 	}
771 
772 	/* Clear status for most stats */
773 
774 	/* BER/PER counter reset */
775 	rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
776 	if (rc < 0)
777 		goto err;
778 
779 	/* CNR counter reset */
780 	rc = mb86a20s_readreg(state, 0x45);
781 	if (rc < 0)
782 		goto err;
783 	val = rc;
784 	rc = mb86a20s_writereg(state, 0x45, val | 0x10);
785 	if (rc < 0)
786 		goto err;
787 	rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
788 	if (rc < 0)
789 		goto err;
790 
791 	/* MER counter reset */
792 	rc = mb86a20s_writereg(state, 0x50, 0x50);
793 	if (rc < 0)
794 		goto err;
795 	rc = mb86a20s_readreg(state, 0x51);
796 	if (rc < 0)
797 		goto err;
798 	val = rc;
799 	rc = mb86a20s_writereg(state, 0x51, val | 0x01);
800 	if (rc < 0)
801 		goto err;
802 	rc = mb86a20s_writereg(state, 0x51, val & 0x06);
803 	if (rc < 0)
804 		goto err;
805 
806 	goto ok;
807 err:
808 	dev_err(&state->i2c->dev,
809 		"%s: Can't reset FE statistics (error %d).\n",
810 		__func__, rc);
811 ok:
812 	return rc;
813 }
814 
815 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
816 				unsigned layer,
817 				u32 *error, u32 *count)
818 {
819 	struct mb86a20s_state *state = fe->demodulator_priv;
820 	int rc, val;
821 
822 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
823 
824 	if (layer >= NUM_LAYERS)
825 		return -EINVAL;
826 
827 	/* Check if the BER measures are already available */
828 	rc = mb86a20s_readreg(state, 0x54);
829 	if (rc < 0)
830 		return rc;
831 
832 	/* Check if data is available for that layer */
833 	if (!(rc & (1 << layer))) {
834 		dev_dbg(&state->i2c->dev,
835 			"%s: preBER for layer %c is not available yet.\n",
836 			__func__, 'A' + layer);
837 		return -EBUSY;
838 	}
839 
840 	/* Read Bit Error Count */
841 	rc = mb86a20s_readreg(state, 0x55 + layer * 3);
842 	if (rc < 0)
843 		return rc;
844 	*error = rc << 16;
845 	rc = mb86a20s_readreg(state, 0x56 + layer * 3);
846 	if (rc < 0)
847 		return rc;
848 	*error |= rc << 8;
849 	rc = mb86a20s_readreg(state, 0x57 + layer * 3);
850 	if (rc < 0)
851 		return rc;
852 	*error |= rc;
853 
854 	dev_dbg(&state->i2c->dev,
855 		"%s: bit error before Viterbi for layer %c: %d.\n",
856 		__func__, 'A' + layer, *error);
857 
858 	/* Read Bit Count */
859 	rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
860 	if (rc < 0)
861 		return rc;
862 	rc = mb86a20s_readreg(state, 0x51);
863 	if (rc < 0)
864 		return rc;
865 	*count = rc << 16;
866 	rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
867 	if (rc < 0)
868 		return rc;
869 	rc = mb86a20s_readreg(state, 0x51);
870 	if (rc < 0)
871 		return rc;
872 	*count |= rc << 8;
873 	rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
874 	if (rc < 0)
875 		return rc;
876 	rc = mb86a20s_readreg(state, 0x51);
877 	if (rc < 0)
878 		return rc;
879 	*count |= rc;
880 
881 	dev_dbg(&state->i2c->dev,
882 		"%s: bit count before Viterbi for layer %c: %d.\n",
883 		__func__, 'A' + layer, *count);
884 
885 
886 	/*
887 	 * As we get TMCC data from the frontend, we can better estimate the
888 	 * BER bit counters, in order to do the BER measure during a longer
889 	 * time. Use those data, if available, to update the bit count
890 	 * measure.
891 	 */
892 
893 	if (state->estimated_rate[layer]
894 	    && state->estimated_rate[layer] != *count) {
895 		dev_dbg(&state->i2c->dev,
896 			"%s: updating layer %c preBER counter to %d.\n",
897 			__func__, 'A' + layer, state->estimated_rate[layer]);
898 
899 		/* Turn off BER before Viterbi */
900 		rc = mb86a20s_writereg(state, 0x52, 0x00);
901 
902 		/* Update counter for this layer */
903 		rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
904 		if (rc < 0)
905 			return rc;
906 		rc = mb86a20s_writereg(state, 0x51,
907 				       state->estimated_rate[layer] >> 16);
908 		if (rc < 0)
909 			return rc;
910 		rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
911 		if (rc < 0)
912 			return rc;
913 		rc = mb86a20s_writereg(state, 0x51,
914 				       state->estimated_rate[layer] >> 8);
915 		if (rc < 0)
916 			return rc;
917 		rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
918 		if (rc < 0)
919 			return rc;
920 		rc = mb86a20s_writereg(state, 0x51,
921 				       state->estimated_rate[layer]);
922 		if (rc < 0)
923 			return rc;
924 
925 		/* Turn on BER before Viterbi */
926 		rc = mb86a20s_writereg(state, 0x52, 0x01);
927 
928 		/* Reset all preBER counters */
929 		rc = mb86a20s_writereg(state, 0x53, 0x00);
930 		if (rc < 0)
931 			return rc;
932 		rc = mb86a20s_writereg(state, 0x53, 0x07);
933 	} else {
934 		/* Reset counter to collect new data */
935 		rc = mb86a20s_readreg(state, 0x53);
936 		if (rc < 0)
937 			return rc;
938 		val = rc;
939 		rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
940 		if (rc < 0)
941 			return rc;
942 		rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
943 	}
944 
945 	return rc;
946 }
947 
948 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
949 				 unsigned layer,
950 				  u32 *error, u32 *count)
951 {
952 	struct mb86a20s_state *state = fe->demodulator_priv;
953 	u32 counter, collect_rate;
954 	int rc, val;
955 
956 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
957 
958 	if (layer >= NUM_LAYERS)
959 		return -EINVAL;
960 
961 	/* Check if the BER measures are already available */
962 	rc = mb86a20s_readreg(state, 0x60);
963 	if (rc < 0)
964 		return rc;
965 
966 	/* Check if data is available for that layer */
967 	if (!(rc & (1 << layer))) {
968 		dev_dbg(&state->i2c->dev,
969 			"%s: post BER for layer %c is not available yet.\n",
970 			__func__, 'A' + layer);
971 		return -EBUSY;
972 	}
973 
974 	/* Read Bit Error Count */
975 	rc = mb86a20s_readreg(state, 0x64 + layer * 3);
976 	if (rc < 0)
977 		return rc;
978 	*error = rc << 16;
979 	rc = mb86a20s_readreg(state, 0x65 + layer * 3);
980 	if (rc < 0)
981 		return rc;
982 	*error |= rc << 8;
983 	rc = mb86a20s_readreg(state, 0x66 + layer * 3);
984 	if (rc < 0)
985 		return rc;
986 	*error |= rc;
987 
988 	dev_dbg(&state->i2c->dev,
989 		"%s: post bit error for layer %c: %d.\n",
990 		__func__, 'A' + layer, *error);
991 
992 	/* Read Bit Count */
993 	rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
994 	if (rc < 0)
995 		return rc;
996 	rc = mb86a20s_readreg(state, 0x51);
997 	if (rc < 0)
998 		return rc;
999 	counter = rc << 8;
1000 	rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1001 	if (rc < 0)
1002 		return rc;
1003 	rc = mb86a20s_readreg(state, 0x51);
1004 	if (rc < 0)
1005 		return rc;
1006 	counter |= rc;
1007 	*count = counter * 204 * 8;
1008 
1009 	dev_dbg(&state->i2c->dev,
1010 		"%s: post bit count for layer %c: %d.\n",
1011 		__func__, 'A' + layer, *count);
1012 
1013 	/*
1014 	 * As we get TMCC data from the frontend, we can better estimate the
1015 	 * BER bit counters, in order to do the BER measure during a longer
1016 	 * time. Use those data, if available, to update the bit count
1017 	 * measure.
1018 	 */
1019 
1020 	if (!state->estimated_rate[layer])
1021 		goto reset_measurement;
1022 
1023 	collect_rate = state->estimated_rate[layer] / 204 / 8;
1024 	if (collect_rate < 32)
1025 		collect_rate = 32;
1026 	if (collect_rate > 65535)
1027 		collect_rate = 65535;
1028 	if (collect_rate != counter) {
1029 		dev_dbg(&state->i2c->dev,
1030 			"%s: updating postBER counter on layer %c to %d.\n",
1031 			__func__, 'A' + layer, collect_rate);
1032 
1033 		/* Turn off BER after Viterbi */
1034 		rc = mb86a20s_writereg(state, 0x5e, 0x00);
1035 
1036 		/* Update counter for this layer */
1037 		rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1038 		if (rc < 0)
1039 			return rc;
1040 		rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1041 		if (rc < 0)
1042 			return rc;
1043 		rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1044 		if (rc < 0)
1045 			return rc;
1046 		rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1047 		if (rc < 0)
1048 			return rc;
1049 
1050 		/* Turn on BER after Viterbi */
1051 		rc = mb86a20s_writereg(state, 0x5e, 0x07);
1052 
1053 		/* Reset all preBER counters */
1054 		rc = mb86a20s_writereg(state, 0x5f, 0x00);
1055 		if (rc < 0)
1056 			return rc;
1057 		rc = mb86a20s_writereg(state, 0x5f, 0x07);
1058 
1059 		return rc;
1060 	}
1061 
1062 reset_measurement:
1063 	/* Reset counter to collect new data */
1064 	rc = mb86a20s_readreg(state, 0x5f);
1065 	if (rc < 0)
1066 		return rc;
1067 	val = rc;
1068 	rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1069 	if (rc < 0)
1070 		return rc;
1071 	rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1072 
1073 	return rc;
1074 }
1075 
1076 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1077 			    unsigned layer,
1078 			    u32 *error, u32 *count)
1079 {
1080 	struct mb86a20s_state *state = fe->demodulator_priv;
1081 	int rc, val;
1082 	u32 collect_rate;
1083 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1084 
1085 	if (layer >= NUM_LAYERS)
1086 		return -EINVAL;
1087 
1088 	/* Check if the PER measures are already available */
1089 	rc = mb86a20s_writereg(state, 0x50, 0xb8);
1090 	if (rc < 0)
1091 		return rc;
1092 	rc = mb86a20s_readreg(state, 0x51);
1093 	if (rc < 0)
1094 		return rc;
1095 
1096 	/* Check if data is available for that layer */
1097 
1098 	if (!(rc & (1 << layer))) {
1099 		dev_dbg(&state->i2c->dev,
1100 			"%s: block counts for layer %c aren't available yet.\n",
1101 			__func__, 'A' + layer);
1102 		return -EBUSY;
1103 	}
1104 
1105 	/* Read Packet error Count */
1106 	rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1107 	if (rc < 0)
1108 		return rc;
1109 	rc = mb86a20s_readreg(state, 0x51);
1110 	if (rc < 0)
1111 		return rc;
1112 	*error = rc << 8;
1113 	rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1114 	if (rc < 0)
1115 		return rc;
1116 	rc = mb86a20s_readreg(state, 0x51);
1117 	if (rc < 0)
1118 		return rc;
1119 	*error |= rc;
1120 	dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1121 		__func__, 'A' + layer, *error);
1122 
1123 	/* Read Bit Count */
1124 	rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1125 	if (rc < 0)
1126 		return rc;
1127 	rc = mb86a20s_readreg(state, 0x51);
1128 	if (rc < 0)
1129 		return rc;
1130 	*count = rc << 8;
1131 	rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1132 	if (rc < 0)
1133 		return rc;
1134 	rc = mb86a20s_readreg(state, 0x51);
1135 	if (rc < 0)
1136 		return rc;
1137 	*count |= rc;
1138 
1139 	dev_dbg(&state->i2c->dev,
1140 		"%s: block count for layer %c: %d.\n",
1141 		__func__, 'A' + layer, *count);
1142 
1143 	/*
1144 	 * As we get TMCC data from the frontend, we can better estimate the
1145 	 * BER bit counters, in order to do the BER measure during a longer
1146 	 * time. Use those data, if available, to update the bit count
1147 	 * measure.
1148 	 */
1149 
1150 	if (!state->estimated_rate[layer])
1151 		goto reset_measurement;
1152 
1153 	collect_rate = state->estimated_rate[layer] / 204 / 8;
1154 	if (collect_rate < 32)
1155 		collect_rate = 32;
1156 	if (collect_rate > 65535)
1157 		collect_rate = 65535;
1158 
1159 	if (collect_rate != *count) {
1160 		dev_dbg(&state->i2c->dev,
1161 			"%s: updating PER counter on layer %c to %d.\n",
1162 			__func__, 'A' + layer, collect_rate);
1163 
1164 		/* Stop PER measurement */
1165 		rc = mb86a20s_writereg(state, 0x50, 0xb0);
1166 		if (rc < 0)
1167 			return rc;
1168 		rc = mb86a20s_writereg(state, 0x51, 0x00);
1169 		if (rc < 0)
1170 			return rc;
1171 
1172 		/* Update this layer's counter */
1173 		rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1174 		if (rc < 0)
1175 			return rc;
1176 		rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1177 		if (rc < 0)
1178 			return rc;
1179 		rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1180 		if (rc < 0)
1181 			return rc;
1182 		rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1183 		if (rc < 0)
1184 			return rc;
1185 
1186 		/* start PER measurement */
1187 		rc = mb86a20s_writereg(state, 0x50, 0xb0);
1188 		if (rc < 0)
1189 			return rc;
1190 		rc = mb86a20s_writereg(state, 0x51, 0x07);
1191 		if (rc < 0)
1192 			return rc;
1193 
1194 		/* Reset all counters to collect new data */
1195 		rc = mb86a20s_writereg(state, 0x50, 0xb1);
1196 		if (rc < 0)
1197 			return rc;
1198 		rc = mb86a20s_writereg(state, 0x51, 0x07);
1199 		if (rc < 0)
1200 			return rc;
1201 		rc = mb86a20s_writereg(state, 0x51, 0x00);
1202 
1203 		return rc;
1204 	}
1205 
1206 reset_measurement:
1207 	/* Reset counter to collect new data */
1208 	rc = mb86a20s_writereg(state, 0x50, 0xb1);
1209 	if (rc < 0)
1210 		return rc;
1211 	rc = mb86a20s_readreg(state, 0x51);
1212 	if (rc < 0)
1213 		return rc;
1214 	val = rc;
1215 	rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1216 	if (rc < 0)
1217 		return rc;
1218 	rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1219 
1220 	return rc;
1221 }
1222 
1223 struct linear_segments {
1224 	unsigned x, y;
1225 };
1226 
1227 /*
1228  * All tables below return a dB/1000 measurement
1229  */
1230 
1231 static const struct linear_segments cnr_to_db_table[] = {
1232 	{ 19648,     0},
1233 	{ 18187,  1000},
1234 	{ 16534,  2000},
1235 	{ 14823,  3000},
1236 	{ 13161,  4000},
1237 	{ 11622,  5000},
1238 	{ 10279,  6000},
1239 	{  9089,  7000},
1240 	{  8042,  8000},
1241 	{  7137,  9000},
1242 	{  6342, 10000},
1243 	{  5641, 11000},
1244 	{  5030, 12000},
1245 	{  4474, 13000},
1246 	{  3988, 14000},
1247 	{  3556, 15000},
1248 	{  3180, 16000},
1249 	{  2841, 17000},
1250 	{  2541, 18000},
1251 	{  2276, 19000},
1252 	{  2038, 20000},
1253 	{  1800, 21000},
1254 	{  1625, 22000},
1255 	{  1462, 23000},
1256 	{  1324, 24000},
1257 	{  1175, 25000},
1258 	{  1063, 26000},
1259 	{   980, 27000},
1260 	{   907, 28000},
1261 	{   840, 29000},
1262 	{   788, 30000},
1263 };
1264 
1265 static const struct linear_segments cnr_64qam_table[] = {
1266 	{ 3922688,     0},
1267 	{ 3920384,  1000},
1268 	{ 3902720,  2000},
1269 	{ 3894784,  3000},
1270 	{ 3882496,  4000},
1271 	{ 3872768,  5000},
1272 	{ 3858944,  6000},
1273 	{ 3851520,  7000},
1274 	{ 3838976,  8000},
1275 	{ 3829248,  9000},
1276 	{ 3818240, 10000},
1277 	{ 3806976, 11000},
1278 	{ 3791872, 12000},
1279 	{ 3767040, 13000},
1280 	{ 3720960, 14000},
1281 	{ 3637504, 15000},
1282 	{ 3498496, 16000},
1283 	{ 3296000, 17000},
1284 	{ 3031040, 18000},
1285 	{ 2715392, 19000},
1286 	{ 2362624, 20000},
1287 	{ 1963264, 21000},
1288 	{ 1649664, 22000},
1289 	{ 1366784, 23000},
1290 	{ 1120768, 24000},
1291 	{  890880, 25000},
1292 	{  723456, 26000},
1293 	{  612096, 27000},
1294 	{  518912, 28000},
1295 	{  448256, 29000},
1296 	{  388864, 30000},
1297 };
1298 
1299 static const struct linear_segments cnr_16qam_table[] = {
1300 	{ 5314816,     0},
1301 	{ 5219072,  1000},
1302 	{ 5118720,  2000},
1303 	{ 4998912,  3000},
1304 	{ 4875520,  4000},
1305 	{ 4736000,  5000},
1306 	{ 4604160,  6000},
1307 	{ 4458752,  7000},
1308 	{ 4300288,  8000},
1309 	{ 4092928,  9000},
1310 	{ 3836160, 10000},
1311 	{ 3521024, 11000},
1312 	{ 3155968, 12000},
1313 	{ 2756864, 13000},
1314 	{ 2347008, 14000},
1315 	{ 1955072, 15000},
1316 	{ 1593600, 16000},
1317 	{ 1297920, 17000},
1318 	{ 1043968, 18000},
1319 	{  839680, 19000},
1320 	{  672256, 20000},
1321 	{  523008, 21000},
1322 	{  424704, 22000},
1323 	{  345088, 23000},
1324 	{  280064, 24000},
1325 	{  221440, 25000},
1326 	{  179712, 26000},
1327 	{  151040, 27000},
1328 	{  128512, 28000},
1329 	{  110080, 29000},
1330 	{   95744, 30000},
1331 };
1332 
1333 static const struct linear_segments cnr_qpsk_table[] = {
1334 	{ 2834176,     0},
1335 	{ 2683648,  1000},
1336 	{ 2536960,  2000},
1337 	{ 2391808,  3000},
1338 	{ 2133248,  4000},
1339 	{ 1906176,  5000},
1340 	{ 1666560,  6000},
1341 	{ 1422080,  7000},
1342 	{ 1189632,  8000},
1343 	{  976384,  9000},
1344 	{  790272, 10000},
1345 	{  633344, 11000},
1346 	{  505600, 12000},
1347 	{  402944, 13000},
1348 	{  320768, 14000},
1349 	{  255488, 15000},
1350 	{  204032, 16000},
1351 	{  163072, 17000},
1352 	{  130304, 18000},
1353 	{  105216, 19000},
1354 	{   83456, 20000},
1355 	{   65024, 21000},
1356 	{   52480, 22000},
1357 	{   42752, 23000},
1358 	{   34560, 24000},
1359 	{   27136, 25000},
1360 	{   22016, 26000},
1361 	{   18432, 27000},
1362 	{   15616, 28000},
1363 	{   13312, 29000},
1364 	{   11520, 30000},
1365 };
1366 
1367 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1368 			     unsigned len)
1369 {
1370 	u64 tmp64;
1371 	u32 dx, dy;
1372 	int i, ret;
1373 
1374 	if (value >= segments[0].x)
1375 		return segments[0].y;
1376 	if (value < segments[len-1].x)
1377 		return segments[len-1].y;
1378 
1379 	for (i = 1; i < len - 1; i++) {
1380 		/* If value is identical, no need to interpolate */
1381 		if (value == segments[i].x)
1382 			return segments[i].y;
1383 		if (value > segments[i].x)
1384 			break;
1385 	}
1386 
1387 	/* Linear interpolation between the two (x,y) points */
1388 	dy = segments[i].y - segments[i - 1].y;
1389 	dx = segments[i - 1].x - segments[i].x;
1390 	tmp64 = value - segments[i].x;
1391 	tmp64 *= dy;
1392 	do_div(tmp64, dx);
1393 	ret = segments[i].y - tmp64;
1394 
1395 	return ret;
1396 }
1397 
1398 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1399 {
1400 	struct mb86a20s_state *state = fe->demodulator_priv;
1401 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1402 	u32 cnr_linear, cnr;
1403 	int rc, val;
1404 
1405 	/* Check if CNR is available */
1406 	rc = mb86a20s_readreg(state, 0x45);
1407 	if (rc < 0)
1408 		return rc;
1409 
1410 	if (!(rc & 0x40)) {
1411 		dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1412 			 __func__);
1413 		return -EBUSY;
1414 	}
1415 	val = rc;
1416 
1417 	rc = mb86a20s_readreg(state, 0x46);
1418 	if (rc < 0)
1419 		return rc;
1420 	cnr_linear = rc << 8;
1421 
1422 	rc = mb86a20s_readreg(state, 0x46);
1423 	if (rc < 0)
1424 		return rc;
1425 	cnr_linear |= rc;
1426 
1427 	cnr = interpolate_value(cnr_linear,
1428 				cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1429 
1430 	c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1431 	c->cnr.stat[0].svalue = cnr;
1432 
1433 	dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1434 		__func__, cnr / 1000, cnr % 1000, cnr_linear);
1435 
1436 	/* CNR counter reset */
1437 	rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1438 	if (rc < 0)
1439 		return rc;
1440 	rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1441 
1442 	return rc;
1443 }
1444 
1445 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1446 {
1447 	struct mb86a20s_state *state = fe->demodulator_priv;
1448 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1449 	u32 mer, cnr;
1450 	int rc, val, layer;
1451 	const struct linear_segments *segs;
1452 	unsigned segs_len;
1453 
1454 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1455 
1456 	/* Check if the measures are already available */
1457 	rc = mb86a20s_writereg(state, 0x50, 0x5b);
1458 	if (rc < 0)
1459 		return rc;
1460 	rc = mb86a20s_readreg(state, 0x51);
1461 	if (rc < 0)
1462 		return rc;
1463 
1464 	/* Check if data is available */
1465 	if (!(rc & 0x01)) {
1466 		dev_dbg(&state->i2c->dev,
1467 			"%s: MER measures aren't available yet.\n", __func__);
1468 		return -EBUSY;
1469 	}
1470 
1471 	/* Read all layers */
1472 	for (layer = 0; layer < NUM_LAYERS; layer++) {
1473 		if (!(c->isdbt_layer_enabled & (1 << layer))) {
1474 			c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1475 			continue;
1476 		}
1477 
1478 		rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1479 		if (rc < 0)
1480 			return rc;
1481 		rc = mb86a20s_readreg(state, 0x51);
1482 		if (rc < 0)
1483 			return rc;
1484 		mer = rc << 16;
1485 		rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1486 		if (rc < 0)
1487 			return rc;
1488 		rc = mb86a20s_readreg(state, 0x51);
1489 		if (rc < 0)
1490 			return rc;
1491 		mer |= rc << 8;
1492 		rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1493 		if (rc < 0)
1494 			return rc;
1495 		rc = mb86a20s_readreg(state, 0x51);
1496 		if (rc < 0)
1497 			return rc;
1498 		mer |= rc;
1499 
1500 		switch (c->layer[layer].modulation) {
1501 		case DQPSK:
1502 		case QPSK:
1503 			segs = cnr_qpsk_table;
1504 			segs_len = ARRAY_SIZE(cnr_qpsk_table);
1505 			break;
1506 		case QAM_16:
1507 			segs = cnr_16qam_table;
1508 			segs_len = ARRAY_SIZE(cnr_16qam_table);
1509 			break;
1510 		default:
1511 		case QAM_64:
1512 			segs = cnr_64qam_table;
1513 			segs_len = ARRAY_SIZE(cnr_64qam_table);
1514 			break;
1515 		}
1516 		cnr = interpolate_value(mer, segs, segs_len);
1517 
1518 		c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1519 		c->cnr.stat[1 + layer].svalue = cnr;
1520 
1521 		dev_dbg(&state->i2c->dev,
1522 			"%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1523 			__func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1524 
1525 	}
1526 
1527 	/* Start a new MER measurement */
1528 	/* MER counter reset */
1529 	rc = mb86a20s_writereg(state, 0x50, 0x50);
1530 	if (rc < 0)
1531 		return rc;
1532 	rc = mb86a20s_readreg(state, 0x51);
1533 	if (rc < 0)
1534 		return rc;
1535 	val = rc;
1536 
1537 	rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1538 	if (rc < 0)
1539 		return rc;
1540 	rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1541 	if (rc < 0)
1542 		return rc;
1543 
1544 	return 0;
1545 }
1546 
1547 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1548 {
1549 	struct mb86a20s_state *state = fe->demodulator_priv;
1550 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1551 	int layer;
1552 
1553 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1554 
1555 	/* Fill the length of each status counter */
1556 
1557 	/* Only global stats */
1558 	c->strength.len = 1;
1559 
1560 	/* Per-layer stats - 3 layers + global */
1561 	c->cnr.len = NUM_LAYERS + 1;
1562 	c->pre_bit_error.len = NUM_LAYERS + 1;
1563 	c->pre_bit_count.len = NUM_LAYERS + 1;
1564 	c->post_bit_error.len = NUM_LAYERS + 1;
1565 	c->post_bit_count.len = NUM_LAYERS + 1;
1566 	c->block_error.len = NUM_LAYERS + 1;
1567 	c->block_count.len = NUM_LAYERS + 1;
1568 
1569 	/* Signal is always available */
1570 	c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1571 	c->strength.stat[0].uvalue = 0;
1572 
1573 	/* Put all of them at FE_SCALE_NOT_AVAILABLE */
1574 	for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1575 		c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1576 		c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1577 		c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1578 		c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1579 		c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1580 		c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1581 		c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1582 	}
1583 }
1584 
1585 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1586 {
1587 	struct mb86a20s_state *state = fe->demodulator_priv;
1588 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1589 	int rc = 0, layer;
1590 	u32 bit_error = 0, bit_count = 0;
1591 	u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1592 	u32 t_post_bit_error = 0, t_post_bit_count = 0;
1593 	u32 block_error = 0, block_count = 0;
1594 	u32 t_block_error = 0, t_block_count = 0;
1595 	int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1596 	int per_layers = 0;
1597 
1598 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1599 
1600 	mb86a20s_get_main_CNR(fe);
1601 
1602 	/* Get per-layer stats */
1603 	mb86a20s_get_blk_error_layer_CNR(fe);
1604 
1605 	/*
1606 	 * At state 7, only CNR is available
1607 	 * For BER measures, state=9 is required
1608 	 * FIXME: we may get MER measures with state=8
1609 	 */
1610 	if (status_nr < 9)
1611 		return 0;
1612 
1613 	for (layer = 0; layer < NUM_LAYERS; layer++) {
1614 		if (c->isdbt_layer_enabled & (1 << layer)) {
1615 			/* Layer is active and has rc segments */
1616 			active_layers++;
1617 
1618 			/* Handle BER before vterbi */
1619 			rc = mb86a20s_get_pre_ber(fe, layer,
1620 						  &bit_error, &bit_count);
1621 			if (rc >= 0) {
1622 				c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1623 				c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1624 				c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1625 				c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1626 			} else if (rc != -EBUSY) {
1627 				/*
1628 					* If an I/O error happened,
1629 					* measures are now unavailable
1630 					*/
1631 				c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1632 				c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1633 				dev_err(&state->i2c->dev,
1634 					"%s: Can't get BER for layer %c (error %d).\n",
1635 					__func__, 'A' + layer, rc);
1636 			}
1637 			if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1638 				pre_ber_layers++;
1639 
1640 			/* Handle BER post vterbi */
1641 			rc = mb86a20s_get_post_ber(fe, layer,
1642 						   &bit_error, &bit_count);
1643 			if (rc >= 0) {
1644 				c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1645 				c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1646 				c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1647 				c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1648 			} else if (rc != -EBUSY) {
1649 				/*
1650 					* If an I/O error happened,
1651 					* measures are now unavailable
1652 					*/
1653 				c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1654 				c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1655 				dev_err(&state->i2c->dev,
1656 					"%s: Can't get BER for layer %c (error %d).\n",
1657 					__func__, 'A' + layer, rc);
1658 			}
1659 			if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1660 				post_ber_layers++;
1661 
1662 			/* Handle Block errors for PER/UCB reports */
1663 			rc = mb86a20s_get_blk_error(fe, layer,
1664 						&block_error,
1665 						&block_count);
1666 			if (rc >= 0) {
1667 				c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1668 				c->block_error.stat[1 + layer].uvalue += block_error;
1669 				c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1670 				c->block_count.stat[1 + layer].uvalue += block_count;
1671 			} else if (rc != -EBUSY) {
1672 				/*
1673 					* If an I/O error happened,
1674 					* measures are now unavailable
1675 					*/
1676 				c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1677 				c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1678 				dev_err(&state->i2c->dev,
1679 					"%s: Can't get PER for layer %c (error %d).\n",
1680 					__func__, 'A' + layer, rc);
1681 
1682 			}
1683 			if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1684 				per_layers++;
1685 
1686 			/* Update total preBER */
1687 			t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1688 			t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1689 
1690 			/* Update total postBER */
1691 			t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1692 			t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1693 
1694 			/* Update total PER */
1695 			t_block_error += c->block_error.stat[1 + layer].uvalue;
1696 			t_block_count += c->block_count.stat[1 + layer].uvalue;
1697 		}
1698 	}
1699 
1700 	/*
1701 	 * Start showing global count if at least one error count is
1702 	 * available.
1703 	 */
1704 	if (pre_ber_layers) {
1705 		/*
1706 		 * At least one per-layer BER measure was read. We can now
1707 		 * calculate the total BER
1708 		 *
1709 		 * Total Bit Error/Count is calculated as the sum of the
1710 		 * bit errors on all active layers.
1711 		 */
1712 		c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1713 		c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1714 		c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1715 		c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1716 	} else {
1717 		c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1718 		c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1719 	}
1720 
1721 	/*
1722 	 * Start showing global count if at least one error count is
1723 	 * available.
1724 	 */
1725 	if (post_ber_layers) {
1726 		/*
1727 		 * At least one per-layer BER measure was read. We can now
1728 		 * calculate the total BER
1729 		 *
1730 		 * Total Bit Error/Count is calculated as the sum of the
1731 		 * bit errors on all active layers.
1732 		 */
1733 		c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1734 		c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1735 		c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1736 		c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1737 	} else {
1738 		c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1739 		c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1740 	}
1741 
1742 	if (per_layers) {
1743 		/*
1744 		 * At least one per-layer UCB measure was read. We can now
1745 		 * calculate the total UCB
1746 		 *
1747 		 * Total block Error/Count is calculated as the sum of the
1748 		 * block errors on all active layers.
1749 		 */
1750 		c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1751 		c->block_error.stat[0].uvalue = t_block_error;
1752 		c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1753 		c->block_count.stat[0].uvalue = t_block_count;
1754 	} else {
1755 		c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1756 		c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1757 	}
1758 
1759 	return rc;
1760 }
1761 
1762 /*
1763  * The functions below are called via DVB callbacks, so they need to
1764  * properly use the I2C gate control
1765  */
1766 
1767 static int mb86a20s_initfe(struct dvb_frontend *fe)
1768 {
1769 	struct mb86a20s_state *state = fe->demodulator_priv;
1770 	u64 pll;
1771 	u32 fclk;
1772 	int rc;
1773 	u8  regD5 = 1, reg71, reg09 = 0x3a;
1774 
1775 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1776 
1777 	if (fe->ops.i2c_gate_ctrl)
1778 		fe->ops.i2c_gate_ctrl(fe, 0);
1779 
1780 	/* Initialize the frontend */
1781 	rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1782 	if (rc < 0)
1783 		goto err;
1784 
1785 	if (!state->inversion)
1786 		reg09 |= 0x04;
1787 	rc = mb86a20s_writereg(state, 0x09, reg09);
1788 	if (rc < 0)
1789 		goto err;
1790 	if (!state->bw)
1791 		reg71 = 1;
1792 	else
1793 		reg71 = 0;
1794 	rc = mb86a20s_writereg(state, 0x39, reg71);
1795 	if (rc < 0)
1796 		goto err;
1797 	rc = mb86a20s_writereg(state, 0x71, state->bw);
1798 	if (rc < 0)
1799 		goto err;
1800 	if (state->subchannel) {
1801 		rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1802 		if (rc < 0)
1803 			goto err;
1804 	}
1805 
1806 	fclk = state->config->fclk;
1807 	if (!fclk)
1808 		fclk = 32571428;
1809 
1810 	/* Adjust IF frequency to match tuner */
1811 	if (fe->ops.tuner_ops.get_if_frequency)
1812 		fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1813 
1814 	if (!state->if_freq)
1815 		state->if_freq = 3300000;
1816 
1817 	pll = (((u64)1) << 34) * state->if_freq;
1818 	do_div(pll, 63 * fclk);
1819 	pll = (1 << 25) - pll;
1820 	rc = mb86a20s_writereg(state, 0x28, 0x2a);
1821 	if (rc < 0)
1822 		goto err;
1823 	rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1824 	if (rc < 0)
1825 		goto err;
1826 	rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1827 	if (rc < 0)
1828 		goto err;
1829 	rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1830 	if (rc < 0)
1831 		goto err;
1832 	dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1833 		__func__, fclk, state->if_freq, (long long)pll);
1834 
1835 	/* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1836 	pll = state->if_freq * 1677721600L;
1837 	do_div(pll, 1628571429L);
1838 	rc = mb86a20s_writereg(state, 0x28, 0x20);
1839 	if (rc < 0)
1840 		goto err;
1841 	rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1842 	if (rc < 0)
1843 		goto err;
1844 	rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1845 	if (rc < 0)
1846 		goto err;
1847 	rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1848 	if (rc < 0)
1849 		goto err;
1850 	dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1851 		__func__, state->if_freq, (long long)pll);
1852 
1853 	if (!state->config->is_serial)
1854 		regD5 &= ~1;
1855 
1856 	rc = mb86a20s_writereg(state, 0x50, 0xd5);
1857 	if (rc < 0)
1858 		goto err;
1859 	rc = mb86a20s_writereg(state, 0x51, regD5);
1860 	if (rc < 0)
1861 		goto err;
1862 
1863 	rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1864 	if (rc < 0)
1865 		goto err;
1866 
1867 
1868 err:
1869 	if (fe->ops.i2c_gate_ctrl)
1870 		fe->ops.i2c_gate_ctrl(fe, 1);
1871 
1872 	if (rc < 0) {
1873 		state->need_init = true;
1874 		dev_info(&state->i2c->dev,
1875 			 "mb86a20s: Init failed. Will try again later\n");
1876 	} else {
1877 		state->need_init = false;
1878 		dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1879 	}
1880 	return rc;
1881 }
1882 
1883 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1884 {
1885 	struct mb86a20s_state *state = fe->demodulator_priv;
1886 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1887 	int rc, if_freq;
1888 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1889 
1890 	if (!c->isdbt_layer_enabled)
1891 		c->isdbt_layer_enabled = 7;
1892 
1893 	if (c->isdbt_layer_enabled == 1)
1894 		state->bw = MB86A20S_1SEG;
1895 	else if (c->isdbt_partial_reception)
1896 		state->bw = MB86A20S_13SEG_PARTIAL;
1897 	else
1898 		state->bw = MB86A20S_13SEG;
1899 
1900 	if (c->inversion == INVERSION_ON)
1901 		state->inversion = true;
1902 	else
1903 		state->inversion = false;
1904 
1905 	if (!c->isdbt_sb_mode) {
1906 		state->subchannel = 0;
1907 	} else {
1908 		if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1909 			c->isdbt_sb_subchannel = 0;
1910 
1911 		state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1912 	}
1913 
1914 	/*
1915 	 * Gate should already be opened, but it doesn't hurt to
1916 	 * double-check
1917 	 */
1918 	if (fe->ops.i2c_gate_ctrl)
1919 		fe->ops.i2c_gate_ctrl(fe, 1);
1920 	fe->ops.tuner_ops.set_params(fe);
1921 
1922 	if (fe->ops.tuner_ops.get_if_frequency)
1923 		fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1924 
1925 	/*
1926 	 * Make it more reliable: if, for some reason, the initial
1927 	 * device initialization doesn't happen, initialize it when
1928 	 * a SBTVD parameters are adjusted.
1929 	 *
1930 	 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1931 	 * the agc callback logic is not called during DVB attach time,
1932 	 * causing mb86a20s to not be initialized with Kworld SBTVD.
1933 	 * So, this hack is needed, in order to make Kworld SBTVD to work.
1934 	 *
1935 	 * It is also needed to change the IF after the initial init.
1936 	 *
1937 	 * HACK: Always init the frontend when set_frontend is called:
1938 	 * it was noticed that, on some devices, it fails to lock on a
1939 	 * different channel. So, it is better to reset everything, even
1940 	 * wasting some time, than to loose channel lock.
1941 	 */
1942 	mb86a20s_initfe(fe);
1943 
1944 	if (fe->ops.i2c_gate_ctrl)
1945 		fe->ops.i2c_gate_ctrl(fe, 0);
1946 
1947 	rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1948 	mb86a20s_reset_counters(fe);
1949 	mb86a20s_stats_not_ready(fe);
1950 
1951 	if (fe->ops.i2c_gate_ctrl)
1952 		fe->ops.i2c_gate_ctrl(fe, 1);
1953 
1954 	return rc;
1955 }
1956 
1957 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1958 					  fe_status_t *status)
1959 {
1960 	struct mb86a20s_state *state = fe->demodulator_priv;
1961 	int rc, status_nr;
1962 
1963 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1964 
1965 	if (fe->ops.i2c_gate_ctrl)
1966 		fe->ops.i2c_gate_ctrl(fe, 0);
1967 
1968 	/* Get lock */
1969 	status_nr = mb86a20s_read_status(fe, status);
1970 	if (status_nr < 7) {
1971 		mb86a20s_stats_not_ready(fe);
1972 		mb86a20s_reset_frontend_cache(fe);
1973 	}
1974 	if (status_nr < 0) {
1975 		dev_err(&state->i2c->dev,
1976 			"%s: Can't read frontend lock status\n", __func__);
1977 		goto error;
1978 	}
1979 
1980 	/* Get signal strength */
1981 	rc = mb86a20s_read_signal_strength(fe);
1982 	if (rc < 0) {
1983 		dev_err(&state->i2c->dev,
1984 			"%s: Can't reset VBER registers.\n", __func__);
1985 		mb86a20s_stats_not_ready(fe);
1986 		mb86a20s_reset_frontend_cache(fe);
1987 
1988 		rc = 0;		/* Status is OK */
1989 		goto error;
1990 	}
1991 
1992 	if (status_nr >= 7) {
1993 		/* Get TMCC info*/
1994 		rc = mb86a20s_get_frontend(fe);
1995 		if (rc < 0) {
1996 			dev_err(&state->i2c->dev,
1997 				"%s: Can't get FE TMCC data.\n", __func__);
1998 			rc = 0;		/* Status is OK */
1999 			goto error;
2000 		}
2001 
2002 		/* Get statistics */
2003 		rc = mb86a20s_get_stats(fe, status_nr);
2004 		if (rc < 0 && rc != -EBUSY) {
2005 			dev_err(&state->i2c->dev,
2006 				"%s: Can't get FE statistics.\n", __func__);
2007 			rc = 0;
2008 			goto error;
2009 		}
2010 		rc = 0;	/* Don't return EBUSY to userspace */
2011 	}
2012 	goto ok;
2013 
2014 error:
2015 	mb86a20s_stats_not_ready(fe);
2016 
2017 ok:
2018 	if (fe->ops.i2c_gate_ctrl)
2019 		fe->ops.i2c_gate_ctrl(fe, 1);
2020 
2021 	return rc;
2022 }
2023 
2024 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2025 						    u16 *strength)
2026 {
2027 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2028 
2029 
2030 	*strength = c->strength.stat[0].uvalue;
2031 
2032 	return 0;
2033 }
2034 
2035 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2036 {
2037 	/*
2038 	 * get_frontend is now handled together with other stats
2039 	 * retrival, when read_status() is called, as some statistics
2040 	 * will depend on the layers detection.
2041 	 */
2042 	return 0;
2043 };
2044 
2045 static int mb86a20s_tune(struct dvb_frontend *fe,
2046 			bool re_tune,
2047 			unsigned int mode_flags,
2048 			unsigned int *delay,
2049 			fe_status_t *status)
2050 {
2051 	struct mb86a20s_state *state = fe->demodulator_priv;
2052 	int rc = 0;
2053 
2054 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2055 
2056 	if (re_tune)
2057 		rc = mb86a20s_set_frontend(fe);
2058 
2059 	if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2060 		mb86a20s_read_status_and_stats(fe, status);
2061 
2062 	return rc;
2063 }
2064 
2065 static void mb86a20s_release(struct dvb_frontend *fe)
2066 {
2067 	struct mb86a20s_state *state = fe->demodulator_priv;
2068 
2069 	dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2070 
2071 	kfree(state);
2072 }
2073 
2074 static struct dvb_frontend_ops mb86a20s_ops;
2075 
2076 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2077 				    struct i2c_adapter *i2c)
2078 {
2079 	struct mb86a20s_state *state;
2080 	u8	rev;
2081 
2082 	dev_dbg(&i2c->dev, "%s called.\n", __func__);
2083 
2084 	/* allocate memory for the internal state */
2085 	state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
2086 	if (state == NULL) {
2087 		dev_err(&i2c->dev,
2088 			"%s: unable to allocate memory for state\n", __func__);
2089 		goto error;
2090 	}
2091 
2092 	/* setup the state */
2093 	state->config = config;
2094 	state->i2c = i2c;
2095 
2096 	/* create dvb_frontend */
2097 	memcpy(&state->frontend.ops, &mb86a20s_ops,
2098 		sizeof(struct dvb_frontend_ops));
2099 	state->frontend.demodulator_priv = state;
2100 
2101 	/* Check if it is a mb86a20s frontend */
2102 	rev = mb86a20s_readreg(state, 0);
2103 
2104 	if (rev == 0x13) {
2105 		dev_info(&i2c->dev,
2106 			 "Detected a Fujitsu mb86a20s frontend\n");
2107 	} else {
2108 		dev_dbg(&i2c->dev,
2109 			"Frontend revision %d is unknown - aborting.\n",
2110 		       rev);
2111 		goto error;
2112 	}
2113 
2114 	return &state->frontend;
2115 
2116 error:
2117 	kfree(state);
2118 	return NULL;
2119 }
2120 EXPORT_SYMBOL(mb86a20s_attach);
2121 
2122 static struct dvb_frontend_ops mb86a20s_ops = {
2123 	.delsys = { SYS_ISDBT },
2124 	/* Use dib8000 values per default */
2125 	.info = {
2126 		.name = "Fujitsu mb86A20s",
2127 		.caps = FE_CAN_RECOVER  |
2128 			FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2129 			FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2130 			FE_CAN_QPSK     | FE_CAN_QAM_16  | FE_CAN_QAM_64 |
2131 			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2132 			FE_CAN_GUARD_INTERVAL_AUTO    | FE_CAN_HIERARCHY_AUTO,
2133 		/* Actually, those values depend on the used tuner */
2134 		.frequency_min = 45000000,
2135 		.frequency_max = 864000000,
2136 		.frequency_stepsize = 62500,
2137 	},
2138 
2139 	.release = mb86a20s_release,
2140 
2141 	.init = mb86a20s_initfe,
2142 	.set_frontend = mb86a20s_set_frontend,
2143 	.get_frontend = mb86a20s_get_frontend_dummy,
2144 	.read_status = mb86a20s_read_status_and_stats,
2145 	.read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2146 	.tune = mb86a20s_tune,
2147 };
2148 
2149 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2150 MODULE_AUTHOR("Mauro Carvalho Chehab");
2151 MODULE_LICENSE("GPL");
2152