1 /* 2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver 3 * 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com> 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <asm/div64.h> 19 20 #include "dvb_frontend.h" 21 #include "mb86a20s.h" 22 23 #define NUM_LAYERS 3 24 25 static int debug = 1; 26 module_param(debug, int, 0644); 27 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 28 29 enum mb86a20s_bandwidth { 30 MB86A20S_13SEG = 0, 31 MB86A20S_13SEG_PARTIAL = 1, 32 MB86A20S_1SEG = 2, 33 MB86A20S_3SEG = 3, 34 }; 35 36 u8 mb86a20s_subchannel[] = { 37 0xb0, 0xc0, 0xd0, 0xe0, 38 0xf0, 0x00, 0x10, 0x20, 39 }; 40 41 struct mb86a20s_state { 42 struct i2c_adapter *i2c; 43 const struct mb86a20s_config *config; 44 u32 last_frequency; 45 46 struct dvb_frontend frontend; 47 48 u32 if_freq; 49 enum mb86a20s_bandwidth bw; 50 bool inversion; 51 u32 subchannel; 52 53 u32 estimated_rate[NUM_LAYERS]; 54 unsigned long get_strength_time; 55 56 bool need_init; 57 }; 58 59 struct regdata { 60 u8 reg; 61 u8 data; 62 }; 63 64 #define BER_SAMPLING_RATE 1 /* Seconds */ 65 66 /* 67 * Initialization sequence: Use whatevere default values that PV SBTVD 68 * does on its initialisation, obtained via USB snoop 69 */ 70 static struct regdata mb86a20s_init1[] = { 71 { 0x70, 0x0f }, 72 { 0x70, 0xff }, 73 { 0x08, 0x01 }, 74 { 0x50, 0xd1 }, { 0x51, 0x20 }, 75 }; 76 77 static struct regdata mb86a20s_init2[] = { 78 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, 79 { 0x3b, 0x21 }, 80 { 0x3c, 0x38 }, 81 { 0x01, 0x0d }, 82 { 0x04, 0x08 }, { 0x05, 0x03 }, 83 { 0x04, 0x0e }, { 0x05, 0x00 }, 84 { 0x04, 0x0f }, { 0x05, 0x37 }, 85 { 0x04, 0x0b }, { 0x05, 0x78 }, 86 { 0x04, 0x00 }, { 0x05, 0x00 }, 87 { 0x04, 0x01 }, { 0x05, 0x1e }, 88 { 0x04, 0x02 }, { 0x05, 0x07 }, 89 { 0x04, 0x03 }, { 0x05, 0xd0 }, 90 { 0x04, 0x09 }, { 0x05, 0x00 }, 91 { 0x04, 0x0a }, { 0x05, 0xff }, 92 { 0x04, 0x27 }, { 0x05, 0x00 }, 93 { 0x04, 0x28 }, { 0x05, 0x00 }, 94 { 0x04, 0x1e }, { 0x05, 0x00 }, 95 { 0x04, 0x29 }, { 0x05, 0x64 }, 96 { 0x04, 0x32 }, { 0x05, 0x02 }, 97 { 0x04, 0x14 }, { 0x05, 0x02 }, 98 { 0x04, 0x04 }, { 0x05, 0x00 }, 99 { 0x04, 0x05 }, { 0x05, 0x22 }, 100 { 0x04, 0x06 }, { 0x05, 0x0e }, 101 { 0x04, 0x07 }, { 0x05, 0xd8 }, 102 { 0x04, 0x12 }, { 0x05, 0x00 }, 103 { 0x04, 0x13 }, { 0x05, 0xff }, 104 { 0x04, 0x15 }, { 0x05, 0x4e }, 105 { 0x04, 0x16 }, { 0x05, 0x20 }, 106 107 /* 108 * On this demod, when the bit count reaches the count below, 109 * it collects the bit error count. The bit counters are initialized 110 * to 65535 here. This warrants that all of them will be quickly 111 * calculated when device gets locked. As TMCC is parsed, the values 112 * will be adjusted later in the driver's code. 113 */ 114 { 0x52, 0x01 }, /* Turn on BER before Viterbi */ 115 { 0x50, 0xa7 }, { 0x51, 0x00 }, 116 { 0x50, 0xa8 }, { 0x51, 0xff }, 117 { 0x50, 0xa9 }, { 0x51, 0xff }, 118 { 0x50, 0xaa }, { 0x51, 0x00 }, 119 { 0x50, 0xab }, { 0x51, 0xff }, 120 { 0x50, 0xac }, { 0x51, 0xff }, 121 { 0x50, 0xad }, { 0x51, 0x00 }, 122 { 0x50, 0xae }, { 0x51, 0xff }, 123 { 0x50, 0xaf }, { 0x51, 0xff }, 124 125 /* 126 * On this demod, post BER counts blocks. When the count reaches the 127 * value below, it collects the block error count. The block counters 128 * are initialized to 127 here. This warrants that all of them will be 129 * quickly calculated when device gets locked. As TMCC is parsed, the 130 * values will be adjusted later in the driver's code. 131 */ 132 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */ 133 { 0x50, 0xdc }, { 0x51, 0x00 }, 134 { 0x50, 0xdd }, { 0x51, 0x7f }, 135 { 0x50, 0xde }, { 0x51, 0x00 }, 136 { 0x50, 0xdf }, { 0x51, 0x7f }, 137 { 0x50, 0xe0 }, { 0x51, 0x00 }, 138 { 0x50, 0xe1 }, { 0x51, 0x7f }, 139 140 /* 141 * On this demod, when the block count reaches the count below, 142 * it collects the block error count. The block counters are initialized 143 * to 127 here. This warrants that all of them will be quickly 144 * calculated when device gets locked. As TMCC is parsed, the values 145 * will be adjusted later in the driver's code. 146 */ 147 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */ 148 { 0x50, 0xb2 }, { 0x51, 0x00 }, 149 { 0x50, 0xb3 }, { 0x51, 0x7f }, 150 { 0x50, 0xb4 }, { 0x51, 0x00 }, 151 { 0x50, 0xb5 }, { 0x51, 0x7f }, 152 { 0x50, 0xb6 }, { 0x51, 0x00 }, 153 { 0x50, 0xb7 }, { 0x51, 0x7f }, 154 155 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */ 156 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ 157 { 0x45, 0x04 }, /* CN symbol 4 */ 158 { 0x48, 0x04 }, /* CN manual mode */ 159 160 { 0x50, 0xd6 }, { 0x51, 0x1f }, 161 { 0x50, 0xd2 }, { 0x51, 0x03 }, 162 { 0x50, 0xd7 }, { 0x51, 0xbf }, 163 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff }, 164 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c }, 165 166 { 0x04, 0x40 }, { 0x05, 0x00 }, 167 { 0x28, 0x00 }, { 0x2b, 0x08 }, 168 { 0x28, 0x05 }, { 0x2b, 0x00 }, 169 { 0x1c, 0x01 }, 170 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f }, 171 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 }, 172 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 }, 173 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 }, 174 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 }, 175 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, 176 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 }, 177 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 }, 178 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b }, 179 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 }, 180 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d }, 181 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 }, 182 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b }, 183 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 184 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 }, 185 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 }, 186 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 }, 187 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, 188 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, 189 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef }, 190 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 }, 191 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 }, 192 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d }, 193 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 }, 194 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba }, 195 { 0x50, 0x1e }, { 0x51, 0x5d }, 196 { 0x50, 0x22 }, { 0x51, 0x00 }, 197 { 0x50, 0x23 }, { 0x51, 0xc8 }, 198 { 0x50, 0x24 }, { 0x51, 0x00 }, 199 { 0x50, 0x25 }, { 0x51, 0xf0 }, 200 { 0x50, 0x26 }, { 0x51, 0x00 }, 201 { 0x50, 0x27 }, { 0x51, 0xc3 }, 202 { 0x50, 0x39 }, { 0x51, 0x02 }, 203 { 0xec, 0x0f }, 204 { 0xeb, 0x1f }, 205 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 206 { 0xd0, 0x00 }, 207 }; 208 209 static struct regdata mb86a20s_reset_reception[] = { 210 { 0x70, 0xf0 }, 211 { 0x70, 0xff }, 212 { 0x08, 0x01 }, 213 { 0x08, 0x00 }, 214 }; 215 216 static struct regdata mb86a20s_per_ber_reset[] = { 217 { 0x53, 0x00 }, /* pre BER Counter reset */ 218 { 0x53, 0x07 }, 219 220 { 0x5f, 0x00 }, /* post BER Counter reset */ 221 { 0x5f, 0x07 }, 222 223 { 0x50, 0xb1 }, /* PER Counter reset */ 224 { 0x51, 0x07 }, 225 { 0x51, 0x00 }, 226 }; 227 228 /* 229 * I2C read/write functions and macros 230 */ 231 232 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, 233 u8 i2c_addr, u8 reg, u8 data) 234 { 235 u8 buf[] = { reg, data }; 236 struct i2c_msg msg = { 237 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 238 }; 239 int rc; 240 241 rc = i2c_transfer(state->i2c, &msg, 1); 242 if (rc != 1) { 243 dev_err(&state->i2c->dev, 244 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", 245 __func__, rc, reg, data); 246 return rc; 247 } 248 249 return 0; 250 } 251 252 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, 253 u8 i2c_addr, struct regdata *rd, int size) 254 { 255 int i, rc; 256 257 for (i = 0; i < size; i++) { 258 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, 259 rd[i].data); 260 if (rc < 0) 261 return rc; 262 } 263 return 0; 264 } 265 266 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, 267 u8 i2c_addr, u8 reg) 268 { 269 u8 val; 270 int rc; 271 struct i2c_msg msg[] = { 272 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 273 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } 274 }; 275 276 rc = i2c_transfer(state->i2c, msg, 2); 277 278 if (rc != 2) { 279 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", 280 __func__, reg, rc); 281 return (rc < 0) ? rc : -EIO; 282 } 283 284 return val; 285 } 286 287 #define mb86a20s_readreg(state, reg) \ 288 mb86a20s_i2c_readreg(state, state->config->demod_address, reg) 289 #define mb86a20s_writereg(state, reg, val) \ 290 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) 291 #define mb86a20s_writeregdata(state, regdata) \ 292 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ 293 regdata, ARRAY_SIZE(regdata)) 294 295 /* 296 * Ancillary internal routines (likely compiled inlined) 297 * 298 * The functions below assume that gateway lock has already obtained 299 */ 300 301 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status) 302 { 303 struct mb86a20s_state *state = fe->demodulator_priv; 304 int val; 305 306 *status = 0; 307 308 val = mb86a20s_readreg(state, 0x0a) & 0xf; 309 if (val < 0) 310 return val; 311 312 if (val >= 2) 313 *status |= FE_HAS_SIGNAL; 314 315 if (val >= 4) 316 *status |= FE_HAS_CARRIER; 317 318 if (val >= 5) 319 *status |= FE_HAS_VITERBI; 320 321 if (val >= 7) 322 *status |= FE_HAS_SYNC; 323 324 if (val >= 8) /* Maybe 9? */ 325 *status |= FE_HAS_LOCK; 326 327 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", 328 __func__, *status, val); 329 330 return val; 331 } 332 333 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) 334 { 335 struct mb86a20s_state *state = fe->demodulator_priv; 336 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 337 int rc; 338 unsigned rf_max, rf_min, rf; 339 340 if (state->get_strength_time && 341 (!time_after(jiffies, state->get_strength_time))) 342 return c->strength.stat[0].uvalue; 343 344 /* Reset its value if an error happen */ 345 c->strength.stat[0].uvalue = 0; 346 347 /* Does a binary search to get RF strength */ 348 rf_max = 0xfff; 349 rf_min = 0; 350 do { 351 rf = (rf_max + rf_min) / 2; 352 rc = mb86a20s_writereg(state, 0x04, 0x1f); 353 if (rc < 0) 354 return rc; 355 rc = mb86a20s_writereg(state, 0x05, rf >> 8); 356 if (rc < 0) 357 return rc; 358 rc = mb86a20s_writereg(state, 0x04, 0x20); 359 if (rc < 0) 360 return rc; 361 rc = mb86a20s_writereg(state, 0x05, rf); 362 if (rc < 0) 363 return rc; 364 365 rc = mb86a20s_readreg(state, 0x02); 366 if (rc < 0) 367 return rc; 368 if (rc & 0x08) 369 rf_min = (rf_max + rf_min) / 2; 370 else 371 rf_max = (rf_max + rf_min) / 2; 372 if (rf_max - rf_min < 4) { 373 rf = (rf_max + rf_min) / 2; 374 375 /* Rescale it from 2^12 (4096) to 2^16 */ 376 rf = rf << (16 - 12); 377 if (rf) 378 rf |= (1 << 12) - 1; 379 380 dev_dbg(&state->i2c->dev, 381 "%s: signal strength = %d (%d < RF=%d < %d)\n", 382 __func__, rf, rf_min, rf >> 4, rf_max); 383 c->strength.stat[0].uvalue = rf; 384 state->get_strength_time = jiffies + 385 msecs_to_jiffies(1000); 386 return 0; 387 } 388 } while (1); 389 } 390 391 static int mb86a20s_get_modulation(struct mb86a20s_state *state, 392 unsigned layer) 393 { 394 int rc; 395 static unsigned char reg[] = { 396 [0] = 0x86, /* Layer A */ 397 [1] = 0x8a, /* Layer B */ 398 [2] = 0x8e, /* Layer C */ 399 }; 400 401 if (layer >= ARRAY_SIZE(reg)) 402 return -EINVAL; 403 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 404 if (rc < 0) 405 return rc; 406 rc = mb86a20s_readreg(state, 0x6e); 407 if (rc < 0) 408 return rc; 409 switch ((rc >> 4) & 0x07) { 410 case 0: 411 return DQPSK; 412 case 1: 413 return QPSK; 414 case 2: 415 return QAM_16; 416 case 3: 417 return QAM_64; 418 default: 419 return QAM_AUTO; 420 } 421 } 422 423 static int mb86a20s_get_fec(struct mb86a20s_state *state, 424 unsigned layer) 425 { 426 int rc; 427 428 static unsigned char reg[] = { 429 [0] = 0x87, /* Layer A */ 430 [1] = 0x8b, /* Layer B */ 431 [2] = 0x8f, /* Layer C */ 432 }; 433 434 if (layer >= ARRAY_SIZE(reg)) 435 return -EINVAL; 436 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 437 if (rc < 0) 438 return rc; 439 rc = mb86a20s_readreg(state, 0x6e); 440 if (rc < 0) 441 return rc; 442 switch ((rc >> 4) & 0x07) { 443 case 0: 444 return FEC_1_2; 445 case 1: 446 return FEC_2_3; 447 case 2: 448 return FEC_3_4; 449 case 3: 450 return FEC_5_6; 451 case 4: 452 return FEC_7_8; 453 default: 454 return FEC_AUTO; 455 } 456 } 457 458 static int mb86a20s_get_interleaving(struct mb86a20s_state *state, 459 unsigned layer) 460 { 461 int rc; 462 463 static unsigned char reg[] = { 464 [0] = 0x88, /* Layer A */ 465 [1] = 0x8c, /* Layer B */ 466 [2] = 0x90, /* Layer C */ 467 }; 468 469 if (layer >= ARRAY_SIZE(reg)) 470 return -EINVAL; 471 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 472 if (rc < 0) 473 return rc; 474 rc = mb86a20s_readreg(state, 0x6e); 475 if (rc < 0) 476 return rc; 477 478 switch ((rc >> 4) & 0x07) { 479 case 1: 480 return GUARD_INTERVAL_1_4; 481 case 2: 482 return GUARD_INTERVAL_1_8; 483 case 3: 484 return GUARD_INTERVAL_1_16; 485 case 4: 486 return GUARD_INTERVAL_1_32; 487 488 default: 489 case 0: 490 return GUARD_INTERVAL_AUTO; 491 } 492 } 493 494 static int mb86a20s_get_segment_count(struct mb86a20s_state *state, 495 unsigned layer) 496 { 497 int rc, count; 498 static unsigned char reg[] = { 499 [0] = 0x89, /* Layer A */ 500 [1] = 0x8d, /* Layer B */ 501 [2] = 0x91, /* Layer C */ 502 }; 503 504 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 505 506 if (layer >= ARRAY_SIZE(reg)) 507 return -EINVAL; 508 509 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 510 if (rc < 0) 511 return rc; 512 rc = mb86a20s_readreg(state, 0x6e); 513 if (rc < 0) 514 return rc; 515 count = (rc >> 4) & 0x0f; 516 517 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); 518 519 return count; 520 } 521 522 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) 523 { 524 struct mb86a20s_state *state = fe->demodulator_priv; 525 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 526 527 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 528 529 /* Fixed parameters */ 530 c->delivery_system = SYS_ISDBT; 531 c->bandwidth_hz = 6000000; 532 533 /* Initialize values that will be later autodetected */ 534 c->isdbt_layer_enabled = 0; 535 c->transmission_mode = TRANSMISSION_MODE_AUTO; 536 c->guard_interval = GUARD_INTERVAL_AUTO; 537 c->isdbt_sb_mode = 0; 538 c->isdbt_sb_segment_count = 0; 539 } 540 541 /* 542 * Estimates the bit rate using the per-segment bit rate given by 543 * ABNT/NBR 15601 spec (table 4). 544 */ 545 static u32 isdbt_rate[3][5][4] = { 546 { /* DQPSK/QPSK */ 547 { 280850, 312060, 330420, 340430 }, /* 1/2 */ 548 { 374470, 416080, 440560, 453910 }, /* 2/3 */ 549 { 421280, 468090, 495630, 510650 }, /* 3/4 */ 550 { 468090, 520100, 550700, 567390 }, /* 5/6 */ 551 { 491500, 546110, 578230, 595760 }, /* 7/8 */ 552 }, { /* QAM16 */ 553 { 561710, 624130, 660840, 680870 }, /* 1/2 */ 554 { 748950, 832170, 881120, 907820 }, /* 2/3 */ 555 { 842570, 936190, 991260, 1021300 }, /* 3/4 */ 556 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ 557 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ 558 }, { /* QAM64 */ 559 { 842570, 936190, 991260, 1021300 }, /* 1/2 */ 560 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ 561 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ 562 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ 563 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ 564 } 565 }; 566 567 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, 568 u32 modulation, u32 forward_error_correction, 569 u32 interleaving, 570 u32 segment) 571 { 572 struct mb86a20s_state *state = fe->demodulator_priv; 573 u32 rate; 574 int mod, fec, guard; 575 576 /* 577 * If modulation/fec/interleaving is not detected, the default is 578 * to consider the lowest bit rate, to avoid taking too long time 579 * to get BER. 580 */ 581 switch (modulation) { 582 case DQPSK: 583 case QPSK: 584 default: 585 mod = 0; 586 break; 587 case QAM_16: 588 mod = 1; 589 break; 590 case QAM_64: 591 mod = 2; 592 break; 593 } 594 595 switch (forward_error_correction) { 596 default: 597 case FEC_1_2: 598 case FEC_AUTO: 599 fec = 0; 600 break; 601 case FEC_2_3: 602 fec = 1; 603 break; 604 case FEC_3_4: 605 fec = 2; 606 break; 607 case FEC_5_6: 608 fec = 3; 609 break; 610 case FEC_7_8: 611 fec = 4; 612 break; 613 } 614 615 switch (interleaving) { 616 default: 617 case GUARD_INTERVAL_1_4: 618 guard = 0; 619 break; 620 case GUARD_INTERVAL_1_8: 621 guard = 1; 622 break; 623 case GUARD_INTERVAL_1_16: 624 guard = 2; 625 break; 626 case GUARD_INTERVAL_1_32: 627 guard = 3; 628 break; 629 } 630 631 /* Samples BER at BER_SAMPLING_RATE seconds */ 632 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE; 633 634 /* Avoids sampling too quickly or to overflow the register */ 635 if (rate < 256) 636 rate = 256; 637 else if (rate > (1 << 24) - 1) 638 rate = (1 << 24) - 1; 639 640 dev_dbg(&state->i2c->dev, 641 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", 642 __func__, 'A' + layer, 643 segment * isdbt_rate[mod][fec][guard]/1000, 644 rate, rate); 645 646 state->estimated_rate[layer] = rate; 647 } 648 649 static int mb86a20s_get_frontend(struct dvb_frontend *fe) 650 { 651 struct mb86a20s_state *state = fe->demodulator_priv; 652 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 653 int layer, rc; 654 655 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 656 657 /* Reset frontend cache to default values */ 658 mb86a20s_reset_frontend_cache(fe); 659 660 /* Check for partial reception */ 661 rc = mb86a20s_writereg(state, 0x6d, 0x85); 662 if (rc < 0) 663 return rc; 664 rc = mb86a20s_readreg(state, 0x6e); 665 if (rc < 0) 666 return rc; 667 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; 668 669 /* Get per-layer data */ 670 671 for (layer = 0; layer < NUM_LAYERS; layer++) { 672 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", 673 __func__, 'A' + layer); 674 675 rc = mb86a20s_get_segment_count(state, layer); 676 if (rc < 0) 677 goto noperlayer_error; 678 if (rc >= 0 && rc < 14) { 679 c->layer[layer].segment_count = rc; 680 } else { 681 c->layer[layer].segment_count = 0; 682 state->estimated_rate[layer] = 0; 683 continue; 684 } 685 c->isdbt_layer_enabled |= 1 << layer; 686 rc = mb86a20s_get_modulation(state, layer); 687 if (rc < 0) 688 goto noperlayer_error; 689 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", 690 __func__, rc); 691 c->layer[layer].modulation = rc; 692 rc = mb86a20s_get_fec(state, layer); 693 if (rc < 0) 694 goto noperlayer_error; 695 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", 696 __func__, rc); 697 c->layer[layer].fec = rc; 698 rc = mb86a20s_get_interleaving(state, layer); 699 if (rc < 0) 700 goto noperlayer_error; 701 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", 702 __func__, rc); 703 c->layer[layer].interleaving = rc; 704 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation, 705 c->layer[layer].fec, 706 c->layer[layer].interleaving, 707 c->layer[layer].segment_count); 708 } 709 710 rc = mb86a20s_writereg(state, 0x6d, 0x84); 711 if (rc < 0) 712 return rc; 713 if ((rc & 0x60) == 0x20) { 714 c->isdbt_sb_mode = 1; 715 /* At least, one segment should exist */ 716 if (!c->isdbt_sb_segment_count) 717 c->isdbt_sb_segment_count = 1; 718 } 719 720 /* Get transmission mode and guard interval */ 721 rc = mb86a20s_readreg(state, 0x07); 722 if (rc < 0) 723 return rc; 724 if ((rc & 0x60) == 0x20) { 725 switch (rc & 0x0c >> 2) { 726 case 0: 727 c->transmission_mode = TRANSMISSION_MODE_2K; 728 break; 729 case 1: 730 c->transmission_mode = TRANSMISSION_MODE_4K; 731 break; 732 case 2: 733 c->transmission_mode = TRANSMISSION_MODE_8K; 734 break; 735 } 736 } 737 if (!(rc & 0x10)) { 738 switch (rc & 0x3) { 739 case 0: 740 c->guard_interval = GUARD_INTERVAL_1_4; 741 break; 742 case 1: 743 c->guard_interval = GUARD_INTERVAL_1_8; 744 break; 745 case 2: 746 c->guard_interval = GUARD_INTERVAL_1_16; 747 break; 748 } 749 } 750 return 0; 751 752 noperlayer_error: 753 754 /* per-layer info is incomplete; discard all per-layer */ 755 c->isdbt_layer_enabled = 0; 756 757 return rc; 758 } 759 760 static int mb86a20s_reset_counters(struct dvb_frontend *fe) 761 { 762 struct mb86a20s_state *state = fe->demodulator_priv; 763 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 764 int rc, val; 765 766 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 767 768 /* Reset the counters, if the channel changed */ 769 if (state->last_frequency != c->frequency) { 770 memset(&c->cnr, 0, sizeof(c->cnr)); 771 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); 772 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); 773 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 774 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 775 memset(&c->block_error, 0, sizeof(c->block_error)); 776 memset(&c->block_count, 0, sizeof(c->block_count)); 777 778 state->last_frequency = c->frequency; 779 } 780 781 /* Clear status for most stats */ 782 783 /* BER/PER counter reset */ 784 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); 785 if (rc < 0) 786 goto err; 787 788 /* CNR counter reset */ 789 rc = mb86a20s_readreg(state, 0x45); 790 if (rc < 0) 791 goto err; 792 val = rc; 793 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 794 if (rc < 0) 795 goto err; 796 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 797 if (rc < 0) 798 goto err; 799 800 /* MER counter reset */ 801 rc = mb86a20s_writereg(state, 0x50, 0x50); 802 if (rc < 0) 803 goto err; 804 rc = mb86a20s_readreg(state, 0x51); 805 if (rc < 0) 806 goto err; 807 val = rc; 808 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 809 if (rc < 0) 810 goto err; 811 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 812 if (rc < 0) 813 goto err; 814 815 goto ok; 816 err: 817 dev_err(&state->i2c->dev, 818 "%s: Can't reset FE statistics (error %d).\n", 819 __func__, rc); 820 ok: 821 return rc; 822 } 823 824 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe, 825 unsigned layer, 826 u32 *error, u32 *count) 827 { 828 struct mb86a20s_state *state = fe->demodulator_priv; 829 int rc, val; 830 831 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 832 833 if (layer >= NUM_LAYERS) 834 return -EINVAL; 835 836 /* Check if the BER measures are already available */ 837 rc = mb86a20s_readreg(state, 0x54); 838 if (rc < 0) 839 return rc; 840 841 /* Check if data is available for that layer */ 842 if (!(rc & (1 << layer))) { 843 dev_dbg(&state->i2c->dev, 844 "%s: preBER for layer %c is not available yet.\n", 845 __func__, 'A' + layer); 846 return -EBUSY; 847 } 848 849 /* Read Bit Error Count */ 850 rc = mb86a20s_readreg(state, 0x55 + layer * 3); 851 if (rc < 0) 852 return rc; 853 *error = rc << 16; 854 rc = mb86a20s_readreg(state, 0x56 + layer * 3); 855 if (rc < 0) 856 return rc; 857 *error |= rc << 8; 858 rc = mb86a20s_readreg(state, 0x57 + layer * 3); 859 if (rc < 0) 860 return rc; 861 *error |= rc; 862 863 dev_dbg(&state->i2c->dev, 864 "%s: bit error before Viterbi for layer %c: %d.\n", 865 __func__, 'A' + layer, *error); 866 867 /* Read Bit Count */ 868 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 869 if (rc < 0) 870 return rc; 871 rc = mb86a20s_readreg(state, 0x51); 872 if (rc < 0) 873 return rc; 874 *count = rc << 16; 875 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 876 if (rc < 0) 877 return rc; 878 rc = mb86a20s_readreg(state, 0x51); 879 if (rc < 0) 880 return rc; 881 *count |= rc << 8; 882 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 883 if (rc < 0) 884 return rc; 885 rc = mb86a20s_readreg(state, 0x51); 886 if (rc < 0) 887 return rc; 888 *count |= rc; 889 890 dev_dbg(&state->i2c->dev, 891 "%s: bit count before Viterbi for layer %c: %d.\n", 892 __func__, 'A' + layer, *count); 893 894 895 /* 896 * As we get TMCC data from the frontend, we can better estimate the 897 * BER bit counters, in order to do the BER measure during a longer 898 * time. Use those data, if available, to update the bit count 899 * measure. 900 */ 901 902 if (state->estimated_rate[layer] 903 && state->estimated_rate[layer] != *count) { 904 dev_dbg(&state->i2c->dev, 905 "%s: updating layer %c preBER counter to %d.\n", 906 __func__, 'A' + layer, state->estimated_rate[layer]); 907 908 /* Turn off BER before Viterbi */ 909 rc = mb86a20s_writereg(state, 0x52, 0x00); 910 911 /* Update counter for this layer */ 912 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 913 if (rc < 0) 914 return rc; 915 rc = mb86a20s_writereg(state, 0x51, 916 state->estimated_rate[layer] >> 16); 917 if (rc < 0) 918 return rc; 919 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 920 if (rc < 0) 921 return rc; 922 rc = mb86a20s_writereg(state, 0x51, 923 state->estimated_rate[layer] >> 8); 924 if (rc < 0) 925 return rc; 926 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 927 if (rc < 0) 928 return rc; 929 rc = mb86a20s_writereg(state, 0x51, 930 state->estimated_rate[layer]); 931 if (rc < 0) 932 return rc; 933 934 /* Turn on BER before Viterbi */ 935 rc = mb86a20s_writereg(state, 0x52, 0x01); 936 937 /* Reset all preBER counters */ 938 rc = mb86a20s_writereg(state, 0x53, 0x00); 939 if (rc < 0) 940 return rc; 941 rc = mb86a20s_writereg(state, 0x53, 0x07); 942 } else { 943 /* Reset counter to collect new data */ 944 rc = mb86a20s_readreg(state, 0x53); 945 if (rc < 0) 946 return rc; 947 val = rc; 948 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); 949 if (rc < 0) 950 return rc; 951 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); 952 } 953 954 return rc; 955 } 956 957 static int mb86a20s_get_post_ber(struct dvb_frontend *fe, 958 unsigned layer, 959 u32 *error, u32 *count) 960 { 961 struct mb86a20s_state *state = fe->demodulator_priv; 962 u32 counter, collect_rate; 963 int rc, val; 964 965 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 966 967 if (layer >= NUM_LAYERS) 968 return -EINVAL; 969 970 /* Check if the BER measures are already available */ 971 rc = mb86a20s_readreg(state, 0x60); 972 if (rc < 0) 973 return rc; 974 975 /* Check if data is available for that layer */ 976 if (!(rc & (1 << layer))) { 977 dev_dbg(&state->i2c->dev, 978 "%s: post BER for layer %c is not available yet.\n", 979 __func__, 'A' + layer); 980 return -EBUSY; 981 } 982 983 /* Read Bit Error Count */ 984 rc = mb86a20s_readreg(state, 0x64 + layer * 3); 985 if (rc < 0) 986 return rc; 987 *error = rc << 16; 988 rc = mb86a20s_readreg(state, 0x65 + layer * 3); 989 if (rc < 0) 990 return rc; 991 *error |= rc << 8; 992 rc = mb86a20s_readreg(state, 0x66 + layer * 3); 993 if (rc < 0) 994 return rc; 995 *error |= rc; 996 997 dev_dbg(&state->i2c->dev, 998 "%s: post bit error for layer %c: %d.\n", 999 __func__, 'A' + layer, *error); 1000 1001 /* Read Bit Count */ 1002 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1003 if (rc < 0) 1004 return rc; 1005 rc = mb86a20s_readreg(state, 0x51); 1006 if (rc < 0) 1007 return rc; 1008 counter = rc << 8; 1009 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1010 if (rc < 0) 1011 return rc; 1012 rc = mb86a20s_readreg(state, 0x51); 1013 if (rc < 0) 1014 return rc; 1015 counter |= rc; 1016 *count = counter * 204 * 8; 1017 1018 dev_dbg(&state->i2c->dev, 1019 "%s: post bit count for layer %c: %d.\n", 1020 __func__, 'A' + layer, *count); 1021 1022 /* 1023 * As we get TMCC data from the frontend, we can better estimate the 1024 * BER bit counters, in order to do the BER measure during a longer 1025 * time. Use those data, if available, to update the bit count 1026 * measure. 1027 */ 1028 1029 if (!state->estimated_rate[layer]) 1030 goto reset_measurement; 1031 1032 collect_rate = state->estimated_rate[layer] / 204 / 8; 1033 if (collect_rate < 32) 1034 collect_rate = 32; 1035 if (collect_rate > 65535) 1036 collect_rate = 65535; 1037 if (collect_rate != counter) { 1038 dev_dbg(&state->i2c->dev, 1039 "%s: updating postBER counter on layer %c to %d.\n", 1040 __func__, 'A' + layer, collect_rate); 1041 1042 /* Turn off BER after Viterbi */ 1043 rc = mb86a20s_writereg(state, 0x5e, 0x00); 1044 1045 /* Update counter for this layer */ 1046 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1047 if (rc < 0) 1048 return rc; 1049 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1050 if (rc < 0) 1051 return rc; 1052 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1053 if (rc < 0) 1054 return rc; 1055 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1056 if (rc < 0) 1057 return rc; 1058 1059 /* Turn on BER after Viterbi */ 1060 rc = mb86a20s_writereg(state, 0x5e, 0x07); 1061 1062 /* Reset all preBER counters */ 1063 rc = mb86a20s_writereg(state, 0x5f, 0x00); 1064 if (rc < 0) 1065 return rc; 1066 rc = mb86a20s_writereg(state, 0x5f, 0x07); 1067 1068 return rc; 1069 } 1070 1071 reset_measurement: 1072 /* Reset counter to collect new data */ 1073 rc = mb86a20s_readreg(state, 0x5f); 1074 if (rc < 0) 1075 return rc; 1076 val = rc; 1077 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); 1078 if (rc < 0) 1079 return rc; 1080 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); 1081 1082 return rc; 1083 } 1084 1085 static int mb86a20s_get_blk_error(struct dvb_frontend *fe, 1086 unsigned layer, 1087 u32 *error, u32 *count) 1088 { 1089 struct mb86a20s_state *state = fe->demodulator_priv; 1090 int rc, val; 1091 u32 collect_rate; 1092 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1093 1094 if (layer >= NUM_LAYERS) 1095 return -EINVAL; 1096 1097 /* Check if the PER measures are already available */ 1098 rc = mb86a20s_writereg(state, 0x50, 0xb8); 1099 if (rc < 0) 1100 return rc; 1101 rc = mb86a20s_readreg(state, 0x51); 1102 if (rc < 0) 1103 return rc; 1104 1105 /* Check if data is available for that layer */ 1106 1107 if (!(rc & (1 << layer))) { 1108 dev_dbg(&state->i2c->dev, 1109 "%s: block counts for layer %c aren't available yet.\n", 1110 __func__, 'A' + layer); 1111 return -EBUSY; 1112 } 1113 1114 /* Read Packet error Count */ 1115 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); 1116 if (rc < 0) 1117 return rc; 1118 rc = mb86a20s_readreg(state, 0x51); 1119 if (rc < 0) 1120 return rc; 1121 *error = rc << 8; 1122 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); 1123 if (rc < 0) 1124 return rc; 1125 rc = mb86a20s_readreg(state, 0x51); 1126 if (rc < 0) 1127 return rc; 1128 *error |= rc; 1129 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n", 1130 __func__, 'A' + layer, *error); 1131 1132 /* Read Bit Count */ 1133 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1134 if (rc < 0) 1135 return rc; 1136 rc = mb86a20s_readreg(state, 0x51); 1137 if (rc < 0) 1138 return rc; 1139 *count = rc << 8; 1140 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1141 if (rc < 0) 1142 return rc; 1143 rc = mb86a20s_readreg(state, 0x51); 1144 if (rc < 0) 1145 return rc; 1146 *count |= rc; 1147 1148 dev_dbg(&state->i2c->dev, 1149 "%s: block count for layer %c: %d.\n", 1150 __func__, 'A' + layer, *count); 1151 1152 /* 1153 * As we get TMCC data from the frontend, we can better estimate the 1154 * BER bit counters, in order to do the BER measure during a longer 1155 * time. Use those data, if available, to update the bit count 1156 * measure. 1157 */ 1158 1159 if (!state->estimated_rate[layer]) 1160 goto reset_measurement; 1161 1162 collect_rate = state->estimated_rate[layer] / 204 / 8; 1163 if (collect_rate < 32) 1164 collect_rate = 32; 1165 if (collect_rate > 65535) 1166 collect_rate = 65535; 1167 1168 if (collect_rate != *count) { 1169 dev_dbg(&state->i2c->dev, 1170 "%s: updating PER counter on layer %c to %d.\n", 1171 __func__, 'A' + layer, collect_rate); 1172 1173 /* Stop PER measurement */ 1174 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1175 if (rc < 0) 1176 return rc; 1177 rc = mb86a20s_writereg(state, 0x51, 0x00); 1178 if (rc < 0) 1179 return rc; 1180 1181 /* Update this layer's counter */ 1182 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1183 if (rc < 0) 1184 return rc; 1185 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1186 if (rc < 0) 1187 return rc; 1188 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1189 if (rc < 0) 1190 return rc; 1191 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1192 if (rc < 0) 1193 return rc; 1194 1195 /* start PER measurement */ 1196 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1197 if (rc < 0) 1198 return rc; 1199 rc = mb86a20s_writereg(state, 0x51, 0x07); 1200 if (rc < 0) 1201 return rc; 1202 1203 /* Reset all counters to collect new data */ 1204 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1205 if (rc < 0) 1206 return rc; 1207 rc = mb86a20s_writereg(state, 0x51, 0x07); 1208 if (rc < 0) 1209 return rc; 1210 rc = mb86a20s_writereg(state, 0x51, 0x00); 1211 1212 return rc; 1213 } 1214 1215 reset_measurement: 1216 /* Reset counter to collect new data */ 1217 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1218 if (rc < 0) 1219 return rc; 1220 rc = mb86a20s_readreg(state, 0x51); 1221 if (rc < 0) 1222 return rc; 1223 val = rc; 1224 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); 1225 if (rc < 0) 1226 return rc; 1227 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); 1228 1229 return rc; 1230 } 1231 1232 struct linear_segments { 1233 unsigned x, y; 1234 }; 1235 1236 /* 1237 * All tables below return a dB/1000 measurement 1238 */ 1239 1240 static struct linear_segments cnr_to_db_table[] = { 1241 { 19648, 0}, 1242 { 18187, 1000}, 1243 { 16534, 2000}, 1244 { 14823, 3000}, 1245 { 13161, 4000}, 1246 { 11622, 5000}, 1247 { 10279, 6000}, 1248 { 9089, 7000}, 1249 { 8042, 8000}, 1250 { 7137, 9000}, 1251 { 6342, 10000}, 1252 { 5641, 11000}, 1253 { 5030, 12000}, 1254 { 4474, 13000}, 1255 { 3988, 14000}, 1256 { 3556, 15000}, 1257 { 3180, 16000}, 1258 { 2841, 17000}, 1259 { 2541, 18000}, 1260 { 2276, 19000}, 1261 { 2038, 20000}, 1262 { 1800, 21000}, 1263 { 1625, 22000}, 1264 { 1462, 23000}, 1265 { 1324, 24000}, 1266 { 1175, 25000}, 1267 { 1063, 26000}, 1268 { 980, 27000}, 1269 { 907, 28000}, 1270 { 840, 29000}, 1271 { 788, 30000}, 1272 }; 1273 1274 static struct linear_segments cnr_64qam_table[] = { 1275 { 3922688, 0}, 1276 { 3920384, 1000}, 1277 { 3902720, 2000}, 1278 { 3894784, 3000}, 1279 { 3882496, 4000}, 1280 { 3872768, 5000}, 1281 { 3858944, 6000}, 1282 { 3851520, 7000}, 1283 { 3838976, 8000}, 1284 { 3829248, 9000}, 1285 { 3818240, 10000}, 1286 { 3806976, 11000}, 1287 { 3791872, 12000}, 1288 { 3767040, 13000}, 1289 { 3720960, 14000}, 1290 { 3637504, 15000}, 1291 { 3498496, 16000}, 1292 { 3296000, 17000}, 1293 { 3031040, 18000}, 1294 { 2715392, 19000}, 1295 { 2362624, 20000}, 1296 { 1963264, 21000}, 1297 { 1649664, 22000}, 1298 { 1366784, 23000}, 1299 { 1120768, 24000}, 1300 { 890880, 25000}, 1301 { 723456, 26000}, 1302 { 612096, 27000}, 1303 { 518912, 28000}, 1304 { 448256, 29000}, 1305 { 388864, 30000}, 1306 }; 1307 1308 static struct linear_segments cnr_16qam_table[] = { 1309 { 5314816, 0}, 1310 { 5219072, 1000}, 1311 { 5118720, 2000}, 1312 { 4998912, 3000}, 1313 { 4875520, 4000}, 1314 { 4736000, 5000}, 1315 { 4604160, 6000}, 1316 { 4458752, 7000}, 1317 { 4300288, 8000}, 1318 { 4092928, 9000}, 1319 { 3836160, 10000}, 1320 { 3521024, 11000}, 1321 { 3155968, 12000}, 1322 { 2756864, 13000}, 1323 { 2347008, 14000}, 1324 { 1955072, 15000}, 1325 { 1593600, 16000}, 1326 { 1297920, 17000}, 1327 { 1043968, 18000}, 1328 { 839680, 19000}, 1329 { 672256, 20000}, 1330 { 523008, 21000}, 1331 { 424704, 22000}, 1332 { 345088, 23000}, 1333 { 280064, 24000}, 1334 { 221440, 25000}, 1335 { 179712, 26000}, 1336 { 151040, 27000}, 1337 { 128512, 28000}, 1338 { 110080, 29000}, 1339 { 95744, 30000}, 1340 }; 1341 1342 struct linear_segments cnr_qpsk_table[] = { 1343 { 2834176, 0}, 1344 { 2683648, 1000}, 1345 { 2536960, 2000}, 1346 { 2391808, 3000}, 1347 { 2133248, 4000}, 1348 { 1906176, 5000}, 1349 { 1666560, 6000}, 1350 { 1422080, 7000}, 1351 { 1189632, 8000}, 1352 { 976384, 9000}, 1353 { 790272, 10000}, 1354 { 633344, 11000}, 1355 { 505600, 12000}, 1356 { 402944, 13000}, 1357 { 320768, 14000}, 1358 { 255488, 15000}, 1359 { 204032, 16000}, 1360 { 163072, 17000}, 1361 { 130304, 18000}, 1362 { 105216, 19000}, 1363 { 83456, 20000}, 1364 { 65024, 21000}, 1365 { 52480, 22000}, 1366 { 42752, 23000}, 1367 { 34560, 24000}, 1368 { 27136, 25000}, 1369 { 22016, 26000}, 1370 { 18432, 27000}, 1371 { 15616, 28000}, 1372 { 13312, 29000}, 1373 { 11520, 30000}, 1374 }; 1375 1376 static u32 interpolate_value(u32 value, struct linear_segments *segments, 1377 unsigned len) 1378 { 1379 u64 tmp64; 1380 u32 dx, dy; 1381 int i, ret; 1382 1383 if (value >= segments[0].x) 1384 return segments[0].y; 1385 if (value < segments[len-1].x) 1386 return segments[len-1].y; 1387 1388 for (i = 1; i < len - 1; i++) { 1389 /* If value is identical, no need to interpolate */ 1390 if (value == segments[i].x) 1391 return segments[i].y; 1392 if (value > segments[i].x) 1393 break; 1394 } 1395 1396 /* Linear interpolation between the two (x,y) points */ 1397 dy = segments[i].y - segments[i - 1].y; 1398 dx = segments[i - 1].x - segments[i].x; 1399 tmp64 = value - segments[i].x; 1400 tmp64 *= dy; 1401 do_div(tmp64, dx); 1402 ret = segments[i].y - tmp64; 1403 1404 return ret; 1405 } 1406 1407 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe) 1408 { 1409 struct mb86a20s_state *state = fe->demodulator_priv; 1410 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1411 u32 cnr_linear, cnr; 1412 int rc, val; 1413 1414 /* Check if CNR is available */ 1415 rc = mb86a20s_readreg(state, 0x45); 1416 if (rc < 0) 1417 return rc; 1418 1419 if (!(rc & 0x40)) { 1420 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n", 1421 __func__); 1422 return -EBUSY; 1423 } 1424 val = rc; 1425 1426 rc = mb86a20s_readreg(state, 0x46); 1427 if (rc < 0) 1428 return rc; 1429 cnr_linear = rc << 8; 1430 1431 rc = mb86a20s_readreg(state, 0x46); 1432 if (rc < 0) 1433 return rc; 1434 cnr_linear |= rc; 1435 1436 cnr = interpolate_value(cnr_linear, 1437 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table)); 1438 1439 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 1440 c->cnr.stat[0].svalue = cnr; 1441 1442 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", 1443 __func__, cnr / 1000, cnr % 1000, cnr_linear); 1444 1445 /* CNR counter reset */ 1446 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 1447 if (rc < 0) 1448 return rc; 1449 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 1450 1451 return rc; 1452 } 1453 1454 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe) 1455 { 1456 struct mb86a20s_state *state = fe->demodulator_priv; 1457 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1458 u32 mer, cnr; 1459 int rc, val, layer; 1460 struct linear_segments *segs; 1461 unsigned segs_len; 1462 1463 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1464 1465 /* Check if the measures are already available */ 1466 rc = mb86a20s_writereg(state, 0x50, 0x5b); 1467 if (rc < 0) 1468 return rc; 1469 rc = mb86a20s_readreg(state, 0x51); 1470 if (rc < 0) 1471 return rc; 1472 1473 /* Check if data is available */ 1474 if (!(rc & 0x01)) { 1475 dev_dbg(&state->i2c->dev, 1476 "%s: MER measures aren't available yet.\n", __func__); 1477 return -EBUSY; 1478 } 1479 1480 /* Read all layers */ 1481 for (layer = 0; layer < NUM_LAYERS; layer++) { 1482 if (!(c->isdbt_layer_enabled & (1 << layer))) { 1483 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1484 continue; 1485 } 1486 1487 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3); 1488 if (rc < 0) 1489 return rc; 1490 rc = mb86a20s_readreg(state, 0x51); 1491 if (rc < 0) 1492 return rc; 1493 mer = rc << 16; 1494 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3); 1495 if (rc < 0) 1496 return rc; 1497 rc = mb86a20s_readreg(state, 0x51); 1498 if (rc < 0) 1499 return rc; 1500 mer |= rc << 8; 1501 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3); 1502 if (rc < 0) 1503 return rc; 1504 rc = mb86a20s_readreg(state, 0x51); 1505 if (rc < 0) 1506 return rc; 1507 mer |= rc; 1508 1509 switch (c->layer[layer].modulation) { 1510 case DQPSK: 1511 case QPSK: 1512 segs = cnr_qpsk_table; 1513 segs_len = ARRAY_SIZE(cnr_qpsk_table); 1514 break; 1515 case QAM_16: 1516 segs = cnr_16qam_table; 1517 segs_len = ARRAY_SIZE(cnr_16qam_table); 1518 break; 1519 default: 1520 case QAM_64: 1521 segs = cnr_64qam_table; 1522 segs_len = ARRAY_SIZE(cnr_64qam_table); 1523 break; 1524 } 1525 cnr = interpolate_value(mer, segs, segs_len); 1526 1527 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL; 1528 c->cnr.stat[1 + layer].svalue = cnr; 1529 1530 dev_dbg(&state->i2c->dev, 1531 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n", 1532 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer); 1533 1534 } 1535 1536 /* Start a new MER measurement */ 1537 /* MER counter reset */ 1538 rc = mb86a20s_writereg(state, 0x50, 0x50); 1539 if (rc < 0) 1540 return rc; 1541 rc = mb86a20s_readreg(state, 0x51); 1542 if (rc < 0) 1543 return rc; 1544 val = rc; 1545 1546 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 1547 if (rc < 0) 1548 return rc; 1549 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 1550 if (rc < 0) 1551 return rc; 1552 1553 return 0; 1554 } 1555 1556 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) 1557 { 1558 struct mb86a20s_state *state = fe->demodulator_priv; 1559 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1560 int layer; 1561 1562 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1563 1564 /* Fill the length of each status counter */ 1565 1566 /* Only global stats */ 1567 c->strength.len = 1; 1568 1569 /* Per-layer stats - 3 layers + global */ 1570 c->cnr.len = NUM_LAYERS + 1; 1571 c->pre_bit_error.len = NUM_LAYERS + 1; 1572 c->pre_bit_count.len = NUM_LAYERS + 1; 1573 c->post_bit_error.len = NUM_LAYERS + 1; 1574 c->post_bit_count.len = NUM_LAYERS + 1; 1575 c->block_error.len = NUM_LAYERS + 1; 1576 c->block_count.len = NUM_LAYERS + 1; 1577 1578 /* Signal is always available */ 1579 c->strength.stat[0].scale = FE_SCALE_RELATIVE; 1580 c->strength.stat[0].uvalue = 0; 1581 1582 /* Put all of them at FE_SCALE_NOT_AVAILABLE */ 1583 for (layer = 0; layer < NUM_LAYERS + 1; layer++) { 1584 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1585 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1586 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1587 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1588 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1589 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1590 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1591 } 1592 } 1593 1594 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr) 1595 { 1596 struct mb86a20s_state *state = fe->demodulator_priv; 1597 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1598 int rc = 0, layer; 1599 u32 bit_error = 0, bit_count = 0; 1600 u32 t_pre_bit_error = 0, t_pre_bit_count = 0; 1601 u32 t_post_bit_error = 0, t_post_bit_count = 0; 1602 u32 block_error = 0, block_count = 0; 1603 u32 t_block_error = 0, t_block_count = 0; 1604 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0; 1605 int per_layers = 0; 1606 1607 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1608 1609 mb86a20s_get_main_CNR(fe); 1610 1611 /* Get per-layer stats */ 1612 mb86a20s_get_blk_error_layer_CNR(fe); 1613 1614 /* 1615 * At state 7, only CNR is available 1616 * For BER measures, state=9 is required 1617 * FIXME: we may get MER measures with state=8 1618 */ 1619 if (status_nr < 9) 1620 return 0; 1621 1622 for (layer = 0; layer < NUM_LAYERS; layer++) { 1623 if (c->isdbt_layer_enabled & (1 << layer)) { 1624 /* Layer is active and has rc segments */ 1625 active_layers++; 1626 1627 /* Handle BER before vterbi */ 1628 rc = mb86a20s_get_pre_ber(fe, layer, 1629 &bit_error, &bit_count); 1630 if (rc >= 0) { 1631 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1632 c->pre_bit_error.stat[1 + layer].uvalue += bit_error; 1633 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1634 c->pre_bit_count.stat[1 + layer].uvalue += bit_count; 1635 } else if (rc != -EBUSY) { 1636 /* 1637 * If an I/O error happened, 1638 * measures are now unavailable 1639 */ 1640 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1641 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1642 dev_err(&state->i2c->dev, 1643 "%s: Can't get BER for layer %c (error %d).\n", 1644 __func__, 'A' + layer, rc); 1645 } 1646 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1647 pre_ber_layers++; 1648 1649 /* Handle BER post vterbi */ 1650 rc = mb86a20s_get_post_ber(fe, layer, 1651 &bit_error, &bit_count); 1652 if (rc >= 0) { 1653 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1654 c->post_bit_error.stat[1 + layer].uvalue += bit_error; 1655 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1656 c->post_bit_count.stat[1 + layer].uvalue += bit_count; 1657 } else if (rc != -EBUSY) { 1658 /* 1659 * If an I/O error happened, 1660 * measures are now unavailable 1661 */ 1662 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1663 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1664 dev_err(&state->i2c->dev, 1665 "%s: Can't get BER for layer %c (error %d).\n", 1666 __func__, 'A' + layer, rc); 1667 } 1668 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1669 post_ber_layers++; 1670 1671 /* Handle Block errors for PER/UCB reports */ 1672 rc = mb86a20s_get_blk_error(fe, layer, 1673 &block_error, 1674 &block_count); 1675 if (rc >= 0) { 1676 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1677 c->block_error.stat[1 + layer].uvalue += block_error; 1678 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1679 c->block_count.stat[1 + layer].uvalue += block_count; 1680 } else if (rc != -EBUSY) { 1681 /* 1682 * If an I/O error happened, 1683 * measures are now unavailable 1684 */ 1685 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1686 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1687 dev_err(&state->i2c->dev, 1688 "%s: Can't get PER for layer %c (error %d).\n", 1689 __func__, 'A' + layer, rc); 1690 1691 } 1692 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1693 per_layers++; 1694 1695 /* Update total preBER */ 1696 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue; 1697 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue; 1698 1699 /* Update total postBER */ 1700 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue; 1701 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue; 1702 1703 /* Update total PER */ 1704 t_block_error += c->block_error.stat[1 + layer].uvalue; 1705 t_block_count += c->block_count.stat[1 + layer].uvalue; 1706 } 1707 } 1708 1709 /* 1710 * Start showing global count if at least one error count is 1711 * available. 1712 */ 1713 if (pre_ber_layers) { 1714 /* 1715 * At least one per-layer BER measure was read. We can now 1716 * calculate the total BER 1717 * 1718 * Total Bit Error/Count is calculated as the sum of the 1719 * bit errors on all active layers. 1720 */ 1721 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1722 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; 1723 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1724 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; 1725 } else { 1726 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1727 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1728 } 1729 1730 /* 1731 * Start showing global count if at least one error count is 1732 * available. 1733 */ 1734 if (post_ber_layers) { 1735 /* 1736 * At least one per-layer BER measure was read. We can now 1737 * calculate the total BER 1738 * 1739 * Total Bit Error/Count is calculated as the sum of the 1740 * bit errors on all active layers. 1741 */ 1742 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1743 c->post_bit_error.stat[0].uvalue = t_post_bit_error; 1744 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1745 c->post_bit_count.stat[0].uvalue = t_post_bit_count; 1746 } else { 1747 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1748 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1749 } 1750 1751 if (per_layers) { 1752 /* 1753 * At least one per-layer UCB measure was read. We can now 1754 * calculate the total UCB 1755 * 1756 * Total block Error/Count is calculated as the sum of the 1757 * block errors on all active layers. 1758 */ 1759 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1760 c->block_error.stat[0].uvalue = t_block_error; 1761 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1762 c->block_count.stat[0].uvalue = t_block_count; 1763 } else { 1764 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1765 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1766 } 1767 1768 return rc; 1769 } 1770 1771 /* 1772 * The functions below are called via DVB callbacks, so they need to 1773 * properly use the I2C gate control 1774 */ 1775 1776 static int mb86a20s_initfe(struct dvb_frontend *fe) 1777 { 1778 struct mb86a20s_state *state = fe->demodulator_priv; 1779 u64 pll; 1780 u32 fclk; 1781 int rc; 1782 u8 regD5 = 1, reg71, reg09 = 0x3a; 1783 1784 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1785 1786 if (fe->ops.i2c_gate_ctrl) 1787 fe->ops.i2c_gate_ctrl(fe, 0); 1788 1789 /* Initialize the frontend */ 1790 rc = mb86a20s_writeregdata(state, mb86a20s_init1); 1791 if (rc < 0) 1792 goto err; 1793 1794 if (!state->inversion) 1795 reg09 |= 0x04; 1796 rc = mb86a20s_writereg(state, 0x09, reg09); 1797 if (rc < 0) 1798 goto err; 1799 if (!state->bw) 1800 reg71 = 1; 1801 else 1802 reg71 = 0; 1803 rc = mb86a20s_writereg(state, 0x39, reg71); 1804 if (rc < 0) 1805 goto err; 1806 rc = mb86a20s_writereg(state, 0x71, state->bw); 1807 if (rc < 0) 1808 goto err; 1809 if (state->subchannel) { 1810 rc = mb86a20s_writereg(state, 0x44, state->subchannel); 1811 if (rc < 0) 1812 goto err; 1813 } 1814 1815 fclk = state->config->fclk; 1816 if (!fclk) 1817 fclk = 32571428; 1818 1819 /* Adjust IF frequency to match tuner */ 1820 if (fe->ops.tuner_ops.get_if_frequency) 1821 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq); 1822 1823 if (!state->if_freq) 1824 state->if_freq = 3300000; 1825 1826 pll = (((u64)1) << 34) * state->if_freq; 1827 do_div(pll, 63 * fclk); 1828 pll = (1 << 25) - pll; 1829 rc = mb86a20s_writereg(state, 0x28, 0x2a); 1830 if (rc < 0) 1831 goto err; 1832 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1833 if (rc < 0) 1834 goto err; 1835 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1836 if (rc < 0) 1837 goto err; 1838 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1839 if (rc < 0) 1840 goto err; 1841 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n", 1842 __func__, fclk, state->if_freq, (long long)pll); 1843 1844 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */ 1845 pll = state->if_freq * 1677721600L; 1846 do_div(pll, 1628571429L); 1847 rc = mb86a20s_writereg(state, 0x28, 0x20); 1848 if (rc < 0) 1849 goto err; 1850 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1851 if (rc < 0) 1852 goto err; 1853 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1854 if (rc < 0) 1855 goto err; 1856 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1857 if (rc < 0) 1858 goto err; 1859 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n", 1860 __func__, state->if_freq, (long long)pll); 1861 1862 if (!state->config->is_serial) 1863 regD5 &= ~1; 1864 1865 rc = mb86a20s_writereg(state, 0x50, 0xd5); 1866 if (rc < 0) 1867 goto err; 1868 rc = mb86a20s_writereg(state, 0x51, regD5); 1869 if (rc < 0) 1870 goto err; 1871 1872 rc = mb86a20s_writeregdata(state, mb86a20s_init2); 1873 if (rc < 0) 1874 goto err; 1875 1876 1877 err: 1878 if (fe->ops.i2c_gate_ctrl) 1879 fe->ops.i2c_gate_ctrl(fe, 1); 1880 1881 if (rc < 0) { 1882 state->need_init = true; 1883 dev_info(&state->i2c->dev, 1884 "mb86a20s: Init failed. Will try again later\n"); 1885 } else { 1886 state->need_init = false; 1887 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); 1888 } 1889 return rc; 1890 } 1891 1892 static int mb86a20s_set_frontend(struct dvb_frontend *fe) 1893 { 1894 struct mb86a20s_state *state = fe->demodulator_priv; 1895 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1896 int rc, if_freq; 1897 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1898 1899 if (!c->isdbt_layer_enabled) 1900 c->isdbt_layer_enabled = 7; 1901 1902 if (c->isdbt_layer_enabled == 1) 1903 state->bw = MB86A20S_1SEG; 1904 else if (c->isdbt_partial_reception) 1905 state->bw = MB86A20S_13SEG_PARTIAL; 1906 else 1907 state->bw = MB86A20S_13SEG; 1908 1909 if (c->inversion == INVERSION_ON) 1910 state->inversion = true; 1911 else 1912 state->inversion = false; 1913 1914 if (!c->isdbt_sb_mode) { 1915 state->subchannel = 0; 1916 } else { 1917 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel)) 1918 c->isdbt_sb_subchannel = 0; 1919 1920 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel]; 1921 } 1922 1923 /* 1924 * Gate should already be opened, but it doesn't hurt to 1925 * double-check 1926 */ 1927 if (fe->ops.i2c_gate_ctrl) 1928 fe->ops.i2c_gate_ctrl(fe, 1); 1929 fe->ops.tuner_ops.set_params(fe); 1930 1931 if (fe->ops.tuner_ops.get_if_frequency) 1932 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq); 1933 1934 /* 1935 * Make it more reliable: if, for some reason, the initial 1936 * device initialization doesn't happen, initialize it when 1937 * a SBTVD parameters are adjusted. 1938 * 1939 * Unfortunately, due to a hard to track bug at tda829x/tda18271, 1940 * the agc callback logic is not called during DVB attach time, 1941 * causing mb86a20s to not be initialized with Kworld SBTVD. 1942 * So, this hack is needed, in order to make Kworld SBTVD to work. 1943 * 1944 * It is also needed to change the IF after the initial init. 1945 * 1946 * HACK: Always init the frontend when set_frontend is called: 1947 * it was noticed that, on some devices, it fails to lock on a 1948 * different channel. So, it is better to reset everything, even 1949 * wasting some time, than to loose channel lock. 1950 */ 1951 mb86a20s_initfe(fe); 1952 1953 if (fe->ops.i2c_gate_ctrl) 1954 fe->ops.i2c_gate_ctrl(fe, 0); 1955 1956 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); 1957 mb86a20s_reset_counters(fe); 1958 mb86a20s_stats_not_ready(fe); 1959 1960 if (fe->ops.i2c_gate_ctrl) 1961 fe->ops.i2c_gate_ctrl(fe, 1); 1962 1963 return rc; 1964 } 1965 1966 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, 1967 fe_status_t *status) 1968 { 1969 struct mb86a20s_state *state = fe->demodulator_priv; 1970 int rc, status_nr; 1971 1972 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1973 1974 if (fe->ops.i2c_gate_ctrl) 1975 fe->ops.i2c_gate_ctrl(fe, 0); 1976 1977 /* Get lock */ 1978 status_nr = mb86a20s_read_status(fe, status); 1979 if (status_nr < 7) { 1980 mb86a20s_stats_not_ready(fe); 1981 mb86a20s_reset_frontend_cache(fe); 1982 } 1983 if (status_nr < 0) { 1984 dev_err(&state->i2c->dev, 1985 "%s: Can't read frontend lock status\n", __func__); 1986 goto error; 1987 } 1988 1989 /* Get signal strength */ 1990 rc = mb86a20s_read_signal_strength(fe); 1991 if (rc < 0) { 1992 dev_err(&state->i2c->dev, 1993 "%s: Can't reset VBER registers.\n", __func__); 1994 mb86a20s_stats_not_ready(fe); 1995 mb86a20s_reset_frontend_cache(fe); 1996 1997 rc = 0; /* Status is OK */ 1998 goto error; 1999 } 2000 2001 if (status_nr >= 7) { 2002 /* Get TMCC info*/ 2003 rc = mb86a20s_get_frontend(fe); 2004 if (rc < 0) { 2005 dev_err(&state->i2c->dev, 2006 "%s: Can't get FE TMCC data.\n", __func__); 2007 rc = 0; /* Status is OK */ 2008 goto error; 2009 } 2010 2011 /* Get statistics */ 2012 rc = mb86a20s_get_stats(fe, status_nr); 2013 if (rc < 0 && rc != -EBUSY) { 2014 dev_err(&state->i2c->dev, 2015 "%s: Can't get FE statistics.\n", __func__); 2016 rc = 0; 2017 goto error; 2018 } 2019 rc = 0; /* Don't return EBUSY to userspace */ 2020 } 2021 goto ok; 2022 2023 error: 2024 mb86a20s_stats_not_ready(fe); 2025 2026 ok: 2027 if (fe->ops.i2c_gate_ctrl) 2028 fe->ops.i2c_gate_ctrl(fe, 1); 2029 2030 return rc; 2031 } 2032 2033 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, 2034 u16 *strength) 2035 { 2036 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 2037 2038 2039 *strength = c->strength.stat[0].uvalue; 2040 2041 return 0; 2042 } 2043 2044 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe) 2045 { 2046 /* 2047 * get_frontend is now handled together with other stats 2048 * retrival, when read_status() is called, as some statistics 2049 * will depend on the layers detection. 2050 */ 2051 return 0; 2052 }; 2053 2054 static int mb86a20s_tune(struct dvb_frontend *fe, 2055 bool re_tune, 2056 unsigned int mode_flags, 2057 unsigned int *delay, 2058 fe_status_t *status) 2059 { 2060 struct mb86a20s_state *state = fe->demodulator_priv; 2061 int rc = 0; 2062 2063 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 2064 2065 if (re_tune) 2066 rc = mb86a20s_set_frontend(fe); 2067 2068 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 2069 mb86a20s_read_status_and_stats(fe, status); 2070 2071 return rc; 2072 } 2073 2074 static void mb86a20s_release(struct dvb_frontend *fe) 2075 { 2076 struct mb86a20s_state *state = fe->demodulator_priv; 2077 2078 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 2079 2080 kfree(state); 2081 } 2082 2083 static struct dvb_frontend_ops mb86a20s_ops; 2084 2085 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, 2086 struct i2c_adapter *i2c) 2087 { 2088 struct mb86a20s_state *state; 2089 u8 rev; 2090 2091 dev_dbg(&i2c->dev, "%s called.\n", __func__); 2092 2093 /* allocate memory for the internal state */ 2094 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); 2095 if (state == NULL) { 2096 dev_err(&i2c->dev, 2097 "%s: unable to allocate memory for state\n", __func__); 2098 goto error; 2099 } 2100 2101 /* setup the state */ 2102 state->config = config; 2103 state->i2c = i2c; 2104 2105 /* create dvb_frontend */ 2106 memcpy(&state->frontend.ops, &mb86a20s_ops, 2107 sizeof(struct dvb_frontend_ops)); 2108 state->frontend.demodulator_priv = state; 2109 2110 /* Check if it is a mb86a20s frontend */ 2111 rev = mb86a20s_readreg(state, 0); 2112 2113 if (rev == 0x13) { 2114 dev_info(&i2c->dev, 2115 "Detected a Fujitsu mb86a20s frontend\n"); 2116 } else { 2117 dev_dbg(&i2c->dev, 2118 "Frontend revision %d is unknown - aborting.\n", 2119 rev); 2120 goto error; 2121 } 2122 2123 return &state->frontend; 2124 2125 error: 2126 kfree(state); 2127 return NULL; 2128 } 2129 EXPORT_SYMBOL(mb86a20s_attach); 2130 2131 static struct dvb_frontend_ops mb86a20s_ops = { 2132 .delsys = { SYS_ISDBT }, 2133 /* Use dib8000 values per default */ 2134 .info = { 2135 .name = "Fujitsu mb86A20s", 2136 .caps = FE_CAN_RECOVER | 2137 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 2138 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 2139 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2140 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | 2141 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 2142 /* Actually, those values depend on the used tuner */ 2143 .frequency_min = 45000000, 2144 .frequency_max = 864000000, 2145 .frequency_stepsize = 62500, 2146 }, 2147 2148 .release = mb86a20s_release, 2149 2150 .init = mb86a20s_initfe, 2151 .set_frontend = mb86a20s_set_frontend, 2152 .get_frontend = mb86a20s_get_frontend_dummy, 2153 .read_status = mb86a20s_read_status_and_stats, 2154 .read_signal_strength = mb86a20s_read_signal_strength_from_cache, 2155 .tune = mb86a20s_tune, 2156 }; 2157 2158 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); 2159 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 2160 MODULE_LICENSE("GPL"); 2161