1 /* 2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver 3 * 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com> 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <asm/div64.h> 19 20 #include "dvb_frontend.h" 21 #include "mb86a20s.h" 22 23 static int debug = 1; 24 module_param(debug, int, 0644); 25 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 26 27 struct mb86a20s_state { 28 struct i2c_adapter *i2c; 29 const struct mb86a20s_config *config; 30 u32 last_frequency; 31 32 struct dvb_frontend frontend; 33 34 u32 estimated_rate[3]; 35 36 bool need_init; 37 }; 38 39 struct regdata { 40 u8 reg; 41 u8 data; 42 }; 43 44 #define BER_SAMPLING_RATE 1 /* Seconds */ 45 46 /* 47 * Initialization sequence: Use whatevere default values that PV SBTVD 48 * does on its initialisation, obtained via USB snoop 49 */ 50 static struct regdata mb86a20s_init[] = { 51 { 0x70, 0x0f }, 52 { 0x70, 0xff }, 53 { 0x08, 0x01 }, 54 { 0x09, 0x3e }, 55 { 0x50, 0xd1 }, { 0x51, 0x22 }, 56 { 0x39, 0x01 }, 57 { 0x71, 0x00 }, 58 { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 }, 59 { 0x28, 0x20 }, { 0x29, 0x33 }, { 0x2a, 0xdf }, { 0x2b, 0xa9 }, 60 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, 61 { 0x3b, 0x21 }, 62 { 0x3c, 0x3a }, 63 { 0x01, 0x0d }, 64 { 0x04, 0x08 }, { 0x05, 0x05 }, 65 { 0x04, 0x0e }, { 0x05, 0x00 }, 66 { 0x04, 0x0f }, { 0x05, 0x14 }, 67 { 0x04, 0x0b }, { 0x05, 0x8c }, 68 { 0x04, 0x00 }, { 0x05, 0x00 }, 69 { 0x04, 0x01 }, { 0x05, 0x07 }, 70 { 0x04, 0x02 }, { 0x05, 0x0f }, 71 { 0x04, 0x03 }, { 0x05, 0xa0 }, 72 { 0x04, 0x09 }, { 0x05, 0x00 }, 73 { 0x04, 0x0a }, { 0x05, 0xff }, 74 { 0x04, 0x27 }, { 0x05, 0x64 }, 75 { 0x04, 0x28 }, { 0x05, 0x00 }, 76 { 0x04, 0x1e }, { 0x05, 0xff }, 77 { 0x04, 0x29 }, { 0x05, 0x0a }, 78 { 0x04, 0x32 }, { 0x05, 0x0a }, 79 { 0x04, 0x14 }, { 0x05, 0x02 }, 80 { 0x04, 0x04 }, { 0x05, 0x00 }, 81 { 0x04, 0x05 }, { 0x05, 0x22 }, 82 { 0x04, 0x06 }, { 0x05, 0x0e }, 83 { 0x04, 0x07 }, { 0x05, 0xd8 }, 84 { 0x04, 0x12 }, { 0x05, 0x00 }, 85 { 0x04, 0x13 }, { 0x05, 0xff }, 86 { 0x04, 0x15 }, { 0x05, 0x4e }, 87 { 0x04, 0x16 }, { 0x05, 0x20 }, 88 89 /* 90 * On this demod, when the bit count reaches the count below, 91 * it collects the bit error count. The bit counters are initialized 92 * to 65535 here. This warrants that all of them will be quickly 93 * calculated when device gets locked. As TMCC is parsed, the values 94 * will be adjusted later in the driver's code. 95 */ 96 { 0x52, 0x01 }, /* Turn on BER before Viterbi */ 97 { 0x50, 0xa7 }, { 0x51, 0x00 }, 98 { 0x50, 0xa8 }, { 0x51, 0xff }, 99 { 0x50, 0xa9 }, { 0x51, 0xff }, 100 { 0x50, 0xaa }, { 0x51, 0x00 }, 101 { 0x50, 0xab }, { 0x51, 0xff }, 102 { 0x50, 0xac }, { 0x51, 0xff }, 103 { 0x50, 0xad }, { 0x51, 0x00 }, 104 { 0x50, 0xae }, { 0x51, 0xff }, 105 { 0x50, 0xaf }, { 0x51, 0xff }, 106 107 /* 108 * On this demod, post BER counts blocks. When the count reaches the 109 * value below, it collects the block error count. The block counters 110 * are initialized to 127 here. This warrants that all of them will be 111 * quickly calculated when device gets locked. As TMCC is parsed, the 112 * values will be adjusted later in the driver's code. 113 */ 114 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */ 115 { 0x50, 0xdc }, { 0x51, 0x00 }, 116 { 0x50, 0xdd }, { 0x51, 0x7f }, 117 { 0x50, 0xde }, { 0x51, 0x00 }, 118 { 0x50, 0xdf }, { 0x51, 0x7f }, 119 { 0x50, 0xe0 }, { 0x51, 0x00 }, 120 { 0x50, 0xe1 }, { 0x51, 0x7f }, 121 122 /* 123 * On this demod, when the block count reaches the count below, 124 * it collects the block error count. The block counters are initialized 125 * to 127 here. This warrants that all of them will be quickly 126 * calculated when device gets locked. As TMCC is parsed, the values 127 * will be adjusted later in the driver's code. 128 */ 129 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */ 130 { 0x50, 0xb2 }, { 0x51, 0x00 }, 131 { 0x50, 0xb3 }, { 0x51, 0x7f }, 132 { 0x50, 0xb4 }, { 0x51, 0x00 }, 133 { 0x50, 0xb5 }, { 0x51, 0x7f }, 134 { 0x50, 0xb6 }, { 0x51, 0x00 }, 135 { 0x50, 0xb7 }, { 0x51, 0x7f }, 136 137 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */ 138 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ 139 { 0x45, 0x04 }, /* CN symbol 4 */ 140 { 0x48, 0x04 }, /* CN manual mode */ 141 142 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */ 143 { 0x50, 0xd6 }, { 0x51, 0x1f }, 144 { 0x50, 0xd2 }, { 0x51, 0x03 }, 145 { 0x50, 0xd7 }, { 0x51, 0x3f }, 146 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 }, 147 { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c }, 148 149 { 0x04, 0x40 }, { 0x05, 0x00 }, 150 { 0x28, 0x00 }, { 0x29, 0x10 }, 151 { 0x28, 0x05 }, { 0x29, 0x02 }, 152 { 0x1c, 0x01 }, 153 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 }, 154 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d }, 155 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, 156 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 }, 157 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 }, 158 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 }, 159 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, 160 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 }, 161 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e }, 162 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e }, 163 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 }, 164 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, 165 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 }, 166 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 }, 167 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe }, 168 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 }, 169 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee }, 170 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 }, 171 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f }, 172 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 }, 173 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 }, 174 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a }, 175 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc }, 176 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba }, 177 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 }, 178 { 0x50, 0x1e }, { 0x51, 0x5d }, 179 { 0x50, 0x22 }, { 0x51, 0x00 }, 180 { 0x50, 0x23 }, { 0x51, 0xc8 }, 181 { 0x50, 0x24 }, { 0x51, 0x00 }, 182 { 0x50, 0x25 }, { 0x51, 0xf0 }, 183 { 0x50, 0x26 }, { 0x51, 0x00 }, 184 { 0x50, 0x27 }, { 0x51, 0xc3 }, 185 { 0x50, 0x39 }, { 0x51, 0x02 }, 186 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 187 { 0xd0, 0x00 }, 188 }; 189 190 static struct regdata mb86a20s_reset_reception[] = { 191 { 0x70, 0xf0 }, 192 { 0x70, 0xff }, 193 { 0x08, 0x01 }, 194 { 0x08, 0x00 }, 195 }; 196 197 static struct regdata mb86a20s_per_ber_reset[] = { 198 { 0x53, 0x00 }, /* pre BER Counter reset */ 199 { 0x53, 0x07 }, 200 201 { 0x5f, 0x00 }, /* post BER Counter reset */ 202 { 0x5f, 0x07 }, 203 204 { 0x50, 0xb1 }, /* PER Counter reset */ 205 { 0x51, 0x07 }, 206 { 0x51, 0x00 }, 207 }; 208 209 /* 210 * I2C read/write functions and macros 211 */ 212 213 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, 214 u8 i2c_addr, u8 reg, u8 data) 215 { 216 u8 buf[] = { reg, data }; 217 struct i2c_msg msg = { 218 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 219 }; 220 int rc; 221 222 rc = i2c_transfer(state->i2c, &msg, 1); 223 if (rc != 1) { 224 dev_err(&state->i2c->dev, 225 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", 226 __func__, rc, reg, data); 227 return rc; 228 } 229 230 return 0; 231 } 232 233 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, 234 u8 i2c_addr, struct regdata *rd, int size) 235 { 236 int i, rc; 237 238 for (i = 0; i < size; i++) { 239 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, 240 rd[i].data); 241 if (rc < 0) 242 return rc; 243 } 244 return 0; 245 } 246 247 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, 248 u8 i2c_addr, u8 reg) 249 { 250 u8 val; 251 int rc; 252 struct i2c_msg msg[] = { 253 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 254 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } 255 }; 256 257 rc = i2c_transfer(state->i2c, msg, 2); 258 259 if (rc != 2) { 260 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", 261 __func__, reg, rc); 262 return (rc < 0) ? rc : -EIO; 263 } 264 265 return val; 266 } 267 268 #define mb86a20s_readreg(state, reg) \ 269 mb86a20s_i2c_readreg(state, state->config->demod_address, reg) 270 #define mb86a20s_writereg(state, reg, val) \ 271 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) 272 #define mb86a20s_writeregdata(state, regdata) \ 273 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ 274 regdata, ARRAY_SIZE(regdata)) 275 276 /* 277 * Ancillary internal routines (likely compiled inlined) 278 * 279 * The functions below assume that gateway lock has already obtained 280 */ 281 282 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status) 283 { 284 struct mb86a20s_state *state = fe->demodulator_priv; 285 int val; 286 287 *status = 0; 288 289 val = mb86a20s_readreg(state, 0x0a) & 0xf; 290 if (val < 0) 291 return val; 292 293 if (val >= 2) 294 *status |= FE_HAS_SIGNAL; 295 296 if (val >= 4) 297 *status |= FE_HAS_CARRIER; 298 299 if (val >= 5) 300 *status |= FE_HAS_VITERBI; 301 302 if (val >= 7) 303 *status |= FE_HAS_SYNC; 304 305 if (val >= 8) /* Maybe 9? */ 306 *status |= FE_HAS_LOCK; 307 308 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", 309 __func__, *status, val); 310 311 return 0; 312 } 313 314 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) 315 { 316 struct mb86a20s_state *state = fe->demodulator_priv; 317 int rc; 318 unsigned rf_max, rf_min, rf; 319 320 /* Does a binary search to get RF strength */ 321 rf_max = 0xfff; 322 rf_min = 0; 323 do { 324 rf = (rf_max + rf_min) / 2; 325 rc = mb86a20s_writereg(state, 0x04, 0x1f); 326 if (rc < 0) 327 return rc; 328 rc = mb86a20s_writereg(state, 0x05, rf >> 8); 329 if (rc < 0) 330 return rc; 331 rc = mb86a20s_writereg(state, 0x04, 0x20); 332 if (rc < 0) 333 return rc; 334 rc = mb86a20s_writereg(state, 0x04, rf); 335 if (rc < 0) 336 return rc; 337 338 rc = mb86a20s_readreg(state, 0x02); 339 if (rc < 0) 340 return rc; 341 if (rc & 0x08) 342 rf_min = (rf_max + rf_min) / 2; 343 else 344 rf_max = (rf_max + rf_min) / 2; 345 if (rf_max - rf_min < 4) { 346 rf = (rf_max + rf_min) / 2; 347 348 /* Rescale it from 2^12 (4096) to 2^16 */ 349 rf <<= (16 - 12); 350 dev_dbg(&state->i2c->dev, 351 "%s: signal strength = %d (%d < RF=%d < %d)\n", 352 __func__, rf, rf_min, rf >> 4, rf_max); 353 return rf; 354 } 355 } while (1); 356 357 return 0; 358 } 359 360 static int mb86a20s_get_modulation(struct mb86a20s_state *state, 361 unsigned layer) 362 { 363 int rc; 364 static unsigned char reg[] = { 365 [0] = 0x86, /* Layer A */ 366 [1] = 0x8a, /* Layer B */ 367 [2] = 0x8e, /* Layer C */ 368 }; 369 370 if (layer >= ARRAY_SIZE(reg)) 371 return -EINVAL; 372 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 373 if (rc < 0) 374 return rc; 375 rc = mb86a20s_readreg(state, 0x6e); 376 if (rc < 0) 377 return rc; 378 switch ((rc >> 4) & 0x07) { 379 case 0: 380 return DQPSK; 381 case 1: 382 return QPSK; 383 case 2: 384 return QAM_16; 385 case 3: 386 return QAM_64; 387 default: 388 return QAM_AUTO; 389 } 390 } 391 392 static int mb86a20s_get_fec(struct mb86a20s_state *state, 393 unsigned layer) 394 { 395 int rc; 396 397 static unsigned char reg[] = { 398 [0] = 0x87, /* Layer A */ 399 [1] = 0x8b, /* Layer B */ 400 [2] = 0x8f, /* Layer C */ 401 }; 402 403 if (layer >= ARRAY_SIZE(reg)) 404 return -EINVAL; 405 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 406 if (rc < 0) 407 return rc; 408 rc = mb86a20s_readreg(state, 0x6e); 409 if (rc < 0) 410 return rc; 411 switch ((rc >> 4) & 0x07) { 412 case 0: 413 return FEC_1_2; 414 case 1: 415 return FEC_2_3; 416 case 2: 417 return FEC_3_4; 418 case 3: 419 return FEC_5_6; 420 case 4: 421 return FEC_7_8; 422 default: 423 return FEC_AUTO; 424 } 425 } 426 427 static int mb86a20s_get_interleaving(struct mb86a20s_state *state, 428 unsigned layer) 429 { 430 int rc; 431 432 static unsigned char reg[] = { 433 [0] = 0x88, /* Layer A */ 434 [1] = 0x8c, /* Layer B */ 435 [2] = 0x90, /* Layer C */ 436 }; 437 438 if (layer >= ARRAY_SIZE(reg)) 439 return -EINVAL; 440 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 441 if (rc < 0) 442 return rc; 443 rc = mb86a20s_readreg(state, 0x6e); 444 if (rc < 0) 445 return rc; 446 447 switch ((rc >> 4) & 0x07) { 448 case 1: 449 return GUARD_INTERVAL_1_4; 450 case 2: 451 return GUARD_INTERVAL_1_8; 452 case 3: 453 return GUARD_INTERVAL_1_16; 454 case 4: 455 return GUARD_INTERVAL_1_32; 456 457 default: 458 case 0: 459 return GUARD_INTERVAL_AUTO; 460 } 461 } 462 463 static int mb86a20s_get_segment_count(struct mb86a20s_state *state, 464 unsigned layer) 465 { 466 int rc, count; 467 static unsigned char reg[] = { 468 [0] = 0x89, /* Layer A */ 469 [1] = 0x8d, /* Layer B */ 470 [2] = 0x91, /* Layer C */ 471 }; 472 473 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 474 475 if (layer >= ARRAY_SIZE(reg)) 476 return -EINVAL; 477 478 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 479 if (rc < 0) 480 return rc; 481 rc = mb86a20s_readreg(state, 0x6e); 482 if (rc < 0) 483 return rc; 484 count = (rc >> 4) & 0x0f; 485 486 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); 487 488 return count; 489 } 490 491 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) 492 { 493 struct mb86a20s_state *state = fe->demodulator_priv; 494 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 495 496 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 497 498 /* Fixed parameters */ 499 c->delivery_system = SYS_ISDBT; 500 c->bandwidth_hz = 6000000; 501 502 /* Initialize values that will be later autodetected */ 503 c->isdbt_layer_enabled = 0; 504 c->transmission_mode = TRANSMISSION_MODE_AUTO; 505 c->guard_interval = GUARD_INTERVAL_AUTO; 506 c->isdbt_sb_mode = 0; 507 c->isdbt_sb_segment_count = 0; 508 } 509 510 /* 511 * Estimates the bit rate using the per-segment bit rate given by 512 * ABNT/NBR 15601 spec (table 4). 513 */ 514 static u32 isdbt_rate[3][5][4] = { 515 { /* DQPSK/QPSK */ 516 { 280850, 312060, 330420, 340430 }, /* 1/2 */ 517 { 374470, 416080, 440560, 453910 }, /* 2/3 */ 518 { 421280, 468090, 495630, 510650 }, /* 3/4 */ 519 { 468090, 520100, 550700, 567390 }, /* 5/6 */ 520 { 491500, 546110, 578230, 595760 }, /* 7/8 */ 521 }, { /* QAM16 */ 522 { 561710, 624130, 660840, 680870 }, /* 1/2 */ 523 { 748950, 832170, 881120, 907820 }, /* 2/3 */ 524 { 842570, 936190, 991260, 1021300 }, /* 3/4 */ 525 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ 526 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ 527 }, { /* QAM64 */ 528 { 842570, 936190, 991260, 1021300 }, /* 1/2 */ 529 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ 530 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ 531 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ 532 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ 533 } 534 }; 535 536 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, 537 u32 modulation, u32 fec, u32 interleaving, 538 u32 segment) 539 { 540 struct mb86a20s_state *state = fe->demodulator_priv; 541 u32 rate; 542 int m, f, i; 543 544 /* 545 * If modulation/fec/interleaving is not detected, the default is 546 * to consider the lowest bit rate, to avoid taking too long time 547 * to get BER. 548 */ 549 switch (modulation) { 550 case DQPSK: 551 case QPSK: 552 default: 553 m = 0; 554 break; 555 case QAM_16: 556 m = 1; 557 break; 558 case QAM_64: 559 m = 2; 560 break; 561 } 562 563 switch (fec) { 564 default: 565 case FEC_1_2: 566 case FEC_AUTO: 567 f = 0; 568 break; 569 case FEC_2_3: 570 f = 1; 571 break; 572 case FEC_3_4: 573 f = 2; 574 break; 575 case FEC_5_6: 576 f = 3; 577 break; 578 case FEC_7_8: 579 f = 4; 580 break; 581 } 582 583 switch (interleaving) { 584 default: 585 case GUARD_INTERVAL_1_4: 586 i = 0; 587 break; 588 case GUARD_INTERVAL_1_8: 589 i = 1; 590 break; 591 case GUARD_INTERVAL_1_16: 592 i = 2; 593 break; 594 case GUARD_INTERVAL_1_32: 595 i = 3; 596 break; 597 } 598 599 /* Samples BER at BER_SAMPLING_RATE seconds */ 600 rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE; 601 602 /* Avoids sampling too quickly or to overflow the register */ 603 if (rate < 256) 604 rate = 256; 605 else if (rate > (1 << 24) - 1) 606 rate = (1 << 24) - 1; 607 608 dev_dbg(&state->i2c->dev, 609 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", 610 __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000, 611 rate, rate); 612 613 state->estimated_rate[i] = rate; 614 } 615 616 617 static int mb86a20s_get_frontend(struct dvb_frontend *fe) 618 { 619 struct mb86a20s_state *state = fe->demodulator_priv; 620 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 621 int i, rc; 622 623 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 624 625 /* Reset frontend cache to default values */ 626 mb86a20s_reset_frontend_cache(fe); 627 628 /* Check for partial reception */ 629 rc = mb86a20s_writereg(state, 0x6d, 0x85); 630 if (rc < 0) 631 return rc; 632 rc = mb86a20s_readreg(state, 0x6e); 633 if (rc < 0) 634 return rc; 635 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; 636 637 /* Get per-layer data */ 638 639 for (i = 0; i < 3; i++) { 640 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", 641 __func__, 'A' + i); 642 643 rc = mb86a20s_get_segment_count(state, i); 644 if (rc < 0) 645 goto noperlayer_error; 646 if (rc >= 0 && rc < 14) { 647 c->layer[i].segment_count = rc; 648 } else { 649 c->layer[i].segment_count = 0; 650 state->estimated_rate[i] = 0; 651 continue; 652 } 653 c->isdbt_layer_enabled |= 1 << i; 654 rc = mb86a20s_get_modulation(state, i); 655 if (rc < 0) 656 goto noperlayer_error; 657 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", 658 __func__, rc); 659 c->layer[i].modulation = rc; 660 rc = mb86a20s_get_fec(state, i); 661 if (rc < 0) 662 goto noperlayer_error; 663 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", 664 __func__, rc); 665 c->layer[i].fec = rc; 666 rc = mb86a20s_get_interleaving(state, i); 667 if (rc < 0) 668 goto noperlayer_error; 669 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", 670 __func__, rc); 671 c->layer[i].interleaving = rc; 672 mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation, 673 c->layer[i].fec, 674 c->layer[i].interleaving, 675 c->layer[i].segment_count); 676 } 677 678 rc = mb86a20s_writereg(state, 0x6d, 0x84); 679 if (rc < 0) 680 return rc; 681 if ((rc & 0x60) == 0x20) { 682 c->isdbt_sb_mode = 1; 683 /* At least, one segment should exist */ 684 if (!c->isdbt_sb_segment_count) 685 c->isdbt_sb_segment_count = 1; 686 } 687 688 /* Get transmission mode and guard interval */ 689 rc = mb86a20s_readreg(state, 0x07); 690 if (rc < 0) 691 return rc; 692 if ((rc & 0x60) == 0x20) { 693 switch (rc & 0x0c >> 2) { 694 case 0: 695 c->transmission_mode = TRANSMISSION_MODE_2K; 696 break; 697 case 1: 698 c->transmission_mode = TRANSMISSION_MODE_4K; 699 break; 700 case 2: 701 c->transmission_mode = TRANSMISSION_MODE_8K; 702 break; 703 } 704 } 705 if (!(rc & 0x10)) { 706 switch (rc & 0x3) { 707 case 0: 708 c->guard_interval = GUARD_INTERVAL_1_4; 709 break; 710 case 1: 711 c->guard_interval = GUARD_INTERVAL_1_8; 712 break; 713 case 2: 714 c->guard_interval = GUARD_INTERVAL_1_16; 715 break; 716 } 717 } 718 return 0; 719 720 noperlayer_error: 721 722 /* per-layer info is incomplete; discard all per-layer */ 723 c->isdbt_layer_enabled = 0; 724 725 return rc; 726 } 727 728 static int mb86a20s_reset_counters(struct dvb_frontend *fe) 729 { 730 struct mb86a20s_state *state = fe->demodulator_priv; 731 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 732 int rc, val; 733 734 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 735 736 /* Reset the counters, if the channel changed */ 737 if (state->last_frequency != c->frequency) { 738 memset(&c->strength, 0, sizeof(c->strength)); 739 memset(&c->cnr, 0, sizeof(c->cnr)); 740 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); 741 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); 742 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 743 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 744 memset(&c->block_error, 0, sizeof(c->block_error)); 745 memset(&c->block_count, 0, sizeof(c->block_count)); 746 747 state->last_frequency = c->frequency; 748 } 749 750 /* Clear status for most stats */ 751 752 /* BER/PER counter reset */ 753 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); 754 if (rc < 0) 755 goto err; 756 757 /* CNR counter reset */ 758 rc = mb86a20s_readreg(state, 0x45); 759 if (rc < 0) 760 goto err; 761 val = rc; 762 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 763 if (rc < 0) 764 goto err; 765 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 766 if (rc < 0) 767 goto err; 768 769 /* MER counter reset */ 770 rc = mb86a20s_writereg(state, 0x50, 0x50); 771 if (rc < 0) 772 goto err; 773 rc = mb86a20s_readreg(state, 0x51); 774 if (rc < 0) 775 goto err; 776 val = rc; 777 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 778 if (rc < 0) 779 goto err; 780 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 781 if (rc < 0) 782 goto err; 783 784 goto ok; 785 err: 786 dev_err(&state->i2c->dev, 787 "%s: Can't reset FE statistics (error %d).\n", 788 __func__, rc); 789 ok: 790 return rc; 791 } 792 793 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe, 794 unsigned layer, 795 u32 *error, u32 *count) 796 { 797 struct mb86a20s_state *state = fe->demodulator_priv; 798 int rc, val; 799 800 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 801 802 if (layer >= 3) 803 return -EINVAL; 804 805 /* Check if the BER measures are already available */ 806 rc = mb86a20s_readreg(state, 0x54); 807 if (rc < 0) 808 return rc; 809 810 /* Check if data is available for that layer */ 811 if (!(rc & (1 << layer))) { 812 dev_dbg(&state->i2c->dev, 813 "%s: preBER for layer %c is not available yet.\n", 814 __func__, 'A' + layer); 815 return -EBUSY; 816 } 817 818 /* Read Bit Error Count */ 819 rc = mb86a20s_readreg(state, 0x55 + layer * 3); 820 if (rc < 0) 821 return rc; 822 *error = rc << 16; 823 rc = mb86a20s_readreg(state, 0x56 + layer * 3); 824 if (rc < 0) 825 return rc; 826 *error |= rc << 8; 827 rc = mb86a20s_readreg(state, 0x57 + layer * 3); 828 if (rc < 0) 829 return rc; 830 *error |= rc; 831 832 dev_dbg(&state->i2c->dev, 833 "%s: bit error before Viterbi for layer %c: %d.\n", 834 __func__, 'A' + layer, *error); 835 836 /* Read Bit Count */ 837 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 838 if (rc < 0) 839 return rc; 840 rc = mb86a20s_readreg(state, 0x51); 841 if (rc < 0) 842 return rc; 843 *count = rc << 16; 844 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 845 if (rc < 0) 846 return rc; 847 rc = mb86a20s_readreg(state, 0x51); 848 if (rc < 0) 849 return rc; 850 *count |= rc << 8; 851 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 852 if (rc < 0) 853 return rc; 854 rc = mb86a20s_readreg(state, 0x51); 855 if (rc < 0) 856 return rc; 857 *count |= rc; 858 859 dev_dbg(&state->i2c->dev, 860 "%s: bit count before Viterbi for layer %c: %d.\n", 861 __func__, 'A' + layer, *count); 862 863 864 /* 865 * As we get TMCC data from the frontend, we can better estimate the 866 * BER bit counters, in order to do the BER measure during a longer 867 * time. Use those data, if available, to update the bit count 868 * measure. 869 */ 870 871 if (state->estimated_rate[layer] 872 && state->estimated_rate[layer] != *count) { 873 dev_dbg(&state->i2c->dev, 874 "%s: updating layer %c preBER counter to %d.\n", 875 __func__, 'A' + layer, state->estimated_rate[layer]); 876 877 /* Turn off BER before Viterbi */ 878 rc = mb86a20s_writereg(state, 0x52, 0x00); 879 880 /* Update counter for this layer */ 881 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 882 if (rc < 0) 883 return rc; 884 rc = mb86a20s_writereg(state, 0x51, 885 state->estimated_rate[layer] >> 16); 886 if (rc < 0) 887 return rc; 888 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 889 if (rc < 0) 890 return rc; 891 rc = mb86a20s_writereg(state, 0x51, 892 state->estimated_rate[layer] >> 8); 893 if (rc < 0) 894 return rc; 895 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 896 if (rc < 0) 897 return rc; 898 rc = mb86a20s_writereg(state, 0x51, 899 state->estimated_rate[layer]); 900 if (rc < 0) 901 return rc; 902 903 /* Turn on BER before Viterbi */ 904 rc = mb86a20s_writereg(state, 0x52, 0x01); 905 906 /* Reset all preBER counters */ 907 rc = mb86a20s_writereg(state, 0x53, 0x00); 908 if (rc < 0) 909 return rc; 910 rc = mb86a20s_writereg(state, 0x53, 0x07); 911 } else { 912 /* Reset counter to collect new data */ 913 rc = mb86a20s_readreg(state, 0x53); 914 if (rc < 0) 915 return rc; 916 val = rc; 917 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); 918 if (rc < 0) 919 return rc; 920 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); 921 } 922 923 return rc; 924 } 925 926 static int mb86a20s_get_post_ber(struct dvb_frontend *fe, 927 unsigned layer, 928 u32 *error, u32 *count) 929 { 930 struct mb86a20s_state *state = fe->demodulator_priv; 931 u32 counter, collect_rate; 932 int rc, val; 933 934 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 935 936 if (layer >= 3) 937 return -EINVAL; 938 939 /* Check if the BER measures are already available */ 940 rc = mb86a20s_readreg(state, 0x60); 941 if (rc < 0) 942 return rc; 943 944 /* Check if data is available for that layer */ 945 if (!(rc & (1 << layer))) { 946 dev_dbg(&state->i2c->dev, 947 "%s: post BER for layer %c is not available yet.\n", 948 __func__, 'A' + layer); 949 return -EBUSY; 950 } 951 952 /* Read Bit Error Count */ 953 rc = mb86a20s_readreg(state, 0x64 + layer * 3); 954 if (rc < 0) 955 return rc; 956 *error = rc << 16; 957 rc = mb86a20s_readreg(state, 0x65 + layer * 3); 958 if (rc < 0) 959 return rc; 960 *error |= rc << 8; 961 rc = mb86a20s_readreg(state, 0x66 + layer * 3); 962 if (rc < 0) 963 return rc; 964 *error |= rc; 965 966 dev_dbg(&state->i2c->dev, 967 "%s: post bit error for layer %c: %d.\n", 968 __func__, 'A' + layer, *error); 969 970 /* Read Bit Count */ 971 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 972 if (rc < 0) 973 return rc; 974 rc = mb86a20s_readreg(state, 0x51); 975 if (rc < 0) 976 return rc; 977 counter = rc << 8; 978 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 979 if (rc < 0) 980 return rc; 981 rc = mb86a20s_readreg(state, 0x51); 982 if (rc < 0) 983 return rc; 984 counter |= rc; 985 *count = counter * 204 * 8; 986 987 dev_dbg(&state->i2c->dev, 988 "%s: post bit count for layer %c: %d.\n", 989 __func__, 'A' + layer, *count); 990 991 /* 992 * As we get TMCC data from the frontend, we can better estimate the 993 * BER bit counters, in order to do the BER measure during a longer 994 * time. Use those data, if available, to update the bit count 995 * measure. 996 */ 997 998 if (!state->estimated_rate[layer]) 999 goto reset_measurement; 1000 1001 collect_rate = state->estimated_rate[layer] / 204 / 8; 1002 if (collect_rate < 32) 1003 collect_rate = 32; 1004 if (collect_rate > 65535) 1005 collect_rate = 65535; 1006 if (collect_rate != counter) { 1007 dev_dbg(&state->i2c->dev, 1008 "%s: updating postBER counter on layer %c to %d.\n", 1009 __func__, 'A' + layer, collect_rate); 1010 1011 /* Turn off BER after Viterbi */ 1012 rc = mb86a20s_writereg(state, 0x5e, 0x00); 1013 1014 /* Update counter for this layer */ 1015 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1016 if (rc < 0) 1017 return rc; 1018 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1019 if (rc < 0) 1020 return rc; 1021 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1022 if (rc < 0) 1023 return rc; 1024 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1025 if (rc < 0) 1026 return rc; 1027 1028 /* Turn on BER after Viterbi */ 1029 rc = mb86a20s_writereg(state, 0x5e, 0x07); 1030 1031 /* Reset all preBER counters */ 1032 rc = mb86a20s_writereg(state, 0x5f, 0x00); 1033 if (rc < 0) 1034 return rc; 1035 rc = mb86a20s_writereg(state, 0x5f, 0x07); 1036 1037 return rc; 1038 } 1039 1040 reset_measurement: 1041 /* Reset counter to collect new data */ 1042 rc = mb86a20s_readreg(state, 0x5f); 1043 if (rc < 0) 1044 return rc; 1045 val = rc; 1046 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); 1047 if (rc < 0) 1048 return rc; 1049 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); 1050 1051 return rc; 1052 } 1053 1054 static int mb86a20s_get_blk_error(struct dvb_frontend *fe, 1055 unsigned layer, 1056 u32 *error, u32 *count) 1057 { 1058 struct mb86a20s_state *state = fe->demodulator_priv; 1059 int rc, val; 1060 u32 collect_rate; 1061 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1062 1063 if (layer >= 3) 1064 return -EINVAL; 1065 1066 /* Check if the PER measures are already available */ 1067 rc = mb86a20s_writereg(state, 0x50, 0xb8); 1068 if (rc < 0) 1069 return rc; 1070 rc = mb86a20s_readreg(state, 0x51); 1071 if (rc < 0) 1072 return rc; 1073 1074 /* Check if data is available for that layer */ 1075 1076 if (!(rc & (1 << layer))) { 1077 dev_dbg(&state->i2c->dev, 1078 "%s: block counts for layer %c aren't available yet.\n", 1079 __func__, 'A' + layer); 1080 return -EBUSY; 1081 } 1082 1083 /* Read Packet error Count */ 1084 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); 1085 if (rc < 0) 1086 return rc; 1087 rc = mb86a20s_readreg(state, 0x51); 1088 if (rc < 0) 1089 return rc; 1090 *error = rc << 8; 1091 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); 1092 if (rc < 0) 1093 return rc; 1094 rc = mb86a20s_readreg(state, 0x51); 1095 if (rc < 0) 1096 return rc; 1097 *error |= rc; 1098 dev_err(&state->i2c->dev, "%s: block error for layer %c: %d.\n", 1099 __func__, 'A' + layer, *error); 1100 1101 /* Read Bit Count */ 1102 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1103 if (rc < 0) 1104 return rc; 1105 rc = mb86a20s_readreg(state, 0x51); 1106 if (rc < 0) 1107 return rc; 1108 *count = rc << 8; 1109 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1110 if (rc < 0) 1111 return rc; 1112 rc = mb86a20s_readreg(state, 0x51); 1113 if (rc < 0) 1114 return rc; 1115 *count |= rc; 1116 1117 dev_dbg(&state->i2c->dev, 1118 "%s: block count for layer %c: %d.\n", 1119 __func__, 'A' + layer, *count); 1120 1121 /* 1122 * As we get TMCC data from the frontend, we can better estimate the 1123 * BER bit counters, in order to do the BER measure during a longer 1124 * time. Use those data, if available, to update the bit count 1125 * measure. 1126 */ 1127 1128 if (!state->estimated_rate[layer]) 1129 goto reset_measurement; 1130 1131 collect_rate = state->estimated_rate[layer] / 204 / 8; 1132 if (collect_rate < 32) 1133 collect_rate = 32; 1134 if (collect_rate > 65535) 1135 collect_rate = 65535; 1136 1137 if (collect_rate != *count) { 1138 dev_dbg(&state->i2c->dev, 1139 "%s: updating PER counter on layer %c to %d.\n", 1140 __func__, 'A' + layer, collect_rate); 1141 1142 /* Stop PER measurement */ 1143 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1144 if (rc < 0) 1145 return rc; 1146 rc = mb86a20s_writereg(state, 0x51, 0x00); 1147 if (rc < 0) 1148 return rc; 1149 1150 /* Update this layer's counter */ 1151 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1152 if (rc < 0) 1153 return rc; 1154 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1155 if (rc < 0) 1156 return rc; 1157 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1158 if (rc < 0) 1159 return rc; 1160 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1161 if (rc < 0) 1162 return rc; 1163 1164 /* start PER measurement */ 1165 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1166 if (rc < 0) 1167 return rc; 1168 rc = mb86a20s_writereg(state, 0x51, 0x07); 1169 if (rc < 0) 1170 return rc; 1171 1172 /* Reset all counters to collect new data */ 1173 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1174 if (rc < 0) 1175 return rc; 1176 rc = mb86a20s_writereg(state, 0x51, 0x07); 1177 if (rc < 0) 1178 return rc; 1179 rc = mb86a20s_writereg(state, 0x51, 0x00); 1180 1181 return rc; 1182 } 1183 1184 reset_measurement: 1185 /* Reset counter to collect new data */ 1186 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1187 if (rc < 0) 1188 return rc; 1189 rc = mb86a20s_readreg(state, 0x51); 1190 if (rc < 0) 1191 return rc; 1192 val = rc; 1193 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); 1194 if (rc < 0) 1195 return rc; 1196 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); 1197 1198 return rc; 1199 } 1200 1201 struct linear_segments { 1202 unsigned x, y; 1203 }; 1204 1205 /* 1206 * All tables below return a dB/1000 measurement 1207 */ 1208 1209 static struct linear_segments cnr_to_db_table[] = { 1210 { 19648, 0}, 1211 { 18187, 1000}, 1212 { 16534, 2000}, 1213 { 14823, 3000}, 1214 { 13161, 4000}, 1215 { 11622, 5000}, 1216 { 10279, 6000}, 1217 { 9089, 7000}, 1218 { 8042, 8000}, 1219 { 7137, 9000}, 1220 { 6342, 10000}, 1221 { 5641, 11000}, 1222 { 5030, 12000}, 1223 { 4474, 13000}, 1224 { 3988, 14000}, 1225 { 3556, 15000}, 1226 { 3180, 16000}, 1227 { 2841, 17000}, 1228 { 2541, 18000}, 1229 { 2276, 19000}, 1230 { 2038, 20000}, 1231 { 1800, 21000}, 1232 { 1625, 22000}, 1233 { 1462, 23000}, 1234 { 1324, 24000}, 1235 { 1175, 25000}, 1236 { 1063, 26000}, 1237 { 980, 27000}, 1238 { 907, 28000}, 1239 { 840, 29000}, 1240 { 788, 30000}, 1241 }; 1242 1243 static struct linear_segments cnr_64qam_table[] = { 1244 { 3922688, 0}, 1245 { 3920384, 1000}, 1246 { 3902720, 2000}, 1247 { 3894784, 3000}, 1248 { 3882496, 4000}, 1249 { 3872768, 5000}, 1250 { 3858944, 6000}, 1251 { 3851520, 7000}, 1252 { 3838976, 8000}, 1253 { 3829248, 9000}, 1254 { 3818240, 10000}, 1255 { 3806976, 11000}, 1256 { 3791872, 12000}, 1257 { 3767040, 13000}, 1258 { 3720960, 14000}, 1259 { 3637504, 15000}, 1260 { 3498496, 16000}, 1261 { 3296000, 17000}, 1262 { 3031040, 18000}, 1263 { 2715392, 19000}, 1264 { 2362624, 20000}, 1265 { 1963264, 21000}, 1266 { 1649664, 22000}, 1267 { 1366784, 23000}, 1268 { 1120768, 24000}, 1269 { 890880, 25000}, 1270 { 723456, 26000}, 1271 { 612096, 27000}, 1272 { 518912, 28000}, 1273 { 448256, 29000}, 1274 { 388864, 30000}, 1275 }; 1276 1277 static struct linear_segments cnr_16qam_table[] = { 1278 { 5314816, 0}, 1279 { 5219072, 1000}, 1280 { 5118720, 2000}, 1281 { 4998912, 3000}, 1282 { 4875520, 4000}, 1283 { 4736000, 5000}, 1284 { 4604160, 6000}, 1285 { 4458752, 7000}, 1286 { 4300288, 8000}, 1287 { 4092928, 9000}, 1288 { 3836160, 10000}, 1289 { 3521024, 11000}, 1290 { 3155968, 12000}, 1291 { 2756864, 13000}, 1292 { 2347008, 14000}, 1293 { 1955072, 15000}, 1294 { 1593600, 16000}, 1295 { 1297920, 17000}, 1296 { 1043968, 18000}, 1297 { 839680, 19000}, 1298 { 672256, 20000}, 1299 { 523008, 21000}, 1300 { 424704, 22000}, 1301 { 345088, 23000}, 1302 { 280064, 24000}, 1303 { 221440, 25000}, 1304 { 179712, 26000}, 1305 { 151040, 27000}, 1306 { 128512, 28000}, 1307 { 110080, 29000}, 1308 { 95744, 30000}, 1309 }; 1310 1311 struct linear_segments cnr_qpsk_table[] = { 1312 { 2834176, 0}, 1313 { 2683648, 1000}, 1314 { 2536960, 2000}, 1315 { 2391808, 3000}, 1316 { 2133248, 4000}, 1317 { 1906176, 5000}, 1318 { 1666560, 6000}, 1319 { 1422080, 7000}, 1320 { 1189632, 8000}, 1321 { 976384, 9000}, 1322 { 790272, 10000}, 1323 { 633344, 11000}, 1324 { 505600, 12000}, 1325 { 402944, 13000}, 1326 { 320768, 14000}, 1327 { 255488, 15000}, 1328 { 204032, 16000}, 1329 { 163072, 17000}, 1330 { 130304, 18000}, 1331 { 105216, 19000}, 1332 { 83456, 20000}, 1333 { 65024, 21000}, 1334 { 52480, 22000}, 1335 { 42752, 23000}, 1336 { 34560, 24000}, 1337 { 27136, 25000}, 1338 { 22016, 26000}, 1339 { 18432, 27000}, 1340 { 15616, 28000}, 1341 { 13312, 29000}, 1342 { 11520, 30000}, 1343 }; 1344 1345 static u32 interpolate_value(u32 value, struct linear_segments *segments, 1346 unsigned len) 1347 { 1348 u64 tmp64; 1349 u32 dx, dy; 1350 int i, ret; 1351 1352 if (value >= segments[0].x) 1353 return segments[0].y; 1354 if (value < segments[len-1].x) 1355 return segments[len-1].y; 1356 1357 for (i = 1; i < len - 1; i++) { 1358 /* If value is identical, no need to interpolate */ 1359 if (value == segments[i].x) 1360 return segments[i].y; 1361 if (value > segments[i].x) 1362 break; 1363 } 1364 1365 /* Linear interpolation between the two (x,y) points */ 1366 dy = segments[i].y - segments[i - 1].y; 1367 dx = segments[i - 1].x - segments[i].x; 1368 tmp64 = value - segments[i].x; 1369 tmp64 *= dy; 1370 do_div(tmp64, dx); 1371 ret = segments[i].y - tmp64; 1372 1373 return ret; 1374 } 1375 1376 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe) 1377 { 1378 struct mb86a20s_state *state = fe->demodulator_priv; 1379 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1380 u32 cnr_linear, cnr; 1381 int rc, val; 1382 1383 /* Check if CNR is available */ 1384 rc = mb86a20s_readreg(state, 0x45); 1385 if (rc < 0) 1386 return rc; 1387 1388 if (!(rc & 0x40)) { 1389 dev_info(&state->i2c->dev, "%s: CNR is not available yet.\n", 1390 __func__); 1391 return -EBUSY; 1392 } 1393 val = rc; 1394 1395 rc = mb86a20s_readreg(state, 0x46); 1396 if (rc < 0) 1397 return rc; 1398 cnr_linear = rc << 8; 1399 1400 rc = mb86a20s_readreg(state, 0x46); 1401 if (rc < 0) 1402 return rc; 1403 cnr_linear |= rc; 1404 1405 cnr = interpolate_value(cnr_linear, 1406 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table)); 1407 1408 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 1409 c->cnr.stat[0].svalue = cnr; 1410 1411 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", 1412 __func__, cnr / 1000, cnr % 1000, cnr_linear); 1413 1414 /* CNR counter reset */ 1415 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 1416 if (rc < 0) 1417 return rc; 1418 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 1419 1420 return rc; 1421 } 1422 1423 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe) 1424 { 1425 struct mb86a20s_state *state = fe->demodulator_priv; 1426 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1427 u32 mer, cnr; 1428 int rc, val, i; 1429 struct linear_segments *segs; 1430 unsigned segs_len; 1431 1432 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1433 1434 /* Check if the measures are already available */ 1435 rc = mb86a20s_writereg(state, 0x50, 0x5b); 1436 if (rc < 0) 1437 return rc; 1438 rc = mb86a20s_readreg(state, 0x51); 1439 if (rc < 0) 1440 return rc; 1441 1442 /* Check if data is available */ 1443 if (!(rc & 0x01)) { 1444 dev_info(&state->i2c->dev, 1445 "%s: MER measures aren't available yet.\n", __func__); 1446 return -EBUSY; 1447 } 1448 1449 /* Read all layers */ 1450 for (i = 0; i < 3; i++) { 1451 if (!(c->isdbt_layer_enabled & (1 << i))) { 1452 c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1453 continue; 1454 } 1455 1456 rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3); 1457 if (rc < 0) 1458 return rc; 1459 rc = mb86a20s_readreg(state, 0x51); 1460 if (rc < 0) 1461 return rc; 1462 mer = rc << 16; 1463 rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3); 1464 if (rc < 0) 1465 return rc; 1466 rc = mb86a20s_readreg(state, 0x51); 1467 if (rc < 0) 1468 return rc; 1469 mer |= rc << 8; 1470 rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3); 1471 if (rc < 0) 1472 return rc; 1473 rc = mb86a20s_readreg(state, 0x51); 1474 if (rc < 0) 1475 return rc; 1476 mer |= rc; 1477 1478 switch (c->layer[i].modulation) { 1479 case DQPSK: 1480 case QPSK: 1481 segs = cnr_qpsk_table; 1482 segs_len = ARRAY_SIZE(cnr_qpsk_table); 1483 break; 1484 case QAM_16: 1485 segs = cnr_16qam_table; 1486 segs_len = ARRAY_SIZE(cnr_16qam_table); 1487 break; 1488 default: 1489 case QAM_64: 1490 segs = cnr_64qam_table; 1491 segs_len = ARRAY_SIZE(cnr_64qam_table); 1492 break; 1493 } 1494 cnr = interpolate_value(mer, segs, segs_len); 1495 1496 c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL; 1497 c->cnr.stat[1 + i].svalue = cnr; 1498 1499 dev_dbg(&state->i2c->dev, 1500 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n", 1501 __func__, 'A' + i, cnr / 1000, cnr % 1000, mer); 1502 1503 } 1504 1505 /* Start a new MER measurement */ 1506 /* MER counter reset */ 1507 rc = mb86a20s_writereg(state, 0x50, 0x50); 1508 if (rc < 0) 1509 return rc; 1510 rc = mb86a20s_readreg(state, 0x51); 1511 if (rc < 0) 1512 return rc; 1513 val = rc; 1514 1515 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 1516 if (rc < 0) 1517 return rc; 1518 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 1519 if (rc < 0) 1520 return rc; 1521 1522 return 0; 1523 } 1524 1525 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) 1526 { 1527 struct mb86a20s_state *state = fe->demodulator_priv; 1528 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1529 int i; 1530 1531 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1532 1533 /* Fill the length of each status counter */ 1534 1535 /* Only global stats */ 1536 c->strength.len = 1; 1537 1538 /* Per-layer stats - 3 layers + global */ 1539 c->cnr.len = 4; 1540 c->pre_bit_error.len = 4; 1541 c->pre_bit_count.len = 4; 1542 c->post_bit_error.len = 4; 1543 c->post_bit_count.len = 4; 1544 c->block_error.len = 4; 1545 c->block_count.len = 4; 1546 1547 /* Signal is always available */ 1548 c->strength.stat[0].scale = FE_SCALE_RELATIVE; 1549 c->strength.stat[0].uvalue = 0; 1550 1551 /* Put all of them at FE_SCALE_NOT_AVAILABLE */ 1552 for (i = 0; i < 4; i++) { 1553 c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1554 c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1555 c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1556 c->post_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1557 c->post_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1558 c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1559 c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1560 } 1561 } 1562 1563 static int mb86a20s_get_stats(struct dvb_frontend *fe) 1564 { 1565 struct mb86a20s_state *state = fe->demodulator_priv; 1566 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1567 int rc = 0, i; 1568 u32 bit_error = 0, bit_count = 0; 1569 u32 t_pre_bit_error = 0, t_pre_bit_count = 0; 1570 u32 t_post_bit_error = 0, t_post_bit_count = 0; 1571 u32 block_error = 0, block_count = 0; 1572 u32 t_block_error = 0, t_block_count = 0; 1573 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0; 1574 int per_layers = 0; 1575 1576 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1577 1578 mb86a20s_get_main_CNR(fe); 1579 1580 /* Get per-layer stats */ 1581 mb86a20s_get_blk_error_layer_CNR(fe); 1582 1583 for (i = 0; i < 3; i++) { 1584 if (c->isdbt_layer_enabled & (1 << i)) { 1585 /* Layer is active and has rc segments */ 1586 active_layers++; 1587 1588 /* Handle BER before vterbi */ 1589 rc = mb86a20s_get_pre_ber(fe, i, 1590 &bit_error, &bit_count); 1591 if (rc >= 0) { 1592 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1593 c->pre_bit_error.stat[1 + i].uvalue += bit_error; 1594 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1595 c->pre_bit_count.stat[1 + i].uvalue += bit_count; 1596 } else if (rc != -EBUSY) { 1597 /* 1598 * If an I/O error happened, 1599 * measures are now unavailable 1600 */ 1601 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1602 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1603 dev_err(&state->i2c->dev, 1604 "%s: Can't get BER for layer %c (error %d).\n", 1605 __func__, 'A' + i, rc); 1606 } 1607 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1608 pre_ber_layers++; 1609 1610 /* Handle BER post vterbi */ 1611 rc = mb86a20s_get_post_ber(fe, i, 1612 &bit_error, &bit_count); 1613 if (rc >= 0) { 1614 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1615 c->post_bit_error.stat[1 + i].uvalue += bit_error; 1616 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1617 c->post_bit_count.stat[1 + i].uvalue += bit_count; 1618 } else if (rc != -EBUSY) { 1619 /* 1620 * If an I/O error happened, 1621 * measures are now unavailable 1622 */ 1623 c->post_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1624 c->post_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1625 dev_err(&state->i2c->dev, 1626 "%s: Can't get BER for layer %c (error %d).\n", 1627 __func__, 'A' + i, rc); 1628 } 1629 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1630 post_ber_layers++; 1631 1632 /* Handle Block errors for PER/UCB reports */ 1633 rc = mb86a20s_get_blk_error(fe, i, 1634 &block_error, 1635 &block_count); 1636 if (rc >= 0) { 1637 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1638 c->block_error.stat[1 + i].uvalue += block_error; 1639 c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1640 c->block_count.stat[1 + i].uvalue += block_count; 1641 } else if (rc != -EBUSY) { 1642 /* 1643 * If an I/O error happened, 1644 * measures are now unavailable 1645 */ 1646 c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1647 c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1648 dev_err(&state->i2c->dev, 1649 "%s: Can't get PER for layer %c (error %d).\n", 1650 __func__, 'A' + i, rc); 1651 1652 } 1653 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1654 per_layers++; 1655 1656 /* Update total preBER */ 1657 t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue; 1658 t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue; 1659 1660 /* Update total postBER */ 1661 t_post_bit_error += c->post_bit_error.stat[1 + i].uvalue; 1662 t_post_bit_count += c->post_bit_count.stat[1 + i].uvalue; 1663 1664 /* Update total PER */ 1665 t_block_error += c->block_error.stat[1 + i].uvalue; 1666 t_block_count += c->block_count.stat[1 + i].uvalue; 1667 } 1668 } 1669 1670 /* 1671 * Start showing global count if at least one error count is 1672 * available. 1673 */ 1674 if (pre_ber_layers) { 1675 /* 1676 * At least one per-layer BER measure was read. We can now 1677 * calculate the total BER 1678 * 1679 * Total Bit Error/Count is calculated as the sum of the 1680 * bit errors on all active layers. 1681 */ 1682 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1683 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; 1684 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1685 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; 1686 } else { 1687 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1688 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1689 } 1690 1691 /* 1692 * Start showing global count if at least one error count is 1693 * available. 1694 */ 1695 if (post_ber_layers) { 1696 /* 1697 * At least one per-layer BER measure was read. We can now 1698 * calculate the total BER 1699 * 1700 * Total Bit Error/Count is calculated as the sum of the 1701 * bit errors on all active layers. 1702 */ 1703 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1704 c->post_bit_error.stat[0].uvalue = t_post_bit_error; 1705 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1706 c->post_bit_count.stat[0].uvalue = t_post_bit_count; 1707 } else { 1708 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1709 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1710 } 1711 1712 if (per_layers) { 1713 /* 1714 * At least one per-layer UCB measure was read. We can now 1715 * calculate the total UCB 1716 * 1717 * Total block Error/Count is calculated as the sum of the 1718 * block errors on all active layers. 1719 */ 1720 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1721 c->block_error.stat[0].uvalue = t_block_error; 1722 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1723 c->block_count.stat[0].uvalue = t_block_count; 1724 } else { 1725 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1726 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1727 } 1728 1729 return rc; 1730 } 1731 1732 /* 1733 * The functions below are called via DVB callbacks, so they need to 1734 * properly use the I2C gate control 1735 */ 1736 1737 static int mb86a20s_initfe(struct dvb_frontend *fe) 1738 { 1739 struct mb86a20s_state *state = fe->demodulator_priv; 1740 int rc; 1741 u8 regD5 = 1; 1742 1743 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1744 1745 if (fe->ops.i2c_gate_ctrl) 1746 fe->ops.i2c_gate_ctrl(fe, 0); 1747 1748 /* Initialize the frontend */ 1749 rc = mb86a20s_writeregdata(state, mb86a20s_init); 1750 if (rc < 0) 1751 goto err; 1752 1753 if (!state->config->is_serial) { 1754 regD5 &= ~1; 1755 1756 rc = mb86a20s_writereg(state, 0x50, 0xd5); 1757 if (rc < 0) 1758 goto err; 1759 rc = mb86a20s_writereg(state, 0x51, regD5); 1760 if (rc < 0) 1761 goto err; 1762 } 1763 1764 err: 1765 if (fe->ops.i2c_gate_ctrl) 1766 fe->ops.i2c_gate_ctrl(fe, 1); 1767 1768 if (rc < 0) { 1769 state->need_init = true; 1770 dev_info(&state->i2c->dev, 1771 "mb86a20s: Init failed. Will try again later\n"); 1772 } else { 1773 state->need_init = false; 1774 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); 1775 } 1776 return rc; 1777 } 1778 1779 static int mb86a20s_set_frontend(struct dvb_frontend *fe) 1780 { 1781 struct mb86a20s_state *state = fe->demodulator_priv; 1782 int rc; 1783 #if 0 1784 /* 1785 * FIXME: Properly implement the set frontend properties 1786 */ 1787 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1788 #endif 1789 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1790 1791 /* 1792 * Gate should already be opened, but it doesn't hurt to 1793 * double-check 1794 */ 1795 if (fe->ops.i2c_gate_ctrl) 1796 fe->ops.i2c_gate_ctrl(fe, 1); 1797 fe->ops.tuner_ops.set_params(fe); 1798 1799 /* 1800 * Make it more reliable: if, for some reason, the initial 1801 * device initialization doesn't happen, initialize it when 1802 * a SBTVD parameters are adjusted. 1803 * 1804 * Unfortunately, due to a hard to track bug at tda829x/tda18271, 1805 * the agc callback logic is not called during DVB attach time, 1806 * causing mb86a20s to not be initialized with Kworld SBTVD. 1807 * So, this hack is needed, in order to make Kworld SBTVD to work. 1808 */ 1809 if (state->need_init) 1810 mb86a20s_initfe(fe); 1811 1812 if (fe->ops.i2c_gate_ctrl) 1813 fe->ops.i2c_gate_ctrl(fe, 0); 1814 1815 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); 1816 mb86a20s_reset_counters(fe); 1817 1818 if (fe->ops.i2c_gate_ctrl) 1819 fe->ops.i2c_gate_ctrl(fe, 1); 1820 1821 return rc; 1822 } 1823 1824 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, 1825 fe_status_t *status) 1826 { 1827 struct mb86a20s_state *state = fe->demodulator_priv; 1828 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1829 int rc; 1830 1831 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1832 1833 if (fe->ops.i2c_gate_ctrl) 1834 fe->ops.i2c_gate_ctrl(fe, 0); 1835 1836 /* Get lock */ 1837 rc = mb86a20s_read_status(fe, status); 1838 if (!(*status & FE_HAS_LOCK)) { 1839 mb86a20s_stats_not_ready(fe); 1840 mb86a20s_reset_frontend_cache(fe); 1841 } 1842 if (rc < 0) { 1843 dev_err(&state->i2c->dev, 1844 "%s: Can't read frontend lock status\n", __func__); 1845 goto error; 1846 } 1847 1848 /* Get signal strength */ 1849 rc = mb86a20s_read_signal_strength(fe); 1850 if (rc < 0) { 1851 dev_err(&state->i2c->dev, 1852 "%s: Can't reset VBER registers.\n", __func__); 1853 mb86a20s_stats_not_ready(fe); 1854 mb86a20s_reset_frontend_cache(fe); 1855 1856 rc = 0; /* Status is OK */ 1857 goto error; 1858 } 1859 /* Fill signal strength */ 1860 c->strength.stat[0].uvalue = rc; 1861 1862 if (*status & FE_HAS_LOCK) { 1863 /* Get TMCC info*/ 1864 rc = mb86a20s_get_frontend(fe); 1865 if (rc < 0) { 1866 dev_err(&state->i2c->dev, 1867 "%s: Can't get FE TMCC data.\n", __func__); 1868 rc = 0; /* Status is OK */ 1869 goto error; 1870 } 1871 1872 /* Get statistics */ 1873 rc = mb86a20s_get_stats(fe); 1874 if (rc < 0 && rc != -EBUSY) { 1875 dev_err(&state->i2c->dev, 1876 "%s: Can't get FE statistics.\n", __func__); 1877 rc = 0; 1878 goto error; 1879 } 1880 rc = 0; /* Don't return EBUSY to userspace */ 1881 } 1882 goto ok; 1883 1884 error: 1885 mb86a20s_stats_not_ready(fe); 1886 1887 ok: 1888 if (fe->ops.i2c_gate_ctrl) 1889 fe->ops.i2c_gate_ctrl(fe, 1); 1890 1891 return rc; 1892 } 1893 1894 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, 1895 u16 *strength) 1896 { 1897 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1898 1899 1900 *strength = c->strength.stat[0].uvalue; 1901 1902 return 0; 1903 } 1904 1905 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe) 1906 { 1907 /* 1908 * get_frontend is now handled together with other stats 1909 * retrival, when read_status() is called, as some statistics 1910 * will depend on the layers detection. 1911 */ 1912 return 0; 1913 }; 1914 1915 static int mb86a20s_tune(struct dvb_frontend *fe, 1916 bool re_tune, 1917 unsigned int mode_flags, 1918 unsigned int *delay, 1919 fe_status_t *status) 1920 { 1921 struct mb86a20s_state *state = fe->demodulator_priv; 1922 int rc = 0; 1923 1924 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1925 1926 if (re_tune) 1927 rc = mb86a20s_set_frontend(fe); 1928 1929 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 1930 mb86a20s_read_status_and_stats(fe, status); 1931 1932 return rc; 1933 } 1934 1935 static void mb86a20s_release(struct dvb_frontend *fe) 1936 { 1937 struct mb86a20s_state *state = fe->demodulator_priv; 1938 1939 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1940 1941 kfree(state); 1942 } 1943 1944 static struct dvb_frontend_ops mb86a20s_ops; 1945 1946 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, 1947 struct i2c_adapter *i2c) 1948 { 1949 struct mb86a20s_state *state; 1950 u8 rev; 1951 1952 dev_dbg(&i2c->dev, "%s called.\n", __func__); 1953 1954 /* allocate memory for the internal state */ 1955 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); 1956 if (state == NULL) { 1957 dev_err(&i2c->dev, 1958 "%s: unable to allocate memory for state\n", __func__); 1959 goto error; 1960 } 1961 1962 /* setup the state */ 1963 state->config = config; 1964 state->i2c = i2c; 1965 1966 /* create dvb_frontend */ 1967 memcpy(&state->frontend.ops, &mb86a20s_ops, 1968 sizeof(struct dvb_frontend_ops)); 1969 state->frontend.demodulator_priv = state; 1970 1971 /* Check if it is a mb86a20s frontend */ 1972 rev = mb86a20s_readreg(state, 0); 1973 1974 if (rev == 0x13) { 1975 dev_info(&i2c->dev, 1976 "Detected a Fujitsu mb86a20s frontend\n"); 1977 } else { 1978 dev_dbg(&i2c->dev, 1979 "Frontend revision %d is unknown - aborting.\n", 1980 rev); 1981 goto error; 1982 } 1983 1984 return &state->frontend; 1985 1986 error: 1987 kfree(state); 1988 return NULL; 1989 } 1990 EXPORT_SYMBOL(mb86a20s_attach); 1991 1992 static struct dvb_frontend_ops mb86a20s_ops = { 1993 .delsys = { SYS_ISDBT }, 1994 /* Use dib8000 values per default */ 1995 .info = { 1996 .name = "Fujitsu mb86A20s", 1997 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER | 1998 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1999 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 2000 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2001 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | 2002 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 2003 /* Actually, those values depend on the used tuner */ 2004 .frequency_min = 45000000, 2005 .frequency_max = 864000000, 2006 .frequency_stepsize = 62500, 2007 }, 2008 2009 .release = mb86a20s_release, 2010 2011 .init = mb86a20s_initfe, 2012 .set_frontend = mb86a20s_set_frontend, 2013 .get_frontend = mb86a20s_get_frontend_dummy, 2014 .read_status = mb86a20s_read_status_and_stats, 2015 .read_signal_strength = mb86a20s_read_signal_strength_from_cache, 2016 .tune = mb86a20s_tune, 2017 }; 2018 2019 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); 2020 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 2021 MODULE_LICENSE("GPL"); 2022