1 /* 2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver 3 * 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <asm/div64.h> 19 20 #include "dvb_frontend.h" 21 #include "mb86a20s.h" 22 23 #define NUM_LAYERS 3 24 25 enum mb86a20s_bandwidth { 26 MB86A20S_13SEG = 0, 27 MB86A20S_13SEG_PARTIAL = 1, 28 MB86A20S_1SEG = 2, 29 MB86A20S_3SEG = 3, 30 }; 31 32 static u8 mb86a20s_subchannel[] = { 33 0xb0, 0xc0, 0xd0, 0xe0, 34 0xf0, 0x00, 0x10, 0x20, 35 }; 36 37 struct mb86a20s_state { 38 struct i2c_adapter *i2c; 39 const struct mb86a20s_config *config; 40 u32 last_frequency; 41 42 struct dvb_frontend frontend; 43 44 u32 if_freq; 45 enum mb86a20s_bandwidth bw; 46 bool inversion; 47 u32 subchannel; 48 49 u32 estimated_rate[NUM_LAYERS]; 50 unsigned long get_strength_time; 51 52 bool need_init; 53 }; 54 55 struct regdata { 56 u8 reg; 57 u8 data; 58 }; 59 60 #define BER_SAMPLING_RATE 1 /* Seconds */ 61 62 /* 63 * Initialization sequence: Use whatevere default values that PV SBTVD 64 * does on its initialisation, obtained via USB snoop 65 */ 66 static struct regdata mb86a20s_init1[] = { 67 { 0x70, 0x0f }, 68 { 0x70, 0xff }, 69 { 0x08, 0x01 }, 70 { 0x50, 0xd1 }, { 0x51, 0x20 }, 71 }; 72 73 static struct regdata mb86a20s_init2[] = { 74 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, 75 { 0x3b, 0x21 }, 76 { 0x3c, 0x38 }, 77 { 0x01, 0x0d }, 78 { 0x04, 0x08 }, { 0x05, 0x03 }, 79 { 0x04, 0x0e }, { 0x05, 0x00 }, 80 { 0x04, 0x0f }, { 0x05, 0x37 }, 81 { 0x04, 0x0b }, { 0x05, 0x78 }, 82 { 0x04, 0x00 }, { 0x05, 0x00 }, 83 { 0x04, 0x01 }, { 0x05, 0x1e }, 84 { 0x04, 0x02 }, { 0x05, 0x07 }, 85 { 0x04, 0x03 }, { 0x05, 0xd0 }, 86 { 0x04, 0x09 }, { 0x05, 0x00 }, 87 { 0x04, 0x0a }, { 0x05, 0xff }, 88 { 0x04, 0x27 }, { 0x05, 0x00 }, 89 { 0x04, 0x28 }, { 0x05, 0x00 }, 90 { 0x04, 0x1e }, { 0x05, 0x00 }, 91 { 0x04, 0x29 }, { 0x05, 0x64 }, 92 { 0x04, 0x32 }, { 0x05, 0x02 }, 93 { 0x04, 0x14 }, { 0x05, 0x02 }, 94 { 0x04, 0x04 }, { 0x05, 0x00 }, 95 { 0x04, 0x05 }, { 0x05, 0x22 }, 96 { 0x04, 0x06 }, { 0x05, 0x0e }, 97 { 0x04, 0x07 }, { 0x05, 0xd8 }, 98 { 0x04, 0x12 }, { 0x05, 0x00 }, 99 { 0x04, 0x13 }, { 0x05, 0xff }, 100 { 0x04, 0x15 }, { 0x05, 0x4e }, 101 { 0x04, 0x16 }, { 0x05, 0x20 }, 102 103 /* 104 * On this demod, when the bit count reaches the count below, 105 * it collects the bit error count. The bit counters are initialized 106 * to 65535 here. This warrants that all of them will be quickly 107 * calculated when device gets locked. As TMCC is parsed, the values 108 * will be adjusted later in the driver's code. 109 */ 110 { 0x52, 0x01 }, /* Turn on BER before Viterbi */ 111 { 0x50, 0xa7 }, { 0x51, 0x00 }, 112 { 0x50, 0xa8 }, { 0x51, 0xff }, 113 { 0x50, 0xa9 }, { 0x51, 0xff }, 114 { 0x50, 0xaa }, { 0x51, 0x00 }, 115 { 0x50, 0xab }, { 0x51, 0xff }, 116 { 0x50, 0xac }, { 0x51, 0xff }, 117 { 0x50, 0xad }, { 0x51, 0x00 }, 118 { 0x50, 0xae }, { 0x51, 0xff }, 119 { 0x50, 0xaf }, { 0x51, 0xff }, 120 121 /* 122 * On this demod, post BER counts blocks. When the count reaches the 123 * value below, it collects the block error count. The block counters 124 * are initialized to 127 here. This warrants that all of them will be 125 * quickly calculated when device gets locked. As TMCC is parsed, the 126 * values will be adjusted later in the driver's code. 127 */ 128 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */ 129 { 0x50, 0xdc }, { 0x51, 0x00 }, 130 { 0x50, 0xdd }, { 0x51, 0x7f }, 131 { 0x50, 0xde }, { 0x51, 0x00 }, 132 { 0x50, 0xdf }, { 0x51, 0x7f }, 133 { 0x50, 0xe0 }, { 0x51, 0x00 }, 134 { 0x50, 0xe1 }, { 0x51, 0x7f }, 135 136 /* 137 * On this demod, when the block count reaches the count below, 138 * it collects the block error count. The block counters are initialized 139 * to 127 here. This warrants that all of them will be quickly 140 * calculated when device gets locked. As TMCC is parsed, the values 141 * will be adjusted later in the driver's code. 142 */ 143 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */ 144 { 0x50, 0xb2 }, { 0x51, 0x00 }, 145 { 0x50, 0xb3 }, { 0x51, 0x7f }, 146 { 0x50, 0xb4 }, { 0x51, 0x00 }, 147 { 0x50, 0xb5 }, { 0x51, 0x7f }, 148 { 0x50, 0xb6 }, { 0x51, 0x00 }, 149 { 0x50, 0xb7 }, { 0x51, 0x7f }, 150 151 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */ 152 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ 153 { 0x45, 0x04 }, /* CN symbol 4 */ 154 { 0x48, 0x04 }, /* CN manual mode */ 155 156 { 0x50, 0xd6 }, { 0x51, 0x1f }, 157 { 0x50, 0xd2 }, { 0x51, 0x03 }, 158 { 0x50, 0xd7 }, { 0x51, 0xbf }, 159 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff }, 160 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c }, 161 162 { 0x04, 0x40 }, { 0x05, 0x00 }, 163 { 0x28, 0x00 }, { 0x2b, 0x08 }, 164 { 0x28, 0x05 }, { 0x2b, 0x00 }, 165 { 0x1c, 0x01 }, 166 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f }, 167 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 }, 168 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 }, 169 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 }, 170 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 }, 171 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, 172 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 }, 173 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 }, 174 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b }, 175 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 }, 176 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d }, 177 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 }, 178 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b }, 179 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 180 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 }, 181 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 }, 182 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 }, 183 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, 184 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, 185 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef }, 186 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 }, 187 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 }, 188 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d }, 189 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 }, 190 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba }, 191 { 0x50, 0x1e }, { 0x51, 0x5d }, 192 { 0x50, 0x22 }, { 0x51, 0x00 }, 193 { 0x50, 0x23 }, { 0x51, 0xc8 }, 194 { 0x50, 0x24 }, { 0x51, 0x00 }, 195 { 0x50, 0x25 }, { 0x51, 0xf0 }, 196 { 0x50, 0x26 }, { 0x51, 0x00 }, 197 { 0x50, 0x27 }, { 0x51, 0xc3 }, 198 { 0x50, 0x39 }, { 0x51, 0x02 }, 199 { 0xec, 0x0f }, 200 { 0xeb, 0x1f }, 201 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 202 { 0xd0, 0x00 }, 203 }; 204 205 static struct regdata mb86a20s_reset_reception[] = { 206 { 0x70, 0xf0 }, 207 { 0x70, 0xff }, 208 { 0x08, 0x01 }, 209 { 0x08, 0x00 }, 210 }; 211 212 static struct regdata mb86a20s_per_ber_reset[] = { 213 { 0x53, 0x00 }, /* pre BER Counter reset */ 214 { 0x53, 0x07 }, 215 216 { 0x5f, 0x00 }, /* post BER Counter reset */ 217 { 0x5f, 0x07 }, 218 219 { 0x50, 0xb1 }, /* PER Counter reset */ 220 { 0x51, 0x07 }, 221 { 0x51, 0x00 }, 222 }; 223 224 /* 225 * I2C read/write functions and macros 226 */ 227 228 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, 229 u8 i2c_addr, u8 reg, u8 data) 230 { 231 u8 buf[] = { reg, data }; 232 struct i2c_msg msg = { 233 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 234 }; 235 int rc; 236 237 rc = i2c_transfer(state->i2c, &msg, 1); 238 if (rc != 1) { 239 dev_err(&state->i2c->dev, 240 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", 241 __func__, rc, reg, data); 242 return rc; 243 } 244 245 return 0; 246 } 247 248 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, 249 u8 i2c_addr, struct regdata *rd, int size) 250 { 251 int i, rc; 252 253 for (i = 0; i < size; i++) { 254 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, 255 rd[i].data); 256 if (rc < 0) 257 return rc; 258 } 259 return 0; 260 } 261 262 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, 263 u8 i2c_addr, u8 reg) 264 { 265 u8 val; 266 int rc; 267 struct i2c_msg msg[] = { 268 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 269 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } 270 }; 271 272 rc = i2c_transfer(state->i2c, msg, 2); 273 274 if (rc != 2) { 275 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", 276 __func__, reg, rc); 277 return (rc < 0) ? rc : -EIO; 278 } 279 280 return val; 281 } 282 283 #define mb86a20s_readreg(state, reg) \ 284 mb86a20s_i2c_readreg(state, state->config->demod_address, reg) 285 #define mb86a20s_writereg(state, reg, val) \ 286 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) 287 #define mb86a20s_writeregdata(state, regdata) \ 288 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ 289 regdata, ARRAY_SIZE(regdata)) 290 291 /* 292 * Ancillary internal routines (likely compiled inlined) 293 * 294 * The functions below assume that gateway lock has already obtained 295 */ 296 297 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status) 298 { 299 struct mb86a20s_state *state = fe->demodulator_priv; 300 int val; 301 302 *status = 0; 303 304 val = mb86a20s_readreg(state, 0x0a) & 0xf; 305 if (val < 0) 306 return val; 307 308 if (val >= 2) 309 *status |= FE_HAS_SIGNAL; 310 311 if (val >= 4) 312 *status |= FE_HAS_CARRIER; 313 314 if (val >= 5) 315 *status |= FE_HAS_VITERBI; 316 317 if (val >= 7) 318 *status |= FE_HAS_SYNC; 319 320 if (val >= 8) /* Maybe 9? */ 321 *status |= FE_HAS_LOCK; 322 323 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", 324 __func__, *status, val); 325 326 return val; 327 } 328 329 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) 330 { 331 struct mb86a20s_state *state = fe->demodulator_priv; 332 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 333 int rc; 334 unsigned rf_max, rf_min, rf; 335 336 if (state->get_strength_time && 337 (!time_after(jiffies, state->get_strength_time))) 338 return c->strength.stat[0].uvalue; 339 340 /* Reset its value if an error happen */ 341 c->strength.stat[0].uvalue = 0; 342 343 /* Does a binary search to get RF strength */ 344 rf_max = 0xfff; 345 rf_min = 0; 346 do { 347 rf = (rf_max + rf_min) / 2; 348 rc = mb86a20s_writereg(state, 0x04, 0x1f); 349 if (rc < 0) 350 return rc; 351 rc = mb86a20s_writereg(state, 0x05, rf >> 8); 352 if (rc < 0) 353 return rc; 354 rc = mb86a20s_writereg(state, 0x04, 0x20); 355 if (rc < 0) 356 return rc; 357 rc = mb86a20s_writereg(state, 0x05, rf); 358 if (rc < 0) 359 return rc; 360 361 rc = mb86a20s_readreg(state, 0x02); 362 if (rc < 0) 363 return rc; 364 if (rc & 0x08) 365 rf_min = (rf_max + rf_min) / 2; 366 else 367 rf_max = (rf_max + rf_min) / 2; 368 if (rf_max - rf_min < 4) { 369 rf = (rf_max + rf_min) / 2; 370 371 /* Rescale it from 2^12 (4096) to 2^16 */ 372 rf = rf << (16 - 12); 373 if (rf) 374 rf |= (1 << 12) - 1; 375 376 dev_dbg(&state->i2c->dev, 377 "%s: signal strength = %d (%d < RF=%d < %d)\n", 378 __func__, rf, rf_min, rf >> 4, rf_max); 379 c->strength.stat[0].uvalue = rf; 380 state->get_strength_time = jiffies + 381 msecs_to_jiffies(1000); 382 return 0; 383 } 384 } while (1); 385 } 386 387 static int mb86a20s_get_modulation(struct mb86a20s_state *state, 388 unsigned layer) 389 { 390 int rc; 391 static unsigned char reg[] = { 392 [0] = 0x86, /* Layer A */ 393 [1] = 0x8a, /* Layer B */ 394 [2] = 0x8e, /* Layer C */ 395 }; 396 397 if (layer >= ARRAY_SIZE(reg)) 398 return -EINVAL; 399 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 400 if (rc < 0) 401 return rc; 402 rc = mb86a20s_readreg(state, 0x6e); 403 if (rc < 0) 404 return rc; 405 switch ((rc >> 4) & 0x07) { 406 case 0: 407 return DQPSK; 408 case 1: 409 return QPSK; 410 case 2: 411 return QAM_16; 412 case 3: 413 return QAM_64; 414 default: 415 return QAM_AUTO; 416 } 417 } 418 419 static int mb86a20s_get_fec(struct mb86a20s_state *state, 420 unsigned layer) 421 { 422 int rc; 423 424 static unsigned char reg[] = { 425 [0] = 0x87, /* Layer A */ 426 [1] = 0x8b, /* Layer B */ 427 [2] = 0x8f, /* Layer C */ 428 }; 429 430 if (layer >= ARRAY_SIZE(reg)) 431 return -EINVAL; 432 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 433 if (rc < 0) 434 return rc; 435 rc = mb86a20s_readreg(state, 0x6e); 436 if (rc < 0) 437 return rc; 438 switch ((rc >> 4) & 0x07) { 439 case 0: 440 return FEC_1_2; 441 case 1: 442 return FEC_2_3; 443 case 2: 444 return FEC_3_4; 445 case 3: 446 return FEC_5_6; 447 case 4: 448 return FEC_7_8; 449 default: 450 return FEC_AUTO; 451 } 452 } 453 454 static int mb86a20s_get_interleaving(struct mb86a20s_state *state, 455 unsigned layer) 456 { 457 int rc; 458 int interleaving[] = { 459 0, 1, 2, 4, 8 460 }; 461 462 static unsigned char reg[] = { 463 [0] = 0x88, /* Layer A */ 464 [1] = 0x8c, /* Layer B */ 465 [2] = 0x90, /* Layer C */ 466 }; 467 468 if (layer >= ARRAY_SIZE(reg)) 469 return -EINVAL; 470 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 471 if (rc < 0) 472 return rc; 473 rc = mb86a20s_readreg(state, 0x6e); 474 if (rc < 0) 475 return rc; 476 477 return interleaving[(rc >> 4) & 0x07]; 478 } 479 480 static int mb86a20s_get_segment_count(struct mb86a20s_state *state, 481 unsigned layer) 482 { 483 int rc, count; 484 static unsigned char reg[] = { 485 [0] = 0x89, /* Layer A */ 486 [1] = 0x8d, /* Layer B */ 487 [2] = 0x91, /* Layer C */ 488 }; 489 490 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 491 492 if (layer >= ARRAY_SIZE(reg)) 493 return -EINVAL; 494 495 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 496 if (rc < 0) 497 return rc; 498 rc = mb86a20s_readreg(state, 0x6e); 499 if (rc < 0) 500 return rc; 501 count = (rc >> 4) & 0x0f; 502 503 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); 504 505 return count; 506 } 507 508 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) 509 { 510 struct mb86a20s_state *state = fe->demodulator_priv; 511 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 512 513 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 514 515 /* Fixed parameters */ 516 c->delivery_system = SYS_ISDBT; 517 c->bandwidth_hz = 6000000; 518 519 /* Initialize values that will be later autodetected */ 520 c->isdbt_layer_enabled = 0; 521 c->transmission_mode = TRANSMISSION_MODE_AUTO; 522 c->guard_interval = GUARD_INTERVAL_AUTO; 523 c->isdbt_sb_mode = 0; 524 c->isdbt_sb_segment_count = 0; 525 } 526 527 /* 528 * Estimates the bit rate using the per-segment bit rate given by 529 * ABNT/NBR 15601 spec (table 4). 530 */ 531 static u32 isdbt_rate[3][5][4] = { 532 { /* DQPSK/QPSK */ 533 { 280850, 312060, 330420, 340430 }, /* 1/2 */ 534 { 374470, 416080, 440560, 453910 }, /* 2/3 */ 535 { 421280, 468090, 495630, 510650 }, /* 3/4 */ 536 { 468090, 520100, 550700, 567390 }, /* 5/6 */ 537 { 491500, 546110, 578230, 595760 }, /* 7/8 */ 538 }, { /* QAM16 */ 539 { 561710, 624130, 660840, 680870 }, /* 1/2 */ 540 { 748950, 832170, 881120, 907820 }, /* 2/3 */ 541 { 842570, 936190, 991260, 1021300 }, /* 3/4 */ 542 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ 543 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ 544 }, { /* QAM64 */ 545 { 842570, 936190, 991260, 1021300 }, /* 1/2 */ 546 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ 547 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ 548 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ 549 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ 550 } 551 }; 552 553 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, 554 u32 modulation, u32 forward_error_correction, 555 u32 guard_interval, 556 u32 segment) 557 { 558 struct mb86a20s_state *state = fe->demodulator_priv; 559 u32 rate; 560 int mod, fec, guard; 561 562 /* 563 * If modulation/fec/guard is not detected, the default is 564 * to consider the lowest bit rate, to avoid taking too long time 565 * to get BER. 566 */ 567 switch (modulation) { 568 case DQPSK: 569 case QPSK: 570 default: 571 mod = 0; 572 break; 573 case QAM_16: 574 mod = 1; 575 break; 576 case QAM_64: 577 mod = 2; 578 break; 579 } 580 581 switch (forward_error_correction) { 582 default: 583 case FEC_1_2: 584 case FEC_AUTO: 585 fec = 0; 586 break; 587 case FEC_2_3: 588 fec = 1; 589 break; 590 case FEC_3_4: 591 fec = 2; 592 break; 593 case FEC_5_6: 594 fec = 3; 595 break; 596 case FEC_7_8: 597 fec = 4; 598 break; 599 } 600 601 switch (guard_interval) { 602 default: 603 case GUARD_INTERVAL_1_4: 604 guard = 0; 605 break; 606 case GUARD_INTERVAL_1_8: 607 guard = 1; 608 break; 609 case GUARD_INTERVAL_1_16: 610 guard = 2; 611 break; 612 case GUARD_INTERVAL_1_32: 613 guard = 3; 614 break; 615 } 616 617 /* Samples BER at BER_SAMPLING_RATE seconds */ 618 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE; 619 620 /* Avoids sampling too quickly or to overflow the register */ 621 if (rate < 256) 622 rate = 256; 623 else if (rate > (1 << 24) - 1) 624 rate = (1 << 24) - 1; 625 626 dev_dbg(&state->i2c->dev, 627 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", 628 __func__, 'A' + layer, 629 segment * isdbt_rate[mod][fec][guard]/1000, 630 rate, rate); 631 632 state->estimated_rate[layer] = rate; 633 } 634 635 static int mb86a20s_get_frontend(struct dvb_frontend *fe) 636 { 637 struct mb86a20s_state *state = fe->demodulator_priv; 638 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 639 int layer, rc; 640 641 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 642 643 /* Reset frontend cache to default values */ 644 mb86a20s_reset_frontend_cache(fe); 645 646 /* Check for partial reception */ 647 rc = mb86a20s_writereg(state, 0x6d, 0x85); 648 if (rc < 0) 649 return rc; 650 rc = mb86a20s_readreg(state, 0x6e); 651 if (rc < 0) 652 return rc; 653 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; 654 655 /* Get per-layer data */ 656 657 for (layer = 0; layer < NUM_LAYERS; layer++) { 658 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", 659 __func__, 'A' + layer); 660 661 rc = mb86a20s_get_segment_count(state, layer); 662 if (rc < 0) 663 goto noperlayer_error; 664 if (rc >= 0 && rc < 14) { 665 c->layer[layer].segment_count = rc; 666 } else { 667 c->layer[layer].segment_count = 0; 668 state->estimated_rate[layer] = 0; 669 continue; 670 } 671 c->isdbt_layer_enabled |= 1 << layer; 672 rc = mb86a20s_get_modulation(state, layer); 673 if (rc < 0) 674 goto noperlayer_error; 675 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", 676 __func__, rc); 677 c->layer[layer].modulation = rc; 678 rc = mb86a20s_get_fec(state, layer); 679 if (rc < 0) 680 goto noperlayer_error; 681 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", 682 __func__, rc); 683 c->layer[layer].fec = rc; 684 rc = mb86a20s_get_interleaving(state, layer); 685 if (rc < 0) 686 goto noperlayer_error; 687 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", 688 __func__, rc); 689 c->layer[layer].interleaving = rc; 690 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation, 691 c->layer[layer].fec, 692 c->guard_interval, 693 c->layer[layer].segment_count); 694 } 695 696 rc = mb86a20s_writereg(state, 0x6d, 0x84); 697 if (rc < 0) 698 return rc; 699 if ((rc & 0x60) == 0x20) { 700 c->isdbt_sb_mode = 1; 701 /* At least, one segment should exist */ 702 if (!c->isdbt_sb_segment_count) 703 c->isdbt_sb_segment_count = 1; 704 } 705 706 /* Get transmission mode and guard interval */ 707 rc = mb86a20s_readreg(state, 0x07); 708 if (rc < 0) 709 return rc; 710 c->transmission_mode = TRANSMISSION_MODE_AUTO; 711 if ((rc & 0x60) == 0x20) { 712 /* Only modes 2 and 3 are supported */ 713 switch ((rc >> 2) & 0x03) { 714 case 1: 715 c->transmission_mode = TRANSMISSION_MODE_4K; 716 break; 717 case 2: 718 c->transmission_mode = TRANSMISSION_MODE_8K; 719 break; 720 } 721 } 722 c->guard_interval = GUARD_INTERVAL_AUTO; 723 if (!(rc & 0x10)) { 724 /* Guard interval 1/32 is not supported */ 725 switch (rc & 0x3) { 726 case 0: 727 c->guard_interval = GUARD_INTERVAL_1_4; 728 break; 729 case 1: 730 c->guard_interval = GUARD_INTERVAL_1_8; 731 break; 732 case 2: 733 c->guard_interval = GUARD_INTERVAL_1_16; 734 break; 735 } 736 } 737 return 0; 738 739 noperlayer_error: 740 741 /* per-layer info is incomplete; discard all per-layer */ 742 c->isdbt_layer_enabled = 0; 743 744 return rc; 745 } 746 747 static int mb86a20s_reset_counters(struct dvb_frontend *fe) 748 { 749 struct mb86a20s_state *state = fe->demodulator_priv; 750 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 751 int rc, val; 752 753 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 754 755 /* Reset the counters, if the channel changed */ 756 if (state->last_frequency != c->frequency) { 757 memset(&c->cnr, 0, sizeof(c->cnr)); 758 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); 759 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); 760 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 761 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 762 memset(&c->block_error, 0, sizeof(c->block_error)); 763 memset(&c->block_count, 0, sizeof(c->block_count)); 764 765 state->last_frequency = c->frequency; 766 } 767 768 /* Clear status for most stats */ 769 770 /* BER/PER counter reset */ 771 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); 772 if (rc < 0) 773 goto err; 774 775 /* CNR counter reset */ 776 rc = mb86a20s_readreg(state, 0x45); 777 if (rc < 0) 778 goto err; 779 val = rc; 780 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 781 if (rc < 0) 782 goto err; 783 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 784 if (rc < 0) 785 goto err; 786 787 /* MER counter reset */ 788 rc = mb86a20s_writereg(state, 0x50, 0x50); 789 if (rc < 0) 790 goto err; 791 rc = mb86a20s_readreg(state, 0x51); 792 if (rc < 0) 793 goto err; 794 val = rc; 795 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 796 if (rc < 0) 797 goto err; 798 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 799 if (rc < 0) 800 goto err; 801 802 goto ok; 803 err: 804 dev_err(&state->i2c->dev, 805 "%s: Can't reset FE statistics (error %d).\n", 806 __func__, rc); 807 ok: 808 return rc; 809 } 810 811 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe, 812 unsigned layer, 813 u32 *error, u32 *count) 814 { 815 struct mb86a20s_state *state = fe->demodulator_priv; 816 int rc, val; 817 818 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 819 820 if (layer >= NUM_LAYERS) 821 return -EINVAL; 822 823 /* Check if the BER measures are already available */ 824 rc = mb86a20s_readreg(state, 0x54); 825 if (rc < 0) 826 return rc; 827 828 /* Check if data is available for that layer */ 829 if (!(rc & (1 << layer))) { 830 dev_dbg(&state->i2c->dev, 831 "%s: preBER for layer %c is not available yet.\n", 832 __func__, 'A' + layer); 833 return -EBUSY; 834 } 835 836 /* Read Bit Error Count */ 837 rc = mb86a20s_readreg(state, 0x55 + layer * 3); 838 if (rc < 0) 839 return rc; 840 *error = rc << 16; 841 rc = mb86a20s_readreg(state, 0x56 + layer * 3); 842 if (rc < 0) 843 return rc; 844 *error |= rc << 8; 845 rc = mb86a20s_readreg(state, 0x57 + layer * 3); 846 if (rc < 0) 847 return rc; 848 *error |= rc; 849 850 dev_dbg(&state->i2c->dev, 851 "%s: bit error before Viterbi for layer %c: %d.\n", 852 __func__, 'A' + layer, *error); 853 854 /* Read Bit Count */ 855 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 856 if (rc < 0) 857 return rc; 858 rc = mb86a20s_readreg(state, 0x51); 859 if (rc < 0) 860 return rc; 861 *count = rc << 16; 862 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 863 if (rc < 0) 864 return rc; 865 rc = mb86a20s_readreg(state, 0x51); 866 if (rc < 0) 867 return rc; 868 *count |= rc << 8; 869 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 870 if (rc < 0) 871 return rc; 872 rc = mb86a20s_readreg(state, 0x51); 873 if (rc < 0) 874 return rc; 875 *count |= rc; 876 877 dev_dbg(&state->i2c->dev, 878 "%s: bit count before Viterbi for layer %c: %d.\n", 879 __func__, 'A' + layer, *count); 880 881 882 /* 883 * As we get TMCC data from the frontend, we can better estimate the 884 * BER bit counters, in order to do the BER measure during a longer 885 * time. Use those data, if available, to update the bit count 886 * measure. 887 */ 888 889 if (state->estimated_rate[layer] 890 && state->estimated_rate[layer] != *count) { 891 dev_dbg(&state->i2c->dev, 892 "%s: updating layer %c preBER counter to %d.\n", 893 __func__, 'A' + layer, state->estimated_rate[layer]); 894 895 /* Turn off BER before Viterbi */ 896 rc = mb86a20s_writereg(state, 0x52, 0x00); 897 898 /* Update counter for this layer */ 899 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 900 if (rc < 0) 901 return rc; 902 rc = mb86a20s_writereg(state, 0x51, 903 state->estimated_rate[layer] >> 16); 904 if (rc < 0) 905 return rc; 906 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 907 if (rc < 0) 908 return rc; 909 rc = mb86a20s_writereg(state, 0x51, 910 state->estimated_rate[layer] >> 8); 911 if (rc < 0) 912 return rc; 913 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 914 if (rc < 0) 915 return rc; 916 rc = mb86a20s_writereg(state, 0x51, 917 state->estimated_rate[layer]); 918 if (rc < 0) 919 return rc; 920 921 /* Turn on BER before Viterbi */ 922 rc = mb86a20s_writereg(state, 0x52, 0x01); 923 924 /* Reset all preBER counters */ 925 rc = mb86a20s_writereg(state, 0x53, 0x00); 926 if (rc < 0) 927 return rc; 928 rc = mb86a20s_writereg(state, 0x53, 0x07); 929 } else { 930 /* Reset counter to collect new data */ 931 rc = mb86a20s_readreg(state, 0x53); 932 if (rc < 0) 933 return rc; 934 val = rc; 935 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); 936 if (rc < 0) 937 return rc; 938 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); 939 } 940 941 return rc; 942 } 943 944 static int mb86a20s_get_post_ber(struct dvb_frontend *fe, 945 unsigned layer, 946 u32 *error, u32 *count) 947 { 948 struct mb86a20s_state *state = fe->demodulator_priv; 949 u32 counter, collect_rate; 950 int rc, val; 951 952 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 953 954 if (layer >= NUM_LAYERS) 955 return -EINVAL; 956 957 /* Check if the BER measures are already available */ 958 rc = mb86a20s_readreg(state, 0x60); 959 if (rc < 0) 960 return rc; 961 962 /* Check if data is available for that layer */ 963 if (!(rc & (1 << layer))) { 964 dev_dbg(&state->i2c->dev, 965 "%s: post BER for layer %c is not available yet.\n", 966 __func__, 'A' + layer); 967 return -EBUSY; 968 } 969 970 /* Read Bit Error Count */ 971 rc = mb86a20s_readreg(state, 0x64 + layer * 3); 972 if (rc < 0) 973 return rc; 974 *error = rc << 16; 975 rc = mb86a20s_readreg(state, 0x65 + layer * 3); 976 if (rc < 0) 977 return rc; 978 *error |= rc << 8; 979 rc = mb86a20s_readreg(state, 0x66 + layer * 3); 980 if (rc < 0) 981 return rc; 982 *error |= rc; 983 984 dev_dbg(&state->i2c->dev, 985 "%s: post bit error for layer %c: %d.\n", 986 __func__, 'A' + layer, *error); 987 988 /* Read Bit Count */ 989 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 990 if (rc < 0) 991 return rc; 992 rc = mb86a20s_readreg(state, 0x51); 993 if (rc < 0) 994 return rc; 995 counter = rc << 8; 996 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 997 if (rc < 0) 998 return rc; 999 rc = mb86a20s_readreg(state, 0x51); 1000 if (rc < 0) 1001 return rc; 1002 counter |= rc; 1003 *count = counter * 204 * 8; 1004 1005 dev_dbg(&state->i2c->dev, 1006 "%s: post bit count for layer %c: %d.\n", 1007 __func__, 'A' + layer, *count); 1008 1009 /* 1010 * As we get TMCC data from the frontend, we can better estimate the 1011 * BER bit counters, in order to do the BER measure during a longer 1012 * time. Use those data, if available, to update the bit count 1013 * measure. 1014 */ 1015 1016 if (!state->estimated_rate[layer]) 1017 goto reset_measurement; 1018 1019 collect_rate = state->estimated_rate[layer] / 204 / 8; 1020 if (collect_rate < 32) 1021 collect_rate = 32; 1022 if (collect_rate > 65535) 1023 collect_rate = 65535; 1024 if (collect_rate != counter) { 1025 dev_dbg(&state->i2c->dev, 1026 "%s: updating postBER counter on layer %c to %d.\n", 1027 __func__, 'A' + layer, collect_rate); 1028 1029 /* Turn off BER after Viterbi */ 1030 rc = mb86a20s_writereg(state, 0x5e, 0x00); 1031 1032 /* Update counter for this layer */ 1033 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1034 if (rc < 0) 1035 return rc; 1036 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1037 if (rc < 0) 1038 return rc; 1039 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1040 if (rc < 0) 1041 return rc; 1042 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1043 if (rc < 0) 1044 return rc; 1045 1046 /* Turn on BER after Viterbi */ 1047 rc = mb86a20s_writereg(state, 0x5e, 0x07); 1048 1049 /* Reset all preBER counters */ 1050 rc = mb86a20s_writereg(state, 0x5f, 0x00); 1051 if (rc < 0) 1052 return rc; 1053 rc = mb86a20s_writereg(state, 0x5f, 0x07); 1054 1055 return rc; 1056 } 1057 1058 reset_measurement: 1059 /* Reset counter to collect new data */ 1060 rc = mb86a20s_readreg(state, 0x5f); 1061 if (rc < 0) 1062 return rc; 1063 val = rc; 1064 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); 1065 if (rc < 0) 1066 return rc; 1067 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); 1068 1069 return rc; 1070 } 1071 1072 static int mb86a20s_get_blk_error(struct dvb_frontend *fe, 1073 unsigned layer, 1074 u32 *error, u32 *count) 1075 { 1076 struct mb86a20s_state *state = fe->demodulator_priv; 1077 int rc, val; 1078 u32 collect_rate; 1079 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1080 1081 if (layer >= NUM_LAYERS) 1082 return -EINVAL; 1083 1084 /* Check if the PER measures are already available */ 1085 rc = mb86a20s_writereg(state, 0x50, 0xb8); 1086 if (rc < 0) 1087 return rc; 1088 rc = mb86a20s_readreg(state, 0x51); 1089 if (rc < 0) 1090 return rc; 1091 1092 /* Check if data is available for that layer */ 1093 1094 if (!(rc & (1 << layer))) { 1095 dev_dbg(&state->i2c->dev, 1096 "%s: block counts for layer %c aren't available yet.\n", 1097 __func__, 'A' + layer); 1098 return -EBUSY; 1099 } 1100 1101 /* Read Packet error Count */ 1102 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); 1103 if (rc < 0) 1104 return rc; 1105 rc = mb86a20s_readreg(state, 0x51); 1106 if (rc < 0) 1107 return rc; 1108 *error = rc << 8; 1109 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); 1110 if (rc < 0) 1111 return rc; 1112 rc = mb86a20s_readreg(state, 0x51); 1113 if (rc < 0) 1114 return rc; 1115 *error |= rc; 1116 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n", 1117 __func__, 'A' + layer, *error); 1118 1119 /* Read Bit Count */ 1120 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1121 if (rc < 0) 1122 return rc; 1123 rc = mb86a20s_readreg(state, 0x51); 1124 if (rc < 0) 1125 return rc; 1126 *count = rc << 8; 1127 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1128 if (rc < 0) 1129 return rc; 1130 rc = mb86a20s_readreg(state, 0x51); 1131 if (rc < 0) 1132 return rc; 1133 *count |= rc; 1134 1135 dev_dbg(&state->i2c->dev, 1136 "%s: block count for layer %c: %d.\n", 1137 __func__, 'A' + layer, *count); 1138 1139 /* 1140 * As we get TMCC data from the frontend, we can better estimate the 1141 * BER bit counters, in order to do the BER measure during a longer 1142 * time. Use those data, if available, to update the bit count 1143 * measure. 1144 */ 1145 1146 if (!state->estimated_rate[layer]) 1147 goto reset_measurement; 1148 1149 collect_rate = state->estimated_rate[layer] / 204 / 8; 1150 if (collect_rate < 32) 1151 collect_rate = 32; 1152 if (collect_rate > 65535) 1153 collect_rate = 65535; 1154 1155 if (collect_rate != *count) { 1156 dev_dbg(&state->i2c->dev, 1157 "%s: updating PER counter on layer %c to %d.\n", 1158 __func__, 'A' + layer, collect_rate); 1159 1160 /* Stop PER measurement */ 1161 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1162 if (rc < 0) 1163 return rc; 1164 rc = mb86a20s_writereg(state, 0x51, 0x00); 1165 if (rc < 0) 1166 return rc; 1167 1168 /* Update this layer's counter */ 1169 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1170 if (rc < 0) 1171 return rc; 1172 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1173 if (rc < 0) 1174 return rc; 1175 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1176 if (rc < 0) 1177 return rc; 1178 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1179 if (rc < 0) 1180 return rc; 1181 1182 /* start PER measurement */ 1183 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1184 if (rc < 0) 1185 return rc; 1186 rc = mb86a20s_writereg(state, 0x51, 0x07); 1187 if (rc < 0) 1188 return rc; 1189 1190 /* Reset all counters to collect new data */ 1191 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1192 if (rc < 0) 1193 return rc; 1194 rc = mb86a20s_writereg(state, 0x51, 0x07); 1195 if (rc < 0) 1196 return rc; 1197 rc = mb86a20s_writereg(state, 0x51, 0x00); 1198 1199 return rc; 1200 } 1201 1202 reset_measurement: 1203 /* Reset counter to collect new data */ 1204 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1205 if (rc < 0) 1206 return rc; 1207 rc = mb86a20s_readreg(state, 0x51); 1208 if (rc < 0) 1209 return rc; 1210 val = rc; 1211 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); 1212 if (rc < 0) 1213 return rc; 1214 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); 1215 1216 return rc; 1217 } 1218 1219 struct linear_segments { 1220 unsigned x, y; 1221 }; 1222 1223 /* 1224 * All tables below return a dB/1000 measurement 1225 */ 1226 1227 static const struct linear_segments cnr_to_db_table[] = { 1228 { 19648, 0}, 1229 { 18187, 1000}, 1230 { 16534, 2000}, 1231 { 14823, 3000}, 1232 { 13161, 4000}, 1233 { 11622, 5000}, 1234 { 10279, 6000}, 1235 { 9089, 7000}, 1236 { 8042, 8000}, 1237 { 7137, 9000}, 1238 { 6342, 10000}, 1239 { 5641, 11000}, 1240 { 5030, 12000}, 1241 { 4474, 13000}, 1242 { 3988, 14000}, 1243 { 3556, 15000}, 1244 { 3180, 16000}, 1245 { 2841, 17000}, 1246 { 2541, 18000}, 1247 { 2276, 19000}, 1248 { 2038, 20000}, 1249 { 1800, 21000}, 1250 { 1625, 22000}, 1251 { 1462, 23000}, 1252 { 1324, 24000}, 1253 { 1175, 25000}, 1254 { 1063, 26000}, 1255 { 980, 27000}, 1256 { 907, 28000}, 1257 { 840, 29000}, 1258 { 788, 30000}, 1259 }; 1260 1261 static const struct linear_segments cnr_64qam_table[] = { 1262 { 3922688, 0}, 1263 { 3920384, 1000}, 1264 { 3902720, 2000}, 1265 { 3894784, 3000}, 1266 { 3882496, 4000}, 1267 { 3872768, 5000}, 1268 { 3858944, 6000}, 1269 { 3851520, 7000}, 1270 { 3838976, 8000}, 1271 { 3829248, 9000}, 1272 { 3818240, 10000}, 1273 { 3806976, 11000}, 1274 { 3791872, 12000}, 1275 { 3767040, 13000}, 1276 { 3720960, 14000}, 1277 { 3637504, 15000}, 1278 { 3498496, 16000}, 1279 { 3296000, 17000}, 1280 { 3031040, 18000}, 1281 { 2715392, 19000}, 1282 { 2362624, 20000}, 1283 { 1963264, 21000}, 1284 { 1649664, 22000}, 1285 { 1366784, 23000}, 1286 { 1120768, 24000}, 1287 { 890880, 25000}, 1288 { 723456, 26000}, 1289 { 612096, 27000}, 1290 { 518912, 28000}, 1291 { 448256, 29000}, 1292 { 388864, 30000}, 1293 }; 1294 1295 static const struct linear_segments cnr_16qam_table[] = { 1296 { 5314816, 0}, 1297 { 5219072, 1000}, 1298 { 5118720, 2000}, 1299 { 4998912, 3000}, 1300 { 4875520, 4000}, 1301 { 4736000, 5000}, 1302 { 4604160, 6000}, 1303 { 4458752, 7000}, 1304 { 4300288, 8000}, 1305 { 4092928, 9000}, 1306 { 3836160, 10000}, 1307 { 3521024, 11000}, 1308 { 3155968, 12000}, 1309 { 2756864, 13000}, 1310 { 2347008, 14000}, 1311 { 1955072, 15000}, 1312 { 1593600, 16000}, 1313 { 1297920, 17000}, 1314 { 1043968, 18000}, 1315 { 839680, 19000}, 1316 { 672256, 20000}, 1317 { 523008, 21000}, 1318 { 424704, 22000}, 1319 { 345088, 23000}, 1320 { 280064, 24000}, 1321 { 221440, 25000}, 1322 { 179712, 26000}, 1323 { 151040, 27000}, 1324 { 128512, 28000}, 1325 { 110080, 29000}, 1326 { 95744, 30000}, 1327 }; 1328 1329 static const struct linear_segments cnr_qpsk_table[] = { 1330 { 2834176, 0}, 1331 { 2683648, 1000}, 1332 { 2536960, 2000}, 1333 { 2391808, 3000}, 1334 { 2133248, 4000}, 1335 { 1906176, 5000}, 1336 { 1666560, 6000}, 1337 { 1422080, 7000}, 1338 { 1189632, 8000}, 1339 { 976384, 9000}, 1340 { 790272, 10000}, 1341 { 633344, 11000}, 1342 { 505600, 12000}, 1343 { 402944, 13000}, 1344 { 320768, 14000}, 1345 { 255488, 15000}, 1346 { 204032, 16000}, 1347 { 163072, 17000}, 1348 { 130304, 18000}, 1349 { 105216, 19000}, 1350 { 83456, 20000}, 1351 { 65024, 21000}, 1352 { 52480, 22000}, 1353 { 42752, 23000}, 1354 { 34560, 24000}, 1355 { 27136, 25000}, 1356 { 22016, 26000}, 1357 { 18432, 27000}, 1358 { 15616, 28000}, 1359 { 13312, 29000}, 1360 { 11520, 30000}, 1361 }; 1362 1363 static u32 interpolate_value(u32 value, const struct linear_segments *segments, 1364 unsigned len) 1365 { 1366 u64 tmp64; 1367 u32 dx, dy; 1368 int i, ret; 1369 1370 if (value >= segments[0].x) 1371 return segments[0].y; 1372 if (value < segments[len-1].x) 1373 return segments[len-1].y; 1374 1375 for (i = 1; i < len - 1; i++) { 1376 /* If value is identical, no need to interpolate */ 1377 if (value == segments[i].x) 1378 return segments[i].y; 1379 if (value > segments[i].x) 1380 break; 1381 } 1382 1383 /* Linear interpolation between the two (x,y) points */ 1384 dy = segments[i].y - segments[i - 1].y; 1385 dx = segments[i - 1].x - segments[i].x; 1386 tmp64 = value - segments[i].x; 1387 tmp64 *= dy; 1388 do_div(tmp64, dx); 1389 ret = segments[i].y - tmp64; 1390 1391 return ret; 1392 } 1393 1394 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe) 1395 { 1396 struct mb86a20s_state *state = fe->demodulator_priv; 1397 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1398 u32 cnr_linear, cnr; 1399 int rc, val; 1400 1401 /* Check if CNR is available */ 1402 rc = mb86a20s_readreg(state, 0x45); 1403 if (rc < 0) 1404 return rc; 1405 1406 if (!(rc & 0x40)) { 1407 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n", 1408 __func__); 1409 return -EBUSY; 1410 } 1411 val = rc; 1412 1413 rc = mb86a20s_readreg(state, 0x46); 1414 if (rc < 0) 1415 return rc; 1416 cnr_linear = rc << 8; 1417 1418 rc = mb86a20s_readreg(state, 0x46); 1419 if (rc < 0) 1420 return rc; 1421 cnr_linear |= rc; 1422 1423 cnr = interpolate_value(cnr_linear, 1424 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table)); 1425 1426 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 1427 c->cnr.stat[0].svalue = cnr; 1428 1429 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", 1430 __func__, cnr / 1000, cnr % 1000, cnr_linear); 1431 1432 /* CNR counter reset */ 1433 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 1434 if (rc < 0) 1435 return rc; 1436 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 1437 1438 return rc; 1439 } 1440 1441 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe) 1442 { 1443 struct mb86a20s_state *state = fe->demodulator_priv; 1444 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1445 u32 mer, cnr; 1446 int rc, val, layer; 1447 const struct linear_segments *segs; 1448 unsigned segs_len; 1449 1450 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1451 1452 /* Check if the measures are already available */ 1453 rc = mb86a20s_writereg(state, 0x50, 0x5b); 1454 if (rc < 0) 1455 return rc; 1456 rc = mb86a20s_readreg(state, 0x51); 1457 if (rc < 0) 1458 return rc; 1459 1460 /* Check if data is available */ 1461 if (!(rc & 0x01)) { 1462 dev_dbg(&state->i2c->dev, 1463 "%s: MER measures aren't available yet.\n", __func__); 1464 return -EBUSY; 1465 } 1466 1467 /* Read all layers */ 1468 for (layer = 0; layer < NUM_LAYERS; layer++) { 1469 if (!(c->isdbt_layer_enabled & (1 << layer))) { 1470 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1471 continue; 1472 } 1473 1474 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3); 1475 if (rc < 0) 1476 return rc; 1477 rc = mb86a20s_readreg(state, 0x51); 1478 if (rc < 0) 1479 return rc; 1480 mer = rc << 16; 1481 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3); 1482 if (rc < 0) 1483 return rc; 1484 rc = mb86a20s_readreg(state, 0x51); 1485 if (rc < 0) 1486 return rc; 1487 mer |= rc << 8; 1488 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3); 1489 if (rc < 0) 1490 return rc; 1491 rc = mb86a20s_readreg(state, 0x51); 1492 if (rc < 0) 1493 return rc; 1494 mer |= rc; 1495 1496 switch (c->layer[layer].modulation) { 1497 case DQPSK: 1498 case QPSK: 1499 segs = cnr_qpsk_table; 1500 segs_len = ARRAY_SIZE(cnr_qpsk_table); 1501 break; 1502 case QAM_16: 1503 segs = cnr_16qam_table; 1504 segs_len = ARRAY_SIZE(cnr_16qam_table); 1505 break; 1506 default: 1507 case QAM_64: 1508 segs = cnr_64qam_table; 1509 segs_len = ARRAY_SIZE(cnr_64qam_table); 1510 break; 1511 } 1512 cnr = interpolate_value(mer, segs, segs_len); 1513 1514 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL; 1515 c->cnr.stat[1 + layer].svalue = cnr; 1516 1517 dev_dbg(&state->i2c->dev, 1518 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n", 1519 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer); 1520 1521 } 1522 1523 /* Start a new MER measurement */ 1524 /* MER counter reset */ 1525 rc = mb86a20s_writereg(state, 0x50, 0x50); 1526 if (rc < 0) 1527 return rc; 1528 rc = mb86a20s_readreg(state, 0x51); 1529 if (rc < 0) 1530 return rc; 1531 val = rc; 1532 1533 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 1534 if (rc < 0) 1535 return rc; 1536 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 1537 if (rc < 0) 1538 return rc; 1539 1540 return 0; 1541 } 1542 1543 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) 1544 { 1545 struct mb86a20s_state *state = fe->demodulator_priv; 1546 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1547 int layer; 1548 1549 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1550 1551 /* Fill the length of each status counter */ 1552 1553 /* Only global stats */ 1554 c->strength.len = 1; 1555 1556 /* Per-layer stats - 3 layers + global */ 1557 c->cnr.len = NUM_LAYERS + 1; 1558 c->pre_bit_error.len = NUM_LAYERS + 1; 1559 c->pre_bit_count.len = NUM_LAYERS + 1; 1560 c->post_bit_error.len = NUM_LAYERS + 1; 1561 c->post_bit_count.len = NUM_LAYERS + 1; 1562 c->block_error.len = NUM_LAYERS + 1; 1563 c->block_count.len = NUM_LAYERS + 1; 1564 1565 /* Signal is always available */ 1566 c->strength.stat[0].scale = FE_SCALE_RELATIVE; 1567 c->strength.stat[0].uvalue = 0; 1568 1569 /* Put all of them at FE_SCALE_NOT_AVAILABLE */ 1570 for (layer = 0; layer < NUM_LAYERS + 1; layer++) { 1571 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1572 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1573 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1574 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1575 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1576 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1577 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1578 } 1579 } 1580 1581 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr) 1582 { 1583 struct mb86a20s_state *state = fe->demodulator_priv; 1584 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1585 int rc = 0, layer; 1586 u32 bit_error = 0, bit_count = 0; 1587 u32 t_pre_bit_error = 0, t_pre_bit_count = 0; 1588 u32 t_post_bit_error = 0, t_post_bit_count = 0; 1589 u32 block_error = 0, block_count = 0; 1590 u32 t_block_error = 0, t_block_count = 0; 1591 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0; 1592 int per_layers = 0; 1593 1594 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1595 1596 mb86a20s_get_main_CNR(fe); 1597 1598 /* Get per-layer stats */ 1599 mb86a20s_get_blk_error_layer_CNR(fe); 1600 1601 /* 1602 * At state 7, only CNR is available 1603 * For BER measures, state=9 is required 1604 * FIXME: we may get MER measures with state=8 1605 */ 1606 if (status_nr < 9) 1607 return 0; 1608 1609 for (layer = 0; layer < NUM_LAYERS; layer++) { 1610 if (c->isdbt_layer_enabled & (1 << layer)) { 1611 /* Layer is active and has rc segments */ 1612 active_layers++; 1613 1614 /* Handle BER before vterbi */ 1615 rc = mb86a20s_get_pre_ber(fe, layer, 1616 &bit_error, &bit_count); 1617 if (rc >= 0) { 1618 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1619 c->pre_bit_error.stat[1 + layer].uvalue += bit_error; 1620 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1621 c->pre_bit_count.stat[1 + layer].uvalue += bit_count; 1622 } else if (rc != -EBUSY) { 1623 /* 1624 * If an I/O error happened, 1625 * measures are now unavailable 1626 */ 1627 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1628 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1629 dev_err(&state->i2c->dev, 1630 "%s: Can't get BER for layer %c (error %d).\n", 1631 __func__, 'A' + layer, rc); 1632 } 1633 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1634 pre_ber_layers++; 1635 1636 /* Handle BER post vterbi */ 1637 rc = mb86a20s_get_post_ber(fe, layer, 1638 &bit_error, &bit_count); 1639 if (rc >= 0) { 1640 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1641 c->post_bit_error.stat[1 + layer].uvalue += bit_error; 1642 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1643 c->post_bit_count.stat[1 + layer].uvalue += bit_count; 1644 } else if (rc != -EBUSY) { 1645 /* 1646 * If an I/O error happened, 1647 * measures are now unavailable 1648 */ 1649 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1650 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1651 dev_err(&state->i2c->dev, 1652 "%s: Can't get BER for layer %c (error %d).\n", 1653 __func__, 'A' + layer, rc); 1654 } 1655 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1656 post_ber_layers++; 1657 1658 /* Handle Block errors for PER/UCB reports */ 1659 rc = mb86a20s_get_blk_error(fe, layer, 1660 &block_error, 1661 &block_count); 1662 if (rc >= 0) { 1663 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1664 c->block_error.stat[1 + layer].uvalue += block_error; 1665 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1666 c->block_count.stat[1 + layer].uvalue += block_count; 1667 } else if (rc != -EBUSY) { 1668 /* 1669 * If an I/O error happened, 1670 * measures are now unavailable 1671 */ 1672 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1673 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1674 dev_err(&state->i2c->dev, 1675 "%s: Can't get PER for layer %c (error %d).\n", 1676 __func__, 'A' + layer, rc); 1677 1678 } 1679 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1680 per_layers++; 1681 1682 /* Update total preBER */ 1683 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue; 1684 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue; 1685 1686 /* Update total postBER */ 1687 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue; 1688 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue; 1689 1690 /* Update total PER */ 1691 t_block_error += c->block_error.stat[1 + layer].uvalue; 1692 t_block_count += c->block_count.stat[1 + layer].uvalue; 1693 } 1694 } 1695 1696 /* 1697 * Start showing global count if at least one error count is 1698 * available. 1699 */ 1700 if (pre_ber_layers) { 1701 /* 1702 * At least one per-layer BER measure was read. We can now 1703 * calculate the total BER 1704 * 1705 * Total Bit Error/Count is calculated as the sum of the 1706 * bit errors on all active layers. 1707 */ 1708 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1709 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; 1710 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1711 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; 1712 } else { 1713 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1714 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1715 } 1716 1717 /* 1718 * Start showing global count if at least one error count is 1719 * available. 1720 */ 1721 if (post_ber_layers) { 1722 /* 1723 * At least one per-layer BER measure was read. We can now 1724 * calculate the total BER 1725 * 1726 * Total Bit Error/Count is calculated as the sum of the 1727 * bit errors on all active layers. 1728 */ 1729 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1730 c->post_bit_error.stat[0].uvalue = t_post_bit_error; 1731 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1732 c->post_bit_count.stat[0].uvalue = t_post_bit_count; 1733 } else { 1734 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1735 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1736 } 1737 1738 if (per_layers) { 1739 /* 1740 * At least one per-layer UCB measure was read. We can now 1741 * calculate the total UCB 1742 * 1743 * Total block Error/Count is calculated as the sum of the 1744 * block errors on all active layers. 1745 */ 1746 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1747 c->block_error.stat[0].uvalue = t_block_error; 1748 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1749 c->block_count.stat[0].uvalue = t_block_count; 1750 } else { 1751 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1752 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1753 } 1754 1755 return rc; 1756 } 1757 1758 /* 1759 * The functions below are called via DVB callbacks, so they need to 1760 * properly use the I2C gate control 1761 */ 1762 1763 static int mb86a20s_initfe(struct dvb_frontend *fe) 1764 { 1765 struct mb86a20s_state *state = fe->demodulator_priv; 1766 u64 pll; 1767 u32 fclk; 1768 int rc; 1769 u8 regD5 = 1, reg71, reg09 = 0x3a; 1770 1771 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1772 1773 if (fe->ops.i2c_gate_ctrl) 1774 fe->ops.i2c_gate_ctrl(fe, 0); 1775 1776 /* Initialize the frontend */ 1777 rc = mb86a20s_writeregdata(state, mb86a20s_init1); 1778 if (rc < 0) 1779 goto err; 1780 1781 if (!state->inversion) 1782 reg09 |= 0x04; 1783 rc = mb86a20s_writereg(state, 0x09, reg09); 1784 if (rc < 0) 1785 goto err; 1786 if (!state->bw) 1787 reg71 = 1; 1788 else 1789 reg71 = 0; 1790 rc = mb86a20s_writereg(state, 0x39, reg71); 1791 if (rc < 0) 1792 goto err; 1793 rc = mb86a20s_writereg(state, 0x71, state->bw); 1794 if (rc < 0) 1795 goto err; 1796 if (state->subchannel) { 1797 rc = mb86a20s_writereg(state, 0x44, state->subchannel); 1798 if (rc < 0) 1799 goto err; 1800 } 1801 1802 fclk = state->config->fclk; 1803 if (!fclk) 1804 fclk = 32571428; 1805 1806 /* Adjust IF frequency to match tuner */ 1807 if (fe->ops.tuner_ops.get_if_frequency) 1808 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq); 1809 1810 if (!state->if_freq) 1811 state->if_freq = 3300000; 1812 1813 pll = (((u64)1) << 34) * state->if_freq; 1814 do_div(pll, 63 * fclk); 1815 pll = (1 << 25) - pll; 1816 rc = mb86a20s_writereg(state, 0x28, 0x2a); 1817 if (rc < 0) 1818 goto err; 1819 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1820 if (rc < 0) 1821 goto err; 1822 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1823 if (rc < 0) 1824 goto err; 1825 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1826 if (rc < 0) 1827 goto err; 1828 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n", 1829 __func__, fclk, state->if_freq, (long long)pll); 1830 1831 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */ 1832 pll = state->if_freq * 1677721600L; 1833 do_div(pll, 1628571429L); 1834 rc = mb86a20s_writereg(state, 0x28, 0x20); 1835 if (rc < 0) 1836 goto err; 1837 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1838 if (rc < 0) 1839 goto err; 1840 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1841 if (rc < 0) 1842 goto err; 1843 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1844 if (rc < 0) 1845 goto err; 1846 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n", 1847 __func__, state->if_freq, (long long)pll); 1848 1849 if (!state->config->is_serial) 1850 regD5 &= ~1; 1851 1852 rc = mb86a20s_writereg(state, 0x50, 0xd5); 1853 if (rc < 0) 1854 goto err; 1855 rc = mb86a20s_writereg(state, 0x51, regD5); 1856 if (rc < 0) 1857 goto err; 1858 1859 rc = mb86a20s_writeregdata(state, mb86a20s_init2); 1860 if (rc < 0) 1861 goto err; 1862 1863 1864 err: 1865 if (fe->ops.i2c_gate_ctrl) 1866 fe->ops.i2c_gate_ctrl(fe, 1); 1867 1868 if (rc < 0) { 1869 state->need_init = true; 1870 dev_info(&state->i2c->dev, 1871 "mb86a20s: Init failed. Will try again later\n"); 1872 } else { 1873 state->need_init = false; 1874 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); 1875 } 1876 return rc; 1877 } 1878 1879 static int mb86a20s_set_frontend(struct dvb_frontend *fe) 1880 { 1881 struct mb86a20s_state *state = fe->demodulator_priv; 1882 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1883 int rc, if_freq; 1884 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1885 1886 if (!c->isdbt_layer_enabled) 1887 c->isdbt_layer_enabled = 7; 1888 1889 if (c->isdbt_layer_enabled == 1) 1890 state->bw = MB86A20S_1SEG; 1891 else if (c->isdbt_partial_reception) 1892 state->bw = MB86A20S_13SEG_PARTIAL; 1893 else 1894 state->bw = MB86A20S_13SEG; 1895 1896 if (c->inversion == INVERSION_ON) 1897 state->inversion = true; 1898 else 1899 state->inversion = false; 1900 1901 if (!c->isdbt_sb_mode) { 1902 state->subchannel = 0; 1903 } else { 1904 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel)) 1905 c->isdbt_sb_subchannel = 0; 1906 1907 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel]; 1908 } 1909 1910 /* 1911 * Gate should already be opened, but it doesn't hurt to 1912 * double-check 1913 */ 1914 if (fe->ops.i2c_gate_ctrl) 1915 fe->ops.i2c_gate_ctrl(fe, 1); 1916 fe->ops.tuner_ops.set_params(fe); 1917 1918 if (fe->ops.tuner_ops.get_if_frequency) 1919 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq); 1920 1921 /* 1922 * Make it more reliable: if, for some reason, the initial 1923 * device initialization doesn't happen, initialize it when 1924 * a SBTVD parameters are adjusted. 1925 * 1926 * Unfortunately, due to a hard to track bug at tda829x/tda18271, 1927 * the agc callback logic is not called during DVB attach time, 1928 * causing mb86a20s to not be initialized with Kworld SBTVD. 1929 * So, this hack is needed, in order to make Kworld SBTVD to work. 1930 * 1931 * It is also needed to change the IF after the initial init. 1932 * 1933 * HACK: Always init the frontend when set_frontend is called: 1934 * it was noticed that, on some devices, it fails to lock on a 1935 * different channel. So, it is better to reset everything, even 1936 * wasting some time, than to loose channel lock. 1937 */ 1938 mb86a20s_initfe(fe); 1939 1940 if (fe->ops.i2c_gate_ctrl) 1941 fe->ops.i2c_gate_ctrl(fe, 0); 1942 1943 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); 1944 mb86a20s_reset_counters(fe); 1945 mb86a20s_stats_not_ready(fe); 1946 1947 if (fe->ops.i2c_gate_ctrl) 1948 fe->ops.i2c_gate_ctrl(fe, 1); 1949 1950 return rc; 1951 } 1952 1953 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, 1954 enum fe_status *status) 1955 { 1956 struct mb86a20s_state *state = fe->demodulator_priv; 1957 int rc, status_nr; 1958 1959 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1960 1961 if (fe->ops.i2c_gate_ctrl) 1962 fe->ops.i2c_gate_ctrl(fe, 0); 1963 1964 /* Get lock */ 1965 status_nr = mb86a20s_read_status(fe, status); 1966 if (status_nr < 7) { 1967 mb86a20s_stats_not_ready(fe); 1968 mb86a20s_reset_frontend_cache(fe); 1969 } 1970 if (status_nr < 0) { 1971 dev_err(&state->i2c->dev, 1972 "%s: Can't read frontend lock status\n", __func__); 1973 goto error; 1974 } 1975 1976 /* Get signal strength */ 1977 rc = mb86a20s_read_signal_strength(fe); 1978 if (rc < 0) { 1979 dev_err(&state->i2c->dev, 1980 "%s: Can't reset VBER registers.\n", __func__); 1981 mb86a20s_stats_not_ready(fe); 1982 mb86a20s_reset_frontend_cache(fe); 1983 1984 rc = 0; /* Status is OK */ 1985 goto error; 1986 } 1987 1988 if (status_nr >= 7) { 1989 /* Get TMCC info*/ 1990 rc = mb86a20s_get_frontend(fe); 1991 if (rc < 0) { 1992 dev_err(&state->i2c->dev, 1993 "%s: Can't get FE TMCC data.\n", __func__); 1994 rc = 0; /* Status is OK */ 1995 goto error; 1996 } 1997 1998 /* Get statistics */ 1999 rc = mb86a20s_get_stats(fe, status_nr); 2000 if (rc < 0 && rc != -EBUSY) { 2001 dev_err(&state->i2c->dev, 2002 "%s: Can't get FE statistics.\n", __func__); 2003 rc = 0; 2004 goto error; 2005 } 2006 rc = 0; /* Don't return EBUSY to userspace */ 2007 } 2008 goto ok; 2009 2010 error: 2011 mb86a20s_stats_not_ready(fe); 2012 2013 ok: 2014 if (fe->ops.i2c_gate_ctrl) 2015 fe->ops.i2c_gate_ctrl(fe, 1); 2016 2017 return rc; 2018 } 2019 2020 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, 2021 u16 *strength) 2022 { 2023 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 2024 2025 2026 *strength = c->strength.stat[0].uvalue; 2027 2028 return 0; 2029 } 2030 2031 static int mb86a20s_tune(struct dvb_frontend *fe, 2032 bool re_tune, 2033 unsigned int mode_flags, 2034 unsigned int *delay, 2035 enum fe_status *status) 2036 { 2037 struct mb86a20s_state *state = fe->demodulator_priv; 2038 int rc = 0; 2039 2040 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 2041 2042 if (re_tune) 2043 rc = mb86a20s_set_frontend(fe); 2044 2045 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 2046 mb86a20s_read_status_and_stats(fe, status); 2047 2048 return rc; 2049 } 2050 2051 static void mb86a20s_release(struct dvb_frontend *fe) 2052 { 2053 struct mb86a20s_state *state = fe->demodulator_priv; 2054 2055 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 2056 2057 kfree(state); 2058 } 2059 2060 static struct dvb_frontend_ops mb86a20s_ops; 2061 2062 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, 2063 struct i2c_adapter *i2c) 2064 { 2065 struct mb86a20s_state *state; 2066 u8 rev; 2067 2068 dev_dbg(&i2c->dev, "%s called.\n", __func__); 2069 2070 /* allocate memory for the internal state */ 2071 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); 2072 if (state == NULL) { 2073 dev_err(&i2c->dev, 2074 "%s: unable to allocate memory for state\n", __func__); 2075 goto error; 2076 } 2077 2078 /* setup the state */ 2079 state->config = config; 2080 state->i2c = i2c; 2081 2082 /* create dvb_frontend */ 2083 memcpy(&state->frontend.ops, &mb86a20s_ops, 2084 sizeof(struct dvb_frontend_ops)); 2085 state->frontend.demodulator_priv = state; 2086 2087 /* Check if it is a mb86a20s frontend */ 2088 rev = mb86a20s_readreg(state, 0); 2089 2090 if (rev == 0x13) { 2091 dev_info(&i2c->dev, 2092 "Detected a Fujitsu mb86a20s frontend\n"); 2093 } else { 2094 dev_dbg(&i2c->dev, 2095 "Frontend revision %d is unknown - aborting.\n", 2096 rev); 2097 goto error; 2098 } 2099 2100 return &state->frontend; 2101 2102 error: 2103 kfree(state); 2104 return NULL; 2105 } 2106 EXPORT_SYMBOL(mb86a20s_attach); 2107 2108 static struct dvb_frontend_ops mb86a20s_ops = { 2109 .delsys = { SYS_ISDBT }, 2110 /* Use dib8000 values per default */ 2111 .info = { 2112 .name = "Fujitsu mb86A20s", 2113 .caps = FE_CAN_RECOVER | 2114 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 2115 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 2116 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2117 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | 2118 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 2119 /* Actually, those values depend on the used tuner */ 2120 .frequency_min = 45000000, 2121 .frequency_max = 864000000, 2122 .frequency_stepsize = 62500, 2123 }, 2124 2125 .release = mb86a20s_release, 2126 2127 .init = mb86a20s_initfe, 2128 .set_frontend = mb86a20s_set_frontend, 2129 .read_status = mb86a20s_read_status_and_stats, 2130 .read_signal_strength = mb86a20s_read_signal_strength_from_cache, 2131 .tune = mb86a20s_tune, 2132 }; 2133 2134 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); 2135 MODULE_AUTHOR("Mauro Carvalho Chehab"); 2136 MODULE_LICENSE("GPL"); 2137