1 /* 2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver 3 * 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <asm/div64.h> 19 20 #include "dvb_frontend.h" 21 #include "mb86a20s.h" 22 23 #define NUM_LAYERS 3 24 25 enum mb86a20s_bandwidth { 26 MB86A20S_13SEG = 0, 27 MB86A20S_13SEG_PARTIAL = 1, 28 MB86A20S_1SEG = 2, 29 MB86A20S_3SEG = 3, 30 }; 31 32 static u8 mb86a20s_subchannel[] = { 33 0xb0, 0xc0, 0xd0, 0xe0, 34 0xf0, 0x00, 0x10, 0x20, 35 }; 36 37 struct mb86a20s_state { 38 struct i2c_adapter *i2c; 39 const struct mb86a20s_config *config; 40 u32 last_frequency; 41 42 struct dvb_frontend frontend; 43 44 u32 if_freq; 45 enum mb86a20s_bandwidth bw; 46 bool inversion; 47 u32 subchannel; 48 49 u32 estimated_rate[NUM_LAYERS]; 50 unsigned long get_strength_time; 51 52 bool need_init; 53 }; 54 55 struct regdata { 56 u8 reg; 57 u8 data; 58 }; 59 60 #define BER_SAMPLING_RATE 1 /* Seconds */ 61 62 /* 63 * Initialization sequence: Use whatevere default values that PV SBTVD 64 * does on its initialisation, obtained via USB snoop 65 */ 66 static struct regdata mb86a20s_init1[] = { 67 { 0x70, 0x0f }, 68 { 0x70, 0xff }, 69 { 0x08, 0x01 }, 70 { 0x50, 0xd1 }, { 0x51, 0x20 }, 71 }; 72 73 static struct regdata mb86a20s_init2[] = { 74 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, 75 { 0x3b, 0x21 }, 76 { 0x3c, 0x38 }, 77 { 0x01, 0x0d }, 78 { 0x04, 0x08 }, { 0x05, 0x03 }, 79 { 0x04, 0x0e }, { 0x05, 0x00 }, 80 { 0x04, 0x0f }, { 0x05, 0x37 }, 81 { 0x04, 0x0b }, { 0x05, 0x78 }, 82 { 0x04, 0x00 }, { 0x05, 0x00 }, 83 { 0x04, 0x01 }, { 0x05, 0x1e }, 84 { 0x04, 0x02 }, { 0x05, 0x07 }, 85 { 0x04, 0x03 }, { 0x05, 0xd0 }, 86 { 0x04, 0x09 }, { 0x05, 0x00 }, 87 { 0x04, 0x0a }, { 0x05, 0xff }, 88 { 0x04, 0x27 }, { 0x05, 0x00 }, 89 { 0x04, 0x28 }, { 0x05, 0x00 }, 90 { 0x04, 0x1e }, { 0x05, 0x00 }, 91 { 0x04, 0x29 }, { 0x05, 0x64 }, 92 { 0x04, 0x32 }, { 0x05, 0x02 }, 93 { 0x04, 0x14 }, { 0x05, 0x02 }, 94 { 0x04, 0x04 }, { 0x05, 0x00 }, 95 { 0x04, 0x05 }, { 0x05, 0x22 }, 96 { 0x04, 0x06 }, { 0x05, 0x0e }, 97 { 0x04, 0x07 }, { 0x05, 0xd8 }, 98 { 0x04, 0x12 }, { 0x05, 0x00 }, 99 { 0x04, 0x13 }, { 0x05, 0xff }, 100 { 0x04, 0x15 }, { 0x05, 0x4e }, 101 { 0x04, 0x16 }, { 0x05, 0x20 }, 102 103 /* 104 * On this demod, when the bit count reaches the count below, 105 * it collects the bit error count. The bit counters are initialized 106 * to 65535 here. This warrants that all of them will be quickly 107 * calculated when device gets locked. As TMCC is parsed, the values 108 * will be adjusted later in the driver's code. 109 */ 110 { 0x52, 0x01 }, /* Turn on BER before Viterbi */ 111 { 0x50, 0xa7 }, { 0x51, 0x00 }, 112 { 0x50, 0xa8 }, { 0x51, 0xff }, 113 { 0x50, 0xa9 }, { 0x51, 0xff }, 114 { 0x50, 0xaa }, { 0x51, 0x00 }, 115 { 0x50, 0xab }, { 0x51, 0xff }, 116 { 0x50, 0xac }, { 0x51, 0xff }, 117 { 0x50, 0xad }, { 0x51, 0x00 }, 118 { 0x50, 0xae }, { 0x51, 0xff }, 119 { 0x50, 0xaf }, { 0x51, 0xff }, 120 121 /* 122 * On this demod, post BER counts blocks. When the count reaches the 123 * value below, it collects the block error count. The block counters 124 * are initialized to 127 here. This warrants that all of them will be 125 * quickly calculated when device gets locked. As TMCC is parsed, the 126 * values will be adjusted later in the driver's code. 127 */ 128 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */ 129 { 0x50, 0xdc }, { 0x51, 0x00 }, 130 { 0x50, 0xdd }, { 0x51, 0x7f }, 131 { 0x50, 0xde }, { 0x51, 0x00 }, 132 { 0x50, 0xdf }, { 0x51, 0x7f }, 133 { 0x50, 0xe0 }, { 0x51, 0x00 }, 134 { 0x50, 0xe1 }, { 0x51, 0x7f }, 135 136 /* 137 * On this demod, when the block count reaches the count below, 138 * it collects the block error count. The block counters are initialized 139 * to 127 here. This warrants that all of them will be quickly 140 * calculated when device gets locked. As TMCC is parsed, the values 141 * will be adjusted later in the driver's code. 142 */ 143 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */ 144 { 0x50, 0xb2 }, { 0x51, 0x00 }, 145 { 0x50, 0xb3 }, { 0x51, 0x7f }, 146 { 0x50, 0xb4 }, { 0x51, 0x00 }, 147 { 0x50, 0xb5 }, { 0x51, 0x7f }, 148 { 0x50, 0xb6 }, { 0x51, 0x00 }, 149 { 0x50, 0xb7 }, { 0x51, 0x7f }, 150 151 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */ 152 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ 153 { 0x45, 0x04 }, /* CN symbol 4 */ 154 { 0x48, 0x04 }, /* CN manual mode */ 155 156 { 0x50, 0xd6 }, { 0x51, 0x1f }, 157 { 0x50, 0xd2 }, { 0x51, 0x03 }, 158 { 0x50, 0xd7 }, { 0x51, 0xbf }, 159 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff }, 160 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c }, 161 162 { 0x04, 0x40 }, { 0x05, 0x00 }, 163 { 0x28, 0x00 }, { 0x2b, 0x08 }, 164 { 0x28, 0x05 }, { 0x2b, 0x00 }, 165 { 0x1c, 0x01 }, 166 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f }, 167 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 }, 168 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 }, 169 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 }, 170 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 }, 171 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, 172 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 }, 173 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 }, 174 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b }, 175 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 }, 176 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d }, 177 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 }, 178 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b }, 179 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 180 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 }, 181 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 }, 182 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 }, 183 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, 184 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, 185 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef }, 186 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 }, 187 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 }, 188 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d }, 189 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 }, 190 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba }, 191 { 0x50, 0x1e }, { 0x51, 0x5d }, 192 { 0x50, 0x22 }, { 0x51, 0x00 }, 193 { 0x50, 0x23 }, { 0x51, 0xc8 }, 194 { 0x50, 0x24 }, { 0x51, 0x00 }, 195 { 0x50, 0x25 }, { 0x51, 0xf0 }, 196 { 0x50, 0x26 }, { 0x51, 0x00 }, 197 { 0x50, 0x27 }, { 0x51, 0xc3 }, 198 { 0x50, 0x39 }, { 0x51, 0x02 }, 199 { 0xec, 0x0f }, 200 { 0xeb, 0x1f }, 201 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 202 { 0xd0, 0x00 }, 203 }; 204 205 static struct regdata mb86a20s_reset_reception[] = { 206 { 0x70, 0xf0 }, 207 { 0x70, 0xff }, 208 { 0x08, 0x01 }, 209 { 0x08, 0x00 }, 210 }; 211 212 static struct regdata mb86a20s_per_ber_reset[] = { 213 { 0x53, 0x00 }, /* pre BER Counter reset */ 214 { 0x53, 0x07 }, 215 216 { 0x5f, 0x00 }, /* post BER Counter reset */ 217 { 0x5f, 0x07 }, 218 219 { 0x50, 0xb1 }, /* PER Counter reset */ 220 { 0x51, 0x07 }, 221 { 0x51, 0x00 }, 222 }; 223 224 /* 225 * I2C read/write functions and macros 226 */ 227 228 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, 229 u8 i2c_addr, u8 reg, u8 data) 230 { 231 u8 buf[] = { reg, data }; 232 struct i2c_msg msg = { 233 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 234 }; 235 int rc; 236 237 rc = i2c_transfer(state->i2c, &msg, 1); 238 if (rc != 1) { 239 dev_err(&state->i2c->dev, 240 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", 241 __func__, rc, reg, data); 242 return rc; 243 } 244 245 return 0; 246 } 247 248 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, 249 u8 i2c_addr, struct regdata *rd, int size) 250 { 251 int i, rc; 252 253 for (i = 0; i < size; i++) { 254 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, 255 rd[i].data); 256 if (rc < 0) 257 return rc; 258 } 259 return 0; 260 } 261 262 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, 263 u8 i2c_addr, u8 reg) 264 { 265 u8 val; 266 int rc; 267 struct i2c_msg msg[] = { 268 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 269 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } 270 }; 271 272 rc = i2c_transfer(state->i2c, msg, 2); 273 274 if (rc != 2) { 275 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", 276 __func__, reg, rc); 277 return (rc < 0) ? rc : -EIO; 278 } 279 280 return val; 281 } 282 283 #define mb86a20s_readreg(state, reg) \ 284 mb86a20s_i2c_readreg(state, state->config->demod_address, reg) 285 #define mb86a20s_writereg(state, reg, val) \ 286 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) 287 #define mb86a20s_writeregdata(state, regdata) \ 288 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ 289 regdata, ARRAY_SIZE(regdata)) 290 291 /* 292 * Ancillary internal routines (likely compiled inlined) 293 * 294 * The functions below assume that gateway lock has already obtained 295 */ 296 297 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status) 298 { 299 struct mb86a20s_state *state = fe->demodulator_priv; 300 int val; 301 302 *status = 0; 303 304 val = mb86a20s_readreg(state, 0x0a); 305 if (val < 0) 306 return val; 307 308 val &= 0xf; 309 if (val >= 2) 310 *status |= FE_HAS_SIGNAL; 311 312 if (val >= 4) 313 *status |= FE_HAS_CARRIER; 314 315 if (val >= 5) 316 *status |= FE_HAS_VITERBI; 317 318 if (val >= 7) 319 *status |= FE_HAS_SYNC; 320 321 if (val >= 8) /* Maybe 9? */ 322 *status |= FE_HAS_LOCK; 323 324 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", 325 __func__, *status, val); 326 327 return val; 328 } 329 330 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) 331 { 332 struct mb86a20s_state *state = fe->demodulator_priv; 333 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 334 int rc; 335 unsigned rf_max, rf_min, rf; 336 337 if (state->get_strength_time && 338 (!time_after(jiffies, state->get_strength_time))) 339 return c->strength.stat[0].uvalue; 340 341 /* Reset its value if an error happen */ 342 c->strength.stat[0].uvalue = 0; 343 344 /* Does a binary search to get RF strength */ 345 rf_max = 0xfff; 346 rf_min = 0; 347 do { 348 rf = (rf_max + rf_min) / 2; 349 rc = mb86a20s_writereg(state, 0x04, 0x1f); 350 if (rc < 0) 351 return rc; 352 rc = mb86a20s_writereg(state, 0x05, rf >> 8); 353 if (rc < 0) 354 return rc; 355 rc = mb86a20s_writereg(state, 0x04, 0x20); 356 if (rc < 0) 357 return rc; 358 rc = mb86a20s_writereg(state, 0x05, rf); 359 if (rc < 0) 360 return rc; 361 362 rc = mb86a20s_readreg(state, 0x02); 363 if (rc < 0) 364 return rc; 365 if (rc & 0x08) 366 rf_min = (rf_max + rf_min) / 2; 367 else 368 rf_max = (rf_max + rf_min) / 2; 369 if (rf_max - rf_min < 4) { 370 rf = (rf_max + rf_min) / 2; 371 372 /* Rescale it from 2^12 (4096) to 2^16 */ 373 rf = rf << (16 - 12); 374 if (rf) 375 rf |= (1 << 12) - 1; 376 377 dev_dbg(&state->i2c->dev, 378 "%s: signal strength = %d (%d < RF=%d < %d)\n", 379 __func__, rf, rf_min, rf >> 4, rf_max); 380 c->strength.stat[0].uvalue = rf; 381 state->get_strength_time = jiffies + 382 msecs_to_jiffies(1000); 383 return 0; 384 } 385 } while (1); 386 } 387 388 static int mb86a20s_get_modulation(struct mb86a20s_state *state, 389 unsigned layer) 390 { 391 int rc; 392 static unsigned char reg[] = { 393 [0] = 0x86, /* Layer A */ 394 [1] = 0x8a, /* Layer B */ 395 [2] = 0x8e, /* Layer C */ 396 }; 397 398 if (layer >= ARRAY_SIZE(reg)) 399 return -EINVAL; 400 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 401 if (rc < 0) 402 return rc; 403 rc = mb86a20s_readreg(state, 0x6e); 404 if (rc < 0) 405 return rc; 406 switch ((rc >> 4) & 0x07) { 407 case 0: 408 return DQPSK; 409 case 1: 410 return QPSK; 411 case 2: 412 return QAM_16; 413 case 3: 414 return QAM_64; 415 default: 416 return QAM_AUTO; 417 } 418 } 419 420 static int mb86a20s_get_fec(struct mb86a20s_state *state, 421 unsigned layer) 422 { 423 int rc; 424 425 static unsigned char reg[] = { 426 [0] = 0x87, /* Layer A */ 427 [1] = 0x8b, /* Layer B */ 428 [2] = 0x8f, /* Layer C */ 429 }; 430 431 if (layer >= ARRAY_SIZE(reg)) 432 return -EINVAL; 433 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 434 if (rc < 0) 435 return rc; 436 rc = mb86a20s_readreg(state, 0x6e); 437 if (rc < 0) 438 return rc; 439 switch ((rc >> 4) & 0x07) { 440 case 0: 441 return FEC_1_2; 442 case 1: 443 return FEC_2_3; 444 case 2: 445 return FEC_3_4; 446 case 3: 447 return FEC_5_6; 448 case 4: 449 return FEC_7_8; 450 default: 451 return FEC_AUTO; 452 } 453 } 454 455 static int mb86a20s_get_interleaving(struct mb86a20s_state *state, 456 unsigned layer) 457 { 458 int rc; 459 int interleaving[] = { 460 0, 1, 2, 4, 8 461 }; 462 463 static unsigned char reg[] = { 464 [0] = 0x88, /* Layer A */ 465 [1] = 0x8c, /* Layer B */ 466 [2] = 0x90, /* Layer C */ 467 }; 468 469 if (layer >= ARRAY_SIZE(reg)) 470 return -EINVAL; 471 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 472 if (rc < 0) 473 return rc; 474 rc = mb86a20s_readreg(state, 0x6e); 475 if (rc < 0) 476 return rc; 477 478 return interleaving[(rc >> 4) & 0x07]; 479 } 480 481 static int mb86a20s_get_segment_count(struct mb86a20s_state *state, 482 unsigned layer) 483 { 484 int rc, count; 485 static unsigned char reg[] = { 486 [0] = 0x89, /* Layer A */ 487 [1] = 0x8d, /* Layer B */ 488 [2] = 0x91, /* Layer C */ 489 }; 490 491 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 492 493 if (layer >= ARRAY_SIZE(reg)) 494 return -EINVAL; 495 496 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 497 if (rc < 0) 498 return rc; 499 rc = mb86a20s_readreg(state, 0x6e); 500 if (rc < 0) 501 return rc; 502 count = (rc >> 4) & 0x0f; 503 504 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); 505 506 return count; 507 } 508 509 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) 510 { 511 struct mb86a20s_state *state = fe->demodulator_priv; 512 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 513 514 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 515 516 /* Fixed parameters */ 517 c->delivery_system = SYS_ISDBT; 518 c->bandwidth_hz = 6000000; 519 520 /* Initialize values that will be later autodetected */ 521 c->isdbt_layer_enabled = 0; 522 c->transmission_mode = TRANSMISSION_MODE_AUTO; 523 c->guard_interval = GUARD_INTERVAL_AUTO; 524 c->isdbt_sb_mode = 0; 525 c->isdbt_sb_segment_count = 0; 526 } 527 528 /* 529 * Estimates the bit rate using the per-segment bit rate given by 530 * ABNT/NBR 15601 spec (table 4). 531 */ 532 static u32 isdbt_rate[3][5][4] = { 533 { /* DQPSK/QPSK */ 534 { 280850, 312060, 330420, 340430 }, /* 1/2 */ 535 { 374470, 416080, 440560, 453910 }, /* 2/3 */ 536 { 421280, 468090, 495630, 510650 }, /* 3/4 */ 537 { 468090, 520100, 550700, 567390 }, /* 5/6 */ 538 { 491500, 546110, 578230, 595760 }, /* 7/8 */ 539 }, { /* QAM16 */ 540 { 561710, 624130, 660840, 680870 }, /* 1/2 */ 541 { 748950, 832170, 881120, 907820 }, /* 2/3 */ 542 { 842570, 936190, 991260, 1021300 }, /* 3/4 */ 543 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ 544 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ 545 }, { /* QAM64 */ 546 { 842570, 936190, 991260, 1021300 }, /* 1/2 */ 547 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ 548 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ 549 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ 550 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ 551 } 552 }; 553 554 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, 555 u32 modulation, u32 forward_error_correction, 556 u32 guard_interval, 557 u32 segment) 558 { 559 struct mb86a20s_state *state = fe->demodulator_priv; 560 u32 rate; 561 int mod, fec, guard; 562 563 /* 564 * If modulation/fec/guard is not detected, the default is 565 * to consider the lowest bit rate, to avoid taking too long time 566 * to get BER. 567 */ 568 switch (modulation) { 569 case DQPSK: 570 case QPSK: 571 default: 572 mod = 0; 573 break; 574 case QAM_16: 575 mod = 1; 576 break; 577 case QAM_64: 578 mod = 2; 579 break; 580 } 581 582 switch (forward_error_correction) { 583 default: 584 case FEC_1_2: 585 case FEC_AUTO: 586 fec = 0; 587 break; 588 case FEC_2_3: 589 fec = 1; 590 break; 591 case FEC_3_4: 592 fec = 2; 593 break; 594 case FEC_5_6: 595 fec = 3; 596 break; 597 case FEC_7_8: 598 fec = 4; 599 break; 600 } 601 602 switch (guard_interval) { 603 default: 604 case GUARD_INTERVAL_1_4: 605 guard = 0; 606 break; 607 case GUARD_INTERVAL_1_8: 608 guard = 1; 609 break; 610 case GUARD_INTERVAL_1_16: 611 guard = 2; 612 break; 613 case GUARD_INTERVAL_1_32: 614 guard = 3; 615 break; 616 } 617 618 /* Samples BER at BER_SAMPLING_RATE seconds */ 619 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE; 620 621 /* Avoids sampling too quickly or to overflow the register */ 622 if (rate < 256) 623 rate = 256; 624 else if (rate > (1 << 24) - 1) 625 rate = (1 << 24) - 1; 626 627 dev_dbg(&state->i2c->dev, 628 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", 629 __func__, 'A' + layer, 630 segment * isdbt_rate[mod][fec][guard]/1000, 631 rate, rate); 632 633 state->estimated_rate[layer] = rate; 634 } 635 636 static int mb86a20s_get_frontend(struct dvb_frontend *fe) 637 { 638 struct mb86a20s_state *state = fe->demodulator_priv; 639 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 640 int layer, rc; 641 642 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 643 644 /* Reset frontend cache to default values */ 645 mb86a20s_reset_frontend_cache(fe); 646 647 /* Check for partial reception */ 648 rc = mb86a20s_writereg(state, 0x6d, 0x85); 649 if (rc < 0) 650 return rc; 651 rc = mb86a20s_readreg(state, 0x6e); 652 if (rc < 0) 653 return rc; 654 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; 655 656 /* Get per-layer data */ 657 658 for (layer = 0; layer < NUM_LAYERS; layer++) { 659 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", 660 __func__, 'A' + layer); 661 662 rc = mb86a20s_get_segment_count(state, layer); 663 if (rc < 0) 664 goto noperlayer_error; 665 if (rc >= 0 && rc < 14) { 666 c->layer[layer].segment_count = rc; 667 } else { 668 c->layer[layer].segment_count = 0; 669 state->estimated_rate[layer] = 0; 670 continue; 671 } 672 c->isdbt_layer_enabled |= 1 << layer; 673 rc = mb86a20s_get_modulation(state, layer); 674 if (rc < 0) 675 goto noperlayer_error; 676 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", 677 __func__, rc); 678 c->layer[layer].modulation = rc; 679 rc = mb86a20s_get_fec(state, layer); 680 if (rc < 0) 681 goto noperlayer_error; 682 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", 683 __func__, rc); 684 c->layer[layer].fec = rc; 685 rc = mb86a20s_get_interleaving(state, layer); 686 if (rc < 0) 687 goto noperlayer_error; 688 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", 689 __func__, rc); 690 c->layer[layer].interleaving = rc; 691 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation, 692 c->layer[layer].fec, 693 c->guard_interval, 694 c->layer[layer].segment_count); 695 } 696 697 rc = mb86a20s_writereg(state, 0x6d, 0x84); 698 if (rc < 0) 699 return rc; 700 if ((rc & 0x60) == 0x20) { 701 c->isdbt_sb_mode = 1; 702 /* At least, one segment should exist */ 703 if (!c->isdbt_sb_segment_count) 704 c->isdbt_sb_segment_count = 1; 705 } 706 707 /* Get transmission mode and guard interval */ 708 rc = mb86a20s_readreg(state, 0x07); 709 if (rc < 0) 710 return rc; 711 c->transmission_mode = TRANSMISSION_MODE_AUTO; 712 if ((rc & 0x60) == 0x20) { 713 /* Only modes 2 and 3 are supported */ 714 switch ((rc >> 2) & 0x03) { 715 case 1: 716 c->transmission_mode = TRANSMISSION_MODE_4K; 717 break; 718 case 2: 719 c->transmission_mode = TRANSMISSION_MODE_8K; 720 break; 721 } 722 } 723 c->guard_interval = GUARD_INTERVAL_AUTO; 724 if (!(rc & 0x10)) { 725 /* Guard interval 1/32 is not supported */ 726 switch (rc & 0x3) { 727 case 0: 728 c->guard_interval = GUARD_INTERVAL_1_4; 729 break; 730 case 1: 731 c->guard_interval = GUARD_INTERVAL_1_8; 732 break; 733 case 2: 734 c->guard_interval = GUARD_INTERVAL_1_16; 735 break; 736 } 737 } 738 return 0; 739 740 noperlayer_error: 741 742 /* per-layer info is incomplete; discard all per-layer */ 743 c->isdbt_layer_enabled = 0; 744 745 return rc; 746 } 747 748 static int mb86a20s_reset_counters(struct dvb_frontend *fe) 749 { 750 struct mb86a20s_state *state = fe->demodulator_priv; 751 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 752 int rc, val; 753 754 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 755 756 /* Reset the counters, if the channel changed */ 757 if (state->last_frequency != c->frequency) { 758 memset(&c->cnr, 0, sizeof(c->cnr)); 759 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); 760 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); 761 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 762 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 763 memset(&c->block_error, 0, sizeof(c->block_error)); 764 memset(&c->block_count, 0, sizeof(c->block_count)); 765 766 state->last_frequency = c->frequency; 767 } 768 769 /* Clear status for most stats */ 770 771 /* BER/PER counter reset */ 772 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); 773 if (rc < 0) 774 goto err; 775 776 /* CNR counter reset */ 777 rc = mb86a20s_readreg(state, 0x45); 778 if (rc < 0) 779 goto err; 780 val = rc; 781 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 782 if (rc < 0) 783 goto err; 784 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 785 if (rc < 0) 786 goto err; 787 788 /* MER counter reset */ 789 rc = mb86a20s_writereg(state, 0x50, 0x50); 790 if (rc < 0) 791 goto err; 792 rc = mb86a20s_readreg(state, 0x51); 793 if (rc < 0) 794 goto err; 795 val = rc; 796 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 797 if (rc < 0) 798 goto err; 799 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 800 if (rc < 0) 801 goto err; 802 803 goto ok; 804 err: 805 dev_err(&state->i2c->dev, 806 "%s: Can't reset FE statistics (error %d).\n", 807 __func__, rc); 808 ok: 809 return rc; 810 } 811 812 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe, 813 unsigned layer, 814 u32 *error, u32 *count) 815 { 816 struct mb86a20s_state *state = fe->demodulator_priv; 817 int rc, val; 818 819 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 820 821 if (layer >= NUM_LAYERS) 822 return -EINVAL; 823 824 /* Check if the BER measures are already available */ 825 rc = mb86a20s_readreg(state, 0x54); 826 if (rc < 0) 827 return rc; 828 829 /* Check if data is available for that layer */ 830 if (!(rc & (1 << layer))) { 831 dev_dbg(&state->i2c->dev, 832 "%s: preBER for layer %c is not available yet.\n", 833 __func__, 'A' + layer); 834 return -EBUSY; 835 } 836 837 /* Read Bit Error Count */ 838 rc = mb86a20s_readreg(state, 0x55 + layer * 3); 839 if (rc < 0) 840 return rc; 841 *error = rc << 16; 842 rc = mb86a20s_readreg(state, 0x56 + layer * 3); 843 if (rc < 0) 844 return rc; 845 *error |= rc << 8; 846 rc = mb86a20s_readreg(state, 0x57 + layer * 3); 847 if (rc < 0) 848 return rc; 849 *error |= rc; 850 851 dev_dbg(&state->i2c->dev, 852 "%s: bit error before Viterbi for layer %c: %d.\n", 853 __func__, 'A' + layer, *error); 854 855 /* Read Bit Count */ 856 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 857 if (rc < 0) 858 return rc; 859 rc = mb86a20s_readreg(state, 0x51); 860 if (rc < 0) 861 return rc; 862 *count = rc << 16; 863 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 864 if (rc < 0) 865 return rc; 866 rc = mb86a20s_readreg(state, 0x51); 867 if (rc < 0) 868 return rc; 869 *count |= rc << 8; 870 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 871 if (rc < 0) 872 return rc; 873 rc = mb86a20s_readreg(state, 0x51); 874 if (rc < 0) 875 return rc; 876 *count |= rc; 877 878 dev_dbg(&state->i2c->dev, 879 "%s: bit count before Viterbi for layer %c: %d.\n", 880 __func__, 'A' + layer, *count); 881 882 883 /* 884 * As we get TMCC data from the frontend, we can better estimate the 885 * BER bit counters, in order to do the BER measure during a longer 886 * time. Use those data, if available, to update the bit count 887 * measure. 888 */ 889 890 if (state->estimated_rate[layer] 891 && state->estimated_rate[layer] != *count) { 892 dev_dbg(&state->i2c->dev, 893 "%s: updating layer %c preBER counter to %d.\n", 894 __func__, 'A' + layer, state->estimated_rate[layer]); 895 896 /* Turn off BER before Viterbi */ 897 rc = mb86a20s_writereg(state, 0x52, 0x00); 898 899 /* Update counter for this layer */ 900 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 901 if (rc < 0) 902 return rc; 903 rc = mb86a20s_writereg(state, 0x51, 904 state->estimated_rate[layer] >> 16); 905 if (rc < 0) 906 return rc; 907 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 908 if (rc < 0) 909 return rc; 910 rc = mb86a20s_writereg(state, 0x51, 911 state->estimated_rate[layer] >> 8); 912 if (rc < 0) 913 return rc; 914 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 915 if (rc < 0) 916 return rc; 917 rc = mb86a20s_writereg(state, 0x51, 918 state->estimated_rate[layer]); 919 if (rc < 0) 920 return rc; 921 922 /* Turn on BER before Viterbi */ 923 rc = mb86a20s_writereg(state, 0x52, 0x01); 924 925 /* Reset all preBER counters */ 926 rc = mb86a20s_writereg(state, 0x53, 0x00); 927 if (rc < 0) 928 return rc; 929 rc = mb86a20s_writereg(state, 0x53, 0x07); 930 } else { 931 /* Reset counter to collect new data */ 932 rc = mb86a20s_readreg(state, 0x53); 933 if (rc < 0) 934 return rc; 935 val = rc; 936 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); 937 if (rc < 0) 938 return rc; 939 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); 940 } 941 942 return rc; 943 } 944 945 static int mb86a20s_get_post_ber(struct dvb_frontend *fe, 946 unsigned layer, 947 u32 *error, u32 *count) 948 { 949 struct mb86a20s_state *state = fe->demodulator_priv; 950 u32 counter, collect_rate; 951 int rc, val; 952 953 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 954 955 if (layer >= NUM_LAYERS) 956 return -EINVAL; 957 958 /* Check if the BER measures are already available */ 959 rc = mb86a20s_readreg(state, 0x60); 960 if (rc < 0) 961 return rc; 962 963 /* Check if data is available for that layer */ 964 if (!(rc & (1 << layer))) { 965 dev_dbg(&state->i2c->dev, 966 "%s: post BER for layer %c is not available yet.\n", 967 __func__, 'A' + layer); 968 return -EBUSY; 969 } 970 971 /* Read Bit Error Count */ 972 rc = mb86a20s_readreg(state, 0x64 + layer * 3); 973 if (rc < 0) 974 return rc; 975 *error = rc << 16; 976 rc = mb86a20s_readreg(state, 0x65 + layer * 3); 977 if (rc < 0) 978 return rc; 979 *error |= rc << 8; 980 rc = mb86a20s_readreg(state, 0x66 + layer * 3); 981 if (rc < 0) 982 return rc; 983 *error |= rc; 984 985 dev_dbg(&state->i2c->dev, 986 "%s: post bit error for layer %c: %d.\n", 987 __func__, 'A' + layer, *error); 988 989 /* Read Bit Count */ 990 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 991 if (rc < 0) 992 return rc; 993 rc = mb86a20s_readreg(state, 0x51); 994 if (rc < 0) 995 return rc; 996 counter = rc << 8; 997 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 998 if (rc < 0) 999 return rc; 1000 rc = mb86a20s_readreg(state, 0x51); 1001 if (rc < 0) 1002 return rc; 1003 counter |= rc; 1004 *count = counter * 204 * 8; 1005 1006 dev_dbg(&state->i2c->dev, 1007 "%s: post bit count for layer %c: %d.\n", 1008 __func__, 'A' + layer, *count); 1009 1010 /* 1011 * As we get TMCC data from the frontend, we can better estimate the 1012 * BER bit counters, in order to do the BER measure during a longer 1013 * time. Use those data, if available, to update the bit count 1014 * measure. 1015 */ 1016 1017 if (!state->estimated_rate[layer]) 1018 goto reset_measurement; 1019 1020 collect_rate = state->estimated_rate[layer] / 204 / 8; 1021 if (collect_rate < 32) 1022 collect_rate = 32; 1023 if (collect_rate > 65535) 1024 collect_rate = 65535; 1025 if (collect_rate != counter) { 1026 dev_dbg(&state->i2c->dev, 1027 "%s: updating postBER counter on layer %c to %d.\n", 1028 __func__, 'A' + layer, collect_rate); 1029 1030 /* Turn off BER after Viterbi */ 1031 rc = mb86a20s_writereg(state, 0x5e, 0x00); 1032 1033 /* Update counter for this layer */ 1034 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1035 if (rc < 0) 1036 return rc; 1037 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1038 if (rc < 0) 1039 return rc; 1040 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1041 if (rc < 0) 1042 return rc; 1043 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1044 if (rc < 0) 1045 return rc; 1046 1047 /* Turn on BER after Viterbi */ 1048 rc = mb86a20s_writereg(state, 0x5e, 0x07); 1049 1050 /* Reset all preBER counters */ 1051 rc = mb86a20s_writereg(state, 0x5f, 0x00); 1052 if (rc < 0) 1053 return rc; 1054 rc = mb86a20s_writereg(state, 0x5f, 0x07); 1055 1056 return rc; 1057 } 1058 1059 reset_measurement: 1060 /* Reset counter to collect new data */ 1061 rc = mb86a20s_readreg(state, 0x5f); 1062 if (rc < 0) 1063 return rc; 1064 val = rc; 1065 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); 1066 if (rc < 0) 1067 return rc; 1068 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); 1069 1070 return rc; 1071 } 1072 1073 static int mb86a20s_get_blk_error(struct dvb_frontend *fe, 1074 unsigned layer, 1075 u32 *error, u32 *count) 1076 { 1077 struct mb86a20s_state *state = fe->demodulator_priv; 1078 int rc, val; 1079 u32 collect_rate; 1080 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1081 1082 if (layer >= NUM_LAYERS) 1083 return -EINVAL; 1084 1085 /* Check if the PER measures are already available */ 1086 rc = mb86a20s_writereg(state, 0x50, 0xb8); 1087 if (rc < 0) 1088 return rc; 1089 rc = mb86a20s_readreg(state, 0x51); 1090 if (rc < 0) 1091 return rc; 1092 1093 /* Check if data is available for that layer */ 1094 1095 if (!(rc & (1 << layer))) { 1096 dev_dbg(&state->i2c->dev, 1097 "%s: block counts for layer %c aren't available yet.\n", 1098 __func__, 'A' + layer); 1099 return -EBUSY; 1100 } 1101 1102 /* Read Packet error Count */ 1103 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); 1104 if (rc < 0) 1105 return rc; 1106 rc = mb86a20s_readreg(state, 0x51); 1107 if (rc < 0) 1108 return rc; 1109 *error = rc << 8; 1110 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); 1111 if (rc < 0) 1112 return rc; 1113 rc = mb86a20s_readreg(state, 0x51); 1114 if (rc < 0) 1115 return rc; 1116 *error |= rc; 1117 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n", 1118 __func__, 'A' + layer, *error); 1119 1120 /* Read Bit Count */ 1121 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1122 if (rc < 0) 1123 return rc; 1124 rc = mb86a20s_readreg(state, 0x51); 1125 if (rc < 0) 1126 return rc; 1127 *count = rc << 8; 1128 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1129 if (rc < 0) 1130 return rc; 1131 rc = mb86a20s_readreg(state, 0x51); 1132 if (rc < 0) 1133 return rc; 1134 *count |= rc; 1135 1136 dev_dbg(&state->i2c->dev, 1137 "%s: block count for layer %c: %d.\n", 1138 __func__, 'A' + layer, *count); 1139 1140 /* 1141 * As we get TMCC data from the frontend, we can better estimate the 1142 * BER bit counters, in order to do the BER measure during a longer 1143 * time. Use those data, if available, to update the bit count 1144 * measure. 1145 */ 1146 1147 if (!state->estimated_rate[layer]) 1148 goto reset_measurement; 1149 1150 collect_rate = state->estimated_rate[layer] / 204 / 8; 1151 if (collect_rate < 32) 1152 collect_rate = 32; 1153 if (collect_rate > 65535) 1154 collect_rate = 65535; 1155 1156 if (collect_rate != *count) { 1157 dev_dbg(&state->i2c->dev, 1158 "%s: updating PER counter on layer %c to %d.\n", 1159 __func__, 'A' + layer, collect_rate); 1160 1161 /* Stop PER measurement */ 1162 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1163 if (rc < 0) 1164 return rc; 1165 rc = mb86a20s_writereg(state, 0x51, 0x00); 1166 if (rc < 0) 1167 return rc; 1168 1169 /* Update this layer's counter */ 1170 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1171 if (rc < 0) 1172 return rc; 1173 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1174 if (rc < 0) 1175 return rc; 1176 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1177 if (rc < 0) 1178 return rc; 1179 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1180 if (rc < 0) 1181 return rc; 1182 1183 /* start PER measurement */ 1184 rc = mb86a20s_writereg(state, 0x50, 0xb0); 1185 if (rc < 0) 1186 return rc; 1187 rc = mb86a20s_writereg(state, 0x51, 0x07); 1188 if (rc < 0) 1189 return rc; 1190 1191 /* Reset all counters to collect new data */ 1192 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1193 if (rc < 0) 1194 return rc; 1195 rc = mb86a20s_writereg(state, 0x51, 0x07); 1196 if (rc < 0) 1197 return rc; 1198 rc = mb86a20s_writereg(state, 0x51, 0x00); 1199 1200 return rc; 1201 } 1202 1203 reset_measurement: 1204 /* Reset counter to collect new data */ 1205 rc = mb86a20s_writereg(state, 0x50, 0xb1); 1206 if (rc < 0) 1207 return rc; 1208 rc = mb86a20s_readreg(state, 0x51); 1209 if (rc < 0) 1210 return rc; 1211 val = rc; 1212 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); 1213 if (rc < 0) 1214 return rc; 1215 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); 1216 1217 return rc; 1218 } 1219 1220 struct linear_segments { 1221 unsigned x, y; 1222 }; 1223 1224 /* 1225 * All tables below return a dB/1000 measurement 1226 */ 1227 1228 static const struct linear_segments cnr_to_db_table[] = { 1229 { 19648, 0}, 1230 { 18187, 1000}, 1231 { 16534, 2000}, 1232 { 14823, 3000}, 1233 { 13161, 4000}, 1234 { 11622, 5000}, 1235 { 10279, 6000}, 1236 { 9089, 7000}, 1237 { 8042, 8000}, 1238 { 7137, 9000}, 1239 { 6342, 10000}, 1240 { 5641, 11000}, 1241 { 5030, 12000}, 1242 { 4474, 13000}, 1243 { 3988, 14000}, 1244 { 3556, 15000}, 1245 { 3180, 16000}, 1246 { 2841, 17000}, 1247 { 2541, 18000}, 1248 { 2276, 19000}, 1249 { 2038, 20000}, 1250 { 1800, 21000}, 1251 { 1625, 22000}, 1252 { 1462, 23000}, 1253 { 1324, 24000}, 1254 { 1175, 25000}, 1255 { 1063, 26000}, 1256 { 980, 27000}, 1257 { 907, 28000}, 1258 { 840, 29000}, 1259 { 788, 30000}, 1260 }; 1261 1262 static const struct linear_segments cnr_64qam_table[] = { 1263 { 3922688, 0}, 1264 { 3920384, 1000}, 1265 { 3902720, 2000}, 1266 { 3894784, 3000}, 1267 { 3882496, 4000}, 1268 { 3872768, 5000}, 1269 { 3858944, 6000}, 1270 { 3851520, 7000}, 1271 { 3838976, 8000}, 1272 { 3829248, 9000}, 1273 { 3818240, 10000}, 1274 { 3806976, 11000}, 1275 { 3791872, 12000}, 1276 { 3767040, 13000}, 1277 { 3720960, 14000}, 1278 { 3637504, 15000}, 1279 { 3498496, 16000}, 1280 { 3296000, 17000}, 1281 { 3031040, 18000}, 1282 { 2715392, 19000}, 1283 { 2362624, 20000}, 1284 { 1963264, 21000}, 1285 { 1649664, 22000}, 1286 { 1366784, 23000}, 1287 { 1120768, 24000}, 1288 { 890880, 25000}, 1289 { 723456, 26000}, 1290 { 612096, 27000}, 1291 { 518912, 28000}, 1292 { 448256, 29000}, 1293 { 388864, 30000}, 1294 }; 1295 1296 static const struct linear_segments cnr_16qam_table[] = { 1297 { 5314816, 0}, 1298 { 5219072, 1000}, 1299 { 5118720, 2000}, 1300 { 4998912, 3000}, 1301 { 4875520, 4000}, 1302 { 4736000, 5000}, 1303 { 4604160, 6000}, 1304 { 4458752, 7000}, 1305 { 4300288, 8000}, 1306 { 4092928, 9000}, 1307 { 3836160, 10000}, 1308 { 3521024, 11000}, 1309 { 3155968, 12000}, 1310 { 2756864, 13000}, 1311 { 2347008, 14000}, 1312 { 1955072, 15000}, 1313 { 1593600, 16000}, 1314 { 1297920, 17000}, 1315 { 1043968, 18000}, 1316 { 839680, 19000}, 1317 { 672256, 20000}, 1318 { 523008, 21000}, 1319 { 424704, 22000}, 1320 { 345088, 23000}, 1321 { 280064, 24000}, 1322 { 221440, 25000}, 1323 { 179712, 26000}, 1324 { 151040, 27000}, 1325 { 128512, 28000}, 1326 { 110080, 29000}, 1327 { 95744, 30000}, 1328 }; 1329 1330 static const struct linear_segments cnr_qpsk_table[] = { 1331 { 2834176, 0}, 1332 { 2683648, 1000}, 1333 { 2536960, 2000}, 1334 { 2391808, 3000}, 1335 { 2133248, 4000}, 1336 { 1906176, 5000}, 1337 { 1666560, 6000}, 1338 { 1422080, 7000}, 1339 { 1189632, 8000}, 1340 { 976384, 9000}, 1341 { 790272, 10000}, 1342 { 633344, 11000}, 1343 { 505600, 12000}, 1344 { 402944, 13000}, 1345 { 320768, 14000}, 1346 { 255488, 15000}, 1347 { 204032, 16000}, 1348 { 163072, 17000}, 1349 { 130304, 18000}, 1350 { 105216, 19000}, 1351 { 83456, 20000}, 1352 { 65024, 21000}, 1353 { 52480, 22000}, 1354 { 42752, 23000}, 1355 { 34560, 24000}, 1356 { 27136, 25000}, 1357 { 22016, 26000}, 1358 { 18432, 27000}, 1359 { 15616, 28000}, 1360 { 13312, 29000}, 1361 { 11520, 30000}, 1362 }; 1363 1364 static u32 interpolate_value(u32 value, const struct linear_segments *segments, 1365 unsigned len) 1366 { 1367 u64 tmp64; 1368 u32 dx, dy; 1369 int i, ret; 1370 1371 if (value >= segments[0].x) 1372 return segments[0].y; 1373 if (value < segments[len-1].x) 1374 return segments[len-1].y; 1375 1376 for (i = 1; i < len - 1; i++) { 1377 /* If value is identical, no need to interpolate */ 1378 if (value == segments[i].x) 1379 return segments[i].y; 1380 if (value > segments[i].x) 1381 break; 1382 } 1383 1384 /* Linear interpolation between the two (x,y) points */ 1385 dy = segments[i].y - segments[i - 1].y; 1386 dx = segments[i - 1].x - segments[i].x; 1387 tmp64 = value - segments[i].x; 1388 tmp64 *= dy; 1389 do_div(tmp64, dx); 1390 ret = segments[i].y - tmp64; 1391 1392 return ret; 1393 } 1394 1395 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe) 1396 { 1397 struct mb86a20s_state *state = fe->demodulator_priv; 1398 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1399 u32 cnr_linear, cnr; 1400 int rc, val; 1401 1402 /* Check if CNR is available */ 1403 rc = mb86a20s_readreg(state, 0x45); 1404 if (rc < 0) 1405 return rc; 1406 1407 if (!(rc & 0x40)) { 1408 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n", 1409 __func__); 1410 return -EBUSY; 1411 } 1412 val = rc; 1413 1414 rc = mb86a20s_readreg(state, 0x46); 1415 if (rc < 0) 1416 return rc; 1417 cnr_linear = rc << 8; 1418 1419 rc = mb86a20s_readreg(state, 0x46); 1420 if (rc < 0) 1421 return rc; 1422 cnr_linear |= rc; 1423 1424 cnr = interpolate_value(cnr_linear, 1425 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table)); 1426 1427 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 1428 c->cnr.stat[0].svalue = cnr; 1429 1430 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", 1431 __func__, cnr / 1000, cnr % 1000, cnr_linear); 1432 1433 /* CNR counter reset */ 1434 rc = mb86a20s_writereg(state, 0x45, val | 0x10); 1435 if (rc < 0) 1436 return rc; 1437 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 1438 1439 return rc; 1440 } 1441 1442 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe) 1443 { 1444 struct mb86a20s_state *state = fe->demodulator_priv; 1445 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1446 u32 mer, cnr; 1447 int rc, val, layer; 1448 const struct linear_segments *segs; 1449 unsigned segs_len; 1450 1451 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1452 1453 /* Check if the measures are already available */ 1454 rc = mb86a20s_writereg(state, 0x50, 0x5b); 1455 if (rc < 0) 1456 return rc; 1457 rc = mb86a20s_readreg(state, 0x51); 1458 if (rc < 0) 1459 return rc; 1460 1461 /* Check if data is available */ 1462 if (!(rc & 0x01)) { 1463 dev_dbg(&state->i2c->dev, 1464 "%s: MER measures aren't available yet.\n", __func__); 1465 return -EBUSY; 1466 } 1467 1468 /* Read all layers */ 1469 for (layer = 0; layer < NUM_LAYERS; layer++) { 1470 if (!(c->isdbt_layer_enabled & (1 << layer))) { 1471 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1472 continue; 1473 } 1474 1475 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3); 1476 if (rc < 0) 1477 return rc; 1478 rc = mb86a20s_readreg(state, 0x51); 1479 if (rc < 0) 1480 return rc; 1481 mer = rc << 16; 1482 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3); 1483 if (rc < 0) 1484 return rc; 1485 rc = mb86a20s_readreg(state, 0x51); 1486 if (rc < 0) 1487 return rc; 1488 mer |= rc << 8; 1489 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3); 1490 if (rc < 0) 1491 return rc; 1492 rc = mb86a20s_readreg(state, 0x51); 1493 if (rc < 0) 1494 return rc; 1495 mer |= rc; 1496 1497 switch (c->layer[layer].modulation) { 1498 case DQPSK: 1499 case QPSK: 1500 segs = cnr_qpsk_table; 1501 segs_len = ARRAY_SIZE(cnr_qpsk_table); 1502 break; 1503 case QAM_16: 1504 segs = cnr_16qam_table; 1505 segs_len = ARRAY_SIZE(cnr_16qam_table); 1506 break; 1507 default: 1508 case QAM_64: 1509 segs = cnr_64qam_table; 1510 segs_len = ARRAY_SIZE(cnr_64qam_table); 1511 break; 1512 } 1513 cnr = interpolate_value(mer, segs, segs_len); 1514 1515 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL; 1516 c->cnr.stat[1 + layer].svalue = cnr; 1517 1518 dev_dbg(&state->i2c->dev, 1519 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n", 1520 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer); 1521 1522 } 1523 1524 /* Start a new MER measurement */ 1525 /* MER counter reset */ 1526 rc = mb86a20s_writereg(state, 0x50, 0x50); 1527 if (rc < 0) 1528 return rc; 1529 rc = mb86a20s_readreg(state, 0x51); 1530 if (rc < 0) 1531 return rc; 1532 val = rc; 1533 1534 rc = mb86a20s_writereg(state, 0x51, val | 0x01); 1535 if (rc < 0) 1536 return rc; 1537 rc = mb86a20s_writereg(state, 0x51, val & 0x06); 1538 if (rc < 0) 1539 return rc; 1540 1541 return 0; 1542 } 1543 1544 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) 1545 { 1546 struct mb86a20s_state *state = fe->demodulator_priv; 1547 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1548 int layer; 1549 1550 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1551 1552 /* Fill the length of each status counter */ 1553 1554 /* Only global stats */ 1555 c->strength.len = 1; 1556 1557 /* Per-layer stats - 3 layers + global */ 1558 c->cnr.len = NUM_LAYERS + 1; 1559 c->pre_bit_error.len = NUM_LAYERS + 1; 1560 c->pre_bit_count.len = NUM_LAYERS + 1; 1561 c->post_bit_error.len = NUM_LAYERS + 1; 1562 c->post_bit_count.len = NUM_LAYERS + 1; 1563 c->block_error.len = NUM_LAYERS + 1; 1564 c->block_count.len = NUM_LAYERS + 1; 1565 1566 /* Signal is always available */ 1567 c->strength.stat[0].scale = FE_SCALE_RELATIVE; 1568 c->strength.stat[0].uvalue = 0; 1569 1570 /* Put all of them at FE_SCALE_NOT_AVAILABLE */ 1571 for (layer = 0; layer < NUM_LAYERS + 1; layer++) { 1572 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1573 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1574 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1575 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1576 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1577 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1578 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; 1579 } 1580 } 1581 1582 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr) 1583 { 1584 struct mb86a20s_state *state = fe->demodulator_priv; 1585 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1586 int rc = 0, layer; 1587 u32 bit_error = 0, bit_count = 0; 1588 u32 t_pre_bit_error = 0, t_pre_bit_count = 0; 1589 u32 t_post_bit_error = 0, t_post_bit_count = 0; 1590 u32 block_error = 0, block_count = 0; 1591 u32 t_block_error = 0, t_block_count = 0; 1592 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0; 1593 int per_layers = 0; 1594 1595 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1596 1597 mb86a20s_get_main_CNR(fe); 1598 1599 /* Get per-layer stats */ 1600 mb86a20s_get_blk_error_layer_CNR(fe); 1601 1602 /* 1603 * At state 7, only CNR is available 1604 * For BER measures, state=9 is required 1605 * FIXME: we may get MER measures with state=8 1606 */ 1607 if (status_nr < 9) 1608 return 0; 1609 1610 for (layer = 0; layer < NUM_LAYERS; layer++) { 1611 if (c->isdbt_layer_enabled & (1 << layer)) { 1612 /* Layer is active and has rc segments */ 1613 active_layers++; 1614 1615 /* Handle BER before vterbi */ 1616 rc = mb86a20s_get_pre_ber(fe, layer, 1617 &bit_error, &bit_count); 1618 if (rc >= 0) { 1619 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1620 c->pre_bit_error.stat[1 + layer].uvalue += bit_error; 1621 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1622 c->pre_bit_count.stat[1 + layer].uvalue += bit_count; 1623 } else if (rc != -EBUSY) { 1624 /* 1625 * If an I/O error happened, 1626 * measures are now unavailable 1627 */ 1628 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1629 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1630 dev_err(&state->i2c->dev, 1631 "%s: Can't get BER for layer %c (error %d).\n", 1632 __func__, 'A' + layer, rc); 1633 } 1634 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1635 pre_ber_layers++; 1636 1637 /* Handle BER post vterbi */ 1638 rc = mb86a20s_get_post_ber(fe, layer, 1639 &bit_error, &bit_count); 1640 if (rc >= 0) { 1641 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1642 c->post_bit_error.stat[1 + layer].uvalue += bit_error; 1643 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1644 c->post_bit_count.stat[1 + layer].uvalue += bit_count; 1645 } else if (rc != -EBUSY) { 1646 /* 1647 * If an I/O error happened, 1648 * measures are now unavailable 1649 */ 1650 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1651 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1652 dev_err(&state->i2c->dev, 1653 "%s: Can't get BER for layer %c (error %d).\n", 1654 __func__, 'A' + layer, rc); 1655 } 1656 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1657 post_ber_layers++; 1658 1659 /* Handle Block errors for PER/UCB reports */ 1660 rc = mb86a20s_get_blk_error(fe, layer, 1661 &block_error, 1662 &block_count); 1663 if (rc >= 0) { 1664 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER; 1665 c->block_error.stat[1 + layer].uvalue += block_error; 1666 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER; 1667 c->block_count.stat[1 + layer].uvalue += block_count; 1668 } else if (rc != -EBUSY) { 1669 /* 1670 * If an I/O error happened, 1671 * measures are now unavailable 1672 */ 1673 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1674 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; 1675 dev_err(&state->i2c->dev, 1676 "%s: Can't get PER for layer %c (error %d).\n", 1677 __func__, 'A' + layer, rc); 1678 1679 } 1680 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) 1681 per_layers++; 1682 1683 /* Update total preBER */ 1684 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue; 1685 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue; 1686 1687 /* Update total postBER */ 1688 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue; 1689 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue; 1690 1691 /* Update total PER */ 1692 t_block_error += c->block_error.stat[1 + layer].uvalue; 1693 t_block_count += c->block_count.stat[1 + layer].uvalue; 1694 } 1695 } 1696 1697 /* 1698 * Start showing global count if at least one error count is 1699 * available. 1700 */ 1701 if (pre_ber_layers) { 1702 /* 1703 * At least one per-layer BER measure was read. We can now 1704 * calculate the total BER 1705 * 1706 * Total Bit Error/Count is calculated as the sum of the 1707 * bit errors on all active layers. 1708 */ 1709 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1710 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; 1711 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1712 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; 1713 } else { 1714 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1715 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1716 } 1717 1718 /* 1719 * Start showing global count if at least one error count is 1720 * available. 1721 */ 1722 if (post_ber_layers) { 1723 /* 1724 * At least one per-layer BER measure was read. We can now 1725 * calculate the total BER 1726 * 1727 * Total Bit Error/Count is calculated as the sum of the 1728 * bit errors on all active layers. 1729 */ 1730 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1731 c->post_bit_error.stat[0].uvalue = t_post_bit_error; 1732 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1733 c->post_bit_count.stat[0].uvalue = t_post_bit_count; 1734 } else { 1735 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1736 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1737 } 1738 1739 if (per_layers) { 1740 /* 1741 * At least one per-layer UCB measure was read. We can now 1742 * calculate the total UCB 1743 * 1744 * Total block Error/Count is calculated as the sum of the 1745 * block errors on all active layers. 1746 */ 1747 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1748 c->block_error.stat[0].uvalue = t_block_error; 1749 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1750 c->block_count.stat[0].uvalue = t_block_count; 1751 } else { 1752 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1753 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1754 } 1755 1756 return rc; 1757 } 1758 1759 /* 1760 * The functions below are called via DVB callbacks, so they need to 1761 * properly use the I2C gate control 1762 */ 1763 1764 static int mb86a20s_initfe(struct dvb_frontend *fe) 1765 { 1766 struct mb86a20s_state *state = fe->demodulator_priv; 1767 u64 pll; 1768 u32 fclk; 1769 int rc; 1770 u8 regD5 = 1, reg71, reg09 = 0x3a; 1771 1772 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1773 1774 if (fe->ops.i2c_gate_ctrl) 1775 fe->ops.i2c_gate_ctrl(fe, 0); 1776 1777 /* Initialize the frontend */ 1778 rc = mb86a20s_writeregdata(state, mb86a20s_init1); 1779 if (rc < 0) 1780 goto err; 1781 1782 if (!state->inversion) 1783 reg09 |= 0x04; 1784 rc = mb86a20s_writereg(state, 0x09, reg09); 1785 if (rc < 0) 1786 goto err; 1787 if (!state->bw) 1788 reg71 = 1; 1789 else 1790 reg71 = 0; 1791 rc = mb86a20s_writereg(state, 0x39, reg71); 1792 if (rc < 0) 1793 goto err; 1794 rc = mb86a20s_writereg(state, 0x71, state->bw); 1795 if (rc < 0) 1796 goto err; 1797 if (state->subchannel) { 1798 rc = mb86a20s_writereg(state, 0x44, state->subchannel); 1799 if (rc < 0) 1800 goto err; 1801 } 1802 1803 fclk = state->config->fclk; 1804 if (!fclk) 1805 fclk = 32571428; 1806 1807 /* Adjust IF frequency to match tuner */ 1808 if (fe->ops.tuner_ops.get_if_frequency) 1809 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq); 1810 1811 if (!state->if_freq) 1812 state->if_freq = 3300000; 1813 1814 pll = (((u64)1) << 34) * state->if_freq; 1815 do_div(pll, 63 * fclk); 1816 pll = (1 << 25) - pll; 1817 rc = mb86a20s_writereg(state, 0x28, 0x2a); 1818 if (rc < 0) 1819 goto err; 1820 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1821 if (rc < 0) 1822 goto err; 1823 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1824 if (rc < 0) 1825 goto err; 1826 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1827 if (rc < 0) 1828 goto err; 1829 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n", 1830 __func__, fclk, state->if_freq, (long long)pll); 1831 1832 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */ 1833 pll = state->if_freq * 1677721600L; 1834 do_div(pll, 1628571429L); 1835 rc = mb86a20s_writereg(state, 0x28, 0x20); 1836 if (rc < 0) 1837 goto err; 1838 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1839 if (rc < 0) 1840 goto err; 1841 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1842 if (rc < 0) 1843 goto err; 1844 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1845 if (rc < 0) 1846 goto err; 1847 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n", 1848 __func__, state->if_freq, (long long)pll); 1849 1850 if (!state->config->is_serial) 1851 regD5 &= ~1; 1852 1853 rc = mb86a20s_writereg(state, 0x50, 0xd5); 1854 if (rc < 0) 1855 goto err; 1856 rc = mb86a20s_writereg(state, 0x51, regD5); 1857 if (rc < 0) 1858 goto err; 1859 1860 rc = mb86a20s_writeregdata(state, mb86a20s_init2); 1861 if (rc < 0) 1862 goto err; 1863 1864 1865 err: 1866 if (fe->ops.i2c_gate_ctrl) 1867 fe->ops.i2c_gate_ctrl(fe, 1); 1868 1869 if (rc < 0) { 1870 state->need_init = true; 1871 dev_info(&state->i2c->dev, 1872 "mb86a20s: Init failed. Will try again later\n"); 1873 } else { 1874 state->need_init = false; 1875 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); 1876 } 1877 return rc; 1878 } 1879 1880 static int mb86a20s_set_frontend(struct dvb_frontend *fe) 1881 { 1882 struct mb86a20s_state *state = fe->demodulator_priv; 1883 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1884 int rc, if_freq; 1885 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1886 1887 if (!c->isdbt_layer_enabled) 1888 c->isdbt_layer_enabled = 7; 1889 1890 if (c->isdbt_layer_enabled == 1) 1891 state->bw = MB86A20S_1SEG; 1892 else if (c->isdbt_partial_reception) 1893 state->bw = MB86A20S_13SEG_PARTIAL; 1894 else 1895 state->bw = MB86A20S_13SEG; 1896 1897 if (c->inversion == INVERSION_ON) 1898 state->inversion = true; 1899 else 1900 state->inversion = false; 1901 1902 if (!c->isdbt_sb_mode) { 1903 state->subchannel = 0; 1904 } else { 1905 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel)) 1906 c->isdbt_sb_subchannel = 0; 1907 1908 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel]; 1909 } 1910 1911 /* 1912 * Gate should already be opened, but it doesn't hurt to 1913 * double-check 1914 */ 1915 if (fe->ops.i2c_gate_ctrl) 1916 fe->ops.i2c_gate_ctrl(fe, 1); 1917 fe->ops.tuner_ops.set_params(fe); 1918 1919 if (fe->ops.tuner_ops.get_if_frequency) 1920 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq); 1921 1922 /* 1923 * Make it more reliable: if, for some reason, the initial 1924 * device initialization doesn't happen, initialize it when 1925 * a SBTVD parameters are adjusted. 1926 * 1927 * Unfortunately, due to a hard to track bug at tda829x/tda18271, 1928 * the agc callback logic is not called during DVB attach time, 1929 * causing mb86a20s to not be initialized with Kworld SBTVD. 1930 * So, this hack is needed, in order to make Kworld SBTVD to work. 1931 * 1932 * It is also needed to change the IF after the initial init. 1933 * 1934 * HACK: Always init the frontend when set_frontend is called: 1935 * it was noticed that, on some devices, it fails to lock on a 1936 * different channel. So, it is better to reset everything, even 1937 * wasting some time, than to loose channel lock. 1938 */ 1939 mb86a20s_initfe(fe); 1940 1941 if (fe->ops.i2c_gate_ctrl) 1942 fe->ops.i2c_gate_ctrl(fe, 0); 1943 1944 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); 1945 mb86a20s_reset_counters(fe); 1946 mb86a20s_stats_not_ready(fe); 1947 1948 if (fe->ops.i2c_gate_ctrl) 1949 fe->ops.i2c_gate_ctrl(fe, 1); 1950 1951 return rc; 1952 } 1953 1954 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, 1955 enum fe_status *status) 1956 { 1957 struct mb86a20s_state *state = fe->demodulator_priv; 1958 int rc, status_nr; 1959 1960 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1961 1962 if (fe->ops.i2c_gate_ctrl) 1963 fe->ops.i2c_gate_ctrl(fe, 0); 1964 1965 /* Get lock */ 1966 status_nr = mb86a20s_read_status(fe, status); 1967 if (status_nr < 7) { 1968 mb86a20s_stats_not_ready(fe); 1969 mb86a20s_reset_frontend_cache(fe); 1970 } 1971 if (status_nr < 0) { 1972 dev_err(&state->i2c->dev, 1973 "%s: Can't read frontend lock status\n", __func__); 1974 goto error; 1975 } 1976 1977 /* Get signal strength */ 1978 rc = mb86a20s_read_signal_strength(fe); 1979 if (rc < 0) { 1980 dev_err(&state->i2c->dev, 1981 "%s: Can't reset VBER registers.\n", __func__); 1982 mb86a20s_stats_not_ready(fe); 1983 mb86a20s_reset_frontend_cache(fe); 1984 1985 rc = 0; /* Status is OK */ 1986 goto error; 1987 } 1988 1989 if (status_nr >= 7) { 1990 /* Get TMCC info*/ 1991 rc = mb86a20s_get_frontend(fe); 1992 if (rc < 0) { 1993 dev_err(&state->i2c->dev, 1994 "%s: Can't get FE TMCC data.\n", __func__); 1995 rc = 0; /* Status is OK */ 1996 goto error; 1997 } 1998 1999 /* Get statistics */ 2000 rc = mb86a20s_get_stats(fe, status_nr); 2001 if (rc < 0 && rc != -EBUSY) { 2002 dev_err(&state->i2c->dev, 2003 "%s: Can't get FE statistics.\n", __func__); 2004 rc = 0; 2005 goto error; 2006 } 2007 rc = 0; /* Don't return EBUSY to userspace */ 2008 } 2009 goto ok; 2010 2011 error: 2012 mb86a20s_stats_not_ready(fe); 2013 2014 ok: 2015 if (fe->ops.i2c_gate_ctrl) 2016 fe->ops.i2c_gate_ctrl(fe, 1); 2017 2018 return rc; 2019 } 2020 2021 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, 2022 u16 *strength) 2023 { 2024 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 2025 2026 2027 *strength = c->strength.stat[0].uvalue; 2028 2029 return 0; 2030 } 2031 2032 static int mb86a20s_tune(struct dvb_frontend *fe, 2033 bool re_tune, 2034 unsigned int mode_flags, 2035 unsigned int *delay, 2036 enum fe_status *status) 2037 { 2038 struct mb86a20s_state *state = fe->demodulator_priv; 2039 int rc = 0; 2040 2041 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 2042 2043 if (re_tune) 2044 rc = mb86a20s_set_frontend(fe); 2045 2046 if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 2047 mb86a20s_read_status_and_stats(fe, status); 2048 2049 return rc; 2050 } 2051 2052 static void mb86a20s_release(struct dvb_frontend *fe) 2053 { 2054 struct mb86a20s_state *state = fe->demodulator_priv; 2055 2056 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 2057 2058 kfree(state); 2059 } 2060 2061 static struct dvb_frontend_ops mb86a20s_ops; 2062 2063 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, 2064 struct i2c_adapter *i2c) 2065 { 2066 struct mb86a20s_state *state; 2067 u8 rev; 2068 2069 dev_dbg(&i2c->dev, "%s called.\n", __func__); 2070 2071 /* allocate memory for the internal state */ 2072 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); 2073 if (state == NULL) { 2074 dev_err(&i2c->dev, 2075 "%s: unable to allocate memory for state\n", __func__); 2076 goto error; 2077 } 2078 2079 /* setup the state */ 2080 state->config = config; 2081 state->i2c = i2c; 2082 2083 /* create dvb_frontend */ 2084 memcpy(&state->frontend.ops, &mb86a20s_ops, 2085 sizeof(struct dvb_frontend_ops)); 2086 state->frontend.demodulator_priv = state; 2087 2088 /* Check if it is a mb86a20s frontend */ 2089 rev = mb86a20s_readreg(state, 0); 2090 2091 if (rev == 0x13) { 2092 dev_info(&i2c->dev, 2093 "Detected a Fujitsu mb86a20s frontend\n"); 2094 } else { 2095 dev_dbg(&i2c->dev, 2096 "Frontend revision %d is unknown - aborting.\n", 2097 rev); 2098 goto error; 2099 } 2100 2101 return &state->frontend; 2102 2103 error: 2104 kfree(state); 2105 return NULL; 2106 } 2107 EXPORT_SYMBOL(mb86a20s_attach); 2108 2109 static struct dvb_frontend_ops mb86a20s_ops = { 2110 .delsys = { SYS_ISDBT }, 2111 /* Use dib8000 values per default */ 2112 .info = { 2113 .name = "Fujitsu mb86A20s", 2114 .caps = FE_CAN_RECOVER | 2115 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 2116 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 2117 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2118 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | 2119 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 2120 /* Actually, those values depend on the used tuner */ 2121 .frequency_min = 45000000, 2122 .frequency_max = 864000000, 2123 .frequency_stepsize = 62500, 2124 }, 2125 2126 .release = mb86a20s_release, 2127 2128 .init = mb86a20s_initfe, 2129 .set_frontend = mb86a20s_set_frontend, 2130 .read_status = mb86a20s_read_status_and_stats, 2131 .read_signal_strength = mb86a20s_read_signal_strength_from_cache, 2132 .tune = mb86a20s_tune, 2133 }; 2134 2135 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); 2136 MODULE_AUTHOR("Mauro Carvalho Chehab"); 2137 MODULE_LICENSE("GPL"); 2138