19a0bf528SMauro Carvalho Chehab /* 29a0bf528SMauro Carvalho Chehab * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver 39a0bf528SMauro Carvalho Chehab * 4a77cfcacSMauro Carvalho Chehab * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com> 59a0bf528SMauro Carvalho Chehab * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> 69a0bf528SMauro Carvalho Chehab * 79a0bf528SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or 89a0bf528SMauro Carvalho Chehab * modify it under the terms of the GNU General Public License as 99a0bf528SMauro Carvalho Chehab * published by the Free Software Foundation version 2. 109a0bf528SMauro Carvalho Chehab * 119a0bf528SMauro Carvalho Chehab * This program is distributed in the hope that it will be useful, 129a0bf528SMauro Carvalho Chehab * but WITHOUT ANY WARRANTY; without even the implied warranty of 139a0bf528SMauro Carvalho Chehab * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 149a0bf528SMauro Carvalho Chehab * General Public License for more details. 159a0bf528SMauro Carvalho Chehab */ 169a0bf528SMauro Carvalho Chehab 179a0bf528SMauro Carvalho Chehab #include <linux/kernel.h> 189a0bf528SMauro Carvalho Chehab #include <asm/div64.h> 199a0bf528SMauro Carvalho Chehab 209a0bf528SMauro Carvalho Chehab #include "dvb_frontend.h" 219a0bf528SMauro Carvalho Chehab #include "mb86a20s.h" 229a0bf528SMauro Carvalho Chehab 234f62a20dSMauro Carvalho Chehab #define NUM_LAYERS 3 244f62a20dSMauro Carvalho Chehab 259a0bf528SMauro Carvalho Chehab static int debug = 1; 269a0bf528SMauro Carvalho Chehab module_param(debug, int, 0644); 279a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 289a0bf528SMauro Carvalho Chehab 2904fa725eSMauro Carvalho Chehab enum mb86a20s_bandwidth { 3004fa725eSMauro Carvalho Chehab MB86A20S_13SEG = 0, 3104fa725eSMauro Carvalho Chehab MB86A20S_13SEG_PARTIAL = 1, 3204fa725eSMauro Carvalho Chehab MB86A20S_1SEG = 2, 3304fa725eSMauro Carvalho Chehab MB86A20S_3SEG = 3, 3404fa725eSMauro Carvalho Chehab }; 3504fa725eSMauro Carvalho Chehab 3604fa725eSMauro Carvalho Chehab u8 mb86a20s_subchannel[] = { 3704fa725eSMauro Carvalho Chehab 0xb0, 0xc0, 0xd0, 0xe0, 3804fa725eSMauro Carvalho Chehab 0xf0, 0x00, 0x10, 0x20, 3904fa725eSMauro Carvalho Chehab }; 4004fa725eSMauro Carvalho Chehab 419a0bf528SMauro Carvalho Chehab struct mb86a20s_state { 429a0bf528SMauro Carvalho Chehab struct i2c_adapter *i2c; 439a0bf528SMauro Carvalho Chehab const struct mb86a20s_config *config; 4409b6d21eSMauro Carvalho Chehab u32 last_frequency; 459a0bf528SMauro Carvalho Chehab 469a0bf528SMauro Carvalho Chehab struct dvb_frontend frontend; 479a0bf528SMauro Carvalho Chehab 48768e6dadSMauro Carvalho Chehab u32 if_freq; 4904fa725eSMauro Carvalho Chehab enum mb86a20s_bandwidth bw; 5004fa725eSMauro Carvalho Chehab bool inversion; 5104fa725eSMauro Carvalho Chehab u32 subchannel; 52768e6dadSMauro Carvalho Chehab 534f62a20dSMauro Carvalho Chehab u32 estimated_rate[NUM_LAYERS]; 540921ecfdSMauro Carvalho Chehab unsigned long get_strength_time; 55d01a8ee3SMauro Carvalho Chehab 569a0bf528SMauro Carvalho Chehab bool need_init; 579a0bf528SMauro Carvalho Chehab }; 589a0bf528SMauro Carvalho Chehab 599a0bf528SMauro Carvalho Chehab struct regdata { 609a0bf528SMauro Carvalho Chehab u8 reg; 619a0bf528SMauro Carvalho Chehab u8 data; 629a0bf528SMauro Carvalho Chehab }; 639a0bf528SMauro Carvalho Chehab 64d01a8ee3SMauro Carvalho Chehab #define BER_SAMPLING_RATE 1 /* Seconds */ 65d01a8ee3SMauro Carvalho Chehab 669a0bf528SMauro Carvalho Chehab /* 679a0bf528SMauro Carvalho Chehab * Initialization sequence: Use whatevere default values that PV SBTVD 689a0bf528SMauro Carvalho Chehab * does on its initialisation, obtained via USB snoop 699a0bf528SMauro Carvalho Chehab */ 70768e6dadSMauro Carvalho Chehab static struct regdata mb86a20s_init1[] = { 719a0bf528SMauro Carvalho Chehab { 0x70, 0x0f }, 729a0bf528SMauro Carvalho Chehab { 0x70, 0xff }, 739a0bf528SMauro Carvalho Chehab { 0x08, 0x01 }, 7417e67d4cSMauro Carvalho Chehab { 0x50, 0xd1 }, { 0x51, 0x20 }, 75768e6dadSMauro Carvalho Chehab }; 76768e6dadSMauro Carvalho Chehab 77768e6dadSMauro Carvalho Chehab static struct regdata mb86a20s_init2[] = { 789a0bf528SMauro Carvalho Chehab { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, 799a0bf528SMauro Carvalho Chehab { 0x3b, 0x21 }, 8017e67d4cSMauro Carvalho Chehab { 0x3c, 0x38 }, 819a0bf528SMauro Carvalho Chehab { 0x01, 0x0d }, 8217e67d4cSMauro Carvalho Chehab { 0x04, 0x08 }, { 0x05, 0x03 }, 839a0bf528SMauro Carvalho Chehab { 0x04, 0x0e }, { 0x05, 0x00 }, 8417e67d4cSMauro Carvalho Chehab { 0x04, 0x0f }, { 0x05, 0x37 }, 8517e67d4cSMauro Carvalho Chehab { 0x04, 0x0b }, { 0x05, 0x78 }, 869a0bf528SMauro Carvalho Chehab { 0x04, 0x00 }, { 0x05, 0x00 }, 8717e67d4cSMauro Carvalho Chehab { 0x04, 0x01 }, { 0x05, 0x1e }, 8817e67d4cSMauro Carvalho Chehab { 0x04, 0x02 }, { 0x05, 0x07 }, 8917e67d4cSMauro Carvalho Chehab { 0x04, 0x03 }, { 0x05, 0xd0 }, 909a0bf528SMauro Carvalho Chehab { 0x04, 0x09 }, { 0x05, 0x00 }, 919a0bf528SMauro Carvalho Chehab { 0x04, 0x0a }, { 0x05, 0xff }, 9217e67d4cSMauro Carvalho Chehab { 0x04, 0x27 }, { 0x05, 0x00 }, 939a0bf528SMauro Carvalho Chehab { 0x04, 0x28 }, { 0x05, 0x00 }, 9417e67d4cSMauro Carvalho Chehab { 0x04, 0x1e }, { 0x05, 0x00 }, 9517e67d4cSMauro Carvalho Chehab { 0x04, 0x29 }, { 0x05, 0x64 }, 9617e67d4cSMauro Carvalho Chehab { 0x04, 0x32 }, { 0x05, 0x02 }, 979a0bf528SMauro Carvalho Chehab { 0x04, 0x14 }, { 0x05, 0x02 }, 989a0bf528SMauro Carvalho Chehab { 0x04, 0x04 }, { 0x05, 0x00 }, 999a0bf528SMauro Carvalho Chehab { 0x04, 0x05 }, { 0x05, 0x22 }, 1009a0bf528SMauro Carvalho Chehab { 0x04, 0x06 }, { 0x05, 0x0e }, 1019a0bf528SMauro Carvalho Chehab { 0x04, 0x07 }, { 0x05, 0xd8 }, 1029a0bf528SMauro Carvalho Chehab { 0x04, 0x12 }, { 0x05, 0x00 }, 1039a0bf528SMauro Carvalho Chehab { 0x04, 0x13 }, { 0x05, 0xff }, 1049a0bf528SMauro Carvalho Chehab { 0x04, 0x15 }, { 0x05, 0x4e }, 1059a0bf528SMauro Carvalho Chehab { 0x04, 0x16 }, { 0x05, 0x20 }, 10609b6d21eSMauro Carvalho Chehab 10709b6d21eSMauro Carvalho Chehab /* 10809b6d21eSMauro Carvalho Chehab * On this demod, when the bit count reaches the count below, 10909b6d21eSMauro Carvalho Chehab * it collects the bit error count. The bit counters are initialized 11009b6d21eSMauro Carvalho Chehab * to 65535 here. This warrants that all of them will be quickly 11109b6d21eSMauro Carvalho Chehab * calculated when device gets locked. As TMCC is parsed, the values 112d01a8ee3SMauro Carvalho Chehab * will be adjusted later in the driver's code. 11309b6d21eSMauro Carvalho Chehab */ 11409b6d21eSMauro Carvalho Chehab { 0x52, 0x01 }, /* Turn on BER before Viterbi */ 11509b6d21eSMauro Carvalho Chehab { 0x50, 0xa7 }, { 0x51, 0x00 }, 1169a0bf528SMauro Carvalho Chehab { 0x50, 0xa8 }, { 0x51, 0xff }, 1179a0bf528SMauro Carvalho Chehab { 0x50, 0xa9 }, { 0x51, 0xff }, 11809b6d21eSMauro Carvalho Chehab { 0x50, 0xaa }, { 0x51, 0x00 }, 1199a0bf528SMauro Carvalho Chehab { 0x50, 0xab }, { 0x51, 0xff }, 1209a0bf528SMauro Carvalho Chehab { 0x50, 0xac }, { 0x51, 0xff }, 12109b6d21eSMauro Carvalho Chehab { 0x50, 0xad }, { 0x51, 0x00 }, 1229a0bf528SMauro Carvalho Chehab { 0x50, 0xae }, { 0x51, 0xff }, 1239a0bf528SMauro Carvalho Chehab { 0x50, 0xaf }, { 0x51, 0xff }, 12409b6d21eSMauro Carvalho Chehab 125d9b6f08aSMauro Carvalho Chehab /* 126d9b6f08aSMauro Carvalho Chehab * On this demod, post BER counts blocks. When the count reaches the 127d9b6f08aSMauro Carvalho Chehab * value below, it collects the block error count. The block counters 128d9b6f08aSMauro Carvalho Chehab * are initialized to 127 here. This warrants that all of them will be 129d9b6f08aSMauro Carvalho Chehab * quickly calculated when device gets locked. As TMCC is parsed, the 130d9b6f08aSMauro Carvalho Chehab * values will be adjusted later in the driver's code. 131d9b6f08aSMauro Carvalho Chehab */ 132d9b6f08aSMauro Carvalho Chehab { 0x5e, 0x07 }, /* Turn on BER after Viterbi */ 133d9b6f08aSMauro Carvalho Chehab { 0x50, 0xdc }, { 0x51, 0x00 }, 134d9b6f08aSMauro Carvalho Chehab { 0x50, 0xdd }, { 0x51, 0x7f }, 135d9b6f08aSMauro Carvalho Chehab { 0x50, 0xde }, { 0x51, 0x00 }, 136d9b6f08aSMauro Carvalho Chehab { 0x50, 0xdf }, { 0x51, 0x7f }, 137d9b6f08aSMauro Carvalho Chehab { 0x50, 0xe0 }, { 0x51, 0x00 }, 138d9b6f08aSMauro Carvalho Chehab { 0x50, 0xe1 }, { 0x51, 0x7f }, 139593ae89aSMauro Carvalho Chehab 140593ae89aSMauro Carvalho Chehab /* 141593ae89aSMauro Carvalho Chehab * On this demod, when the block count reaches the count below, 142593ae89aSMauro Carvalho Chehab * it collects the block error count. The block counters are initialized 143593ae89aSMauro Carvalho Chehab * to 127 here. This warrants that all of them will be quickly 144593ae89aSMauro Carvalho Chehab * calculated when device gets locked. As TMCC is parsed, the values 145593ae89aSMauro Carvalho Chehab * will be adjusted later in the driver's code. 146593ae89aSMauro Carvalho Chehab */ 147593ae89aSMauro Carvalho Chehab { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */ 148593ae89aSMauro Carvalho Chehab { 0x50, 0xb2 }, { 0x51, 0x00 }, 149593ae89aSMauro Carvalho Chehab { 0x50, 0xb3 }, { 0x51, 0x7f }, 150593ae89aSMauro Carvalho Chehab { 0x50, 0xb4 }, { 0x51, 0x00 }, 151593ae89aSMauro Carvalho Chehab { 0x50, 0xb5 }, { 0x51, 0x7f }, 152593ae89aSMauro Carvalho Chehab { 0x50, 0xb6 }, { 0x51, 0x00 }, 153593ae89aSMauro Carvalho Chehab { 0x50, 0xb7 }, { 0x51, 0x7f }, 15425188bd0SMauro Carvalho Chehab 15525188bd0SMauro Carvalho Chehab { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */ 15609b6d21eSMauro Carvalho Chehab { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ 15709b6d21eSMauro Carvalho Chehab { 0x45, 0x04 }, /* CN symbol 4 */ 15825188bd0SMauro Carvalho Chehab { 0x48, 0x04 }, /* CN manual mode */ 15925188bd0SMauro Carvalho Chehab 1609a0bf528SMauro Carvalho Chehab { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */ 1619a0bf528SMauro Carvalho Chehab { 0x50, 0xd6 }, { 0x51, 0x1f }, 1629a0bf528SMauro Carvalho Chehab { 0x50, 0xd2 }, { 0x51, 0x03 }, 16317e67d4cSMauro Carvalho Chehab { 0x50, 0xd7 }, { 0x51, 0xbf }, 16417e67d4cSMauro Carvalho Chehab { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff }, 16517e67d4cSMauro Carvalho Chehab { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c }, 166ce77d120SMauro Carvalho Chehab 167ce77d120SMauro Carvalho Chehab { 0x04, 0x40 }, { 0x05, 0x00 }, 16817e67d4cSMauro Carvalho Chehab { 0x28, 0x00 }, { 0x2b, 0x08 }, 16917e67d4cSMauro Carvalho Chehab { 0x28, 0x05 }, { 0x2b, 0x00 }, 1709a0bf528SMauro Carvalho Chehab { 0x1c, 0x01 }, 17117e67d4cSMauro Carvalho Chehab { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f }, 17217e67d4cSMauro Carvalho Chehab { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 }, 17317e67d4cSMauro Carvalho Chehab { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 }, 17417e67d4cSMauro Carvalho Chehab { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 }, 17517e67d4cSMauro Carvalho Chehab { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 }, 17617e67d4cSMauro Carvalho Chehab { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, 17717e67d4cSMauro Carvalho Chehab { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 }, 17817e67d4cSMauro Carvalho Chehab { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 }, 17917e67d4cSMauro Carvalho Chehab { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b }, 18017e67d4cSMauro Carvalho Chehab { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 }, 18117e67d4cSMauro Carvalho Chehab { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d }, 18217e67d4cSMauro Carvalho Chehab { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 }, 18317e67d4cSMauro Carvalho Chehab { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b }, 18417e67d4cSMauro Carvalho Chehab { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 18517e67d4cSMauro Carvalho Chehab { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 }, 18617e67d4cSMauro Carvalho Chehab { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 }, 18717e67d4cSMauro Carvalho Chehab { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 }, 18817e67d4cSMauro Carvalho Chehab { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, 18917e67d4cSMauro Carvalho Chehab { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, 19017e67d4cSMauro Carvalho Chehab { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef }, 19117e67d4cSMauro Carvalho Chehab { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 }, 19217e67d4cSMauro Carvalho Chehab { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 }, 19317e67d4cSMauro Carvalho Chehab { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d }, 19417e67d4cSMauro Carvalho Chehab { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 }, 19517e67d4cSMauro Carvalho Chehab { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba }, 1969a0bf528SMauro Carvalho Chehab { 0x50, 0x1e }, { 0x51, 0x5d }, 1979a0bf528SMauro Carvalho Chehab { 0x50, 0x22 }, { 0x51, 0x00 }, 1989a0bf528SMauro Carvalho Chehab { 0x50, 0x23 }, { 0x51, 0xc8 }, 1999a0bf528SMauro Carvalho Chehab { 0x50, 0x24 }, { 0x51, 0x00 }, 2009a0bf528SMauro Carvalho Chehab { 0x50, 0x25 }, { 0x51, 0xf0 }, 2019a0bf528SMauro Carvalho Chehab { 0x50, 0x26 }, { 0x51, 0x00 }, 2029a0bf528SMauro Carvalho Chehab { 0x50, 0x27 }, { 0x51, 0xc3 }, 2039a0bf528SMauro Carvalho Chehab { 0x50, 0x39 }, { 0x51, 0x02 }, 20417e67d4cSMauro Carvalho Chehab { 0xec, 0x0f }, 20517e67d4cSMauro Carvalho Chehab { 0xeb, 0x1f }, 2069a0bf528SMauro Carvalho Chehab { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 2079a0bf528SMauro Carvalho Chehab { 0xd0, 0x00 }, 2089a0bf528SMauro Carvalho Chehab }; 2099a0bf528SMauro Carvalho Chehab 2109a0bf528SMauro Carvalho Chehab static struct regdata mb86a20s_reset_reception[] = { 2119a0bf528SMauro Carvalho Chehab { 0x70, 0xf0 }, 2129a0bf528SMauro Carvalho Chehab { 0x70, 0xff }, 2139a0bf528SMauro Carvalho Chehab { 0x08, 0x01 }, 2149a0bf528SMauro Carvalho Chehab { 0x08, 0x00 }, 2159a0bf528SMauro Carvalho Chehab }; 2169a0bf528SMauro Carvalho Chehab 217d9b6f08aSMauro Carvalho Chehab static struct regdata mb86a20s_per_ber_reset[] = { 218d9b6f08aSMauro Carvalho Chehab { 0x53, 0x00 }, /* pre BER Counter reset */ 21909b6d21eSMauro Carvalho Chehab { 0x53, 0x07 }, 22009b6d21eSMauro Carvalho Chehab 221d9b6f08aSMauro Carvalho Chehab { 0x5f, 0x00 }, /* post BER Counter reset */ 222d9b6f08aSMauro Carvalho Chehab { 0x5f, 0x07 }, 223d9b6f08aSMauro Carvalho Chehab 22409b6d21eSMauro Carvalho Chehab { 0x50, 0xb1 }, /* PER Counter reset */ 22509b6d21eSMauro Carvalho Chehab { 0x51, 0x07 }, 22609b6d21eSMauro Carvalho Chehab { 0x51, 0x00 }, 22709b6d21eSMauro Carvalho Chehab }; 22809b6d21eSMauro Carvalho Chehab 229dd4493efSMauro Carvalho Chehab /* 230dd4493efSMauro Carvalho Chehab * I2C read/write functions and macros 231dd4493efSMauro Carvalho Chehab */ 232dd4493efSMauro Carvalho Chehab 2339a0bf528SMauro Carvalho Chehab static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, 23409b6d21eSMauro Carvalho Chehab u8 i2c_addr, u8 reg, u8 data) 2359a0bf528SMauro Carvalho Chehab { 2369a0bf528SMauro Carvalho Chehab u8 buf[] = { reg, data }; 2379a0bf528SMauro Carvalho Chehab struct i2c_msg msg = { 2389a0bf528SMauro Carvalho Chehab .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 2399a0bf528SMauro Carvalho Chehab }; 2409a0bf528SMauro Carvalho Chehab int rc; 2419a0bf528SMauro Carvalho Chehab 2429a0bf528SMauro Carvalho Chehab rc = i2c_transfer(state->i2c, &msg, 1); 2439a0bf528SMauro Carvalho Chehab if (rc != 1) { 244f66d81b5SMauro Carvalho Chehab dev_err(&state->i2c->dev, 245f66d81b5SMauro Carvalho Chehab "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", 246f66d81b5SMauro Carvalho Chehab __func__, rc, reg, data); 2479a0bf528SMauro Carvalho Chehab return rc; 2489a0bf528SMauro Carvalho Chehab } 2499a0bf528SMauro Carvalho Chehab 2509a0bf528SMauro Carvalho Chehab return 0; 2519a0bf528SMauro Carvalho Chehab } 2529a0bf528SMauro Carvalho Chehab 2539a0bf528SMauro Carvalho Chehab static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, 2549a0bf528SMauro Carvalho Chehab u8 i2c_addr, struct regdata *rd, int size) 2559a0bf528SMauro Carvalho Chehab { 2569a0bf528SMauro Carvalho Chehab int i, rc; 2579a0bf528SMauro Carvalho Chehab 2589a0bf528SMauro Carvalho Chehab for (i = 0; i < size; i++) { 2599a0bf528SMauro Carvalho Chehab rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, 2609a0bf528SMauro Carvalho Chehab rd[i].data); 2619a0bf528SMauro Carvalho Chehab if (rc < 0) 2629a0bf528SMauro Carvalho Chehab return rc; 2639a0bf528SMauro Carvalho Chehab } 2649a0bf528SMauro Carvalho Chehab return 0; 2659a0bf528SMauro Carvalho Chehab } 2669a0bf528SMauro Carvalho Chehab 2679a0bf528SMauro Carvalho Chehab static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, 2689a0bf528SMauro Carvalho Chehab u8 i2c_addr, u8 reg) 2699a0bf528SMauro Carvalho Chehab { 2709a0bf528SMauro Carvalho Chehab u8 val; 2719a0bf528SMauro Carvalho Chehab int rc; 2729a0bf528SMauro Carvalho Chehab struct i2c_msg msg[] = { 2739a0bf528SMauro Carvalho Chehab { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 2749a0bf528SMauro Carvalho Chehab { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } 2759a0bf528SMauro Carvalho Chehab }; 2769a0bf528SMauro Carvalho Chehab 2779a0bf528SMauro Carvalho Chehab rc = i2c_transfer(state->i2c, msg, 2); 2789a0bf528SMauro Carvalho Chehab 2799a0bf528SMauro Carvalho Chehab if (rc != 2) { 280f66d81b5SMauro Carvalho Chehab dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", 281f66d81b5SMauro Carvalho Chehab __func__, reg, rc); 282f66d81b5SMauro Carvalho Chehab return (rc < 0) ? rc : -EIO; 2839a0bf528SMauro Carvalho Chehab } 2849a0bf528SMauro Carvalho Chehab 2859a0bf528SMauro Carvalho Chehab return val; 2869a0bf528SMauro Carvalho Chehab } 2879a0bf528SMauro Carvalho Chehab 2889a0bf528SMauro Carvalho Chehab #define mb86a20s_readreg(state, reg) \ 2899a0bf528SMauro Carvalho Chehab mb86a20s_i2c_readreg(state, state->config->demod_address, reg) 2909a0bf528SMauro Carvalho Chehab #define mb86a20s_writereg(state, reg, val) \ 2919a0bf528SMauro Carvalho Chehab mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) 2929a0bf528SMauro Carvalho Chehab #define mb86a20s_writeregdata(state, regdata) \ 2939a0bf528SMauro Carvalho Chehab mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ 2949a0bf528SMauro Carvalho Chehab regdata, ARRAY_SIZE(regdata)) 2959a0bf528SMauro Carvalho Chehab 29609b6d21eSMauro Carvalho Chehab /* 29709b6d21eSMauro Carvalho Chehab * Ancillary internal routines (likely compiled inlined) 29809b6d21eSMauro Carvalho Chehab * 29909b6d21eSMauro Carvalho Chehab * The functions below assume that gateway lock has already obtained 30009b6d21eSMauro Carvalho Chehab */ 30109b6d21eSMauro Carvalho Chehab 302dd4493efSMauro Carvalho Chehab static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status) 3039a0bf528SMauro Carvalho Chehab { 3049a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 305dd4493efSMauro Carvalho Chehab int val; 3069a0bf528SMauro Carvalho Chehab 307dd4493efSMauro Carvalho Chehab *status = 0; 3089a0bf528SMauro Carvalho Chehab 309dd4493efSMauro Carvalho Chehab val = mb86a20s_readreg(state, 0x0a) & 0xf; 310dd4493efSMauro Carvalho Chehab if (val < 0) 311dd4493efSMauro Carvalho Chehab return val; 3129a0bf528SMauro Carvalho Chehab 313dd4493efSMauro Carvalho Chehab if (val >= 2) 314dd4493efSMauro Carvalho Chehab *status |= FE_HAS_SIGNAL; 3159a0bf528SMauro Carvalho Chehab 316dd4493efSMauro Carvalho Chehab if (val >= 4) 317dd4493efSMauro Carvalho Chehab *status |= FE_HAS_CARRIER; 3189a0bf528SMauro Carvalho Chehab 319dd4493efSMauro Carvalho Chehab if (val >= 5) 320dd4493efSMauro Carvalho Chehab *status |= FE_HAS_VITERBI; 3219a0bf528SMauro Carvalho Chehab 322dd4493efSMauro Carvalho Chehab if (val >= 7) 323dd4493efSMauro Carvalho Chehab *status |= FE_HAS_SYNC; 3249a0bf528SMauro Carvalho Chehab 325dd4493efSMauro Carvalho Chehab if (val >= 8) /* Maybe 9? */ 326dd4493efSMauro Carvalho Chehab *status |= FE_HAS_LOCK; 327dd4493efSMauro Carvalho Chehab 328f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", 329f66d81b5SMauro Carvalho Chehab __func__, *status, val); 330dd4493efSMauro Carvalho Chehab 33115b1c5a0SMauro Carvalho Chehab return val; 3329a0bf528SMauro Carvalho Chehab } 3339a0bf528SMauro Carvalho Chehab 33409b6d21eSMauro Carvalho Chehab static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) 3359a0bf528SMauro Carvalho Chehab { 3369a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 3370921ecfdSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 33809b6d21eSMauro Carvalho Chehab int rc; 3399a0bf528SMauro Carvalho Chehab unsigned rf_max, rf_min, rf; 3409a0bf528SMauro Carvalho Chehab 3410921ecfdSMauro Carvalho Chehab if (state->get_strength_time && 3420921ecfdSMauro Carvalho Chehab (!time_after(jiffies, state->get_strength_time))) 3430921ecfdSMauro Carvalho Chehab return c->strength.stat[0].uvalue; 3440921ecfdSMauro Carvalho Chehab 3450921ecfdSMauro Carvalho Chehab /* Reset its value if an error happen */ 3460921ecfdSMauro Carvalho Chehab c->strength.stat[0].uvalue = 0; 3470921ecfdSMauro Carvalho Chehab 3489a0bf528SMauro Carvalho Chehab /* Does a binary search to get RF strength */ 3499a0bf528SMauro Carvalho Chehab rf_max = 0xfff; 3509a0bf528SMauro Carvalho Chehab rf_min = 0; 3519a0bf528SMauro Carvalho Chehab do { 3529a0bf528SMauro Carvalho Chehab rf = (rf_max + rf_min) / 2; 35309b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x04, 0x1f); 35409b6d21eSMauro Carvalho Chehab if (rc < 0) 35509b6d21eSMauro Carvalho Chehab return rc; 35609b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x05, rf >> 8); 35709b6d21eSMauro Carvalho Chehab if (rc < 0) 35809b6d21eSMauro Carvalho Chehab return rc; 35909b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x04, 0x20); 36009b6d21eSMauro Carvalho Chehab if (rc < 0) 36109b6d21eSMauro Carvalho Chehab return rc; 362dad78c56SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x05, rf); 36309b6d21eSMauro Carvalho Chehab if (rc < 0) 36409b6d21eSMauro Carvalho Chehab return rc; 3659a0bf528SMauro Carvalho Chehab 36609b6d21eSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x02); 36709b6d21eSMauro Carvalho Chehab if (rc < 0) 36809b6d21eSMauro Carvalho Chehab return rc; 36909b6d21eSMauro Carvalho Chehab if (rc & 0x08) 3709a0bf528SMauro Carvalho Chehab rf_min = (rf_max + rf_min) / 2; 3719a0bf528SMauro Carvalho Chehab else 3729a0bf528SMauro Carvalho Chehab rf_max = (rf_max + rf_min) / 2; 3739a0bf528SMauro Carvalho Chehab if (rf_max - rf_min < 4) { 37409b6d21eSMauro Carvalho Chehab rf = (rf_max + rf_min) / 2; 37509b6d21eSMauro Carvalho Chehab 37609b6d21eSMauro Carvalho Chehab /* Rescale it from 2^12 (4096) to 2^16 */ 3770921ecfdSMauro Carvalho Chehab rf = rf << (16 - 12); 3780921ecfdSMauro Carvalho Chehab if (rf) 3790921ecfdSMauro Carvalho Chehab rf |= (1 << 12) - 1; 3800921ecfdSMauro Carvalho Chehab 381f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 382f66d81b5SMauro Carvalho Chehab "%s: signal strength = %d (%d < RF=%d < %d)\n", 383f66d81b5SMauro Carvalho Chehab __func__, rf, rf_min, rf >> 4, rf_max); 3840921ecfdSMauro Carvalho Chehab c->strength.stat[0].uvalue = rf; 3850921ecfdSMauro Carvalho Chehab state->get_strength_time = jiffies + 3860921ecfdSMauro Carvalho Chehab msecs_to_jiffies(1000); 3870921ecfdSMauro Carvalho Chehab return 0; 3889a0bf528SMauro Carvalho Chehab } 3899a0bf528SMauro Carvalho Chehab } while (1); 3909a0bf528SMauro Carvalho Chehab } 3919a0bf528SMauro Carvalho Chehab 3929a0bf528SMauro Carvalho Chehab static int mb86a20s_get_modulation(struct mb86a20s_state *state, 3939a0bf528SMauro Carvalho Chehab unsigned layer) 3949a0bf528SMauro Carvalho Chehab { 3959a0bf528SMauro Carvalho Chehab int rc; 3969a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 3979a0bf528SMauro Carvalho Chehab [0] = 0x86, /* Layer A */ 3989a0bf528SMauro Carvalho Chehab [1] = 0x8a, /* Layer B */ 3999a0bf528SMauro Carvalho Chehab [2] = 0x8e, /* Layer C */ 4009a0bf528SMauro Carvalho Chehab }; 4019a0bf528SMauro Carvalho Chehab 4029a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 4039a0bf528SMauro Carvalho Chehab return -EINVAL; 4049a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 4059a0bf528SMauro Carvalho Chehab if (rc < 0) 4069a0bf528SMauro Carvalho Chehab return rc; 4079a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 4089a0bf528SMauro Carvalho Chehab if (rc < 0) 4099a0bf528SMauro Carvalho Chehab return rc; 41004585921SMauro Carvalho Chehab switch ((rc >> 4) & 0x07) { 4119a0bf528SMauro Carvalho Chehab case 0: 4129a0bf528SMauro Carvalho Chehab return DQPSK; 4139a0bf528SMauro Carvalho Chehab case 1: 4149a0bf528SMauro Carvalho Chehab return QPSK; 4159a0bf528SMauro Carvalho Chehab case 2: 4169a0bf528SMauro Carvalho Chehab return QAM_16; 4179a0bf528SMauro Carvalho Chehab case 3: 4189a0bf528SMauro Carvalho Chehab return QAM_64; 4199a0bf528SMauro Carvalho Chehab default: 4209a0bf528SMauro Carvalho Chehab return QAM_AUTO; 4219a0bf528SMauro Carvalho Chehab } 4229a0bf528SMauro Carvalho Chehab } 4239a0bf528SMauro Carvalho Chehab 4249a0bf528SMauro Carvalho Chehab static int mb86a20s_get_fec(struct mb86a20s_state *state, 4259a0bf528SMauro Carvalho Chehab unsigned layer) 4269a0bf528SMauro Carvalho Chehab { 4279a0bf528SMauro Carvalho Chehab int rc; 4289a0bf528SMauro Carvalho Chehab 4299a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 4309a0bf528SMauro Carvalho Chehab [0] = 0x87, /* Layer A */ 4319a0bf528SMauro Carvalho Chehab [1] = 0x8b, /* Layer B */ 4329a0bf528SMauro Carvalho Chehab [2] = 0x8f, /* Layer C */ 4339a0bf528SMauro Carvalho Chehab }; 4349a0bf528SMauro Carvalho Chehab 4359a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 4369a0bf528SMauro Carvalho Chehab return -EINVAL; 4379a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 4389a0bf528SMauro Carvalho Chehab if (rc < 0) 4399a0bf528SMauro Carvalho Chehab return rc; 4409a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 4419a0bf528SMauro Carvalho Chehab if (rc < 0) 4429a0bf528SMauro Carvalho Chehab return rc; 44304585921SMauro Carvalho Chehab switch ((rc >> 4) & 0x07) { 4449a0bf528SMauro Carvalho Chehab case 0: 4459a0bf528SMauro Carvalho Chehab return FEC_1_2; 4469a0bf528SMauro Carvalho Chehab case 1: 4479a0bf528SMauro Carvalho Chehab return FEC_2_3; 4489a0bf528SMauro Carvalho Chehab case 2: 4499a0bf528SMauro Carvalho Chehab return FEC_3_4; 4509a0bf528SMauro Carvalho Chehab case 3: 4519a0bf528SMauro Carvalho Chehab return FEC_5_6; 4529a0bf528SMauro Carvalho Chehab case 4: 4539a0bf528SMauro Carvalho Chehab return FEC_7_8; 4549a0bf528SMauro Carvalho Chehab default: 4559a0bf528SMauro Carvalho Chehab return FEC_AUTO; 4569a0bf528SMauro Carvalho Chehab } 4579a0bf528SMauro Carvalho Chehab } 4589a0bf528SMauro Carvalho Chehab 4599a0bf528SMauro Carvalho Chehab static int mb86a20s_get_interleaving(struct mb86a20s_state *state, 4609a0bf528SMauro Carvalho Chehab unsigned layer) 4619a0bf528SMauro Carvalho Chehab { 4629a0bf528SMauro Carvalho Chehab int rc; 4639a0bf528SMauro Carvalho Chehab 4649a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 4659a0bf528SMauro Carvalho Chehab [0] = 0x88, /* Layer A */ 4669a0bf528SMauro Carvalho Chehab [1] = 0x8c, /* Layer B */ 4679a0bf528SMauro Carvalho Chehab [2] = 0x90, /* Layer C */ 4689a0bf528SMauro Carvalho Chehab }; 4699a0bf528SMauro Carvalho Chehab 4709a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 4719a0bf528SMauro Carvalho Chehab return -EINVAL; 4729a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 4739a0bf528SMauro Carvalho Chehab if (rc < 0) 4749a0bf528SMauro Carvalho Chehab return rc; 4759a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 4769a0bf528SMauro Carvalho Chehab if (rc < 0) 4779a0bf528SMauro Carvalho Chehab return rc; 47804585921SMauro Carvalho Chehab 47904585921SMauro Carvalho Chehab switch ((rc >> 4) & 0x07) { 48004585921SMauro Carvalho Chehab case 1: 48104585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_4; 48204585921SMauro Carvalho Chehab case 2: 48304585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_8; 48404585921SMauro Carvalho Chehab case 3: 48504585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_16; 48604585921SMauro Carvalho Chehab case 4: 48704585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_32; 48804585921SMauro Carvalho Chehab 48904585921SMauro Carvalho Chehab default: 49004585921SMauro Carvalho Chehab case 0: 49104585921SMauro Carvalho Chehab return GUARD_INTERVAL_AUTO; 49204585921SMauro Carvalho Chehab } 4939a0bf528SMauro Carvalho Chehab } 4949a0bf528SMauro Carvalho Chehab 4959a0bf528SMauro Carvalho Chehab static int mb86a20s_get_segment_count(struct mb86a20s_state *state, 4969a0bf528SMauro Carvalho Chehab unsigned layer) 4979a0bf528SMauro Carvalho Chehab { 4989a0bf528SMauro Carvalho Chehab int rc, count; 4999a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 5009a0bf528SMauro Carvalho Chehab [0] = 0x89, /* Layer A */ 5019a0bf528SMauro Carvalho Chehab [1] = 0x8d, /* Layer B */ 5029a0bf528SMauro Carvalho Chehab [2] = 0x91, /* Layer C */ 5039a0bf528SMauro Carvalho Chehab }; 5049a0bf528SMauro Carvalho Chehab 505f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 506f66d81b5SMauro Carvalho Chehab 5079a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 5089a0bf528SMauro Carvalho Chehab return -EINVAL; 509f66d81b5SMauro Carvalho Chehab 5109a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 5119a0bf528SMauro Carvalho Chehab if (rc < 0) 5129a0bf528SMauro Carvalho Chehab return rc; 5139a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 5149a0bf528SMauro Carvalho Chehab if (rc < 0) 5159a0bf528SMauro Carvalho Chehab return rc; 5169a0bf528SMauro Carvalho Chehab count = (rc >> 4) & 0x0f; 5179a0bf528SMauro Carvalho Chehab 518f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); 519f66d81b5SMauro Carvalho Chehab 5209a0bf528SMauro Carvalho Chehab return count; 5219a0bf528SMauro Carvalho Chehab } 5229a0bf528SMauro Carvalho Chehab 523a77cfcacSMauro Carvalho Chehab static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) 524a77cfcacSMauro Carvalho Chehab { 525f66d81b5SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 526a77cfcacSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 527a77cfcacSMauro Carvalho Chehab 528f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 529f66d81b5SMauro Carvalho Chehab 530a77cfcacSMauro Carvalho Chehab /* Fixed parameters */ 531a77cfcacSMauro Carvalho Chehab c->delivery_system = SYS_ISDBT; 532a77cfcacSMauro Carvalho Chehab c->bandwidth_hz = 6000000; 533a77cfcacSMauro Carvalho Chehab 534a77cfcacSMauro Carvalho Chehab /* Initialize values that will be later autodetected */ 535a77cfcacSMauro Carvalho Chehab c->isdbt_layer_enabled = 0; 536a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_AUTO; 537a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_AUTO; 538a77cfcacSMauro Carvalho Chehab c->isdbt_sb_mode = 0; 539a77cfcacSMauro Carvalho Chehab c->isdbt_sb_segment_count = 0; 540a77cfcacSMauro Carvalho Chehab } 541a77cfcacSMauro Carvalho Chehab 542d01a8ee3SMauro Carvalho Chehab /* 543d01a8ee3SMauro Carvalho Chehab * Estimates the bit rate using the per-segment bit rate given by 544d01a8ee3SMauro Carvalho Chehab * ABNT/NBR 15601 spec (table 4). 545d01a8ee3SMauro Carvalho Chehab */ 546d01a8ee3SMauro Carvalho Chehab static u32 isdbt_rate[3][5][4] = { 547d01a8ee3SMauro Carvalho Chehab { /* DQPSK/QPSK */ 548d01a8ee3SMauro Carvalho Chehab { 280850, 312060, 330420, 340430 }, /* 1/2 */ 549d01a8ee3SMauro Carvalho Chehab { 374470, 416080, 440560, 453910 }, /* 2/3 */ 550d01a8ee3SMauro Carvalho Chehab { 421280, 468090, 495630, 510650 }, /* 3/4 */ 551d01a8ee3SMauro Carvalho Chehab { 468090, 520100, 550700, 567390 }, /* 5/6 */ 552d01a8ee3SMauro Carvalho Chehab { 491500, 546110, 578230, 595760 }, /* 7/8 */ 553d01a8ee3SMauro Carvalho Chehab }, { /* QAM16 */ 554d01a8ee3SMauro Carvalho Chehab { 561710, 624130, 660840, 680870 }, /* 1/2 */ 555d01a8ee3SMauro Carvalho Chehab { 748950, 832170, 881120, 907820 }, /* 2/3 */ 556d01a8ee3SMauro Carvalho Chehab { 842570, 936190, 991260, 1021300 }, /* 3/4 */ 557d01a8ee3SMauro Carvalho Chehab { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ 558d01a8ee3SMauro Carvalho Chehab { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ 559d01a8ee3SMauro Carvalho Chehab }, { /* QAM64 */ 560d01a8ee3SMauro Carvalho Chehab { 842570, 936190, 991260, 1021300 }, /* 1/2 */ 561d01a8ee3SMauro Carvalho Chehab { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ 562d01a8ee3SMauro Carvalho Chehab { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ 563d01a8ee3SMauro Carvalho Chehab { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ 564d01a8ee3SMauro Carvalho Chehab { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ 565d01a8ee3SMauro Carvalho Chehab } 566d01a8ee3SMauro Carvalho Chehab }; 567d01a8ee3SMauro Carvalho Chehab 568d01a8ee3SMauro Carvalho Chehab static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, 569d01a8ee3SMauro Carvalho Chehab u32 modulation, u32 fec, u32 interleaving, 570d01a8ee3SMauro Carvalho Chehab u32 segment) 571d01a8ee3SMauro Carvalho Chehab { 572d01a8ee3SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 573d01a8ee3SMauro Carvalho Chehab u32 rate; 574d01a8ee3SMauro Carvalho Chehab int m, f, i; 575d01a8ee3SMauro Carvalho Chehab 576d01a8ee3SMauro Carvalho Chehab /* 577d01a8ee3SMauro Carvalho Chehab * If modulation/fec/interleaving is not detected, the default is 578d01a8ee3SMauro Carvalho Chehab * to consider the lowest bit rate, to avoid taking too long time 579d01a8ee3SMauro Carvalho Chehab * to get BER. 580d01a8ee3SMauro Carvalho Chehab */ 581d01a8ee3SMauro Carvalho Chehab switch (modulation) { 582d01a8ee3SMauro Carvalho Chehab case DQPSK: 583d01a8ee3SMauro Carvalho Chehab case QPSK: 584d01a8ee3SMauro Carvalho Chehab default: 585d01a8ee3SMauro Carvalho Chehab m = 0; 586d01a8ee3SMauro Carvalho Chehab break; 587d01a8ee3SMauro Carvalho Chehab case QAM_16: 588d01a8ee3SMauro Carvalho Chehab m = 1; 589d01a8ee3SMauro Carvalho Chehab break; 590d01a8ee3SMauro Carvalho Chehab case QAM_64: 591d01a8ee3SMauro Carvalho Chehab m = 2; 592d01a8ee3SMauro Carvalho Chehab break; 593d01a8ee3SMauro Carvalho Chehab } 594d01a8ee3SMauro Carvalho Chehab 595d01a8ee3SMauro Carvalho Chehab switch (fec) { 596d01a8ee3SMauro Carvalho Chehab default: 597d01a8ee3SMauro Carvalho Chehab case FEC_1_2: 598d01a8ee3SMauro Carvalho Chehab case FEC_AUTO: 599d01a8ee3SMauro Carvalho Chehab f = 0; 600d01a8ee3SMauro Carvalho Chehab break; 601d01a8ee3SMauro Carvalho Chehab case FEC_2_3: 602d01a8ee3SMauro Carvalho Chehab f = 1; 603d01a8ee3SMauro Carvalho Chehab break; 604d01a8ee3SMauro Carvalho Chehab case FEC_3_4: 605d01a8ee3SMauro Carvalho Chehab f = 2; 606d01a8ee3SMauro Carvalho Chehab break; 607d01a8ee3SMauro Carvalho Chehab case FEC_5_6: 608d01a8ee3SMauro Carvalho Chehab f = 3; 609d01a8ee3SMauro Carvalho Chehab break; 610d01a8ee3SMauro Carvalho Chehab case FEC_7_8: 611d01a8ee3SMauro Carvalho Chehab f = 4; 612d01a8ee3SMauro Carvalho Chehab break; 613d01a8ee3SMauro Carvalho Chehab } 614d01a8ee3SMauro Carvalho Chehab 615d01a8ee3SMauro Carvalho Chehab switch (interleaving) { 616d01a8ee3SMauro Carvalho Chehab default: 617d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_4: 618d01a8ee3SMauro Carvalho Chehab i = 0; 619d01a8ee3SMauro Carvalho Chehab break; 620d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_8: 621d01a8ee3SMauro Carvalho Chehab i = 1; 622d01a8ee3SMauro Carvalho Chehab break; 623d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_16: 624d01a8ee3SMauro Carvalho Chehab i = 2; 625d01a8ee3SMauro Carvalho Chehab break; 626d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_32: 627d01a8ee3SMauro Carvalho Chehab i = 3; 628d01a8ee3SMauro Carvalho Chehab break; 629d01a8ee3SMauro Carvalho Chehab } 630d01a8ee3SMauro Carvalho Chehab 631d01a8ee3SMauro Carvalho Chehab /* Samples BER at BER_SAMPLING_RATE seconds */ 632d01a8ee3SMauro Carvalho Chehab rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE; 633d01a8ee3SMauro Carvalho Chehab 634d01a8ee3SMauro Carvalho Chehab /* Avoids sampling too quickly or to overflow the register */ 635d01a8ee3SMauro Carvalho Chehab if (rate < 256) 636d01a8ee3SMauro Carvalho Chehab rate = 256; 637d01a8ee3SMauro Carvalho Chehab else if (rate > (1 << 24) - 1) 638d01a8ee3SMauro Carvalho Chehab rate = (1 << 24) - 1; 639d01a8ee3SMauro Carvalho Chehab 640d01a8ee3SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 641d01a8ee3SMauro Carvalho Chehab "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", 642d01a8ee3SMauro Carvalho Chehab __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000, 643d01a8ee3SMauro Carvalho Chehab rate, rate); 644d01a8ee3SMauro Carvalho Chehab 645d01a8ee3SMauro Carvalho Chehab state->estimated_rate[i] = rate; 646d01a8ee3SMauro Carvalho Chehab } 647d01a8ee3SMauro Carvalho Chehab 648d01a8ee3SMauro Carvalho Chehab 6499a0bf528SMauro Carvalho Chehab static int mb86a20s_get_frontend(struct dvb_frontend *fe) 6509a0bf528SMauro Carvalho Chehab { 6519a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 652a77cfcacSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6539a0bf528SMauro Carvalho Chehab int i, rc; 6549a0bf528SMauro Carvalho Chehab 655f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 656f66d81b5SMauro Carvalho Chehab 657a77cfcacSMauro Carvalho Chehab /* Reset frontend cache to default values */ 658a77cfcacSMauro Carvalho Chehab mb86a20s_reset_frontend_cache(fe); 6599a0bf528SMauro Carvalho Chehab 6609a0bf528SMauro Carvalho Chehab /* Check for partial reception */ 6619a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, 0x85); 662a77cfcacSMauro Carvalho Chehab if (rc < 0) 663a77cfcacSMauro Carvalho Chehab return rc; 6649a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 665a77cfcacSMauro Carvalho Chehab if (rc < 0) 666a77cfcacSMauro Carvalho Chehab return rc; 667a77cfcacSMauro Carvalho Chehab c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; 6689a0bf528SMauro Carvalho Chehab 6699a0bf528SMauro Carvalho Chehab /* Get per-layer data */ 670a77cfcacSMauro Carvalho Chehab 6714f62a20dSMauro Carvalho Chehab for (i = 0; i < NUM_LAYERS; i++) { 672f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", 673f66d81b5SMauro Carvalho Chehab __func__, 'A' + i); 674f66d81b5SMauro Carvalho Chehab 6759a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_segment_count(state, i); 676a77cfcacSMauro Carvalho Chehab if (rc < 0) 677f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 678d01a8ee3SMauro Carvalho Chehab if (rc >= 0 && rc < 14) { 679a77cfcacSMauro Carvalho Chehab c->layer[i].segment_count = rc; 680d01a8ee3SMauro Carvalho Chehab } else { 681a77cfcacSMauro Carvalho Chehab c->layer[i].segment_count = 0; 682d01a8ee3SMauro Carvalho Chehab state->estimated_rate[i] = 0; 6839a0bf528SMauro Carvalho Chehab continue; 684a77cfcacSMauro Carvalho Chehab } 685a77cfcacSMauro Carvalho Chehab c->isdbt_layer_enabled |= 1 << i; 6869a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_modulation(state, i); 687a77cfcacSMauro Carvalho Chehab if (rc < 0) 688f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 689f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", 690f66d81b5SMauro Carvalho Chehab __func__, rc); 691a77cfcacSMauro Carvalho Chehab c->layer[i].modulation = rc; 6929a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_fec(state, i); 693a77cfcacSMauro Carvalho Chehab if (rc < 0) 694f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 695f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", 696f66d81b5SMauro Carvalho Chehab __func__, rc); 697a77cfcacSMauro Carvalho Chehab c->layer[i].fec = rc; 6989a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_interleaving(state, i); 699a77cfcacSMauro Carvalho Chehab if (rc < 0) 700f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 701f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", 702f66d81b5SMauro Carvalho Chehab __func__, rc); 703a77cfcacSMauro Carvalho Chehab c->layer[i].interleaving = rc; 704d01a8ee3SMauro Carvalho Chehab mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation, 705d01a8ee3SMauro Carvalho Chehab c->layer[i].fec, 706d01a8ee3SMauro Carvalho Chehab c->layer[i].interleaving, 707d01a8ee3SMauro Carvalho Chehab c->layer[i].segment_count); 7089a0bf528SMauro Carvalho Chehab } 7099a0bf528SMauro Carvalho Chehab 7109a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, 0x84); 711a77cfcacSMauro Carvalho Chehab if (rc < 0) 712a77cfcacSMauro Carvalho Chehab return rc; 713a77cfcacSMauro Carvalho Chehab if ((rc & 0x60) == 0x20) { 714a77cfcacSMauro Carvalho Chehab c->isdbt_sb_mode = 1; 7159a0bf528SMauro Carvalho Chehab /* At least, one segment should exist */ 716a77cfcacSMauro Carvalho Chehab if (!c->isdbt_sb_segment_count) 717a77cfcacSMauro Carvalho Chehab c->isdbt_sb_segment_count = 1; 718a77cfcacSMauro Carvalho Chehab } 7199a0bf528SMauro Carvalho Chehab 7209a0bf528SMauro Carvalho Chehab /* Get transmission mode and guard interval */ 7219a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x07); 722a77cfcacSMauro Carvalho Chehab if (rc < 0) 723a77cfcacSMauro Carvalho Chehab return rc; 7249a0bf528SMauro Carvalho Chehab if ((rc & 0x60) == 0x20) { 7259a0bf528SMauro Carvalho Chehab switch (rc & 0x0c >> 2) { 7269a0bf528SMauro Carvalho Chehab case 0: 727a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_2K; 7289a0bf528SMauro Carvalho Chehab break; 7299a0bf528SMauro Carvalho Chehab case 1: 730a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_4K; 7319a0bf528SMauro Carvalho Chehab break; 7329a0bf528SMauro Carvalho Chehab case 2: 733a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_8K; 7349a0bf528SMauro Carvalho Chehab break; 7359a0bf528SMauro Carvalho Chehab } 7369a0bf528SMauro Carvalho Chehab } 7379a0bf528SMauro Carvalho Chehab if (!(rc & 0x10)) { 7389a0bf528SMauro Carvalho Chehab switch (rc & 0x3) { 7399a0bf528SMauro Carvalho Chehab case 0: 740a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_4; 7419a0bf528SMauro Carvalho Chehab break; 7429a0bf528SMauro Carvalho Chehab case 1: 743a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_8; 7449a0bf528SMauro Carvalho Chehab break; 7459a0bf528SMauro Carvalho Chehab case 2: 746a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_16; 7479a0bf528SMauro Carvalho Chehab break; 7489a0bf528SMauro Carvalho Chehab } 7499a0bf528SMauro Carvalho Chehab } 75009b6d21eSMauro Carvalho Chehab return 0; 7519a0bf528SMauro Carvalho Chehab 752f66d81b5SMauro Carvalho Chehab noperlayer_error: 75309b6d21eSMauro Carvalho Chehab 75409b6d21eSMauro Carvalho Chehab /* per-layer info is incomplete; discard all per-layer */ 75509b6d21eSMauro Carvalho Chehab c->isdbt_layer_enabled = 0; 7569a0bf528SMauro Carvalho Chehab 757a77cfcacSMauro Carvalho Chehab return rc; 7589a0bf528SMauro Carvalho Chehab } 7599a0bf528SMauro Carvalho Chehab 76009b6d21eSMauro Carvalho Chehab static int mb86a20s_reset_counters(struct dvb_frontend *fe) 76109b6d21eSMauro Carvalho Chehab { 76209b6d21eSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 76309b6d21eSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 76409b6d21eSMauro Carvalho Chehab int rc, val; 76509b6d21eSMauro Carvalho Chehab 76609b6d21eSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 76709b6d21eSMauro Carvalho Chehab 76809b6d21eSMauro Carvalho Chehab /* Reset the counters, if the channel changed */ 76909b6d21eSMauro Carvalho Chehab if (state->last_frequency != c->frequency) { 77009b6d21eSMauro Carvalho Chehab memset(&c->cnr, 0, sizeof(c->cnr)); 77109b6d21eSMauro Carvalho Chehab memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); 77209b6d21eSMauro Carvalho Chehab memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); 773d9b6f08aSMauro Carvalho Chehab memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 774d9b6f08aSMauro Carvalho Chehab memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 77509b6d21eSMauro Carvalho Chehab memset(&c->block_error, 0, sizeof(c->block_error)); 77609b6d21eSMauro Carvalho Chehab memset(&c->block_count, 0, sizeof(c->block_count)); 77709b6d21eSMauro Carvalho Chehab 77809b6d21eSMauro Carvalho Chehab state->last_frequency = c->frequency; 77909b6d21eSMauro Carvalho Chehab } 78009b6d21eSMauro Carvalho Chehab 78109b6d21eSMauro Carvalho Chehab /* Clear status for most stats */ 78209b6d21eSMauro Carvalho Chehab 783d9b6f08aSMauro Carvalho Chehab /* BER/PER counter reset */ 784d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); 78509b6d21eSMauro Carvalho Chehab if (rc < 0) 78609b6d21eSMauro Carvalho Chehab goto err; 78709b6d21eSMauro Carvalho Chehab 78809b6d21eSMauro Carvalho Chehab /* CNR counter reset */ 78909b6d21eSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x45); 79009b6d21eSMauro Carvalho Chehab if (rc < 0) 79109b6d21eSMauro Carvalho Chehab goto err; 79209b6d21eSMauro Carvalho Chehab val = rc; 79309b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val | 0x10); 79409b6d21eSMauro Carvalho Chehab if (rc < 0) 79509b6d21eSMauro Carvalho Chehab goto err; 79609b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 79709b6d21eSMauro Carvalho Chehab if (rc < 0) 79809b6d21eSMauro Carvalho Chehab goto err; 79909b6d21eSMauro Carvalho Chehab 80009b6d21eSMauro Carvalho Chehab /* MER counter reset */ 80109b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x50); 80209b6d21eSMauro Carvalho Chehab if (rc < 0) 80309b6d21eSMauro Carvalho Chehab goto err; 80409b6d21eSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 80509b6d21eSMauro Carvalho Chehab if (rc < 0) 80609b6d21eSMauro Carvalho Chehab goto err; 80709b6d21eSMauro Carvalho Chehab val = rc; 80809b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val | 0x01); 80909b6d21eSMauro Carvalho Chehab if (rc < 0) 81009b6d21eSMauro Carvalho Chehab goto err; 81109b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val & 0x06); 81209b6d21eSMauro Carvalho Chehab if (rc < 0) 81309b6d21eSMauro Carvalho Chehab goto err; 81409b6d21eSMauro Carvalho Chehab 815149d518aSMauro Carvalho Chehab goto ok; 81609b6d21eSMauro Carvalho Chehab err: 817149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 818149d518aSMauro Carvalho Chehab "%s: Can't reset FE statistics (error %d).\n", 819149d518aSMauro Carvalho Chehab __func__, rc); 820149d518aSMauro Carvalho Chehab ok: 82109b6d21eSMauro Carvalho Chehab return rc; 82209b6d21eSMauro Carvalho Chehab } 82309b6d21eSMauro Carvalho Chehab 824ad0abbf1SMauro Carvalho Chehab static int mb86a20s_get_pre_ber(struct dvb_frontend *fe, 825149d518aSMauro Carvalho Chehab unsigned layer, 826149d518aSMauro Carvalho Chehab u32 *error, u32 *count) 827149d518aSMauro Carvalho Chehab { 828149d518aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 829ad0abbf1SMauro Carvalho Chehab int rc, val; 830149d518aSMauro Carvalho Chehab 831149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 832149d518aSMauro Carvalho Chehab 8334f62a20dSMauro Carvalho Chehab if (layer >= NUM_LAYERS) 834149d518aSMauro Carvalho Chehab return -EINVAL; 835149d518aSMauro Carvalho Chehab 836149d518aSMauro Carvalho Chehab /* Check if the BER measures are already available */ 837149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x54); 838149d518aSMauro Carvalho Chehab if (rc < 0) 839149d518aSMauro Carvalho Chehab return rc; 840149d518aSMauro Carvalho Chehab 841149d518aSMauro Carvalho Chehab /* Check if data is available for that layer */ 842149d518aSMauro Carvalho Chehab if (!(rc & (1 << layer))) { 843149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 844ad0abbf1SMauro Carvalho Chehab "%s: preBER for layer %c is not available yet.\n", 845149d518aSMauro Carvalho Chehab __func__, 'A' + layer); 846149d518aSMauro Carvalho Chehab return -EBUSY; 847149d518aSMauro Carvalho Chehab } 848149d518aSMauro Carvalho Chehab 849149d518aSMauro Carvalho Chehab /* Read Bit Error Count */ 850149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x55 + layer * 3); 851149d518aSMauro Carvalho Chehab if (rc < 0) 852149d518aSMauro Carvalho Chehab return rc; 853149d518aSMauro Carvalho Chehab *error = rc << 16; 854149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x56 + layer * 3); 855149d518aSMauro Carvalho Chehab if (rc < 0) 856149d518aSMauro Carvalho Chehab return rc; 857149d518aSMauro Carvalho Chehab *error |= rc << 8; 858149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x57 + layer * 3); 859149d518aSMauro Carvalho Chehab if (rc < 0) 860149d518aSMauro Carvalho Chehab return rc; 861149d518aSMauro Carvalho Chehab *error |= rc; 862149d518aSMauro Carvalho Chehab 863149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 864149d518aSMauro Carvalho Chehab "%s: bit error before Viterbi for layer %c: %d.\n", 865149d518aSMauro Carvalho Chehab __func__, 'A' + layer, *error); 866149d518aSMauro Carvalho Chehab 867149d518aSMauro Carvalho Chehab /* Read Bit Count */ 868149d518aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 869149d518aSMauro Carvalho Chehab if (rc < 0) 870149d518aSMauro Carvalho Chehab return rc; 871149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 872149d518aSMauro Carvalho Chehab if (rc < 0) 873149d518aSMauro Carvalho Chehab return rc; 874149d518aSMauro Carvalho Chehab *count = rc << 16; 875149d518aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 876149d518aSMauro Carvalho Chehab if (rc < 0) 877149d518aSMauro Carvalho Chehab return rc; 878149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 879149d518aSMauro Carvalho Chehab if (rc < 0) 880149d518aSMauro Carvalho Chehab return rc; 881149d518aSMauro Carvalho Chehab *count |= rc << 8; 882149d518aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 883149d518aSMauro Carvalho Chehab if (rc < 0) 884149d518aSMauro Carvalho Chehab return rc; 885149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 886149d518aSMauro Carvalho Chehab if (rc < 0) 887149d518aSMauro Carvalho Chehab return rc; 888149d518aSMauro Carvalho Chehab *count |= rc; 889149d518aSMauro Carvalho Chehab 890149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 891149d518aSMauro Carvalho Chehab "%s: bit count before Viterbi for layer %c: %d.\n", 892149d518aSMauro Carvalho Chehab __func__, 'A' + layer, *count); 893149d518aSMauro Carvalho Chehab 894149d518aSMauro Carvalho Chehab 895d01a8ee3SMauro Carvalho Chehab /* 896d01a8ee3SMauro Carvalho Chehab * As we get TMCC data from the frontend, we can better estimate the 897d01a8ee3SMauro Carvalho Chehab * BER bit counters, in order to do the BER measure during a longer 898d01a8ee3SMauro Carvalho Chehab * time. Use those data, if available, to update the bit count 899d01a8ee3SMauro Carvalho Chehab * measure. 900d01a8ee3SMauro Carvalho Chehab */ 901d01a8ee3SMauro Carvalho Chehab 902d01a8ee3SMauro Carvalho Chehab if (state->estimated_rate[layer] 903d01a8ee3SMauro Carvalho Chehab && state->estimated_rate[layer] != *count) { 904d01a8ee3SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 905ad0abbf1SMauro Carvalho Chehab "%s: updating layer %c preBER counter to %d.\n", 906d01a8ee3SMauro Carvalho Chehab __func__, 'A' + layer, state->estimated_rate[layer]); 907ad0abbf1SMauro Carvalho Chehab 908ad0abbf1SMauro Carvalho Chehab /* Turn off BER before Viterbi */ 909ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x52, 0x00); 910ad0abbf1SMauro Carvalho Chehab 911ad0abbf1SMauro Carvalho Chehab /* Update counter for this layer */ 912d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 913d01a8ee3SMauro Carvalho Chehab if (rc < 0) 914d01a8ee3SMauro Carvalho Chehab return rc; 915d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 916d01a8ee3SMauro Carvalho Chehab state->estimated_rate[layer] >> 16); 917d01a8ee3SMauro Carvalho Chehab if (rc < 0) 918d01a8ee3SMauro Carvalho Chehab return rc; 919d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 920d01a8ee3SMauro Carvalho Chehab if (rc < 0) 921d01a8ee3SMauro Carvalho Chehab return rc; 922d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 923d01a8ee3SMauro Carvalho Chehab state->estimated_rate[layer] >> 8); 924d01a8ee3SMauro Carvalho Chehab if (rc < 0) 925d01a8ee3SMauro Carvalho Chehab return rc; 926d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 927d01a8ee3SMauro Carvalho Chehab if (rc < 0) 928d01a8ee3SMauro Carvalho Chehab return rc; 929d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 930d01a8ee3SMauro Carvalho Chehab state->estimated_rate[layer]); 931d01a8ee3SMauro Carvalho Chehab if (rc < 0) 932d01a8ee3SMauro Carvalho Chehab return rc; 933ad0abbf1SMauro Carvalho Chehab 934ad0abbf1SMauro Carvalho Chehab /* Turn on BER before Viterbi */ 935ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x52, 0x01); 936ad0abbf1SMauro Carvalho Chehab 937ad0abbf1SMauro Carvalho Chehab /* Reset all preBER counters */ 938ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, 0x00); 939ad0abbf1SMauro Carvalho Chehab if (rc < 0) 940ad0abbf1SMauro Carvalho Chehab return rc; 941ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, 0x07); 942ad0abbf1SMauro Carvalho Chehab } else { 943ad0abbf1SMauro Carvalho Chehab /* Reset counter to collect new data */ 944ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x53); 945ad0abbf1SMauro Carvalho Chehab if (rc < 0) 946ad0abbf1SMauro Carvalho Chehab return rc; 947ad0abbf1SMauro Carvalho Chehab val = rc; 948ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); 949ad0abbf1SMauro Carvalho Chehab if (rc < 0) 950ad0abbf1SMauro Carvalho Chehab return rc; 951ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); 952d01a8ee3SMauro Carvalho Chehab } 953d01a8ee3SMauro Carvalho Chehab 954d9b6f08aSMauro Carvalho Chehab return rc; 955d9b6f08aSMauro Carvalho Chehab } 956d01a8ee3SMauro Carvalho Chehab 957d9b6f08aSMauro Carvalho Chehab static int mb86a20s_get_post_ber(struct dvb_frontend *fe, 958d9b6f08aSMauro Carvalho Chehab unsigned layer, 959d9b6f08aSMauro Carvalho Chehab u32 *error, u32 *count) 960d9b6f08aSMauro Carvalho Chehab { 961d9b6f08aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 962d9b6f08aSMauro Carvalho Chehab u32 counter, collect_rate; 963d9b6f08aSMauro Carvalho Chehab int rc, val; 964d9b6f08aSMauro Carvalho Chehab 965d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 966d9b6f08aSMauro Carvalho Chehab 9674f62a20dSMauro Carvalho Chehab if (layer >= NUM_LAYERS) 968d9b6f08aSMauro Carvalho Chehab return -EINVAL; 969d9b6f08aSMauro Carvalho Chehab 970d9b6f08aSMauro Carvalho Chehab /* Check if the BER measures are already available */ 971d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x60); 972d9b6f08aSMauro Carvalho Chehab if (rc < 0) 973d9b6f08aSMauro Carvalho Chehab return rc; 974d9b6f08aSMauro Carvalho Chehab 975d9b6f08aSMauro Carvalho Chehab /* Check if data is available for that layer */ 976d9b6f08aSMauro Carvalho Chehab if (!(rc & (1 << layer))) { 977d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 978d9b6f08aSMauro Carvalho Chehab "%s: post BER for layer %c is not available yet.\n", 979d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer); 980d9b6f08aSMauro Carvalho Chehab return -EBUSY; 981d9b6f08aSMauro Carvalho Chehab } 982d9b6f08aSMauro Carvalho Chehab 983d9b6f08aSMauro Carvalho Chehab /* Read Bit Error Count */ 984d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x64 + layer * 3); 985d9b6f08aSMauro Carvalho Chehab if (rc < 0) 986d9b6f08aSMauro Carvalho Chehab return rc; 987d9b6f08aSMauro Carvalho Chehab *error = rc << 16; 988d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x65 + layer * 3); 989d9b6f08aSMauro Carvalho Chehab if (rc < 0) 990d9b6f08aSMauro Carvalho Chehab return rc; 991d9b6f08aSMauro Carvalho Chehab *error |= rc << 8; 992d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x66 + layer * 3); 993d9b6f08aSMauro Carvalho Chehab if (rc < 0) 994d9b6f08aSMauro Carvalho Chehab return rc; 995d9b6f08aSMauro Carvalho Chehab *error |= rc; 996d9b6f08aSMauro Carvalho Chehab 997d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 998d9b6f08aSMauro Carvalho Chehab "%s: post bit error for layer %c: %d.\n", 999d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer, *error); 1000d9b6f08aSMauro Carvalho Chehab 1001d9b6f08aSMauro Carvalho Chehab /* Read Bit Count */ 1002d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1003d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1004d9b6f08aSMauro Carvalho Chehab return rc; 1005d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1006d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1007d9b6f08aSMauro Carvalho Chehab return rc; 1008d9b6f08aSMauro Carvalho Chehab counter = rc << 8; 1009d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1010d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1011d9b6f08aSMauro Carvalho Chehab return rc; 1012d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1013d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1014d9b6f08aSMauro Carvalho Chehab return rc; 1015d9b6f08aSMauro Carvalho Chehab counter |= rc; 1016d9b6f08aSMauro Carvalho Chehab *count = counter * 204 * 8; 1017d9b6f08aSMauro Carvalho Chehab 1018d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1019d9b6f08aSMauro Carvalho Chehab "%s: post bit count for layer %c: %d.\n", 1020d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer, *count); 1021d9b6f08aSMauro Carvalho Chehab 1022d9b6f08aSMauro Carvalho Chehab /* 1023d9b6f08aSMauro Carvalho Chehab * As we get TMCC data from the frontend, we can better estimate the 1024d9b6f08aSMauro Carvalho Chehab * BER bit counters, in order to do the BER measure during a longer 1025d9b6f08aSMauro Carvalho Chehab * time. Use those data, if available, to update the bit count 1026d9b6f08aSMauro Carvalho Chehab * measure. 1027d9b6f08aSMauro Carvalho Chehab */ 1028d9b6f08aSMauro Carvalho Chehab 1029d9b6f08aSMauro Carvalho Chehab if (!state->estimated_rate[layer]) 1030d9b6f08aSMauro Carvalho Chehab goto reset_measurement; 1031d9b6f08aSMauro Carvalho Chehab 1032d9b6f08aSMauro Carvalho Chehab collect_rate = state->estimated_rate[layer] / 204 / 8; 1033d9b6f08aSMauro Carvalho Chehab if (collect_rate < 32) 1034d9b6f08aSMauro Carvalho Chehab collect_rate = 32; 1035d9b6f08aSMauro Carvalho Chehab if (collect_rate > 65535) 1036d9b6f08aSMauro Carvalho Chehab collect_rate = 65535; 1037d9b6f08aSMauro Carvalho Chehab if (collect_rate != counter) { 1038d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1039d9b6f08aSMauro Carvalho Chehab "%s: updating postBER counter on layer %c to %d.\n", 1040d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer, collect_rate); 1041d9b6f08aSMauro Carvalho Chehab 1042d9b6f08aSMauro Carvalho Chehab /* Turn off BER after Viterbi */ 1043d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5e, 0x00); 1044d9b6f08aSMauro Carvalho Chehab 1045d9b6f08aSMauro Carvalho Chehab /* Update counter for this layer */ 1046d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1047d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1048d9b6f08aSMauro Carvalho Chehab return rc; 1049d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1050d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1051d9b6f08aSMauro Carvalho Chehab return rc; 1052d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1053d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1054d9b6f08aSMauro Carvalho Chehab return rc; 1055d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1056d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1057d9b6f08aSMauro Carvalho Chehab return rc; 1058d9b6f08aSMauro Carvalho Chehab 1059d9b6f08aSMauro Carvalho Chehab /* Turn on BER after Viterbi */ 1060d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5e, 0x07); 1061d9b6f08aSMauro Carvalho Chehab 1062d9b6f08aSMauro Carvalho Chehab /* Reset all preBER counters */ 1063d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, 0x00); 1064d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1065d9b6f08aSMauro Carvalho Chehab return rc; 1066d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, 0x07); 1067d9b6f08aSMauro Carvalho Chehab 1068d9b6f08aSMauro Carvalho Chehab return rc; 1069d9b6f08aSMauro Carvalho Chehab } 1070d9b6f08aSMauro Carvalho Chehab 1071d9b6f08aSMauro Carvalho Chehab reset_measurement: 1072149d518aSMauro Carvalho Chehab /* Reset counter to collect new data */ 1073ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x5f); 1074149d518aSMauro Carvalho Chehab if (rc < 0) 1075149d518aSMauro Carvalho Chehab return rc; 1076ad0abbf1SMauro Carvalho Chehab val = rc; 1077ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); 1078ad0abbf1SMauro Carvalho Chehab if (rc < 0) 1079ad0abbf1SMauro Carvalho Chehab return rc; 1080d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); 1081149d518aSMauro Carvalho Chehab 1082ad0abbf1SMauro Carvalho Chehab return rc; 1083149d518aSMauro Carvalho Chehab } 1084149d518aSMauro Carvalho Chehab 1085593ae89aSMauro Carvalho Chehab static int mb86a20s_get_blk_error(struct dvb_frontend *fe, 1086593ae89aSMauro Carvalho Chehab unsigned layer, 1087593ae89aSMauro Carvalho Chehab u32 *error, u32 *count) 1088593ae89aSMauro Carvalho Chehab { 1089593ae89aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1090313cf4efSMauro Carvalho Chehab int rc, val; 1091593ae89aSMauro Carvalho Chehab u32 collect_rate; 1092593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1093593ae89aSMauro Carvalho Chehab 10944f62a20dSMauro Carvalho Chehab if (layer >= NUM_LAYERS) 1095593ae89aSMauro Carvalho Chehab return -EINVAL; 1096593ae89aSMauro Carvalho Chehab 1097593ae89aSMauro Carvalho Chehab /* Check if the PER measures are already available */ 1098593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb8); 1099593ae89aSMauro Carvalho Chehab if (rc < 0) 1100593ae89aSMauro Carvalho Chehab return rc; 1101593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1102593ae89aSMauro Carvalho Chehab if (rc < 0) 1103593ae89aSMauro Carvalho Chehab return rc; 1104593ae89aSMauro Carvalho Chehab 1105593ae89aSMauro Carvalho Chehab /* Check if data is available for that layer */ 1106593ae89aSMauro Carvalho Chehab 1107593ae89aSMauro Carvalho Chehab if (!(rc & (1 << layer))) { 1108593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1109593ae89aSMauro Carvalho Chehab "%s: block counts for layer %c aren't available yet.\n", 1110593ae89aSMauro Carvalho Chehab __func__, 'A' + layer); 1111593ae89aSMauro Carvalho Chehab return -EBUSY; 1112593ae89aSMauro Carvalho Chehab } 1113593ae89aSMauro Carvalho Chehab 1114593ae89aSMauro Carvalho Chehab /* Read Packet error Count */ 1115593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); 1116593ae89aSMauro Carvalho Chehab if (rc < 0) 1117593ae89aSMauro Carvalho Chehab return rc; 1118593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1119593ae89aSMauro Carvalho Chehab if (rc < 0) 1120593ae89aSMauro Carvalho Chehab return rc; 1121593ae89aSMauro Carvalho Chehab *error = rc << 8; 1122593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); 1123593ae89aSMauro Carvalho Chehab if (rc < 0) 1124593ae89aSMauro Carvalho Chehab return rc; 1125593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1126593ae89aSMauro Carvalho Chehab if (rc < 0) 1127593ae89aSMauro Carvalho Chehab return rc; 1128593ae89aSMauro Carvalho Chehab *error |= rc; 1129d56e326fSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n", 1130593ae89aSMauro Carvalho Chehab __func__, 'A' + layer, *error); 1131593ae89aSMauro Carvalho Chehab 1132593ae89aSMauro Carvalho Chehab /* Read Bit Count */ 1133593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1134593ae89aSMauro Carvalho Chehab if (rc < 0) 1135593ae89aSMauro Carvalho Chehab return rc; 1136593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1137593ae89aSMauro Carvalho Chehab if (rc < 0) 1138593ae89aSMauro Carvalho Chehab return rc; 1139593ae89aSMauro Carvalho Chehab *count = rc << 8; 1140593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1141593ae89aSMauro Carvalho Chehab if (rc < 0) 1142593ae89aSMauro Carvalho Chehab return rc; 1143593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1144593ae89aSMauro Carvalho Chehab if (rc < 0) 1145593ae89aSMauro Carvalho Chehab return rc; 1146593ae89aSMauro Carvalho Chehab *count |= rc; 1147593ae89aSMauro Carvalho Chehab 1148593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1149593ae89aSMauro Carvalho Chehab "%s: block count for layer %c: %d.\n", 1150593ae89aSMauro Carvalho Chehab __func__, 'A' + layer, *count); 1151593ae89aSMauro Carvalho Chehab 1152593ae89aSMauro Carvalho Chehab /* 1153593ae89aSMauro Carvalho Chehab * As we get TMCC data from the frontend, we can better estimate the 1154593ae89aSMauro Carvalho Chehab * BER bit counters, in order to do the BER measure during a longer 1155593ae89aSMauro Carvalho Chehab * time. Use those data, if available, to update the bit count 1156593ae89aSMauro Carvalho Chehab * measure. 1157593ae89aSMauro Carvalho Chehab */ 1158593ae89aSMauro Carvalho Chehab 1159593ae89aSMauro Carvalho Chehab if (!state->estimated_rate[layer]) 1160593ae89aSMauro Carvalho Chehab goto reset_measurement; 1161593ae89aSMauro Carvalho Chehab 1162593ae89aSMauro Carvalho Chehab collect_rate = state->estimated_rate[layer] / 204 / 8; 1163593ae89aSMauro Carvalho Chehab if (collect_rate < 32) 1164593ae89aSMauro Carvalho Chehab collect_rate = 32; 1165593ae89aSMauro Carvalho Chehab if (collect_rate > 65535) 1166593ae89aSMauro Carvalho Chehab collect_rate = 65535; 1167593ae89aSMauro Carvalho Chehab 1168593ae89aSMauro Carvalho Chehab if (collect_rate != *count) { 1169593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1170593ae89aSMauro Carvalho Chehab "%s: updating PER counter on layer %c to %d.\n", 1171593ae89aSMauro Carvalho Chehab __func__, 'A' + layer, collect_rate); 1172313cf4efSMauro Carvalho Chehab 1173313cf4efSMauro Carvalho Chehab /* Stop PER measurement */ 1174313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb0); 1175313cf4efSMauro Carvalho Chehab if (rc < 0) 1176313cf4efSMauro Carvalho Chehab return rc; 1177313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x00); 1178313cf4efSMauro Carvalho Chehab if (rc < 0) 1179313cf4efSMauro Carvalho Chehab return rc; 1180313cf4efSMauro Carvalho Chehab 1181313cf4efSMauro Carvalho Chehab /* Update this layer's counter */ 1182593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1183593ae89aSMauro Carvalho Chehab if (rc < 0) 1184593ae89aSMauro Carvalho Chehab return rc; 1185593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1186593ae89aSMauro Carvalho Chehab if (rc < 0) 1187593ae89aSMauro Carvalho Chehab return rc; 1188593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1189593ae89aSMauro Carvalho Chehab if (rc < 0) 1190593ae89aSMauro Carvalho Chehab return rc; 1191593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1192593ae89aSMauro Carvalho Chehab if (rc < 0) 1193593ae89aSMauro Carvalho Chehab return rc; 1194313cf4efSMauro Carvalho Chehab 1195313cf4efSMauro Carvalho Chehab /* start PER measurement */ 1196313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb0); 1197313cf4efSMauro Carvalho Chehab if (rc < 0) 1198313cf4efSMauro Carvalho Chehab return rc; 1199313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x07); 1200313cf4efSMauro Carvalho Chehab if (rc < 0) 1201313cf4efSMauro Carvalho Chehab return rc; 1202313cf4efSMauro Carvalho Chehab 1203313cf4efSMauro Carvalho Chehab /* Reset all counters to collect new data */ 1204313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb1); 1205313cf4efSMauro Carvalho Chehab if (rc < 0) 1206313cf4efSMauro Carvalho Chehab return rc; 1207313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x07); 1208313cf4efSMauro Carvalho Chehab if (rc < 0) 1209313cf4efSMauro Carvalho Chehab return rc; 1210313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x00); 1211313cf4efSMauro Carvalho Chehab 1212313cf4efSMauro Carvalho Chehab return rc; 1213593ae89aSMauro Carvalho Chehab } 1214593ae89aSMauro Carvalho Chehab 1215593ae89aSMauro Carvalho Chehab reset_measurement: 1216593ae89aSMauro Carvalho Chehab /* Reset counter to collect new data */ 1217593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb1); 1218593ae89aSMauro Carvalho Chehab if (rc < 0) 1219593ae89aSMauro Carvalho Chehab return rc; 1220313cf4efSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1221593ae89aSMauro Carvalho Chehab if (rc < 0) 1222593ae89aSMauro Carvalho Chehab return rc; 1223313cf4efSMauro Carvalho Chehab val = rc; 1224313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); 1225593ae89aSMauro Carvalho Chehab if (rc < 0) 1226593ae89aSMauro Carvalho Chehab return rc; 1227313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); 1228593ae89aSMauro Carvalho Chehab 1229313cf4efSMauro Carvalho Chehab return rc; 1230593ae89aSMauro Carvalho Chehab } 1231593ae89aSMauro Carvalho Chehab 123225188bd0SMauro Carvalho Chehab struct linear_segments { 123325188bd0SMauro Carvalho Chehab unsigned x, y; 123425188bd0SMauro Carvalho Chehab }; 123525188bd0SMauro Carvalho Chehab 123625188bd0SMauro Carvalho Chehab /* 123725188bd0SMauro Carvalho Chehab * All tables below return a dB/1000 measurement 123825188bd0SMauro Carvalho Chehab */ 123925188bd0SMauro Carvalho Chehab 124025188bd0SMauro Carvalho Chehab static struct linear_segments cnr_to_db_table[] = { 124125188bd0SMauro Carvalho Chehab { 19648, 0}, 124225188bd0SMauro Carvalho Chehab { 18187, 1000}, 124325188bd0SMauro Carvalho Chehab { 16534, 2000}, 124425188bd0SMauro Carvalho Chehab { 14823, 3000}, 124525188bd0SMauro Carvalho Chehab { 13161, 4000}, 124625188bd0SMauro Carvalho Chehab { 11622, 5000}, 124725188bd0SMauro Carvalho Chehab { 10279, 6000}, 124825188bd0SMauro Carvalho Chehab { 9089, 7000}, 124925188bd0SMauro Carvalho Chehab { 8042, 8000}, 125025188bd0SMauro Carvalho Chehab { 7137, 9000}, 125125188bd0SMauro Carvalho Chehab { 6342, 10000}, 125225188bd0SMauro Carvalho Chehab { 5641, 11000}, 125325188bd0SMauro Carvalho Chehab { 5030, 12000}, 125425188bd0SMauro Carvalho Chehab { 4474, 13000}, 125525188bd0SMauro Carvalho Chehab { 3988, 14000}, 125625188bd0SMauro Carvalho Chehab { 3556, 15000}, 125725188bd0SMauro Carvalho Chehab { 3180, 16000}, 125825188bd0SMauro Carvalho Chehab { 2841, 17000}, 125925188bd0SMauro Carvalho Chehab { 2541, 18000}, 126025188bd0SMauro Carvalho Chehab { 2276, 19000}, 126125188bd0SMauro Carvalho Chehab { 2038, 20000}, 126225188bd0SMauro Carvalho Chehab { 1800, 21000}, 126325188bd0SMauro Carvalho Chehab { 1625, 22000}, 126425188bd0SMauro Carvalho Chehab { 1462, 23000}, 126525188bd0SMauro Carvalho Chehab { 1324, 24000}, 126625188bd0SMauro Carvalho Chehab { 1175, 25000}, 126725188bd0SMauro Carvalho Chehab { 1063, 26000}, 126825188bd0SMauro Carvalho Chehab { 980, 27000}, 126925188bd0SMauro Carvalho Chehab { 907, 28000}, 127025188bd0SMauro Carvalho Chehab { 840, 29000}, 127125188bd0SMauro Carvalho Chehab { 788, 30000}, 127225188bd0SMauro Carvalho Chehab }; 127325188bd0SMauro Carvalho Chehab 127425188bd0SMauro Carvalho Chehab static struct linear_segments cnr_64qam_table[] = { 127525188bd0SMauro Carvalho Chehab { 3922688, 0}, 127625188bd0SMauro Carvalho Chehab { 3920384, 1000}, 127725188bd0SMauro Carvalho Chehab { 3902720, 2000}, 127825188bd0SMauro Carvalho Chehab { 3894784, 3000}, 127925188bd0SMauro Carvalho Chehab { 3882496, 4000}, 128025188bd0SMauro Carvalho Chehab { 3872768, 5000}, 128125188bd0SMauro Carvalho Chehab { 3858944, 6000}, 128225188bd0SMauro Carvalho Chehab { 3851520, 7000}, 128325188bd0SMauro Carvalho Chehab { 3838976, 8000}, 128425188bd0SMauro Carvalho Chehab { 3829248, 9000}, 128525188bd0SMauro Carvalho Chehab { 3818240, 10000}, 128625188bd0SMauro Carvalho Chehab { 3806976, 11000}, 128725188bd0SMauro Carvalho Chehab { 3791872, 12000}, 128825188bd0SMauro Carvalho Chehab { 3767040, 13000}, 128925188bd0SMauro Carvalho Chehab { 3720960, 14000}, 129025188bd0SMauro Carvalho Chehab { 3637504, 15000}, 129125188bd0SMauro Carvalho Chehab { 3498496, 16000}, 129225188bd0SMauro Carvalho Chehab { 3296000, 17000}, 129325188bd0SMauro Carvalho Chehab { 3031040, 18000}, 129425188bd0SMauro Carvalho Chehab { 2715392, 19000}, 129525188bd0SMauro Carvalho Chehab { 2362624, 20000}, 129625188bd0SMauro Carvalho Chehab { 1963264, 21000}, 129725188bd0SMauro Carvalho Chehab { 1649664, 22000}, 129825188bd0SMauro Carvalho Chehab { 1366784, 23000}, 129925188bd0SMauro Carvalho Chehab { 1120768, 24000}, 130025188bd0SMauro Carvalho Chehab { 890880, 25000}, 130125188bd0SMauro Carvalho Chehab { 723456, 26000}, 130225188bd0SMauro Carvalho Chehab { 612096, 27000}, 130325188bd0SMauro Carvalho Chehab { 518912, 28000}, 130425188bd0SMauro Carvalho Chehab { 448256, 29000}, 130525188bd0SMauro Carvalho Chehab { 388864, 30000}, 130625188bd0SMauro Carvalho Chehab }; 130725188bd0SMauro Carvalho Chehab 130825188bd0SMauro Carvalho Chehab static struct linear_segments cnr_16qam_table[] = { 130925188bd0SMauro Carvalho Chehab { 5314816, 0}, 131025188bd0SMauro Carvalho Chehab { 5219072, 1000}, 131125188bd0SMauro Carvalho Chehab { 5118720, 2000}, 131225188bd0SMauro Carvalho Chehab { 4998912, 3000}, 131325188bd0SMauro Carvalho Chehab { 4875520, 4000}, 131425188bd0SMauro Carvalho Chehab { 4736000, 5000}, 131525188bd0SMauro Carvalho Chehab { 4604160, 6000}, 131625188bd0SMauro Carvalho Chehab { 4458752, 7000}, 131725188bd0SMauro Carvalho Chehab { 4300288, 8000}, 131825188bd0SMauro Carvalho Chehab { 4092928, 9000}, 131925188bd0SMauro Carvalho Chehab { 3836160, 10000}, 132025188bd0SMauro Carvalho Chehab { 3521024, 11000}, 132125188bd0SMauro Carvalho Chehab { 3155968, 12000}, 132225188bd0SMauro Carvalho Chehab { 2756864, 13000}, 132325188bd0SMauro Carvalho Chehab { 2347008, 14000}, 132425188bd0SMauro Carvalho Chehab { 1955072, 15000}, 132525188bd0SMauro Carvalho Chehab { 1593600, 16000}, 132625188bd0SMauro Carvalho Chehab { 1297920, 17000}, 132725188bd0SMauro Carvalho Chehab { 1043968, 18000}, 132825188bd0SMauro Carvalho Chehab { 839680, 19000}, 132925188bd0SMauro Carvalho Chehab { 672256, 20000}, 133025188bd0SMauro Carvalho Chehab { 523008, 21000}, 133125188bd0SMauro Carvalho Chehab { 424704, 22000}, 133225188bd0SMauro Carvalho Chehab { 345088, 23000}, 133325188bd0SMauro Carvalho Chehab { 280064, 24000}, 133425188bd0SMauro Carvalho Chehab { 221440, 25000}, 133525188bd0SMauro Carvalho Chehab { 179712, 26000}, 133625188bd0SMauro Carvalho Chehab { 151040, 27000}, 133725188bd0SMauro Carvalho Chehab { 128512, 28000}, 133825188bd0SMauro Carvalho Chehab { 110080, 29000}, 133925188bd0SMauro Carvalho Chehab { 95744, 30000}, 134025188bd0SMauro Carvalho Chehab }; 134125188bd0SMauro Carvalho Chehab 134225188bd0SMauro Carvalho Chehab struct linear_segments cnr_qpsk_table[] = { 134325188bd0SMauro Carvalho Chehab { 2834176, 0}, 134425188bd0SMauro Carvalho Chehab { 2683648, 1000}, 134525188bd0SMauro Carvalho Chehab { 2536960, 2000}, 134625188bd0SMauro Carvalho Chehab { 2391808, 3000}, 134725188bd0SMauro Carvalho Chehab { 2133248, 4000}, 134825188bd0SMauro Carvalho Chehab { 1906176, 5000}, 134925188bd0SMauro Carvalho Chehab { 1666560, 6000}, 135025188bd0SMauro Carvalho Chehab { 1422080, 7000}, 135125188bd0SMauro Carvalho Chehab { 1189632, 8000}, 135225188bd0SMauro Carvalho Chehab { 976384, 9000}, 135325188bd0SMauro Carvalho Chehab { 790272, 10000}, 135425188bd0SMauro Carvalho Chehab { 633344, 11000}, 135525188bd0SMauro Carvalho Chehab { 505600, 12000}, 135625188bd0SMauro Carvalho Chehab { 402944, 13000}, 135725188bd0SMauro Carvalho Chehab { 320768, 14000}, 135825188bd0SMauro Carvalho Chehab { 255488, 15000}, 135925188bd0SMauro Carvalho Chehab { 204032, 16000}, 136025188bd0SMauro Carvalho Chehab { 163072, 17000}, 136125188bd0SMauro Carvalho Chehab { 130304, 18000}, 136225188bd0SMauro Carvalho Chehab { 105216, 19000}, 136325188bd0SMauro Carvalho Chehab { 83456, 20000}, 136425188bd0SMauro Carvalho Chehab { 65024, 21000}, 136525188bd0SMauro Carvalho Chehab { 52480, 22000}, 136625188bd0SMauro Carvalho Chehab { 42752, 23000}, 136725188bd0SMauro Carvalho Chehab { 34560, 24000}, 136825188bd0SMauro Carvalho Chehab { 27136, 25000}, 136925188bd0SMauro Carvalho Chehab { 22016, 26000}, 137025188bd0SMauro Carvalho Chehab { 18432, 27000}, 137125188bd0SMauro Carvalho Chehab { 15616, 28000}, 137225188bd0SMauro Carvalho Chehab { 13312, 29000}, 137325188bd0SMauro Carvalho Chehab { 11520, 30000}, 137425188bd0SMauro Carvalho Chehab }; 137525188bd0SMauro Carvalho Chehab 137625188bd0SMauro Carvalho Chehab static u32 interpolate_value(u32 value, struct linear_segments *segments, 137725188bd0SMauro Carvalho Chehab unsigned len) 137825188bd0SMauro Carvalho Chehab { 137925188bd0SMauro Carvalho Chehab u64 tmp64; 138025188bd0SMauro Carvalho Chehab u32 dx, dy; 138125188bd0SMauro Carvalho Chehab int i, ret; 138225188bd0SMauro Carvalho Chehab 138325188bd0SMauro Carvalho Chehab if (value >= segments[0].x) 138425188bd0SMauro Carvalho Chehab return segments[0].y; 138525188bd0SMauro Carvalho Chehab if (value < segments[len-1].x) 138625188bd0SMauro Carvalho Chehab return segments[len-1].y; 138725188bd0SMauro Carvalho Chehab 138825188bd0SMauro Carvalho Chehab for (i = 1; i < len - 1; i++) { 138925188bd0SMauro Carvalho Chehab /* If value is identical, no need to interpolate */ 139025188bd0SMauro Carvalho Chehab if (value == segments[i].x) 139125188bd0SMauro Carvalho Chehab return segments[i].y; 139225188bd0SMauro Carvalho Chehab if (value > segments[i].x) 139325188bd0SMauro Carvalho Chehab break; 139425188bd0SMauro Carvalho Chehab } 139525188bd0SMauro Carvalho Chehab 139625188bd0SMauro Carvalho Chehab /* Linear interpolation between the two (x,y) points */ 139725188bd0SMauro Carvalho Chehab dy = segments[i].y - segments[i - 1].y; 139825188bd0SMauro Carvalho Chehab dx = segments[i - 1].x - segments[i].x; 139925188bd0SMauro Carvalho Chehab tmp64 = value - segments[i].x; 140025188bd0SMauro Carvalho Chehab tmp64 *= dy; 140125188bd0SMauro Carvalho Chehab do_div(tmp64, dx); 140225188bd0SMauro Carvalho Chehab ret = segments[i].y - tmp64; 140325188bd0SMauro Carvalho Chehab 140425188bd0SMauro Carvalho Chehab return ret; 140525188bd0SMauro Carvalho Chehab } 140625188bd0SMauro Carvalho Chehab 140725188bd0SMauro Carvalho Chehab static int mb86a20s_get_main_CNR(struct dvb_frontend *fe) 140825188bd0SMauro Carvalho Chehab { 140925188bd0SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 141025188bd0SMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 141125188bd0SMauro Carvalho Chehab u32 cnr_linear, cnr; 141225188bd0SMauro Carvalho Chehab int rc, val; 141325188bd0SMauro Carvalho Chehab 141425188bd0SMauro Carvalho Chehab /* Check if CNR is available */ 141525188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x45); 141625188bd0SMauro Carvalho Chehab if (rc < 0) 141725188bd0SMauro Carvalho Chehab return rc; 141825188bd0SMauro Carvalho Chehab 141925188bd0SMauro Carvalho Chehab if (!(rc & 0x40)) { 1420d56e326fSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n", 142125188bd0SMauro Carvalho Chehab __func__); 142225188bd0SMauro Carvalho Chehab return -EBUSY; 142325188bd0SMauro Carvalho Chehab } 142425188bd0SMauro Carvalho Chehab val = rc; 142525188bd0SMauro Carvalho Chehab 142625188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x46); 142725188bd0SMauro Carvalho Chehab if (rc < 0) 142825188bd0SMauro Carvalho Chehab return rc; 142925188bd0SMauro Carvalho Chehab cnr_linear = rc << 8; 143025188bd0SMauro Carvalho Chehab 143125188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x46); 143225188bd0SMauro Carvalho Chehab if (rc < 0) 143325188bd0SMauro Carvalho Chehab return rc; 143425188bd0SMauro Carvalho Chehab cnr_linear |= rc; 143525188bd0SMauro Carvalho Chehab 143625188bd0SMauro Carvalho Chehab cnr = interpolate_value(cnr_linear, 143725188bd0SMauro Carvalho Chehab cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table)); 143825188bd0SMauro Carvalho Chehab 143925188bd0SMauro Carvalho Chehab c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 144025188bd0SMauro Carvalho Chehab c->cnr.stat[0].svalue = cnr; 144125188bd0SMauro Carvalho Chehab 144225188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", 144325188bd0SMauro Carvalho Chehab __func__, cnr / 1000, cnr % 1000, cnr_linear); 144425188bd0SMauro Carvalho Chehab 144525188bd0SMauro Carvalho Chehab /* CNR counter reset */ 144625188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val | 0x10); 144725188bd0SMauro Carvalho Chehab if (rc < 0) 144825188bd0SMauro Carvalho Chehab return rc; 144925188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 145025188bd0SMauro Carvalho Chehab 145125188bd0SMauro Carvalho Chehab return rc; 145225188bd0SMauro Carvalho Chehab } 145325188bd0SMauro Carvalho Chehab 1454593ae89aSMauro Carvalho Chehab static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe) 145525188bd0SMauro Carvalho Chehab { 145625188bd0SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 145725188bd0SMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 145825188bd0SMauro Carvalho Chehab u32 mer, cnr; 145925188bd0SMauro Carvalho Chehab int rc, val, i; 146025188bd0SMauro Carvalho Chehab struct linear_segments *segs; 146125188bd0SMauro Carvalho Chehab unsigned segs_len; 146225188bd0SMauro Carvalho Chehab 146325188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 146425188bd0SMauro Carvalho Chehab 146525188bd0SMauro Carvalho Chehab /* Check if the measures are already available */ 146625188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x5b); 146725188bd0SMauro Carvalho Chehab if (rc < 0) 146825188bd0SMauro Carvalho Chehab return rc; 146925188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 147025188bd0SMauro Carvalho Chehab if (rc < 0) 147125188bd0SMauro Carvalho Chehab return rc; 147225188bd0SMauro Carvalho Chehab 147325188bd0SMauro Carvalho Chehab /* Check if data is available */ 147425188bd0SMauro Carvalho Chehab if (!(rc & 0x01)) { 1475d56e326fSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 147625188bd0SMauro Carvalho Chehab "%s: MER measures aren't available yet.\n", __func__); 147725188bd0SMauro Carvalho Chehab return -EBUSY; 147825188bd0SMauro Carvalho Chehab } 147925188bd0SMauro Carvalho Chehab 148025188bd0SMauro Carvalho Chehab /* Read all layers */ 14814f62a20dSMauro Carvalho Chehab for (i = 0; i < NUM_LAYERS; i++) { 148225188bd0SMauro Carvalho Chehab if (!(c->isdbt_layer_enabled & (1 << i))) { 148325188bd0SMauro Carvalho Chehab c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 148425188bd0SMauro Carvalho Chehab continue; 148525188bd0SMauro Carvalho Chehab } 148625188bd0SMauro Carvalho Chehab 148725188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3); 148825188bd0SMauro Carvalho Chehab if (rc < 0) 148925188bd0SMauro Carvalho Chehab return rc; 149025188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 149125188bd0SMauro Carvalho Chehab if (rc < 0) 149225188bd0SMauro Carvalho Chehab return rc; 149325188bd0SMauro Carvalho Chehab mer = rc << 16; 149425188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3); 149525188bd0SMauro Carvalho Chehab if (rc < 0) 149625188bd0SMauro Carvalho Chehab return rc; 149725188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 149825188bd0SMauro Carvalho Chehab if (rc < 0) 149925188bd0SMauro Carvalho Chehab return rc; 150025188bd0SMauro Carvalho Chehab mer |= rc << 8; 150125188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3); 150225188bd0SMauro Carvalho Chehab if (rc < 0) 150325188bd0SMauro Carvalho Chehab return rc; 150425188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 150525188bd0SMauro Carvalho Chehab if (rc < 0) 150625188bd0SMauro Carvalho Chehab return rc; 150725188bd0SMauro Carvalho Chehab mer |= rc; 150825188bd0SMauro Carvalho Chehab 150925188bd0SMauro Carvalho Chehab switch (c->layer[i].modulation) { 151025188bd0SMauro Carvalho Chehab case DQPSK: 151125188bd0SMauro Carvalho Chehab case QPSK: 151225188bd0SMauro Carvalho Chehab segs = cnr_qpsk_table; 151325188bd0SMauro Carvalho Chehab segs_len = ARRAY_SIZE(cnr_qpsk_table); 151425188bd0SMauro Carvalho Chehab break; 151525188bd0SMauro Carvalho Chehab case QAM_16: 151625188bd0SMauro Carvalho Chehab segs = cnr_16qam_table; 151725188bd0SMauro Carvalho Chehab segs_len = ARRAY_SIZE(cnr_16qam_table); 151825188bd0SMauro Carvalho Chehab break; 151925188bd0SMauro Carvalho Chehab default: 152025188bd0SMauro Carvalho Chehab case QAM_64: 152125188bd0SMauro Carvalho Chehab segs = cnr_64qam_table; 152225188bd0SMauro Carvalho Chehab segs_len = ARRAY_SIZE(cnr_64qam_table); 152325188bd0SMauro Carvalho Chehab break; 152425188bd0SMauro Carvalho Chehab } 152525188bd0SMauro Carvalho Chehab cnr = interpolate_value(mer, segs, segs_len); 152625188bd0SMauro Carvalho Chehab 152725188bd0SMauro Carvalho Chehab c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL; 152825188bd0SMauro Carvalho Chehab c->cnr.stat[1 + i].svalue = cnr; 152925188bd0SMauro Carvalho Chehab 153025188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 153125188bd0SMauro Carvalho Chehab "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n", 153225188bd0SMauro Carvalho Chehab __func__, 'A' + i, cnr / 1000, cnr % 1000, mer); 153325188bd0SMauro Carvalho Chehab 153425188bd0SMauro Carvalho Chehab } 153525188bd0SMauro Carvalho Chehab 153625188bd0SMauro Carvalho Chehab /* Start a new MER measurement */ 153725188bd0SMauro Carvalho Chehab /* MER counter reset */ 153825188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x50); 153925188bd0SMauro Carvalho Chehab if (rc < 0) 154025188bd0SMauro Carvalho Chehab return rc; 154125188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 154225188bd0SMauro Carvalho Chehab if (rc < 0) 154325188bd0SMauro Carvalho Chehab return rc; 154425188bd0SMauro Carvalho Chehab val = rc; 154525188bd0SMauro Carvalho Chehab 154625188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val | 0x01); 154725188bd0SMauro Carvalho Chehab if (rc < 0) 154825188bd0SMauro Carvalho Chehab return rc; 154925188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val & 0x06); 155025188bd0SMauro Carvalho Chehab if (rc < 0) 155125188bd0SMauro Carvalho Chehab return rc; 155225188bd0SMauro Carvalho Chehab 155325188bd0SMauro Carvalho Chehab return 0; 155425188bd0SMauro Carvalho Chehab } 155525188bd0SMauro Carvalho Chehab 155609b6d21eSMauro Carvalho Chehab static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) 155709b6d21eSMauro Carvalho Chehab { 155809b6d21eSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 155909b6d21eSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 156009b6d21eSMauro Carvalho Chehab int i; 156109b6d21eSMauro Carvalho Chehab 156209b6d21eSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 156309b6d21eSMauro Carvalho Chehab 156409b6d21eSMauro Carvalho Chehab /* Fill the length of each status counter */ 156509b6d21eSMauro Carvalho Chehab 156609b6d21eSMauro Carvalho Chehab /* Only global stats */ 156709b6d21eSMauro Carvalho Chehab c->strength.len = 1; 156809b6d21eSMauro Carvalho Chehab 156909b6d21eSMauro Carvalho Chehab /* Per-layer stats - 3 layers + global */ 15704f62a20dSMauro Carvalho Chehab c->cnr.len = NUM_LAYERS + 1; 15714f62a20dSMauro Carvalho Chehab c->pre_bit_error.len = NUM_LAYERS + 1; 15724f62a20dSMauro Carvalho Chehab c->pre_bit_count.len = NUM_LAYERS + 1; 15734f62a20dSMauro Carvalho Chehab c->post_bit_error.len = NUM_LAYERS + 1; 15744f62a20dSMauro Carvalho Chehab c->post_bit_count.len = NUM_LAYERS + 1; 15754f62a20dSMauro Carvalho Chehab c->block_error.len = NUM_LAYERS + 1; 15764f62a20dSMauro Carvalho Chehab c->block_count.len = NUM_LAYERS + 1; 157709b6d21eSMauro Carvalho Chehab 157809b6d21eSMauro Carvalho Chehab /* Signal is always available */ 157909b6d21eSMauro Carvalho Chehab c->strength.stat[0].scale = FE_SCALE_RELATIVE; 158009b6d21eSMauro Carvalho Chehab c->strength.stat[0].uvalue = 0; 158109b6d21eSMauro Carvalho Chehab 158209b6d21eSMauro Carvalho Chehab /* Put all of them at FE_SCALE_NOT_AVAILABLE */ 15834f62a20dSMauro Carvalho Chehab for (i = 0; i < NUM_LAYERS + 1; i++) { 158409b6d21eSMauro Carvalho Chehab c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 158509b6d21eSMauro Carvalho Chehab c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 158609b6d21eSMauro Carvalho Chehab c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1587d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1588d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 158909b6d21eSMauro Carvalho Chehab c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 159009b6d21eSMauro Carvalho Chehab c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 159109b6d21eSMauro Carvalho Chehab } 159209b6d21eSMauro Carvalho Chehab } 159309b6d21eSMauro Carvalho Chehab 159415b1c5a0SMauro Carvalho Chehab static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr) 1595149d518aSMauro Carvalho Chehab { 1596149d518aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1597149d518aSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1598149d518aSMauro Carvalho Chehab int rc = 0, i; 1599149d518aSMauro Carvalho Chehab u32 bit_error = 0, bit_count = 0; 1600149d518aSMauro Carvalho Chehab u32 t_pre_bit_error = 0, t_pre_bit_count = 0; 1601d9b6f08aSMauro Carvalho Chehab u32 t_post_bit_error = 0, t_post_bit_count = 0; 1602593ae89aSMauro Carvalho Chehab u32 block_error = 0, block_count = 0; 1603593ae89aSMauro Carvalho Chehab u32 t_block_error = 0, t_block_count = 0; 1604d9b6f08aSMauro Carvalho Chehab int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0; 1605d9b6f08aSMauro Carvalho Chehab int per_layers = 0; 1606149d518aSMauro Carvalho Chehab 160725188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 160825188bd0SMauro Carvalho Chehab 160925188bd0SMauro Carvalho Chehab mb86a20s_get_main_CNR(fe); 161025188bd0SMauro Carvalho Chehab 1611149d518aSMauro Carvalho Chehab /* Get per-layer stats */ 1612593ae89aSMauro Carvalho Chehab mb86a20s_get_blk_error_layer_CNR(fe); 161325188bd0SMauro Carvalho Chehab 161415b1c5a0SMauro Carvalho Chehab /* 161515b1c5a0SMauro Carvalho Chehab * At state 7, only CNR is available 161615b1c5a0SMauro Carvalho Chehab * For BER measures, state=9 is required 161715b1c5a0SMauro Carvalho Chehab * FIXME: we may get MER measures with state=8 161815b1c5a0SMauro Carvalho Chehab */ 161915b1c5a0SMauro Carvalho Chehab if (status_nr < 9) 162015b1c5a0SMauro Carvalho Chehab return 0; 162115b1c5a0SMauro Carvalho Chehab 16224f62a20dSMauro Carvalho Chehab for (i = 0; i < NUM_LAYERS; i++) { 1623149d518aSMauro Carvalho Chehab if (c->isdbt_layer_enabled & (1 << i)) { 1624149d518aSMauro Carvalho Chehab /* Layer is active and has rc segments */ 1625149d518aSMauro Carvalho Chehab active_layers++; 1626149d518aSMauro Carvalho Chehab 1627149d518aSMauro Carvalho Chehab /* Handle BER before vterbi */ 1628ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_get_pre_ber(fe, i, 1629ad0abbf1SMauro Carvalho Chehab &bit_error, &bit_count); 1630149d518aSMauro Carvalho Chehab if (rc >= 0) { 1631149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1632149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[1 + i].uvalue += bit_error; 1633149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1634149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[1 + i].uvalue += bit_count; 1635149d518aSMauro Carvalho Chehab } else if (rc != -EBUSY) { 1636149d518aSMauro Carvalho Chehab /* 1637149d518aSMauro Carvalho Chehab * If an I/O error happened, 1638149d518aSMauro Carvalho Chehab * measures are now unavailable 1639149d518aSMauro Carvalho Chehab */ 1640149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1641149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1642149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1643149d518aSMauro Carvalho Chehab "%s: Can't get BER for layer %c (error %d).\n", 1644149d518aSMauro Carvalho Chehab __func__, 'A' + i, rc); 1645149d518aSMauro Carvalho Chehab } 1646149d518aSMauro Carvalho Chehab if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1647d9b6f08aSMauro Carvalho Chehab pre_ber_layers++; 1648d9b6f08aSMauro Carvalho Chehab 1649d9b6f08aSMauro Carvalho Chehab /* Handle BER post vterbi */ 1650d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_get_post_ber(fe, i, 1651d9b6f08aSMauro Carvalho Chehab &bit_error, &bit_count); 1652d9b6f08aSMauro Carvalho Chehab if (rc >= 0) { 1653d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1654d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[1 + i].uvalue += bit_error; 1655d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1656d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[1 + i].uvalue += bit_count; 1657d9b6f08aSMauro Carvalho Chehab } else if (rc != -EBUSY) { 1658d9b6f08aSMauro Carvalho Chehab /* 1659d9b6f08aSMauro Carvalho Chehab * If an I/O error happened, 1660d9b6f08aSMauro Carvalho Chehab * measures are now unavailable 1661d9b6f08aSMauro Carvalho Chehab */ 1662d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1663d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1664d9b6f08aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1665d9b6f08aSMauro Carvalho Chehab "%s: Can't get BER for layer %c (error %d).\n", 1666d9b6f08aSMauro Carvalho Chehab __func__, 'A' + i, rc); 1667d9b6f08aSMauro Carvalho Chehab } 1668d9b6f08aSMauro Carvalho Chehab if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1669d9b6f08aSMauro Carvalho Chehab post_ber_layers++; 1670149d518aSMauro Carvalho Chehab 1671593ae89aSMauro Carvalho Chehab /* Handle Block errors for PER/UCB reports */ 1672593ae89aSMauro Carvalho Chehab rc = mb86a20s_get_blk_error(fe, i, 1673593ae89aSMauro Carvalho Chehab &block_error, 1674593ae89aSMauro Carvalho Chehab &block_count); 1675593ae89aSMauro Carvalho Chehab if (rc >= 0) { 1676593ae89aSMauro Carvalho Chehab c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1677593ae89aSMauro Carvalho Chehab c->block_error.stat[1 + i].uvalue += block_error; 1678593ae89aSMauro Carvalho Chehab c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1679593ae89aSMauro Carvalho Chehab c->block_count.stat[1 + i].uvalue += block_count; 1680593ae89aSMauro Carvalho Chehab } else if (rc != -EBUSY) { 1681593ae89aSMauro Carvalho Chehab /* 1682593ae89aSMauro Carvalho Chehab * If an I/O error happened, 1683593ae89aSMauro Carvalho Chehab * measures are now unavailable 1684593ae89aSMauro Carvalho Chehab */ 1685593ae89aSMauro Carvalho Chehab c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1686593ae89aSMauro Carvalho Chehab c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1687593ae89aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1688593ae89aSMauro Carvalho Chehab "%s: Can't get PER for layer %c (error %d).\n", 1689593ae89aSMauro Carvalho Chehab __func__, 'A' + i, rc); 1690593ae89aSMauro Carvalho Chehab 1691593ae89aSMauro Carvalho Chehab } 1692593ae89aSMauro Carvalho Chehab if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1693593ae89aSMauro Carvalho Chehab per_layers++; 1694593ae89aSMauro Carvalho Chehab 1695d9b6f08aSMauro Carvalho Chehab /* Update total preBER */ 1696149d518aSMauro Carvalho Chehab t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue; 1697149d518aSMauro Carvalho Chehab t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue; 1698593ae89aSMauro Carvalho Chehab 1699d9b6f08aSMauro Carvalho Chehab /* Update total postBER */ 1700d9b6f08aSMauro Carvalho Chehab t_post_bit_error += c->post_bit_error.stat[1 + i].uvalue; 1701d9b6f08aSMauro Carvalho Chehab t_post_bit_count += c->post_bit_count.stat[1 + i].uvalue; 1702d9b6f08aSMauro Carvalho Chehab 1703593ae89aSMauro Carvalho Chehab /* Update total PER */ 1704593ae89aSMauro Carvalho Chehab t_block_error += c->block_error.stat[1 + i].uvalue; 1705593ae89aSMauro Carvalho Chehab t_block_count += c->block_count.stat[1 + i].uvalue; 1706149d518aSMauro Carvalho Chehab } 1707149d518aSMauro Carvalho Chehab } 1708149d518aSMauro Carvalho Chehab 1709149d518aSMauro Carvalho Chehab /* 1710149d518aSMauro Carvalho Chehab * Start showing global count if at least one error count is 1711149d518aSMauro Carvalho Chehab * available. 1712149d518aSMauro Carvalho Chehab */ 1713d9b6f08aSMauro Carvalho Chehab if (pre_ber_layers) { 1714149d518aSMauro Carvalho Chehab /* 1715149d518aSMauro Carvalho Chehab * At least one per-layer BER measure was read. We can now 1716149d518aSMauro Carvalho Chehab * calculate the total BER 1717149d518aSMauro Carvalho Chehab * 1718149d518aSMauro Carvalho Chehab * Total Bit Error/Count is calculated as the sum of the 1719149d518aSMauro Carvalho Chehab * bit errors on all active layers. 1720149d518aSMauro Carvalho Chehab */ 1721149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1722149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; 1723149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1724149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; 1725f67102c4SMauro Carvalho Chehab } else { 1726f67102c4SMauro Carvalho Chehab c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1727f67102c4SMauro Carvalho Chehab c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1728149d518aSMauro Carvalho Chehab } 1729149d518aSMauro Carvalho Chehab 1730d9b6f08aSMauro Carvalho Chehab /* 1731d9b6f08aSMauro Carvalho Chehab * Start showing global count if at least one error count is 1732d9b6f08aSMauro Carvalho Chehab * available. 1733d9b6f08aSMauro Carvalho Chehab */ 1734d9b6f08aSMauro Carvalho Chehab if (post_ber_layers) { 1735d9b6f08aSMauro Carvalho Chehab /* 1736d9b6f08aSMauro Carvalho Chehab * At least one per-layer BER measure was read. We can now 1737d9b6f08aSMauro Carvalho Chehab * calculate the total BER 1738d9b6f08aSMauro Carvalho Chehab * 1739d9b6f08aSMauro Carvalho Chehab * Total Bit Error/Count is calculated as the sum of the 1740d9b6f08aSMauro Carvalho Chehab * bit errors on all active layers. 1741d9b6f08aSMauro Carvalho Chehab */ 1742d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1743d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[0].uvalue = t_post_bit_error; 1744d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1745d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[0].uvalue = t_post_bit_count; 1746f67102c4SMauro Carvalho Chehab } else { 1747f67102c4SMauro Carvalho Chehab c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1748f67102c4SMauro Carvalho Chehab c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1749d9b6f08aSMauro Carvalho Chehab } 1750d9b6f08aSMauro Carvalho Chehab 1751593ae89aSMauro Carvalho Chehab if (per_layers) { 1752593ae89aSMauro Carvalho Chehab /* 1753593ae89aSMauro Carvalho Chehab * At least one per-layer UCB measure was read. We can now 1754593ae89aSMauro Carvalho Chehab * calculate the total UCB 1755593ae89aSMauro Carvalho Chehab * 1756593ae89aSMauro Carvalho Chehab * Total block Error/Count is calculated as the sum of the 1757593ae89aSMauro Carvalho Chehab * block errors on all active layers. 1758593ae89aSMauro Carvalho Chehab */ 1759593ae89aSMauro Carvalho Chehab c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1760593ae89aSMauro Carvalho Chehab c->block_error.stat[0].uvalue = t_block_error; 1761593ae89aSMauro Carvalho Chehab c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1762593ae89aSMauro Carvalho Chehab c->block_count.stat[0].uvalue = t_block_count; 1763f67102c4SMauro Carvalho Chehab } else { 1764f67102c4SMauro Carvalho Chehab c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1765f67102c4SMauro Carvalho Chehab c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1766593ae89aSMauro Carvalho Chehab } 1767593ae89aSMauro Carvalho Chehab 1768149d518aSMauro Carvalho Chehab return rc; 1769149d518aSMauro Carvalho Chehab } 177009b6d21eSMauro Carvalho Chehab 177109b6d21eSMauro Carvalho Chehab /* 177209b6d21eSMauro Carvalho Chehab * The functions below are called via DVB callbacks, so they need to 177309b6d21eSMauro Carvalho Chehab * properly use the I2C gate control 177409b6d21eSMauro Carvalho Chehab */ 177509b6d21eSMauro Carvalho Chehab 1776dd4493efSMauro Carvalho Chehab static int mb86a20s_initfe(struct dvb_frontend *fe) 1777dd4493efSMauro Carvalho Chehab { 1778dd4493efSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1779768e6dadSMauro Carvalho Chehab u64 pll; 17800e4bbeddSMauro Carvalho Chehab u32 fclk; 1781dd4493efSMauro Carvalho Chehab int rc; 178204fa725eSMauro Carvalho Chehab u8 regD5 = 1, reg71, reg09 = 0x3a; 1783dd4493efSMauro Carvalho Chehab 1784f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1785dd4493efSMauro Carvalho Chehab 1786dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1787dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); 1788dd4493efSMauro Carvalho Chehab 1789dd4493efSMauro Carvalho Chehab /* Initialize the frontend */ 1790768e6dadSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_init1); 1791dd4493efSMauro Carvalho Chehab if (rc < 0) 1792dd4493efSMauro Carvalho Chehab goto err; 1793dd4493efSMauro Carvalho Chehab 179404fa725eSMauro Carvalho Chehab if (!state->inversion) 179504fa725eSMauro Carvalho Chehab reg09 |= 0x04; 179604fa725eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x09, reg09); 179704fa725eSMauro Carvalho Chehab if (rc < 0) 179804fa725eSMauro Carvalho Chehab goto err; 179904fa725eSMauro Carvalho Chehab if (!state->bw) 180004fa725eSMauro Carvalho Chehab reg71 = 1; 180104fa725eSMauro Carvalho Chehab else 180204fa725eSMauro Carvalho Chehab reg71 = 0; 180304fa725eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x39, reg71); 180404fa725eSMauro Carvalho Chehab if (rc < 0) 180504fa725eSMauro Carvalho Chehab goto err; 180604fa725eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x71, state->bw); 180704fa725eSMauro Carvalho Chehab if (rc < 0) 180804fa725eSMauro Carvalho Chehab goto err; 180904fa725eSMauro Carvalho Chehab if (state->subchannel) { 181004fa725eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x44, state->subchannel); 181104fa725eSMauro Carvalho Chehab if (rc < 0) 181204fa725eSMauro Carvalho Chehab goto err; 181304fa725eSMauro Carvalho Chehab } 181404fa725eSMauro Carvalho Chehab 18150e4bbeddSMauro Carvalho Chehab fclk = state->config->fclk; 18160e4bbeddSMauro Carvalho Chehab if (!fclk) 18170e4bbeddSMauro Carvalho Chehab fclk = 32571428; 18180e4bbeddSMauro Carvalho Chehab 1819768e6dadSMauro Carvalho Chehab /* Adjust IF frequency to match tuner */ 1820768e6dadSMauro Carvalho Chehab if (fe->ops.tuner_ops.get_if_frequency) 1821768e6dadSMauro Carvalho Chehab fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq); 1822768e6dadSMauro Carvalho Chehab 1823768e6dadSMauro Carvalho Chehab if (!state->if_freq) 1824768e6dadSMauro Carvalho Chehab state->if_freq = 3300000; 1825768e6dadSMauro Carvalho Chehab 18260e4bbeddSMauro Carvalho Chehab pll = (((u64)1) << 34) * state->if_freq; 18270e4bbeddSMauro Carvalho Chehab do_div(pll, 63 * fclk); 18280e4bbeddSMauro Carvalho Chehab pll = (1 << 25) - pll; 18290e4bbeddSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x28, 0x2a); 18300e4bbeddSMauro Carvalho Chehab if (rc < 0) 18310e4bbeddSMauro Carvalho Chehab goto err; 18320e4bbeddSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 18330e4bbeddSMauro Carvalho Chehab if (rc < 0) 18340e4bbeddSMauro Carvalho Chehab goto err; 18350e4bbeddSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 18360e4bbeddSMauro Carvalho Chehab if (rc < 0) 18370e4bbeddSMauro Carvalho Chehab goto err; 18380e4bbeddSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 18390e4bbeddSMauro Carvalho Chehab if (rc < 0) 18400e4bbeddSMauro Carvalho Chehab goto err; 18410e4bbeddSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n", 18420e4bbeddSMauro Carvalho Chehab __func__, fclk, state->if_freq, (long long)pll); 18430e4bbeddSMauro Carvalho Chehab 1844768e6dadSMauro Carvalho Chehab /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */ 1845768e6dadSMauro Carvalho Chehab pll = state->if_freq * 1677721600L; 1846768e6dadSMauro Carvalho Chehab do_div(pll, 1628571429L); 1847768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x28, 0x20); 1848768e6dadSMauro Carvalho Chehab if (rc < 0) 1849768e6dadSMauro Carvalho Chehab goto err; 1850768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1851768e6dadSMauro Carvalho Chehab if (rc < 0) 1852768e6dadSMauro Carvalho Chehab goto err; 1853768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1854768e6dadSMauro Carvalho Chehab if (rc < 0) 1855768e6dadSMauro Carvalho Chehab goto err; 1856768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1857768e6dadSMauro Carvalho Chehab if (rc < 0) 1858768e6dadSMauro Carvalho Chehab goto err; 18590e4bbeddSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n", 1860768e6dadSMauro Carvalho Chehab __func__, state->if_freq, (long long)pll); 1861768e6dadSMauro Carvalho Chehab 1862dd4493efSMauro Carvalho Chehab if (!state->config->is_serial) { 1863dd4493efSMauro Carvalho Chehab regD5 &= ~1; 1864dd4493efSMauro Carvalho Chehab 1865dd4493efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xd5); 1866dd4493efSMauro Carvalho Chehab if (rc < 0) 1867dd4493efSMauro Carvalho Chehab goto err; 1868dd4493efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, regD5); 1869dd4493efSMauro Carvalho Chehab if (rc < 0) 1870dd4493efSMauro Carvalho Chehab goto err; 1871dd4493efSMauro Carvalho Chehab } 1872dd4493efSMauro Carvalho Chehab 1873768e6dadSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_init2); 1874768e6dadSMauro Carvalho Chehab if (rc < 0) 1875768e6dadSMauro Carvalho Chehab goto err; 1876768e6dadSMauro Carvalho Chehab 1877768e6dadSMauro Carvalho Chehab 1878dd4493efSMauro Carvalho Chehab err: 1879dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1880dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 1881dd4493efSMauro Carvalho Chehab 1882dd4493efSMauro Carvalho Chehab if (rc < 0) { 1883dd4493efSMauro Carvalho Chehab state->need_init = true; 1884f66d81b5SMauro Carvalho Chehab dev_info(&state->i2c->dev, 1885f66d81b5SMauro Carvalho Chehab "mb86a20s: Init failed. Will try again later\n"); 1886dd4493efSMauro Carvalho Chehab } else { 1887dd4493efSMauro Carvalho Chehab state->need_init = false; 1888f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); 1889dd4493efSMauro Carvalho Chehab } 1890dd4493efSMauro Carvalho Chehab return rc; 1891dd4493efSMauro Carvalho Chehab } 1892dd4493efSMauro Carvalho Chehab 1893dd4493efSMauro Carvalho Chehab static int mb86a20s_set_frontend(struct dvb_frontend *fe) 1894dd4493efSMauro Carvalho Chehab { 1895dd4493efSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1896dd4493efSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 189704fa725eSMauro Carvalho Chehab int rc, if_freq; 1898f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1899dd4493efSMauro Carvalho Chehab 190004fa725eSMauro Carvalho Chehab if (!c->isdbt_layer_enabled) 190104fa725eSMauro Carvalho Chehab c->isdbt_layer_enabled = 7; 190204fa725eSMauro Carvalho Chehab 190304fa725eSMauro Carvalho Chehab if (c->isdbt_layer_enabled == 1) 190404fa725eSMauro Carvalho Chehab state->bw = MB86A20S_1SEG; 190504fa725eSMauro Carvalho Chehab else if (c->isdbt_partial_reception) 190604fa725eSMauro Carvalho Chehab state->bw = MB86A20S_13SEG_PARTIAL; 190704fa725eSMauro Carvalho Chehab else 190804fa725eSMauro Carvalho Chehab state->bw = MB86A20S_13SEG; 190904fa725eSMauro Carvalho Chehab 191004fa725eSMauro Carvalho Chehab if (c->inversion == INVERSION_ON) 191104fa725eSMauro Carvalho Chehab state->inversion = true; 191204fa725eSMauro Carvalho Chehab else 191304fa725eSMauro Carvalho Chehab state->inversion = false; 191404fa725eSMauro Carvalho Chehab 191504fa725eSMauro Carvalho Chehab if (!c->isdbt_sb_mode) { 191604fa725eSMauro Carvalho Chehab state->subchannel = 0; 191704fa725eSMauro Carvalho Chehab } else { 191804fa725eSMauro Carvalho Chehab if (c->isdbt_sb_subchannel > ARRAY_SIZE(mb86a20s_subchannel)) 191904fa725eSMauro Carvalho Chehab c->isdbt_sb_subchannel = 0; 192004fa725eSMauro Carvalho Chehab 192104fa725eSMauro Carvalho Chehab state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel]; 192204fa725eSMauro Carvalho Chehab } 192304fa725eSMauro Carvalho Chehab 1924dd4493efSMauro Carvalho Chehab /* 1925dd4493efSMauro Carvalho Chehab * Gate should already be opened, but it doesn't hurt to 1926dd4493efSMauro Carvalho Chehab * double-check 1927dd4493efSMauro Carvalho Chehab */ 1928dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1929dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 1930dd4493efSMauro Carvalho Chehab fe->ops.tuner_ops.set_params(fe); 1931dd4493efSMauro Carvalho Chehab 1932a78b41d5SMauro Carvalho Chehab if (fe->ops.tuner_ops.get_if_frequency) 1933768e6dadSMauro Carvalho Chehab fe->ops.tuner_ops.get_if_frequency(fe, &if_freq); 1934768e6dadSMauro Carvalho Chehab 1935768e6dadSMauro Carvalho Chehab /* 1936dd4493efSMauro Carvalho Chehab * Make it more reliable: if, for some reason, the initial 1937dd4493efSMauro Carvalho Chehab * device initialization doesn't happen, initialize it when 1938dd4493efSMauro Carvalho Chehab * a SBTVD parameters are adjusted. 1939dd4493efSMauro Carvalho Chehab * 1940dd4493efSMauro Carvalho Chehab * Unfortunately, due to a hard to track bug at tda829x/tda18271, 1941dd4493efSMauro Carvalho Chehab * the agc callback logic is not called during DVB attach time, 1942dd4493efSMauro Carvalho Chehab * causing mb86a20s to not be initialized with Kworld SBTVD. 1943dd4493efSMauro Carvalho Chehab * So, this hack is needed, in order to make Kworld SBTVD to work. 1944768e6dadSMauro Carvalho Chehab * 1945768e6dadSMauro Carvalho Chehab * It is also needed to change the IF after the initial init. 1946a78b41d5SMauro Carvalho Chehab * 1947a78b41d5SMauro Carvalho Chehab * HACK: Always init the frontend when set_frontend is called: 1948a78b41d5SMauro Carvalho Chehab * it was noticed that, on some devices, it fails to lock on a 1949a78b41d5SMauro Carvalho Chehab * different channel. So, it is better to reset everything, even 1950a78b41d5SMauro Carvalho Chehab * wasting some time, than to loose channel lock. 1951dd4493efSMauro Carvalho Chehab */ 1952dd4493efSMauro Carvalho Chehab mb86a20s_initfe(fe); 1953dd4493efSMauro Carvalho Chehab 1954dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1955dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); 1956d01a8ee3SMauro Carvalho Chehab 1957dd4493efSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); 195809b6d21eSMauro Carvalho Chehab mb86a20s_reset_counters(fe); 19593a2e4751SMauro Carvalho Chehab mb86a20s_stats_not_ready(fe); 1960d01a8ee3SMauro Carvalho Chehab 1961dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1962dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 1963dd4493efSMauro Carvalho Chehab 1964dd4493efSMauro Carvalho Chehab return rc; 1965dd4493efSMauro Carvalho Chehab } 1966dd4493efSMauro Carvalho Chehab 196709b6d21eSMauro Carvalho Chehab static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, 1968d36e418aSMauro Carvalho Chehab fe_status_t *status) 1969d36e418aSMauro Carvalho Chehab { 197009b6d21eSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 197115b1c5a0SMauro Carvalho Chehab int rc, status_nr; 1972d36e418aSMauro Carvalho Chehab 197309b6d21eSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1974d36e418aSMauro Carvalho Chehab 1975d36e418aSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1976d36e418aSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); 1977d36e418aSMauro Carvalho Chehab 197809b6d21eSMauro Carvalho Chehab /* Get lock */ 197915b1c5a0SMauro Carvalho Chehab status_nr = mb86a20s_read_status(fe, status); 198015b1c5a0SMauro Carvalho Chehab if (status_nr < 7) { 198109b6d21eSMauro Carvalho Chehab mb86a20s_stats_not_ready(fe); 198209b6d21eSMauro Carvalho Chehab mb86a20s_reset_frontend_cache(fe); 198309b6d21eSMauro Carvalho Chehab } 198415b1c5a0SMauro Carvalho Chehab if (status_nr < 0) { 1985149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1986149d518aSMauro Carvalho Chehab "%s: Can't read frontend lock status\n", __func__); 198709b6d21eSMauro Carvalho Chehab goto error; 1988149d518aSMauro Carvalho Chehab } 198909b6d21eSMauro Carvalho Chehab 199009b6d21eSMauro Carvalho Chehab /* Get signal strength */ 199109b6d21eSMauro Carvalho Chehab rc = mb86a20s_read_signal_strength(fe); 199209b6d21eSMauro Carvalho Chehab if (rc < 0) { 1993149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1994149d518aSMauro Carvalho Chehab "%s: Can't reset VBER registers.\n", __func__); 199509b6d21eSMauro Carvalho Chehab mb86a20s_stats_not_ready(fe); 199609b6d21eSMauro Carvalho Chehab mb86a20s_reset_frontend_cache(fe); 1997149d518aSMauro Carvalho Chehab 1998149d518aSMauro Carvalho Chehab rc = 0; /* Status is OK */ 199909b6d21eSMauro Carvalho Chehab goto error; 200009b6d21eSMauro Carvalho Chehab } 200109b6d21eSMauro Carvalho Chehab 200215b1c5a0SMauro Carvalho Chehab if (status_nr >= 7) { 200309b6d21eSMauro Carvalho Chehab /* Get TMCC info*/ 200409b6d21eSMauro Carvalho Chehab rc = mb86a20s_get_frontend(fe); 2005149d518aSMauro Carvalho Chehab if (rc < 0) { 2006149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 2007149d518aSMauro Carvalho Chehab "%s: Can't get FE TMCC data.\n", __func__); 2008149d518aSMauro Carvalho Chehab rc = 0; /* Status is OK */ 200909b6d21eSMauro Carvalho Chehab goto error; 201009b6d21eSMauro Carvalho Chehab } 201109b6d21eSMauro Carvalho Chehab 2012149d518aSMauro Carvalho Chehab /* Get statistics */ 201315b1c5a0SMauro Carvalho Chehab rc = mb86a20s_get_stats(fe, status_nr); 2014149d518aSMauro Carvalho Chehab if (rc < 0 && rc != -EBUSY) { 2015149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 2016149d518aSMauro Carvalho Chehab "%s: Can't get FE statistics.\n", __func__); 2017149d518aSMauro Carvalho Chehab rc = 0; 2018149d518aSMauro Carvalho Chehab goto error; 2019149d518aSMauro Carvalho Chehab } 2020149d518aSMauro Carvalho Chehab rc = 0; /* Don't return EBUSY to userspace */ 2021149d518aSMauro Carvalho Chehab } 2022149d518aSMauro Carvalho Chehab goto ok; 2023149d518aSMauro Carvalho Chehab 2024149d518aSMauro Carvalho Chehab error: 202509b6d21eSMauro Carvalho Chehab mb86a20s_stats_not_ready(fe); 2026d36e418aSMauro Carvalho Chehab 2027149d518aSMauro Carvalho Chehab ok: 2028d36e418aSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 2029d36e418aSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 2030149d518aSMauro Carvalho Chehab 203109b6d21eSMauro Carvalho Chehab return rc; 2032d36e418aSMauro Carvalho Chehab } 2033d36e418aSMauro Carvalho Chehab 203409b6d21eSMauro Carvalho Chehab static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, 203509b6d21eSMauro Carvalho Chehab u16 *strength) 203609b6d21eSMauro Carvalho Chehab { 203709b6d21eSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 203809b6d21eSMauro Carvalho Chehab 203909b6d21eSMauro Carvalho Chehab 204009b6d21eSMauro Carvalho Chehab *strength = c->strength.stat[0].uvalue; 204109b6d21eSMauro Carvalho Chehab 204209b6d21eSMauro Carvalho Chehab return 0; 204309b6d21eSMauro Carvalho Chehab } 204409b6d21eSMauro Carvalho Chehab 204509b6d21eSMauro Carvalho Chehab static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe) 204609b6d21eSMauro Carvalho Chehab { 204709b6d21eSMauro Carvalho Chehab /* 204809b6d21eSMauro Carvalho Chehab * get_frontend is now handled together with other stats 204909b6d21eSMauro Carvalho Chehab * retrival, when read_status() is called, as some statistics 205009b6d21eSMauro Carvalho Chehab * will depend on the layers detection. 205109b6d21eSMauro Carvalho Chehab */ 205209b6d21eSMauro Carvalho Chehab return 0; 205309b6d21eSMauro Carvalho Chehab }; 205409b6d21eSMauro Carvalho Chehab 20559a0bf528SMauro Carvalho Chehab static int mb86a20s_tune(struct dvb_frontend *fe, 20569a0bf528SMauro Carvalho Chehab bool re_tune, 20579a0bf528SMauro Carvalho Chehab unsigned int mode_flags, 20589a0bf528SMauro Carvalho Chehab unsigned int *delay, 20599a0bf528SMauro Carvalho Chehab fe_status_t *status) 20609a0bf528SMauro Carvalho Chehab { 2061f66d81b5SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 20629a0bf528SMauro Carvalho Chehab int rc = 0; 20639a0bf528SMauro Carvalho Chehab 2064f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 20659a0bf528SMauro Carvalho Chehab 20669a0bf528SMauro Carvalho Chehab if (re_tune) 20679a0bf528SMauro Carvalho Chehab rc = mb86a20s_set_frontend(fe); 20689a0bf528SMauro Carvalho Chehab 20699a0bf528SMauro Carvalho Chehab if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 207009b6d21eSMauro Carvalho Chehab mb86a20s_read_status_and_stats(fe, status); 20719a0bf528SMauro Carvalho Chehab 20729a0bf528SMauro Carvalho Chehab return rc; 20739a0bf528SMauro Carvalho Chehab } 20749a0bf528SMauro Carvalho Chehab 20759a0bf528SMauro Carvalho Chehab static void mb86a20s_release(struct dvb_frontend *fe) 20769a0bf528SMauro Carvalho Chehab { 20779a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 20789a0bf528SMauro Carvalho Chehab 2079f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 20809a0bf528SMauro Carvalho Chehab 20819a0bf528SMauro Carvalho Chehab kfree(state); 20829a0bf528SMauro Carvalho Chehab } 20839a0bf528SMauro Carvalho Chehab 20849a0bf528SMauro Carvalho Chehab static struct dvb_frontend_ops mb86a20s_ops; 20859a0bf528SMauro Carvalho Chehab 20869a0bf528SMauro Carvalho Chehab struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, 20879a0bf528SMauro Carvalho Chehab struct i2c_adapter *i2c) 20889a0bf528SMauro Carvalho Chehab { 2089f66d81b5SMauro Carvalho Chehab struct mb86a20s_state *state; 20909a0bf528SMauro Carvalho Chehab u8 rev; 20919a0bf528SMauro Carvalho Chehab 2092f167e302SMauro Carvalho Chehab dev_dbg(&i2c->dev, "%s called.\n", __func__); 2093f167e302SMauro Carvalho Chehab 20949a0bf528SMauro Carvalho Chehab /* allocate memory for the internal state */ 2095f66d81b5SMauro Carvalho Chehab state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); 20969a0bf528SMauro Carvalho Chehab if (state == NULL) { 2097f167e302SMauro Carvalho Chehab dev_err(&i2c->dev, 2098f66d81b5SMauro Carvalho Chehab "%s: unable to allocate memory for state\n", __func__); 20999a0bf528SMauro Carvalho Chehab goto error; 21009a0bf528SMauro Carvalho Chehab } 21019a0bf528SMauro Carvalho Chehab 21029a0bf528SMauro Carvalho Chehab /* setup the state */ 21039a0bf528SMauro Carvalho Chehab state->config = config; 21049a0bf528SMauro Carvalho Chehab state->i2c = i2c; 21059a0bf528SMauro Carvalho Chehab 21069a0bf528SMauro Carvalho Chehab /* create dvb_frontend */ 21079a0bf528SMauro Carvalho Chehab memcpy(&state->frontend.ops, &mb86a20s_ops, 21089a0bf528SMauro Carvalho Chehab sizeof(struct dvb_frontend_ops)); 21099a0bf528SMauro Carvalho Chehab state->frontend.demodulator_priv = state; 21109a0bf528SMauro Carvalho Chehab 21119a0bf528SMauro Carvalho Chehab /* Check if it is a mb86a20s frontend */ 21129a0bf528SMauro Carvalho Chehab rev = mb86a20s_readreg(state, 0); 21139a0bf528SMauro Carvalho Chehab 21149a0bf528SMauro Carvalho Chehab if (rev == 0x13) { 2115f167e302SMauro Carvalho Chehab dev_info(&i2c->dev, 2116f66d81b5SMauro Carvalho Chehab "Detected a Fujitsu mb86a20s frontend\n"); 21179a0bf528SMauro Carvalho Chehab } else { 2118f167e302SMauro Carvalho Chehab dev_dbg(&i2c->dev, 2119f66d81b5SMauro Carvalho Chehab "Frontend revision %d is unknown - aborting.\n", 21209a0bf528SMauro Carvalho Chehab rev); 21219a0bf528SMauro Carvalho Chehab goto error; 21229a0bf528SMauro Carvalho Chehab } 21239a0bf528SMauro Carvalho Chehab 21249a0bf528SMauro Carvalho Chehab return &state->frontend; 21259a0bf528SMauro Carvalho Chehab 21269a0bf528SMauro Carvalho Chehab error: 21279a0bf528SMauro Carvalho Chehab kfree(state); 21289a0bf528SMauro Carvalho Chehab return NULL; 21299a0bf528SMauro Carvalho Chehab } 21309a0bf528SMauro Carvalho Chehab EXPORT_SYMBOL(mb86a20s_attach); 21319a0bf528SMauro Carvalho Chehab 21329a0bf528SMauro Carvalho Chehab static struct dvb_frontend_ops mb86a20s_ops = { 21339a0bf528SMauro Carvalho Chehab .delsys = { SYS_ISDBT }, 21349a0bf528SMauro Carvalho Chehab /* Use dib8000 values per default */ 21359a0bf528SMauro Carvalho Chehab .info = { 21369a0bf528SMauro Carvalho Chehab .name = "Fujitsu mb86A20s", 213704fa725eSMauro Carvalho Chehab .caps = FE_CAN_RECOVER | 21389a0bf528SMauro Carvalho Chehab FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 21399a0bf528SMauro Carvalho Chehab FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 21409a0bf528SMauro Carvalho Chehab FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 21419a0bf528SMauro Carvalho Chehab FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | 21429a0bf528SMauro Carvalho Chehab FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 21439a0bf528SMauro Carvalho Chehab /* Actually, those values depend on the used tuner */ 21449a0bf528SMauro Carvalho Chehab .frequency_min = 45000000, 21459a0bf528SMauro Carvalho Chehab .frequency_max = 864000000, 21469a0bf528SMauro Carvalho Chehab .frequency_stepsize = 62500, 21479a0bf528SMauro Carvalho Chehab }, 21489a0bf528SMauro Carvalho Chehab 21499a0bf528SMauro Carvalho Chehab .release = mb86a20s_release, 21509a0bf528SMauro Carvalho Chehab 21519a0bf528SMauro Carvalho Chehab .init = mb86a20s_initfe, 21529a0bf528SMauro Carvalho Chehab .set_frontend = mb86a20s_set_frontend, 215309b6d21eSMauro Carvalho Chehab .get_frontend = mb86a20s_get_frontend_dummy, 215409b6d21eSMauro Carvalho Chehab .read_status = mb86a20s_read_status_and_stats, 215509b6d21eSMauro Carvalho Chehab .read_signal_strength = mb86a20s_read_signal_strength_from_cache, 21569a0bf528SMauro Carvalho Chehab .tune = mb86a20s_tune, 21579a0bf528SMauro Carvalho Chehab }; 21589a0bf528SMauro Carvalho Chehab 21599a0bf528SMauro Carvalho Chehab MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); 21609a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 21619a0bf528SMauro Carvalho Chehab MODULE_LICENSE("GPL"); 2162