19a0bf528SMauro Carvalho Chehab /* 29a0bf528SMauro Carvalho Chehab * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver 39a0bf528SMauro Carvalho Chehab * 4a77cfcacSMauro Carvalho Chehab * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com> 59a0bf528SMauro Carvalho Chehab * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> 69a0bf528SMauro Carvalho Chehab * 79a0bf528SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or 89a0bf528SMauro Carvalho Chehab * modify it under the terms of the GNU General Public License as 99a0bf528SMauro Carvalho Chehab * published by the Free Software Foundation version 2. 109a0bf528SMauro Carvalho Chehab * 119a0bf528SMauro Carvalho Chehab * This program is distributed in the hope that it will be useful, 129a0bf528SMauro Carvalho Chehab * but WITHOUT ANY WARRANTY; without even the implied warranty of 139a0bf528SMauro Carvalho Chehab * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 149a0bf528SMauro Carvalho Chehab * General Public License for more details. 159a0bf528SMauro Carvalho Chehab */ 169a0bf528SMauro Carvalho Chehab 179a0bf528SMauro Carvalho Chehab #include <linux/kernel.h> 189a0bf528SMauro Carvalho Chehab #include <asm/div64.h> 199a0bf528SMauro Carvalho Chehab 209a0bf528SMauro Carvalho Chehab #include "dvb_frontend.h" 219a0bf528SMauro Carvalho Chehab #include "mb86a20s.h" 229a0bf528SMauro Carvalho Chehab 239a0bf528SMauro Carvalho Chehab static int debug = 1; 249a0bf528SMauro Carvalho Chehab module_param(debug, int, 0644); 259a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 269a0bf528SMauro Carvalho Chehab 279a0bf528SMauro Carvalho Chehab struct mb86a20s_state { 289a0bf528SMauro Carvalho Chehab struct i2c_adapter *i2c; 299a0bf528SMauro Carvalho Chehab const struct mb86a20s_config *config; 3009b6d21eSMauro Carvalho Chehab u32 last_frequency; 319a0bf528SMauro Carvalho Chehab 329a0bf528SMauro Carvalho Chehab struct dvb_frontend frontend; 339a0bf528SMauro Carvalho Chehab 34768e6dadSMauro Carvalho Chehab u32 if_freq; 35768e6dadSMauro Carvalho Chehab 36d01a8ee3SMauro Carvalho Chehab u32 estimated_rate[3]; 370921ecfdSMauro Carvalho Chehab unsigned long get_strength_time; 38d01a8ee3SMauro Carvalho Chehab 399a0bf528SMauro Carvalho Chehab bool need_init; 409a0bf528SMauro Carvalho Chehab }; 419a0bf528SMauro Carvalho Chehab 429a0bf528SMauro Carvalho Chehab struct regdata { 439a0bf528SMauro Carvalho Chehab u8 reg; 449a0bf528SMauro Carvalho Chehab u8 data; 459a0bf528SMauro Carvalho Chehab }; 469a0bf528SMauro Carvalho Chehab 47d01a8ee3SMauro Carvalho Chehab #define BER_SAMPLING_RATE 1 /* Seconds */ 48d01a8ee3SMauro Carvalho Chehab 499a0bf528SMauro Carvalho Chehab /* 509a0bf528SMauro Carvalho Chehab * Initialization sequence: Use whatevere default values that PV SBTVD 519a0bf528SMauro Carvalho Chehab * does on its initialisation, obtained via USB snoop 529a0bf528SMauro Carvalho Chehab */ 53768e6dadSMauro Carvalho Chehab static struct regdata mb86a20s_init1[] = { 549a0bf528SMauro Carvalho Chehab { 0x70, 0x0f }, 559a0bf528SMauro Carvalho Chehab { 0x70, 0xff }, 569a0bf528SMauro Carvalho Chehab { 0x08, 0x01 }, 579a0bf528SMauro Carvalho Chehab { 0x09, 0x3e }, 589a0bf528SMauro Carvalho Chehab { 0x50, 0xd1 }, { 0x51, 0x22 }, 599a0bf528SMauro Carvalho Chehab { 0x39, 0x01 }, 609a0bf528SMauro Carvalho Chehab { 0x71, 0x00 }, 619a0bf528SMauro Carvalho Chehab { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 }, 62768e6dadSMauro Carvalho Chehab }; 63768e6dadSMauro Carvalho Chehab 64768e6dadSMauro Carvalho Chehab static struct regdata mb86a20s_init2[] = { 659a0bf528SMauro Carvalho Chehab { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, 669a0bf528SMauro Carvalho Chehab { 0x3b, 0x21 }, 679a0bf528SMauro Carvalho Chehab { 0x3c, 0x3a }, 689a0bf528SMauro Carvalho Chehab { 0x01, 0x0d }, 699a0bf528SMauro Carvalho Chehab { 0x04, 0x08 }, { 0x05, 0x05 }, 709a0bf528SMauro Carvalho Chehab { 0x04, 0x0e }, { 0x05, 0x00 }, 719a0bf528SMauro Carvalho Chehab { 0x04, 0x0f }, { 0x05, 0x14 }, 729a0bf528SMauro Carvalho Chehab { 0x04, 0x0b }, { 0x05, 0x8c }, 739a0bf528SMauro Carvalho Chehab { 0x04, 0x00 }, { 0x05, 0x00 }, 749a0bf528SMauro Carvalho Chehab { 0x04, 0x01 }, { 0x05, 0x07 }, 759a0bf528SMauro Carvalho Chehab { 0x04, 0x02 }, { 0x05, 0x0f }, 769a0bf528SMauro Carvalho Chehab { 0x04, 0x03 }, { 0x05, 0xa0 }, 779a0bf528SMauro Carvalho Chehab { 0x04, 0x09 }, { 0x05, 0x00 }, 789a0bf528SMauro Carvalho Chehab { 0x04, 0x0a }, { 0x05, 0xff }, 799a0bf528SMauro Carvalho Chehab { 0x04, 0x27 }, { 0x05, 0x64 }, 809a0bf528SMauro Carvalho Chehab { 0x04, 0x28 }, { 0x05, 0x00 }, 819a0bf528SMauro Carvalho Chehab { 0x04, 0x1e }, { 0x05, 0xff }, 829a0bf528SMauro Carvalho Chehab { 0x04, 0x29 }, { 0x05, 0x0a }, 839a0bf528SMauro Carvalho Chehab { 0x04, 0x32 }, { 0x05, 0x0a }, 849a0bf528SMauro Carvalho Chehab { 0x04, 0x14 }, { 0x05, 0x02 }, 859a0bf528SMauro Carvalho Chehab { 0x04, 0x04 }, { 0x05, 0x00 }, 869a0bf528SMauro Carvalho Chehab { 0x04, 0x05 }, { 0x05, 0x22 }, 879a0bf528SMauro Carvalho Chehab { 0x04, 0x06 }, { 0x05, 0x0e }, 889a0bf528SMauro Carvalho Chehab { 0x04, 0x07 }, { 0x05, 0xd8 }, 899a0bf528SMauro Carvalho Chehab { 0x04, 0x12 }, { 0x05, 0x00 }, 909a0bf528SMauro Carvalho Chehab { 0x04, 0x13 }, { 0x05, 0xff }, 919a0bf528SMauro Carvalho Chehab { 0x04, 0x15 }, { 0x05, 0x4e }, 929a0bf528SMauro Carvalho Chehab { 0x04, 0x16 }, { 0x05, 0x20 }, 9309b6d21eSMauro Carvalho Chehab 9409b6d21eSMauro Carvalho Chehab /* 9509b6d21eSMauro Carvalho Chehab * On this demod, when the bit count reaches the count below, 9609b6d21eSMauro Carvalho Chehab * it collects the bit error count. The bit counters are initialized 9709b6d21eSMauro Carvalho Chehab * to 65535 here. This warrants that all of them will be quickly 9809b6d21eSMauro Carvalho Chehab * calculated when device gets locked. As TMCC is parsed, the values 99d01a8ee3SMauro Carvalho Chehab * will be adjusted later in the driver's code. 10009b6d21eSMauro Carvalho Chehab */ 10109b6d21eSMauro Carvalho Chehab { 0x52, 0x01 }, /* Turn on BER before Viterbi */ 10209b6d21eSMauro Carvalho Chehab { 0x50, 0xa7 }, { 0x51, 0x00 }, 1039a0bf528SMauro Carvalho Chehab { 0x50, 0xa8 }, { 0x51, 0xff }, 1049a0bf528SMauro Carvalho Chehab { 0x50, 0xa9 }, { 0x51, 0xff }, 10509b6d21eSMauro Carvalho Chehab { 0x50, 0xaa }, { 0x51, 0x00 }, 1069a0bf528SMauro Carvalho Chehab { 0x50, 0xab }, { 0x51, 0xff }, 1079a0bf528SMauro Carvalho Chehab { 0x50, 0xac }, { 0x51, 0xff }, 10809b6d21eSMauro Carvalho Chehab { 0x50, 0xad }, { 0x51, 0x00 }, 1099a0bf528SMauro Carvalho Chehab { 0x50, 0xae }, { 0x51, 0xff }, 1109a0bf528SMauro Carvalho Chehab { 0x50, 0xaf }, { 0x51, 0xff }, 11109b6d21eSMauro Carvalho Chehab 112d9b6f08aSMauro Carvalho Chehab /* 113d9b6f08aSMauro Carvalho Chehab * On this demod, post BER counts blocks. When the count reaches the 114d9b6f08aSMauro Carvalho Chehab * value below, it collects the block error count. The block counters 115d9b6f08aSMauro Carvalho Chehab * are initialized to 127 here. This warrants that all of them will be 116d9b6f08aSMauro Carvalho Chehab * quickly calculated when device gets locked. As TMCC is parsed, the 117d9b6f08aSMauro Carvalho Chehab * values will be adjusted later in the driver's code. 118d9b6f08aSMauro Carvalho Chehab */ 119d9b6f08aSMauro Carvalho Chehab { 0x5e, 0x07 }, /* Turn on BER after Viterbi */ 120d9b6f08aSMauro Carvalho Chehab { 0x50, 0xdc }, { 0x51, 0x00 }, 121d9b6f08aSMauro Carvalho Chehab { 0x50, 0xdd }, { 0x51, 0x7f }, 122d9b6f08aSMauro Carvalho Chehab { 0x50, 0xde }, { 0x51, 0x00 }, 123d9b6f08aSMauro Carvalho Chehab { 0x50, 0xdf }, { 0x51, 0x7f }, 124d9b6f08aSMauro Carvalho Chehab { 0x50, 0xe0 }, { 0x51, 0x00 }, 125d9b6f08aSMauro Carvalho Chehab { 0x50, 0xe1 }, { 0x51, 0x7f }, 126593ae89aSMauro Carvalho Chehab 127593ae89aSMauro Carvalho Chehab /* 128593ae89aSMauro Carvalho Chehab * On this demod, when the block count reaches the count below, 129593ae89aSMauro Carvalho Chehab * it collects the block error count. The block counters are initialized 130593ae89aSMauro Carvalho Chehab * to 127 here. This warrants that all of them will be quickly 131593ae89aSMauro Carvalho Chehab * calculated when device gets locked. As TMCC is parsed, the values 132593ae89aSMauro Carvalho Chehab * will be adjusted later in the driver's code. 133593ae89aSMauro Carvalho Chehab */ 134593ae89aSMauro Carvalho Chehab { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */ 135593ae89aSMauro Carvalho Chehab { 0x50, 0xb2 }, { 0x51, 0x00 }, 136593ae89aSMauro Carvalho Chehab { 0x50, 0xb3 }, { 0x51, 0x7f }, 137593ae89aSMauro Carvalho Chehab { 0x50, 0xb4 }, { 0x51, 0x00 }, 138593ae89aSMauro Carvalho Chehab { 0x50, 0xb5 }, { 0x51, 0x7f }, 139593ae89aSMauro Carvalho Chehab { 0x50, 0xb6 }, { 0x51, 0x00 }, 140593ae89aSMauro Carvalho Chehab { 0x50, 0xb7 }, { 0x51, 0x7f }, 14125188bd0SMauro Carvalho Chehab 14225188bd0SMauro Carvalho Chehab { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */ 14309b6d21eSMauro Carvalho Chehab { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ 14409b6d21eSMauro Carvalho Chehab { 0x45, 0x04 }, /* CN symbol 4 */ 14525188bd0SMauro Carvalho Chehab { 0x48, 0x04 }, /* CN manual mode */ 14625188bd0SMauro Carvalho Chehab 1479a0bf528SMauro Carvalho Chehab { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */ 1489a0bf528SMauro Carvalho Chehab { 0x50, 0xd6 }, { 0x51, 0x1f }, 1499a0bf528SMauro Carvalho Chehab { 0x50, 0xd2 }, { 0x51, 0x03 }, 1509a0bf528SMauro Carvalho Chehab { 0x50, 0xd7 }, { 0x51, 0x3f }, 1519a0bf528SMauro Carvalho Chehab { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 }, 1529a0bf528SMauro Carvalho Chehab { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c }, 153ce77d120SMauro Carvalho Chehab 154ce77d120SMauro Carvalho Chehab { 0x04, 0x40 }, { 0x05, 0x00 }, 1559a0bf528SMauro Carvalho Chehab { 0x28, 0x00 }, { 0x29, 0x10 }, 1569a0bf528SMauro Carvalho Chehab { 0x28, 0x05 }, { 0x29, 0x02 }, 1579a0bf528SMauro Carvalho Chehab { 0x1c, 0x01 }, 1589a0bf528SMauro Carvalho Chehab { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 }, 1599a0bf528SMauro Carvalho Chehab { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d }, 1609a0bf528SMauro Carvalho Chehab { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, 1619a0bf528SMauro Carvalho Chehab { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 }, 1629a0bf528SMauro Carvalho Chehab { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 }, 1639a0bf528SMauro Carvalho Chehab { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 }, 1649a0bf528SMauro Carvalho Chehab { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, 1659a0bf528SMauro Carvalho Chehab { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 }, 1669a0bf528SMauro Carvalho Chehab { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e }, 1679a0bf528SMauro Carvalho Chehab { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e }, 1689a0bf528SMauro Carvalho Chehab { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 }, 1699a0bf528SMauro Carvalho Chehab { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, 1709a0bf528SMauro Carvalho Chehab { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 }, 1719a0bf528SMauro Carvalho Chehab { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 }, 1729a0bf528SMauro Carvalho Chehab { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe }, 1739a0bf528SMauro Carvalho Chehab { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 }, 1749a0bf528SMauro Carvalho Chehab { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee }, 1759a0bf528SMauro Carvalho Chehab { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 }, 1769a0bf528SMauro Carvalho Chehab { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f }, 1779a0bf528SMauro Carvalho Chehab { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 }, 1789a0bf528SMauro Carvalho Chehab { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 }, 1799a0bf528SMauro Carvalho Chehab { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a }, 1809a0bf528SMauro Carvalho Chehab { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc }, 1819a0bf528SMauro Carvalho Chehab { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba }, 1829a0bf528SMauro Carvalho Chehab { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 }, 1839a0bf528SMauro Carvalho Chehab { 0x50, 0x1e }, { 0x51, 0x5d }, 1849a0bf528SMauro Carvalho Chehab { 0x50, 0x22 }, { 0x51, 0x00 }, 1859a0bf528SMauro Carvalho Chehab { 0x50, 0x23 }, { 0x51, 0xc8 }, 1869a0bf528SMauro Carvalho Chehab { 0x50, 0x24 }, { 0x51, 0x00 }, 1879a0bf528SMauro Carvalho Chehab { 0x50, 0x25 }, { 0x51, 0xf0 }, 1889a0bf528SMauro Carvalho Chehab { 0x50, 0x26 }, { 0x51, 0x00 }, 1899a0bf528SMauro Carvalho Chehab { 0x50, 0x27 }, { 0x51, 0xc3 }, 1909a0bf528SMauro Carvalho Chehab { 0x50, 0x39 }, { 0x51, 0x02 }, 1919a0bf528SMauro Carvalho Chehab { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, 1929a0bf528SMauro Carvalho Chehab { 0xd0, 0x00 }, 1939a0bf528SMauro Carvalho Chehab }; 1949a0bf528SMauro Carvalho Chehab 1959a0bf528SMauro Carvalho Chehab static struct regdata mb86a20s_reset_reception[] = { 1969a0bf528SMauro Carvalho Chehab { 0x70, 0xf0 }, 1979a0bf528SMauro Carvalho Chehab { 0x70, 0xff }, 1989a0bf528SMauro Carvalho Chehab { 0x08, 0x01 }, 1999a0bf528SMauro Carvalho Chehab { 0x08, 0x00 }, 2009a0bf528SMauro Carvalho Chehab }; 2019a0bf528SMauro Carvalho Chehab 202d9b6f08aSMauro Carvalho Chehab static struct regdata mb86a20s_per_ber_reset[] = { 203d9b6f08aSMauro Carvalho Chehab { 0x53, 0x00 }, /* pre BER Counter reset */ 20409b6d21eSMauro Carvalho Chehab { 0x53, 0x07 }, 20509b6d21eSMauro Carvalho Chehab 206d9b6f08aSMauro Carvalho Chehab { 0x5f, 0x00 }, /* post BER Counter reset */ 207d9b6f08aSMauro Carvalho Chehab { 0x5f, 0x07 }, 208d9b6f08aSMauro Carvalho Chehab 20909b6d21eSMauro Carvalho Chehab { 0x50, 0xb1 }, /* PER Counter reset */ 21009b6d21eSMauro Carvalho Chehab { 0x51, 0x07 }, 21109b6d21eSMauro Carvalho Chehab { 0x51, 0x00 }, 21209b6d21eSMauro Carvalho Chehab }; 21309b6d21eSMauro Carvalho Chehab 214dd4493efSMauro Carvalho Chehab /* 215dd4493efSMauro Carvalho Chehab * I2C read/write functions and macros 216dd4493efSMauro Carvalho Chehab */ 217dd4493efSMauro Carvalho Chehab 2189a0bf528SMauro Carvalho Chehab static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, 21909b6d21eSMauro Carvalho Chehab u8 i2c_addr, u8 reg, u8 data) 2209a0bf528SMauro Carvalho Chehab { 2219a0bf528SMauro Carvalho Chehab u8 buf[] = { reg, data }; 2229a0bf528SMauro Carvalho Chehab struct i2c_msg msg = { 2239a0bf528SMauro Carvalho Chehab .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 2249a0bf528SMauro Carvalho Chehab }; 2259a0bf528SMauro Carvalho Chehab int rc; 2269a0bf528SMauro Carvalho Chehab 2279a0bf528SMauro Carvalho Chehab rc = i2c_transfer(state->i2c, &msg, 1); 2289a0bf528SMauro Carvalho Chehab if (rc != 1) { 229f66d81b5SMauro Carvalho Chehab dev_err(&state->i2c->dev, 230f66d81b5SMauro Carvalho Chehab "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", 231f66d81b5SMauro Carvalho Chehab __func__, rc, reg, data); 2329a0bf528SMauro Carvalho Chehab return rc; 2339a0bf528SMauro Carvalho Chehab } 2349a0bf528SMauro Carvalho Chehab 2359a0bf528SMauro Carvalho Chehab return 0; 2369a0bf528SMauro Carvalho Chehab } 2379a0bf528SMauro Carvalho Chehab 2389a0bf528SMauro Carvalho Chehab static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, 2399a0bf528SMauro Carvalho Chehab u8 i2c_addr, struct regdata *rd, int size) 2409a0bf528SMauro Carvalho Chehab { 2419a0bf528SMauro Carvalho Chehab int i, rc; 2429a0bf528SMauro Carvalho Chehab 2439a0bf528SMauro Carvalho Chehab for (i = 0; i < size; i++) { 2449a0bf528SMauro Carvalho Chehab rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, 2459a0bf528SMauro Carvalho Chehab rd[i].data); 2469a0bf528SMauro Carvalho Chehab if (rc < 0) 2479a0bf528SMauro Carvalho Chehab return rc; 2489a0bf528SMauro Carvalho Chehab } 2499a0bf528SMauro Carvalho Chehab return 0; 2509a0bf528SMauro Carvalho Chehab } 2519a0bf528SMauro Carvalho Chehab 2529a0bf528SMauro Carvalho Chehab static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, 2539a0bf528SMauro Carvalho Chehab u8 i2c_addr, u8 reg) 2549a0bf528SMauro Carvalho Chehab { 2559a0bf528SMauro Carvalho Chehab u8 val; 2569a0bf528SMauro Carvalho Chehab int rc; 2579a0bf528SMauro Carvalho Chehab struct i2c_msg msg[] = { 2589a0bf528SMauro Carvalho Chehab { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, 2599a0bf528SMauro Carvalho Chehab { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } 2609a0bf528SMauro Carvalho Chehab }; 2619a0bf528SMauro Carvalho Chehab 2629a0bf528SMauro Carvalho Chehab rc = i2c_transfer(state->i2c, msg, 2); 2639a0bf528SMauro Carvalho Chehab 2649a0bf528SMauro Carvalho Chehab if (rc != 2) { 265f66d81b5SMauro Carvalho Chehab dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", 266f66d81b5SMauro Carvalho Chehab __func__, reg, rc); 267f66d81b5SMauro Carvalho Chehab return (rc < 0) ? rc : -EIO; 2689a0bf528SMauro Carvalho Chehab } 2699a0bf528SMauro Carvalho Chehab 2709a0bf528SMauro Carvalho Chehab return val; 2719a0bf528SMauro Carvalho Chehab } 2729a0bf528SMauro Carvalho Chehab 2739a0bf528SMauro Carvalho Chehab #define mb86a20s_readreg(state, reg) \ 2749a0bf528SMauro Carvalho Chehab mb86a20s_i2c_readreg(state, state->config->demod_address, reg) 2759a0bf528SMauro Carvalho Chehab #define mb86a20s_writereg(state, reg, val) \ 2769a0bf528SMauro Carvalho Chehab mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) 2779a0bf528SMauro Carvalho Chehab #define mb86a20s_writeregdata(state, regdata) \ 2789a0bf528SMauro Carvalho Chehab mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ 2799a0bf528SMauro Carvalho Chehab regdata, ARRAY_SIZE(regdata)) 2809a0bf528SMauro Carvalho Chehab 28109b6d21eSMauro Carvalho Chehab /* 28209b6d21eSMauro Carvalho Chehab * Ancillary internal routines (likely compiled inlined) 28309b6d21eSMauro Carvalho Chehab * 28409b6d21eSMauro Carvalho Chehab * The functions below assume that gateway lock has already obtained 28509b6d21eSMauro Carvalho Chehab */ 28609b6d21eSMauro Carvalho Chehab 287dd4493efSMauro Carvalho Chehab static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status) 2889a0bf528SMauro Carvalho Chehab { 2899a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 290dd4493efSMauro Carvalho Chehab int val; 2919a0bf528SMauro Carvalho Chehab 292dd4493efSMauro Carvalho Chehab *status = 0; 2939a0bf528SMauro Carvalho Chehab 294dd4493efSMauro Carvalho Chehab val = mb86a20s_readreg(state, 0x0a) & 0xf; 295dd4493efSMauro Carvalho Chehab if (val < 0) 296dd4493efSMauro Carvalho Chehab return val; 2979a0bf528SMauro Carvalho Chehab 298dd4493efSMauro Carvalho Chehab if (val >= 2) 299dd4493efSMauro Carvalho Chehab *status |= FE_HAS_SIGNAL; 3009a0bf528SMauro Carvalho Chehab 301dd4493efSMauro Carvalho Chehab if (val >= 4) 302dd4493efSMauro Carvalho Chehab *status |= FE_HAS_CARRIER; 3039a0bf528SMauro Carvalho Chehab 304dd4493efSMauro Carvalho Chehab if (val >= 5) 305dd4493efSMauro Carvalho Chehab *status |= FE_HAS_VITERBI; 3069a0bf528SMauro Carvalho Chehab 307dd4493efSMauro Carvalho Chehab if (val >= 7) 308dd4493efSMauro Carvalho Chehab *status |= FE_HAS_SYNC; 3099a0bf528SMauro Carvalho Chehab 310dd4493efSMauro Carvalho Chehab if (val >= 8) /* Maybe 9? */ 311dd4493efSMauro Carvalho Chehab *status |= FE_HAS_LOCK; 312dd4493efSMauro Carvalho Chehab 313f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", 314f66d81b5SMauro Carvalho Chehab __func__, *status, val); 315dd4493efSMauro Carvalho Chehab 31615b1c5a0SMauro Carvalho Chehab return val; 3179a0bf528SMauro Carvalho Chehab } 3189a0bf528SMauro Carvalho Chehab 31909b6d21eSMauro Carvalho Chehab static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) 3209a0bf528SMauro Carvalho Chehab { 3219a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 3220921ecfdSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 32309b6d21eSMauro Carvalho Chehab int rc; 3249a0bf528SMauro Carvalho Chehab unsigned rf_max, rf_min, rf; 3259a0bf528SMauro Carvalho Chehab 3260921ecfdSMauro Carvalho Chehab if (state->get_strength_time && 3270921ecfdSMauro Carvalho Chehab (!time_after(jiffies, state->get_strength_time))) 3280921ecfdSMauro Carvalho Chehab return c->strength.stat[0].uvalue; 3290921ecfdSMauro Carvalho Chehab 3300921ecfdSMauro Carvalho Chehab /* Reset its value if an error happen */ 3310921ecfdSMauro Carvalho Chehab c->strength.stat[0].uvalue = 0; 3320921ecfdSMauro Carvalho Chehab 3339a0bf528SMauro Carvalho Chehab /* Does a binary search to get RF strength */ 3349a0bf528SMauro Carvalho Chehab rf_max = 0xfff; 3359a0bf528SMauro Carvalho Chehab rf_min = 0; 3369a0bf528SMauro Carvalho Chehab do { 3379a0bf528SMauro Carvalho Chehab rf = (rf_max + rf_min) / 2; 33809b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x04, 0x1f); 33909b6d21eSMauro Carvalho Chehab if (rc < 0) 34009b6d21eSMauro Carvalho Chehab return rc; 34109b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x05, rf >> 8); 34209b6d21eSMauro Carvalho Chehab if (rc < 0) 34309b6d21eSMauro Carvalho Chehab return rc; 34409b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x04, 0x20); 34509b6d21eSMauro Carvalho Chehab if (rc < 0) 34609b6d21eSMauro Carvalho Chehab return rc; 347dad78c56SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x05, rf); 34809b6d21eSMauro Carvalho Chehab if (rc < 0) 34909b6d21eSMauro Carvalho Chehab return rc; 3509a0bf528SMauro Carvalho Chehab 35109b6d21eSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x02); 35209b6d21eSMauro Carvalho Chehab if (rc < 0) 35309b6d21eSMauro Carvalho Chehab return rc; 35409b6d21eSMauro Carvalho Chehab if (rc & 0x08) 3559a0bf528SMauro Carvalho Chehab rf_min = (rf_max + rf_min) / 2; 3569a0bf528SMauro Carvalho Chehab else 3579a0bf528SMauro Carvalho Chehab rf_max = (rf_max + rf_min) / 2; 3589a0bf528SMauro Carvalho Chehab if (rf_max - rf_min < 4) { 35909b6d21eSMauro Carvalho Chehab rf = (rf_max + rf_min) / 2; 36009b6d21eSMauro Carvalho Chehab 36109b6d21eSMauro Carvalho Chehab /* Rescale it from 2^12 (4096) to 2^16 */ 3620921ecfdSMauro Carvalho Chehab rf = rf << (16 - 12); 3630921ecfdSMauro Carvalho Chehab if (rf) 3640921ecfdSMauro Carvalho Chehab rf |= (1 << 12) - 1; 3650921ecfdSMauro Carvalho Chehab 366f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 367f66d81b5SMauro Carvalho Chehab "%s: signal strength = %d (%d < RF=%d < %d)\n", 368f66d81b5SMauro Carvalho Chehab __func__, rf, rf_min, rf >> 4, rf_max); 3690921ecfdSMauro Carvalho Chehab c->strength.stat[0].uvalue = rf; 3700921ecfdSMauro Carvalho Chehab state->get_strength_time = jiffies + 3710921ecfdSMauro Carvalho Chehab msecs_to_jiffies(1000); 3720921ecfdSMauro Carvalho Chehab return 0; 3739a0bf528SMauro Carvalho Chehab } 3749a0bf528SMauro Carvalho Chehab } while (1); 3759a0bf528SMauro Carvalho Chehab } 3769a0bf528SMauro Carvalho Chehab 3779a0bf528SMauro Carvalho Chehab static int mb86a20s_get_modulation(struct mb86a20s_state *state, 3789a0bf528SMauro Carvalho Chehab unsigned layer) 3799a0bf528SMauro Carvalho Chehab { 3809a0bf528SMauro Carvalho Chehab int rc; 3819a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 3829a0bf528SMauro Carvalho Chehab [0] = 0x86, /* Layer A */ 3839a0bf528SMauro Carvalho Chehab [1] = 0x8a, /* Layer B */ 3849a0bf528SMauro Carvalho Chehab [2] = 0x8e, /* Layer C */ 3859a0bf528SMauro Carvalho Chehab }; 3869a0bf528SMauro Carvalho Chehab 3879a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 3889a0bf528SMauro Carvalho Chehab return -EINVAL; 3899a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 3909a0bf528SMauro Carvalho Chehab if (rc < 0) 3919a0bf528SMauro Carvalho Chehab return rc; 3929a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 3939a0bf528SMauro Carvalho Chehab if (rc < 0) 3949a0bf528SMauro Carvalho Chehab return rc; 39504585921SMauro Carvalho Chehab switch ((rc >> 4) & 0x07) { 3969a0bf528SMauro Carvalho Chehab case 0: 3979a0bf528SMauro Carvalho Chehab return DQPSK; 3989a0bf528SMauro Carvalho Chehab case 1: 3999a0bf528SMauro Carvalho Chehab return QPSK; 4009a0bf528SMauro Carvalho Chehab case 2: 4019a0bf528SMauro Carvalho Chehab return QAM_16; 4029a0bf528SMauro Carvalho Chehab case 3: 4039a0bf528SMauro Carvalho Chehab return QAM_64; 4049a0bf528SMauro Carvalho Chehab default: 4059a0bf528SMauro Carvalho Chehab return QAM_AUTO; 4069a0bf528SMauro Carvalho Chehab } 4079a0bf528SMauro Carvalho Chehab } 4089a0bf528SMauro Carvalho Chehab 4099a0bf528SMauro Carvalho Chehab static int mb86a20s_get_fec(struct mb86a20s_state *state, 4109a0bf528SMauro Carvalho Chehab unsigned layer) 4119a0bf528SMauro Carvalho Chehab { 4129a0bf528SMauro Carvalho Chehab int rc; 4139a0bf528SMauro Carvalho Chehab 4149a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 4159a0bf528SMauro Carvalho Chehab [0] = 0x87, /* Layer A */ 4169a0bf528SMauro Carvalho Chehab [1] = 0x8b, /* Layer B */ 4179a0bf528SMauro Carvalho Chehab [2] = 0x8f, /* Layer C */ 4189a0bf528SMauro Carvalho Chehab }; 4199a0bf528SMauro Carvalho Chehab 4209a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 4219a0bf528SMauro Carvalho Chehab return -EINVAL; 4229a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 4239a0bf528SMauro Carvalho Chehab if (rc < 0) 4249a0bf528SMauro Carvalho Chehab return rc; 4259a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 4269a0bf528SMauro Carvalho Chehab if (rc < 0) 4279a0bf528SMauro Carvalho Chehab return rc; 42804585921SMauro Carvalho Chehab switch ((rc >> 4) & 0x07) { 4299a0bf528SMauro Carvalho Chehab case 0: 4309a0bf528SMauro Carvalho Chehab return FEC_1_2; 4319a0bf528SMauro Carvalho Chehab case 1: 4329a0bf528SMauro Carvalho Chehab return FEC_2_3; 4339a0bf528SMauro Carvalho Chehab case 2: 4349a0bf528SMauro Carvalho Chehab return FEC_3_4; 4359a0bf528SMauro Carvalho Chehab case 3: 4369a0bf528SMauro Carvalho Chehab return FEC_5_6; 4379a0bf528SMauro Carvalho Chehab case 4: 4389a0bf528SMauro Carvalho Chehab return FEC_7_8; 4399a0bf528SMauro Carvalho Chehab default: 4409a0bf528SMauro Carvalho Chehab return FEC_AUTO; 4419a0bf528SMauro Carvalho Chehab } 4429a0bf528SMauro Carvalho Chehab } 4439a0bf528SMauro Carvalho Chehab 4449a0bf528SMauro Carvalho Chehab static int mb86a20s_get_interleaving(struct mb86a20s_state *state, 4459a0bf528SMauro Carvalho Chehab unsigned layer) 4469a0bf528SMauro Carvalho Chehab { 4479a0bf528SMauro Carvalho Chehab int rc; 4489a0bf528SMauro Carvalho Chehab 4499a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 4509a0bf528SMauro Carvalho Chehab [0] = 0x88, /* Layer A */ 4519a0bf528SMauro Carvalho Chehab [1] = 0x8c, /* Layer B */ 4529a0bf528SMauro Carvalho Chehab [2] = 0x90, /* Layer C */ 4539a0bf528SMauro Carvalho Chehab }; 4549a0bf528SMauro Carvalho Chehab 4559a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 4569a0bf528SMauro Carvalho Chehab return -EINVAL; 4579a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 4589a0bf528SMauro Carvalho Chehab if (rc < 0) 4599a0bf528SMauro Carvalho Chehab return rc; 4609a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 4619a0bf528SMauro Carvalho Chehab if (rc < 0) 4629a0bf528SMauro Carvalho Chehab return rc; 46304585921SMauro Carvalho Chehab 46404585921SMauro Carvalho Chehab switch ((rc >> 4) & 0x07) { 46504585921SMauro Carvalho Chehab case 1: 46604585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_4; 46704585921SMauro Carvalho Chehab case 2: 46804585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_8; 46904585921SMauro Carvalho Chehab case 3: 47004585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_16; 47104585921SMauro Carvalho Chehab case 4: 47204585921SMauro Carvalho Chehab return GUARD_INTERVAL_1_32; 47304585921SMauro Carvalho Chehab 47404585921SMauro Carvalho Chehab default: 47504585921SMauro Carvalho Chehab case 0: 47604585921SMauro Carvalho Chehab return GUARD_INTERVAL_AUTO; 47704585921SMauro Carvalho Chehab } 4789a0bf528SMauro Carvalho Chehab } 4799a0bf528SMauro Carvalho Chehab 4809a0bf528SMauro Carvalho Chehab static int mb86a20s_get_segment_count(struct mb86a20s_state *state, 4819a0bf528SMauro Carvalho Chehab unsigned layer) 4829a0bf528SMauro Carvalho Chehab { 4839a0bf528SMauro Carvalho Chehab int rc, count; 4849a0bf528SMauro Carvalho Chehab static unsigned char reg[] = { 4859a0bf528SMauro Carvalho Chehab [0] = 0x89, /* Layer A */ 4869a0bf528SMauro Carvalho Chehab [1] = 0x8d, /* Layer B */ 4879a0bf528SMauro Carvalho Chehab [2] = 0x91, /* Layer C */ 4889a0bf528SMauro Carvalho Chehab }; 4899a0bf528SMauro Carvalho Chehab 490f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 491f66d81b5SMauro Carvalho Chehab 4929a0bf528SMauro Carvalho Chehab if (layer >= ARRAY_SIZE(reg)) 4939a0bf528SMauro Carvalho Chehab return -EINVAL; 494f66d81b5SMauro Carvalho Chehab 4959a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, reg[layer]); 4969a0bf528SMauro Carvalho Chehab if (rc < 0) 4979a0bf528SMauro Carvalho Chehab return rc; 4989a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 4999a0bf528SMauro Carvalho Chehab if (rc < 0) 5009a0bf528SMauro Carvalho Chehab return rc; 5019a0bf528SMauro Carvalho Chehab count = (rc >> 4) & 0x0f; 5029a0bf528SMauro Carvalho Chehab 503f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); 504f66d81b5SMauro Carvalho Chehab 5059a0bf528SMauro Carvalho Chehab return count; 5069a0bf528SMauro Carvalho Chehab } 5079a0bf528SMauro Carvalho Chehab 508a77cfcacSMauro Carvalho Chehab static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) 509a77cfcacSMauro Carvalho Chehab { 510f66d81b5SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 511a77cfcacSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 512a77cfcacSMauro Carvalho Chehab 513f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 514f66d81b5SMauro Carvalho Chehab 515a77cfcacSMauro Carvalho Chehab /* Fixed parameters */ 516a77cfcacSMauro Carvalho Chehab c->delivery_system = SYS_ISDBT; 517a77cfcacSMauro Carvalho Chehab c->bandwidth_hz = 6000000; 518a77cfcacSMauro Carvalho Chehab 519a77cfcacSMauro Carvalho Chehab /* Initialize values that will be later autodetected */ 520a77cfcacSMauro Carvalho Chehab c->isdbt_layer_enabled = 0; 521a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_AUTO; 522a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_AUTO; 523a77cfcacSMauro Carvalho Chehab c->isdbt_sb_mode = 0; 524a77cfcacSMauro Carvalho Chehab c->isdbt_sb_segment_count = 0; 525a77cfcacSMauro Carvalho Chehab } 526a77cfcacSMauro Carvalho Chehab 527d01a8ee3SMauro Carvalho Chehab /* 528d01a8ee3SMauro Carvalho Chehab * Estimates the bit rate using the per-segment bit rate given by 529d01a8ee3SMauro Carvalho Chehab * ABNT/NBR 15601 spec (table 4). 530d01a8ee3SMauro Carvalho Chehab */ 531d01a8ee3SMauro Carvalho Chehab static u32 isdbt_rate[3][5][4] = { 532d01a8ee3SMauro Carvalho Chehab { /* DQPSK/QPSK */ 533d01a8ee3SMauro Carvalho Chehab { 280850, 312060, 330420, 340430 }, /* 1/2 */ 534d01a8ee3SMauro Carvalho Chehab { 374470, 416080, 440560, 453910 }, /* 2/3 */ 535d01a8ee3SMauro Carvalho Chehab { 421280, 468090, 495630, 510650 }, /* 3/4 */ 536d01a8ee3SMauro Carvalho Chehab { 468090, 520100, 550700, 567390 }, /* 5/6 */ 537d01a8ee3SMauro Carvalho Chehab { 491500, 546110, 578230, 595760 }, /* 7/8 */ 538d01a8ee3SMauro Carvalho Chehab }, { /* QAM16 */ 539d01a8ee3SMauro Carvalho Chehab { 561710, 624130, 660840, 680870 }, /* 1/2 */ 540d01a8ee3SMauro Carvalho Chehab { 748950, 832170, 881120, 907820 }, /* 2/3 */ 541d01a8ee3SMauro Carvalho Chehab { 842570, 936190, 991260, 1021300 }, /* 3/4 */ 542d01a8ee3SMauro Carvalho Chehab { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ 543d01a8ee3SMauro Carvalho Chehab { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ 544d01a8ee3SMauro Carvalho Chehab }, { /* QAM64 */ 545d01a8ee3SMauro Carvalho Chehab { 842570, 936190, 991260, 1021300 }, /* 1/2 */ 546d01a8ee3SMauro Carvalho Chehab { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ 547d01a8ee3SMauro Carvalho Chehab { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ 548d01a8ee3SMauro Carvalho Chehab { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ 549d01a8ee3SMauro Carvalho Chehab { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ 550d01a8ee3SMauro Carvalho Chehab } 551d01a8ee3SMauro Carvalho Chehab }; 552d01a8ee3SMauro Carvalho Chehab 553d01a8ee3SMauro Carvalho Chehab static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, 554d01a8ee3SMauro Carvalho Chehab u32 modulation, u32 fec, u32 interleaving, 555d01a8ee3SMauro Carvalho Chehab u32 segment) 556d01a8ee3SMauro Carvalho Chehab { 557d01a8ee3SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 558d01a8ee3SMauro Carvalho Chehab u32 rate; 559d01a8ee3SMauro Carvalho Chehab int m, f, i; 560d01a8ee3SMauro Carvalho Chehab 561d01a8ee3SMauro Carvalho Chehab /* 562d01a8ee3SMauro Carvalho Chehab * If modulation/fec/interleaving is not detected, the default is 563d01a8ee3SMauro Carvalho Chehab * to consider the lowest bit rate, to avoid taking too long time 564d01a8ee3SMauro Carvalho Chehab * to get BER. 565d01a8ee3SMauro Carvalho Chehab */ 566d01a8ee3SMauro Carvalho Chehab switch (modulation) { 567d01a8ee3SMauro Carvalho Chehab case DQPSK: 568d01a8ee3SMauro Carvalho Chehab case QPSK: 569d01a8ee3SMauro Carvalho Chehab default: 570d01a8ee3SMauro Carvalho Chehab m = 0; 571d01a8ee3SMauro Carvalho Chehab break; 572d01a8ee3SMauro Carvalho Chehab case QAM_16: 573d01a8ee3SMauro Carvalho Chehab m = 1; 574d01a8ee3SMauro Carvalho Chehab break; 575d01a8ee3SMauro Carvalho Chehab case QAM_64: 576d01a8ee3SMauro Carvalho Chehab m = 2; 577d01a8ee3SMauro Carvalho Chehab break; 578d01a8ee3SMauro Carvalho Chehab } 579d01a8ee3SMauro Carvalho Chehab 580d01a8ee3SMauro Carvalho Chehab switch (fec) { 581d01a8ee3SMauro Carvalho Chehab default: 582d01a8ee3SMauro Carvalho Chehab case FEC_1_2: 583d01a8ee3SMauro Carvalho Chehab case FEC_AUTO: 584d01a8ee3SMauro Carvalho Chehab f = 0; 585d01a8ee3SMauro Carvalho Chehab break; 586d01a8ee3SMauro Carvalho Chehab case FEC_2_3: 587d01a8ee3SMauro Carvalho Chehab f = 1; 588d01a8ee3SMauro Carvalho Chehab break; 589d01a8ee3SMauro Carvalho Chehab case FEC_3_4: 590d01a8ee3SMauro Carvalho Chehab f = 2; 591d01a8ee3SMauro Carvalho Chehab break; 592d01a8ee3SMauro Carvalho Chehab case FEC_5_6: 593d01a8ee3SMauro Carvalho Chehab f = 3; 594d01a8ee3SMauro Carvalho Chehab break; 595d01a8ee3SMauro Carvalho Chehab case FEC_7_8: 596d01a8ee3SMauro Carvalho Chehab f = 4; 597d01a8ee3SMauro Carvalho Chehab break; 598d01a8ee3SMauro Carvalho Chehab } 599d01a8ee3SMauro Carvalho Chehab 600d01a8ee3SMauro Carvalho Chehab switch (interleaving) { 601d01a8ee3SMauro Carvalho Chehab default: 602d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_4: 603d01a8ee3SMauro Carvalho Chehab i = 0; 604d01a8ee3SMauro Carvalho Chehab break; 605d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_8: 606d01a8ee3SMauro Carvalho Chehab i = 1; 607d01a8ee3SMauro Carvalho Chehab break; 608d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_16: 609d01a8ee3SMauro Carvalho Chehab i = 2; 610d01a8ee3SMauro Carvalho Chehab break; 611d01a8ee3SMauro Carvalho Chehab case GUARD_INTERVAL_1_32: 612d01a8ee3SMauro Carvalho Chehab i = 3; 613d01a8ee3SMauro Carvalho Chehab break; 614d01a8ee3SMauro Carvalho Chehab } 615d01a8ee3SMauro Carvalho Chehab 616d01a8ee3SMauro Carvalho Chehab /* Samples BER at BER_SAMPLING_RATE seconds */ 617d01a8ee3SMauro Carvalho Chehab rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE; 618d01a8ee3SMauro Carvalho Chehab 619d01a8ee3SMauro Carvalho Chehab /* Avoids sampling too quickly or to overflow the register */ 620d01a8ee3SMauro Carvalho Chehab if (rate < 256) 621d01a8ee3SMauro Carvalho Chehab rate = 256; 622d01a8ee3SMauro Carvalho Chehab else if (rate > (1 << 24) - 1) 623d01a8ee3SMauro Carvalho Chehab rate = (1 << 24) - 1; 624d01a8ee3SMauro Carvalho Chehab 625d01a8ee3SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 626d01a8ee3SMauro Carvalho Chehab "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", 627d01a8ee3SMauro Carvalho Chehab __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000, 628d01a8ee3SMauro Carvalho Chehab rate, rate); 629d01a8ee3SMauro Carvalho Chehab 630d01a8ee3SMauro Carvalho Chehab state->estimated_rate[i] = rate; 631d01a8ee3SMauro Carvalho Chehab } 632d01a8ee3SMauro Carvalho Chehab 633d01a8ee3SMauro Carvalho Chehab 6349a0bf528SMauro Carvalho Chehab static int mb86a20s_get_frontend(struct dvb_frontend *fe) 6359a0bf528SMauro Carvalho Chehab { 6369a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 637a77cfcacSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6389a0bf528SMauro Carvalho Chehab int i, rc; 6399a0bf528SMauro Carvalho Chehab 640f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 641f66d81b5SMauro Carvalho Chehab 642a77cfcacSMauro Carvalho Chehab /* Reset frontend cache to default values */ 643a77cfcacSMauro Carvalho Chehab mb86a20s_reset_frontend_cache(fe); 6449a0bf528SMauro Carvalho Chehab 6459a0bf528SMauro Carvalho Chehab /* Check for partial reception */ 6469a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, 0x85); 647a77cfcacSMauro Carvalho Chehab if (rc < 0) 648a77cfcacSMauro Carvalho Chehab return rc; 6499a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x6e); 650a77cfcacSMauro Carvalho Chehab if (rc < 0) 651a77cfcacSMauro Carvalho Chehab return rc; 652a77cfcacSMauro Carvalho Chehab c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; 6539a0bf528SMauro Carvalho Chehab 6549a0bf528SMauro Carvalho Chehab /* Get per-layer data */ 655a77cfcacSMauro Carvalho Chehab 6569a0bf528SMauro Carvalho Chehab for (i = 0; i < 3; i++) { 657f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", 658f66d81b5SMauro Carvalho Chehab __func__, 'A' + i); 659f66d81b5SMauro Carvalho Chehab 6609a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_segment_count(state, i); 661a77cfcacSMauro Carvalho Chehab if (rc < 0) 662f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 663d01a8ee3SMauro Carvalho Chehab if (rc >= 0 && rc < 14) { 664a77cfcacSMauro Carvalho Chehab c->layer[i].segment_count = rc; 665d01a8ee3SMauro Carvalho Chehab } else { 666a77cfcacSMauro Carvalho Chehab c->layer[i].segment_count = 0; 667d01a8ee3SMauro Carvalho Chehab state->estimated_rate[i] = 0; 6689a0bf528SMauro Carvalho Chehab continue; 669a77cfcacSMauro Carvalho Chehab } 670a77cfcacSMauro Carvalho Chehab c->isdbt_layer_enabled |= 1 << i; 6719a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_modulation(state, i); 672a77cfcacSMauro Carvalho Chehab if (rc < 0) 673f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 674f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", 675f66d81b5SMauro Carvalho Chehab __func__, rc); 676a77cfcacSMauro Carvalho Chehab c->layer[i].modulation = rc; 6779a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_fec(state, i); 678a77cfcacSMauro Carvalho Chehab if (rc < 0) 679f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 680f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", 681f66d81b5SMauro Carvalho Chehab __func__, rc); 682a77cfcacSMauro Carvalho Chehab c->layer[i].fec = rc; 6839a0bf528SMauro Carvalho Chehab rc = mb86a20s_get_interleaving(state, i); 684a77cfcacSMauro Carvalho Chehab if (rc < 0) 685f66d81b5SMauro Carvalho Chehab goto noperlayer_error; 686f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", 687f66d81b5SMauro Carvalho Chehab __func__, rc); 688a77cfcacSMauro Carvalho Chehab c->layer[i].interleaving = rc; 689d01a8ee3SMauro Carvalho Chehab mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation, 690d01a8ee3SMauro Carvalho Chehab c->layer[i].fec, 691d01a8ee3SMauro Carvalho Chehab c->layer[i].interleaving, 692d01a8ee3SMauro Carvalho Chehab c->layer[i].segment_count); 6939a0bf528SMauro Carvalho Chehab } 6949a0bf528SMauro Carvalho Chehab 6959a0bf528SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x6d, 0x84); 696a77cfcacSMauro Carvalho Chehab if (rc < 0) 697a77cfcacSMauro Carvalho Chehab return rc; 698a77cfcacSMauro Carvalho Chehab if ((rc & 0x60) == 0x20) { 699a77cfcacSMauro Carvalho Chehab c->isdbt_sb_mode = 1; 7009a0bf528SMauro Carvalho Chehab /* At least, one segment should exist */ 701a77cfcacSMauro Carvalho Chehab if (!c->isdbt_sb_segment_count) 702a77cfcacSMauro Carvalho Chehab c->isdbt_sb_segment_count = 1; 703a77cfcacSMauro Carvalho Chehab } 7049a0bf528SMauro Carvalho Chehab 7059a0bf528SMauro Carvalho Chehab /* Get transmission mode and guard interval */ 7069a0bf528SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x07); 707a77cfcacSMauro Carvalho Chehab if (rc < 0) 708a77cfcacSMauro Carvalho Chehab return rc; 7099a0bf528SMauro Carvalho Chehab if ((rc & 0x60) == 0x20) { 7109a0bf528SMauro Carvalho Chehab switch (rc & 0x0c >> 2) { 7119a0bf528SMauro Carvalho Chehab case 0: 712a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_2K; 7139a0bf528SMauro Carvalho Chehab break; 7149a0bf528SMauro Carvalho Chehab case 1: 715a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_4K; 7169a0bf528SMauro Carvalho Chehab break; 7179a0bf528SMauro Carvalho Chehab case 2: 718a77cfcacSMauro Carvalho Chehab c->transmission_mode = TRANSMISSION_MODE_8K; 7199a0bf528SMauro Carvalho Chehab break; 7209a0bf528SMauro Carvalho Chehab } 7219a0bf528SMauro Carvalho Chehab } 7229a0bf528SMauro Carvalho Chehab if (!(rc & 0x10)) { 7239a0bf528SMauro Carvalho Chehab switch (rc & 0x3) { 7249a0bf528SMauro Carvalho Chehab case 0: 725a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_4; 7269a0bf528SMauro Carvalho Chehab break; 7279a0bf528SMauro Carvalho Chehab case 1: 728a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_8; 7299a0bf528SMauro Carvalho Chehab break; 7309a0bf528SMauro Carvalho Chehab case 2: 731a77cfcacSMauro Carvalho Chehab c->guard_interval = GUARD_INTERVAL_1_16; 7329a0bf528SMauro Carvalho Chehab break; 7339a0bf528SMauro Carvalho Chehab } 7349a0bf528SMauro Carvalho Chehab } 73509b6d21eSMauro Carvalho Chehab return 0; 7369a0bf528SMauro Carvalho Chehab 737f66d81b5SMauro Carvalho Chehab noperlayer_error: 73809b6d21eSMauro Carvalho Chehab 73909b6d21eSMauro Carvalho Chehab /* per-layer info is incomplete; discard all per-layer */ 74009b6d21eSMauro Carvalho Chehab c->isdbt_layer_enabled = 0; 7419a0bf528SMauro Carvalho Chehab 742a77cfcacSMauro Carvalho Chehab return rc; 7439a0bf528SMauro Carvalho Chehab } 7449a0bf528SMauro Carvalho Chehab 74509b6d21eSMauro Carvalho Chehab static int mb86a20s_reset_counters(struct dvb_frontend *fe) 74609b6d21eSMauro Carvalho Chehab { 74709b6d21eSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 74809b6d21eSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 74909b6d21eSMauro Carvalho Chehab int rc, val; 75009b6d21eSMauro Carvalho Chehab 75109b6d21eSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 75209b6d21eSMauro Carvalho Chehab 75309b6d21eSMauro Carvalho Chehab /* Reset the counters, if the channel changed */ 75409b6d21eSMauro Carvalho Chehab if (state->last_frequency != c->frequency) { 75509b6d21eSMauro Carvalho Chehab memset(&c->strength, 0, sizeof(c->strength)); 75609b6d21eSMauro Carvalho Chehab memset(&c->cnr, 0, sizeof(c->cnr)); 75709b6d21eSMauro Carvalho Chehab memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); 75809b6d21eSMauro Carvalho Chehab memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); 759d9b6f08aSMauro Carvalho Chehab memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 760d9b6f08aSMauro Carvalho Chehab memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 76109b6d21eSMauro Carvalho Chehab memset(&c->block_error, 0, sizeof(c->block_error)); 76209b6d21eSMauro Carvalho Chehab memset(&c->block_count, 0, sizeof(c->block_count)); 76309b6d21eSMauro Carvalho Chehab 76409b6d21eSMauro Carvalho Chehab state->last_frequency = c->frequency; 76509b6d21eSMauro Carvalho Chehab } 76609b6d21eSMauro Carvalho Chehab 76709b6d21eSMauro Carvalho Chehab /* Clear status for most stats */ 76809b6d21eSMauro Carvalho Chehab 769d9b6f08aSMauro Carvalho Chehab /* BER/PER counter reset */ 770d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); 77109b6d21eSMauro Carvalho Chehab if (rc < 0) 77209b6d21eSMauro Carvalho Chehab goto err; 77309b6d21eSMauro Carvalho Chehab 77409b6d21eSMauro Carvalho Chehab /* CNR counter reset */ 77509b6d21eSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x45); 77609b6d21eSMauro Carvalho Chehab if (rc < 0) 77709b6d21eSMauro Carvalho Chehab goto err; 77809b6d21eSMauro Carvalho Chehab val = rc; 77909b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val | 0x10); 78009b6d21eSMauro Carvalho Chehab if (rc < 0) 78109b6d21eSMauro Carvalho Chehab goto err; 78209b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 78309b6d21eSMauro Carvalho Chehab if (rc < 0) 78409b6d21eSMauro Carvalho Chehab goto err; 78509b6d21eSMauro Carvalho Chehab 78609b6d21eSMauro Carvalho Chehab /* MER counter reset */ 78709b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x50); 78809b6d21eSMauro Carvalho Chehab if (rc < 0) 78909b6d21eSMauro Carvalho Chehab goto err; 79009b6d21eSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 79109b6d21eSMauro Carvalho Chehab if (rc < 0) 79209b6d21eSMauro Carvalho Chehab goto err; 79309b6d21eSMauro Carvalho Chehab val = rc; 79409b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val | 0x01); 79509b6d21eSMauro Carvalho Chehab if (rc < 0) 79609b6d21eSMauro Carvalho Chehab goto err; 79709b6d21eSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val & 0x06); 79809b6d21eSMauro Carvalho Chehab if (rc < 0) 79909b6d21eSMauro Carvalho Chehab goto err; 80009b6d21eSMauro Carvalho Chehab 801149d518aSMauro Carvalho Chehab goto ok; 80209b6d21eSMauro Carvalho Chehab err: 803149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 804149d518aSMauro Carvalho Chehab "%s: Can't reset FE statistics (error %d).\n", 805149d518aSMauro Carvalho Chehab __func__, rc); 806149d518aSMauro Carvalho Chehab ok: 80709b6d21eSMauro Carvalho Chehab return rc; 80809b6d21eSMauro Carvalho Chehab } 80909b6d21eSMauro Carvalho Chehab 810ad0abbf1SMauro Carvalho Chehab static int mb86a20s_get_pre_ber(struct dvb_frontend *fe, 811149d518aSMauro Carvalho Chehab unsigned layer, 812149d518aSMauro Carvalho Chehab u32 *error, u32 *count) 813149d518aSMauro Carvalho Chehab { 814149d518aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 815ad0abbf1SMauro Carvalho Chehab int rc, val; 816149d518aSMauro Carvalho Chehab 817149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 818149d518aSMauro Carvalho Chehab 819149d518aSMauro Carvalho Chehab if (layer >= 3) 820149d518aSMauro Carvalho Chehab return -EINVAL; 821149d518aSMauro Carvalho Chehab 822149d518aSMauro Carvalho Chehab /* Check if the BER measures are already available */ 823149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x54); 824149d518aSMauro Carvalho Chehab if (rc < 0) 825149d518aSMauro Carvalho Chehab return rc; 826149d518aSMauro Carvalho Chehab 827149d518aSMauro Carvalho Chehab /* Check if data is available for that layer */ 828149d518aSMauro Carvalho Chehab if (!(rc & (1 << layer))) { 829149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 830ad0abbf1SMauro Carvalho Chehab "%s: preBER for layer %c is not available yet.\n", 831149d518aSMauro Carvalho Chehab __func__, 'A' + layer); 832149d518aSMauro Carvalho Chehab return -EBUSY; 833149d518aSMauro Carvalho Chehab } 834149d518aSMauro Carvalho Chehab 835149d518aSMauro Carvalho Chehab /* Read Bit Error Count */ 836149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x55 + layer * 3); 837149d518aSMauro Carvalho Chehab if (rc < 0) 838149d518aSMauro Carvalho Chehab return rc; 839149d518aSMauro Carvalho Chehab *error = rc << 16; 840149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x56 + layer * 3); 841149d518aSMauro Carvalho Chehab if (rc < 0) 842149d518aSMauro Carvalho Chehab return rc; 843149d518aSMauro Carvalho Chehab *error |= rc << 8; 844149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x57 + layer * 3); 845149d518aSMauro Carvalho Chehab if (rc < 0) 846149d518aSMauro Carvalho Chehab return rc; 847149d518aSMauro Carvalho Chehab *error |= rc; 848149d518aSMauro Carvalho Chehab 849149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 850149d518aSMauro Carvalho Chehab "%s: bit error before Viterbi for layer %c: %d.\n", 851149d518aSMauro Carvalho Chehab __func__, 'A' + layer, *error); 852149d518aSMauro Carvalho Chehab 853149d518aSMauro Carvalho Chehab /* Read Bit Count */ 854149d518aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 855149d518aSMauro Carvalho Chehab if (rc < 0) 856149d518aSMauro Carvalho Chehab return rc; 857149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 858149d518aSMauro Carvalho Chehab if (rc < 0) 859149d518aSMauro Carvalho Chehab return rc; 860149d518aSMauro Carvalho Chehab *count = rc << 16; 861149d518aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 862149d518aSMauro Carvalho Chehab if (rc < 0) 863149d518aSMauro Carvalho Chehab return rc; 864149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 865149d518aSMauro Carvalho Chehab if (rc < 0) 866149d518aSMauro Carvalho Chehab return rc; 867149d518aSMauro Carvalho Chehab *count |= rc << 8; 868149d518aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 869149d518aSMauro Carvalho Chehab if (rc < 0) 870149d518aSMauro Carvalho Chehab return rc; 871149d518aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 872149d518aSMauro Carvalho Chehab if (rc < 0) 873149d518aSMauro Carvalho Chehab return rc; 874149d518aSMauro Carvalho Chehab *count |= rc; 875149d518aSMauro Carvalho Chehab 876149d518aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 877149d518aSMauro Carvalho Chehab "%s: bit count before Viterbi for layer %c: %d.\n", 878149d518aSMauro Carvalho Chehab __func__, 'A' + layer, *count); 879149d518aSMauro Carvalho Chehab 880149d518aSMauro Carvalho Chehab 881d01a8ee3SMauro Carvalho Chehab /* 882d01a8ee3SMauro Carvalho Chehab * As we get TMCC data from the frontend, we can better estimate the 883d01a8ee3SMauro Carvalho Chehab * BER bit counters, in order to do the BER measure during a longer 884d01a8ee3SMauro Carvalho Chehab * time. Use those data, if available, to update the bit count 885d01a8ee3SMauro Carvalho Chehab * measure. 886d01a8ee3SMauro Carvalho Chehab */ 887d01a8ee3SMauro Carvalho Chehab 888d01a8ee3SMauro Carvalho Chehab if (state->estimated_rate[layer] 889d01a8ee3SMauro Carvalho Chehab && state->estimated_rate[layer] != *count) { 890d01a8ee3SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 891ad0abbf1SMauro Carvalho Chehab "%s: updating layer %c preBER counter to %d.\n", 892d01a8ee3SMauro Carvalho Chehab __func__, 'A' + layer, state->estimated_rate[layer]); 893ad0abbf1SMauro Carvalho Chehab 894ad0abbf1SMauro Carvalho Chehab /* Turn off BER before Viterbi */ 895ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x52, 0x00); 896ad0abbf1SMauro Carvalho Chehab 897ad0abbf1SMauro Carvalho Chehab /* Update counter for this layer */ 898d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); 899d01a8ee3SMauro Carvalho Chehab if (rc < 0) 900d01a8ee3SMauro Carvalho Chehab return rc; 901d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 902d01a8ee3SMauro Carvalho Chehab state->estimated_rate[layer] >> 16); 903d01a8ee3SMauro Carvalho Chehab if (rc < 0) 904d01a8ee3SMauro Carvalho Chehab return rc; 905d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); 906d01a8ee3SMauro Carvalho Chehab if (rc < 0) 907d01a8ee3SMauro Carvalho Chehab return rc; 908d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 909d01a8ee3SMauro Carvalho Chehab state->estimated_rate[layer] >> 8); 910d01a8ee3SMauro Carvalho Chehab if (rc < 0) 911d01a8ee3SMauro Carvalho Chehab return rc; 912d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); 913d01a8ee3SMauro Carvalho Chehab if (rc < 0) 914d01a8ee3SMauro Carvalho Chehab return rc; 915d01a8ee3SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 916d01a8ee3SMauro Carvalho Chehab state->estimated_rate[layer]); 917d01a8ee3SMauro Carvalho Chehab if (rc < 0) 918d01a8ee3SMauro Carvalho Chehab return rc; 919ad0abbf1SMauro Carvalho Chehab 920ad0abbf1SMauro Carvalho Chehab /* Turn on BER before Viterbi */ 921ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x52, 0x01); 922ad0abbf1SMauro Carvalho Chehab 923ad0abbf1SMauro Carvalho Chehab /* Reset all preBER counters */ 924ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, 0x00); 925ad0abbf1SMauro Carvalho Chehab if (rc < 0) 926ad0abbf1SMauro Carvalho Chehab return rc; 927ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, 0x07); 928ad0abbf1SMauro Carvalho Chehab } else { 929ad0abbf1SMauro Carvalho Chehab /* Reset counter to collect new data */ 930ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x53); 931ad0abbf1SMauro Carvalho Chehab if (rc < 0) 932ad0abbf1SMauro Carvalho Chehab return rc; 933ad0abbf1SMauro Carvalho Chehab val = rc; 934ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); 935ad0abbf1SMauro Carvalho Chehab if (rc < 0) 936ad0abbf1SMauro Carvalho Chehab return rc; 937ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); 938d01a8ee3SMauro Carvalho Chehab } 939d01a8ee3SMauro Carvalho Chehab 940d9b6f08aSMauro Carvalho Chehab return rc; 941d9b6f08aSMauro Carvalho Chehab } 942d01a8ee3SMauro Carvalho Chehab 943d9b6f08aSMauro Carvalho Chehab static int mb86a20s_get_post_ber(struct dvb_frontend *fe, 944d9b6f08aSMauro Carvalho Chehab unsigned layer, 945d9b6f08aSMauro Carvalho Chehab u32 *error, u32 *count) 946d9b6f08aSMauro Carvalho Chehab { 947d9b6f08aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 948d9b6f08aSMauro Carvalho Chehab u32 counter, collect_rate; 949d9b6f08aSMauro Carvalho Chehab int rc, val; 950d9b6f08aSMauro Carvalho Chehab 951d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 952d9b6f08aSMauro Carvalho Chehab 953d9b6f08aSMauro Carvalho Chehab if (layer >= 3) 954d9b6f08aSMauro Carvalho Chehab return -EINVAL; 955d9b6f08aSMauro Carvalho Chehab 956d9b6f08aSMauro Carvalho Chehab /* Check if the BER measures are already available */ 957d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x60); 958d9b6f08aSMauro Carvalho Chehab if (rc < 0) 959d9b6f08aSMauro Carvalho Chehab return rc; 960d9b6f08aSMauro Carvalho Chehab 961d9b6f08aSMauro Carvalho Chehab /* Check if data is available for that layer */ 962d9b6f08aSMauro Carvalho Chehab if (!(rc & (1 << layer))) { 963d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 964d9b6f08aSMauro Carvalho Chehab "%s: post BER for layer %c is not available yet.\n", 965d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer); 966d9b6f08aSMauro Carvalho Chehab return -EBUSY; 967d9b6f08aSMauro Carvalho Chehab } 968d9b6f08aSMauro Carvalho Chehab 969d9b6f08aSMauro Carvalho Chehab /* Read Bit Error Count */ 970d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x64 + layer * 3); 971d9b6f08aSMauro Carvalho Chehab if (rc < 0) 972d9b6f08aSMauro Carvalho Chehab return rc; 973d9b6f08aSMauro Carvalho Chehab *error = rc << 16; 974d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x65 + layer * 3); 975d9b6f08aSMauro Carvalho Chehab if (rc < 0) 976d9b6f08aSMauro Carvalho Chehab return rc; 977d9b6f08aSMauro Carvalho Chehab *error |= rc << 8; 978d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x66 + layer * 3); 979d9b6f08aSMauro Carvalho Chehab if (rc < 0) 980d9b6f08aSMauro Carvalho Chehab return rc; 981d9b6f08aSMauro Carvalho Chehab *error |= rc; 982d9b6f08aSMauro Carvalho Chehab 983d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 984d9b6f08aSMauro Carvalho Chehab "%s: post bit error for layer %c: %d.\n", 985d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer, *error); 986d9b6f08aSMauro Carvalho Chehab 987d9b6f08aSMauro Carvalho Chehab /* Read Bit Count */ 988d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 989d9b6f08aSMauro Carvalho Chehab if (rc < 0) 990d9b6f08aSMauro Carvalho Chehab return rc; 991d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 992d9b6f08aSMauro Carvalho Chehab if (rc < 0) 993d9b6f08aSMauro Carvalho Chehab return rc; 994d9b6f08aSMauro Carvalho Chehab counter = rc << 8; 995d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 996d9b6f08aSMauro Carvalho Chehab if (rc < 0) 997d9b6f08aSMauro Carvalho Chehab return rc; 998d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 999d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1000d9b6f08aSMauro Carvalho Chehab return rc; 1001d9b6f08aSMauro Carvalho Chehab counter |= rc; 1002d9b6f08aSMauro Carvalho Chehab *count = counter * 204 * 8; 1003d9b6f08aSMauro Carvalho Chehab 1004d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1005d9b6f08aSMauro Carvalho Chehab "%s: post bit count for layer %c: %d.\n", 1006d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer, *count); 1007d9b6f08aSMauro Carvalho Chehab 1008d9b6f08aSMauro Carvalho Chehab /* 1009d9b6f08aSMauro Carvalho Chehab * As we get TMCC data from the frontend, we can better estimate the 1010d9b6f08aSMauro Carvalho Chehab * BER bit counters, in order to do the BER measure during a longer 1011d9b6f08aSMauro Carvalho Chehab * time. Use those data, if available, to update the bit count 1012d9b6f08aSMauro Carvalho Chehab * measure. 1013d9b6f08aSMauro Carvalho Chehab */ 1014d9b6f08aSMauro Carvalho Chehab 1015d9b6f08aSMauro Carvalho Chehab if (!state->estimated_rate[layer]) 1016d9b6f08aSMauro Carvalho Chehab goto reset_measurement; 1017d9b6f08aSMauro Carvalho Chehab 1018d9b6f08aSMauro Carvalho Chehab collect_rate = state->estimated_rate[layer] / 204 / 8; 1019d9b6f08aSMauro Carvalho Chehab if (collect_rate < 32) 1020d9b6f08aSMauro Carvalho Chehab collect_rate = 32; 1021d9b6f08aSMauro Carvalho Chehab if (collect_rate > 65535) 1022d9b6f08aSMauro Carvalho Chehab collect_rate = 65535; 1023d9b6f08aSMauro Carvalho Chehab if (collect_rate != counter) { 1024d9b6f08aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1025d9b6f08aSMauro Carvalho Chehab "%s: updating postBER counter on layer %c to %d.\n", 1026d9b6f08aSMauro Carvalho Chehab __func__, 'A' + layer, collect_rate); 1027d9b6f08aSMauro Carvalho Chehab 1028d9b6f08aSMauro Carvalho Chehab /* Turn off BER after Viterbi */ 1029d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5e, 0x00); 1030d9b6f08aSMauro Carvalho Chehab 1031d9b6f08aSMauro Carvalho Chehab /* Update counter for this layer */ 1032d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); 1033d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1034d9b6f08aSMauro Carvalho Chehab return rc; 1035d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1036d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1037d9b6f08aSMauro Carvalho Chehab return rc; 1038d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); 1039d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1040d9b6f08aSMauro Carvalho Chehab return rc; 1041d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1042d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1043d9b6f08aSMauro Carvalho Chehab return rc; 1044d9b6f08aSMauro Carvalho Chehab 1045d9b6f08aSMauro Carvalho Chehab /* Turn on BER after Viterbi */ 1046d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5e, 0x07); 1047d9b6f08aSMauro Carvalho Chehab 1048d9b6f08aSMauro Carvalho Chehab /* Reset all preBER counters */ 1049d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, 0x00); 1050d9b6f08aSMauro Carvalho Chehab if (rc < 0) 1051d9b6f08aSMauro Carvalho Chehab return rc; 1052d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, 0x07); 1053d9b6f08aSMauro Carvalho Chehab 1054d9b6f08aSMauro Carvalho Chehab return rc; 1055d9b6f08aSMauro Carvalho Chehab } 1056d9b6f08aSMauro Carvalho Chehab 1057d9b6f08aSMauro Carvalho Chehab reset_measurement: 1058149d518aSMauro Carvalho Chehab /* Reset counter to collect new data */ 1059ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x5f); 1060149d518aSMauro Carvalho Chehab if (rc < 0) 1061149d518aSMauro Carvalho Chehab return rc; 1062ad0abbf1SMauro Carvalho Chehab val = rc; 1063ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); 1064ad0abbf1SMauro Carvalho Chehab if (rc < 0) 1065ad0abbf1SMauro Carvalho Chehab return rc; 1066d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); 1067149d518aSMauro Carvalho Chehab 1068ad0abbf1SMauro Carvalho Chehab return rc; 1069149d518aSMauro Carvalho Chehab } 1070149d518aSMauro Carvalho Chehab 1071593ae89aSMauro Carvalho Chehab static int mb86a20s_get_blk_error(struct dvb_frontend *fe, 1072593ae89aSMauro Carvalho Chehab unsigned layer, 1073593ae89aSMauro Carvalho Chehab u32 *error, u32 *count) 1074593ae89aSMauro Carvalho Chehab { 1075593ae89aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1076313cf4efSMauro Carvalho Chehab int rc, val; 1077593ae89aSMauro Carvalho Chehab u32 collect_rate; 1078593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1079593ae89aSMauro Carvalho Chehab 1080593ae89aSMauro Carvalho Chehab if (layer >= 3) 1081593ae89aSMauro Carvalho Chehab return -EINVAL; 1082593ae89aSMauro Carvalho Chehab 1083593ae89aSMauro Carvalho Chehab /* Check if the PER measures are already available */ 1084593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb8); 1085593ae89aSMauro Carvalho Chehab if (rc < 0) 1086593ae89aSMauro Carvalho Chehab return rc; 1087593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1088593ae89aSMauro Carvalho Chehab if (rc < 0) 1089593ae89aSMauro Carvalho Chehab return rc; 1090593ae89aSMauro Carvalho Chehab 1091593ae89aSMauro Carvalho Chehab /* Check if data is available for that layer */ 1092593ae89aSMauro Carvalho Chehab 1093593ae89aSMauro Carvalho Chehab if (!(rc & (1 << layer))) { 1094593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1095593ae89aSMauro Carvalho Chehab "%s: block counts for layer %c aren't available yet.\n", 1096593ae89aSMauro Carvalho Chehab __func__, 'A' + layer); 1097593ae89aSMauro Carvalho Chehab return -EBUSY; 1098593ae89aSMauro Carvalho Chehab } 1099593ae89aSMauro Carvalho Chehab 1100593ae89aSMauro Carvalho Chehab /* Read Packet error Count */ 1101593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); 1102593ae89aSMauro Carvalho Chehab if (rc < 0) 1103593ae89aSMauro Carvalho Chehab return rc; 1104593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1105593ae89aSMauro Carvalho Chehab if (rc < 0) 1106593ae89aSMauro Carvalho Chehab return rc; 1107593ae89aSMauro Carvalho Chehab *error = rc << 8; 1108593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); 1109593ae89aSMauro Carvalho Chehab if (rc < 0) 1110593ae89aSMauro Carvalho Chehab return rc; 1111593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1112593ae89aSMauro Carvalho Chehab if (rc < 0) 1113593ae89aSMauro Carvalho Chehab return rc; 1114593ae89aSMauro Carvalho Chehab *error |= rc; 1115d56e326fSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n", 1116593ae89aSMauro Carvalho Chehab __func__, 'A' + layer, *error); 1117593ae89aSMauro Carvalho Chehab 1118593ae89aSMauro Carvalho Chehab /* Read Bit Count */ 1119593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1120593ae89aSMauro Carvalho Chehab if (rc < 0) 1121593ae89aSMauro Carvalho Chehab return rc; 1122593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1123593ae89aSMauro Carvalho Chehab if (rc < 0) 1124593ae89aSMauro Carvalho Chehab return rc; 1125593ae89aSMauro Carvalho Chehab *count = rc << 8; 1126593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1127593ae89aSMauro Carvalho Chehab if (rc < 0) 1128593ae89aSMauro Carvalho Chehab return rc; 1129593ae89aSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1130593ae89aSMauro Carvalho Chehab if (rc < 0) 1131593ae89aSMauro Carvalho Chehab return rc; 1132593ae89aSMauro Carvalho Chehab *count |= rc; 1133593ae89aSMauro Carvalho Chehab 1134593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1135593ae89aSMauro Carvalho Chehab "%s: block count for layer %c: %d.\n", 1136593ae89aSMauro Carvalho Chehab __func__, 'A' + layer, *count); 1137593ae89aSMauro Carvalho Chehab 1138593ae89aSMauro Carvalho Chehab /* 1139593ae89aSMauro Carvalho Chehab * As we get TMCC data from the frontend, we can better estimate the 1140593ae89aSMauro Carvalho Chehab * BER bit counters, in order to do the BER measure during a longer 1141593ae89aSMauro Carvalho Chehab * time. Use those data, if available, to update the bit count 1142593ae89aSMauro Carvalho Chehab * measure. 1143593ae89aSMauro Carvalho Chehab */ 1144593ae89aSMauro Carvalho Chehab 1145593ae89aSMauro Carvalho Chehab if (!state->estimated_rate[layer]) 1146593ae89aSMauro Carvalho Chehab goto reset_measurement; 1147593ae89aSMauro Carvalho Chehab 1148593ae89aSMauro Carvalho Chehab collect_rate = state->estimated_rate[layer] / 204 / 8; 1149593ae89aSMauro Carvalho Chehab if (collect_rate < 32) 1150593ae89aSMauro Carvalho Chehab collect_rate = 32; 1151593ae89aSMauro Carvalho Chehab if (collect_rate > 65535) 1152593ae89aSMauro Carvalho Chehab collect_rate = 65535; 1153593ae89aSMauro Carvalho Chehab 1154593ae89aSMauro Carvalho Chehab if (collect_rate != *count) { 1155593ae89aSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 1156593ae89aSMauro Carvalho Chehab "%s: updating PER counter on layer %c to %d.\n", 1157593ae89aSMauro Carvalho Chehab __func__, 'A' + layer, collect_rate); 1158313cf4efSMauro Carvalho Chehab 1159313cf4efSMauro Carvalho Chehab /* Stop PER measurement */ 1160313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb0); 1161313cf4efSMauro Carvalho Chehab if (rc < 0) 1162313cf4efSMauro Carvalho Chehab return rc; 1163313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x00); 1164313cf4efSMauro Carvalho Chehab if (rc < 0) 1165313cf4efSMauro Carvalho Chehab return rc; 1166313cf4efSMauro Carvalho Chehab 1167313cf4efSMauro Carvalho Chehab /* Update this layer's counter */ 1168593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); 1169593ae89aSMauro Carvalho Chehab if (rc < 0) 1170593ae89aSMauro Carvalho Chehab return rc; 1171593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); 1172593ae89aSMauro Carvalho Chehab if (rc < 0) 1173593ae89aSMauro Carvalho Chehab return rc; 1174593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); 1175593ae89aSMauro Carvalho Chehab if (rc < 0) 1176593ae89aSMauro Carvalho Chehab return rc; 1177593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); 1178593ae89aSMauro Carvalho Chehab if (rc < 0) 1179593ae89aSMauro Carvalho Chehab return rc; 1180313cf4efSMauro Carvalho Chehab 1181313cf4efSMauro Carvalho Chehab /* start PER measurement */ 1182313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb0); 1183313cf4efSMauro Carvalho Chehab if (rc < 0) 1184313cf4efSMauro Carvalho Chehab return rc; 1185313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x07); 1186313cf4efSMauro Carvalho Chehab if (rc < 0) 1187313cf4efSMauro Carvalho Chehab return rc; 1188313cf4efSMauro Carvalho Chehab 1189313cf4efSMauro Carvalho Chehab /* Reset all counters to collect new data */ 1190313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb1); 1191313cf4efSMauro Carvalho Chehab if (rc < 0) 1192313cf4efSMauro Carvalho Chehab return rc; 1193313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x07); 1194313cf4efSMauro Carvalho Chehab if (rc < 0) 1195313cf4efSMauro Carvalho Chehab return rc; 1196313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, 0x00); 1197313cf4efSMauro Carvalho Chehab 1198313cf4efSMauro Carvalho Chehab return rc; 1199593ae89aSMauro Carvalho Chehab } 1200593ae89aSMauro Carvalho Chehab 1201593ae89aSMauro Carvalho Chehab reset_measurement: 1202593ae89aSMauro Carvalho Chehab /* Reset counter to collect new data */ 1203593ae89aSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xb1); 1204593ae89aSMauro Carvalho Chehab if (rc < 0) 1205593ae89aSMauro Carvalho Chehab return rc; 1206313cf4efSMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 1207593ae89aSMauro Carvalho Chehab if (rc < 0) 1208593ae89aSMauro Carvalho Chehab return rc; 1209313cf4efSMauro Carvalho Chehab val = rc; 1210313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); 1211593ae89aSMauro Carvalho Chehab if (rc < 0) 1212593ae89aSMauro Carvalho Chehab return rc; 1213313cf4efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); 1214593ae89aSMauro Carvalho Chehab 1215313cf4efSMauro Carvalho Chehab return rc; 1216593ae89aSMauro Carvalho Chehab } 1217593ae89aSMauro Carvalho Chehab 121825188bd0SMauro Carvalho Chehab struct linear_segments { 121925188bd0SMauro Carvalho Chehab unsigned x, y; 122025188bd0SMauro Carvalho Chehab }; 122125188bd0SMauro Carvalho Chehab 122225188bd0SMauro Carvalho Chehab /* 122325188bd0SMauro Carvalho Chehab * All tables below return a dB/1000 measurement 122425188bd0SMauro Carvalho Chehab */ 122525188bd0SMauro Carvalho Chehab 122625188bd0SMauro Carvalho Chehab static struct linear_segments cnr_to_db_table[] = { 122725188bd0SMauro Carvalho Chehab { 19648, 0}, 122825188bd0SMauro Carvalho Chehab { 18187, 1000}, 122925188bd0SMauro Carvalho Chehab { 16534, 2000}, 123025188bd0SMauro Carvalho Chehab { 14823, 3000}, 123125188bd0SMauro Carvalho Chehab { 13161, 4000}, 123225188bd0SMauro Carvalho Chehab { 11622, 5000}, 123325188bd0SMauro Carvalho Chehab { 10279, 6000}, 123425188bd0SMauro Carvalho Chehab { 9089, 7000}, 123525188bd0SMauro Carvalho Chehab { 8042, 8000}, 123625188bd0SMauro Carvalho Chehab { 7137, 9000}, 123725188bd0SMauro Carvalho Chehab { 6342, 10000}, 123825188bd0SMauro Carvalho Chehab { 5641, 11000}, 123925188bd0SMauro Carvalho Chehab { 5030, 12000}, 124025188bd0SMauro Carvalho Chehab { 4474, 13000}, 124125188bd0SMauro Carvalho Chehab { 3988, 14000}, 124225188bd0SMauro Carvalho Chehab { 3556, 15000}, 124325188bd0SMauro Carvalho Chehab { 3180, 16000}, 124425188bd0SMauro Carvalho Chehab { 2841, 17000}, 124525188bd0SMauro Carvalho Chehab { 2541, 18000}, 124625188bd0SMauro Carvalho Chehab { 2276, 19000}, 124725188bd0SMauro Carvalho Chehab { 2038, 20000}, 124825188bd0SMauro Carvalho Chehab { 1800, 21000}, 124925188bd0SMauro Carvalho Chehab { 1625, 22000}, 125025188bd0SMauro Carvalho Chehab { 1462, 23000}, 125125188bd0SMauro Carvalho Chehab { 1324, 24000}, 125225188bd0SMauro Carvalho Chehab { 1175, 25000}, 125325188bd0SMauro Carvalho Chehab { 1063, 26000}, 125425188bd0SMauro Carvalho Chehab { 980, 27000}, 125525188bd0SMauro Carvalho Chehab { 907, 28000}, 125625188bd0SMauro Carvalho Chehab { 840, 29000}, 125725188bd0SMauro Carvalho Chehab { 788, 30000}, 125825188bd0SMauro Carvalho Chehab }; 125925188bd0SMauro Carvalho Chehab 126025188bd0SMauro Carvalho Chehab static struct linear_segments cnr_64qam_table[] = { 126125188bd0SMauro Carvalho Chehab { 3922688, 0}, 126225188bd0SMauro Carvalho Chehab { 3920384, 1000}, 126325188bd0SMauro Carvalho Chehab { 3902720, 2000}, 126425188bd0SMauro Carvalho Chehab { 3894784, 3000}, 126525188bd0SMauro Carvalho Chehab { 3882496, 4000}, 126625188bd0SMauro Carvalho Chehab { 3872768, 5000}, 126725188bd0SMauro Carvalho Chehab { 3858944, 6000}, 126825188bd0SMauro Carvalho Chehab { 3851520, 7000}, 126925188bd0SMauro Carvalho Chehab { 3838976, 8000}, 127025188bd0SMauro Carvalho Chehab { 3829248, 9000}, 127125188bd0SMauro Carvalho Chehab { 3818240, 10000}, 127225188bd0SMauro Carvalho Chehab { 3806976, 11000}, 127325188bd0SMauro Carvalho Chehab { 3791872, 12000}, 127425188bd0SMauro Carvalho Chehab { 3767040, 13000}, 127525188bd0SMauro Carvalho Chehab { 3720960, 14000}, 127625188bd0SMauro Carvalho Chehab { 3637504, 15000}, 127725188bd0SMauro Carvalho Chehab { 3498496, 16000}, 127825188bd0SMauro Carvalho Chehab { 3296000, 17000}, 127925188bd0SMauro Carvalho Chehab { 3031040, 18000}, 128025188bd0SMauro Carvalho Chehab { 2715392, 19000}, 128125188bd0SMauro Carvalho Chehab { 2362624, 20000}, 128225188bd0SMauro Carvalho Chehab { 1963264, 21000}, 128325188bd0SMauro Carvalho Chehab { 1649664, 22000}, 128425188bd0SMauro Carvalho Chehab { 1366784, 23000}, 128525188bd0SMauro Carvalho Chehab { 1120768, 24000}, 128625188bd0SMauro Carvalho Chehab { 890880, 25000}, 128725188bd0SMauro Carvalho Chehab { 723456, 26000}, 128825188bd0SMauro Carvalho Chehab { 612096, 27000}, 128925188bd0SMauro Carvalho Chehab { 518912, 28000}, 129025188bd0SMauro Carvalho Chehab { 448256, 29000}, 129125188bd0SMauro Carvalho Chehab { 388864, 30000}, 129225188bd0SMauro Carvalho Chehab }; 129325188bd0SMauro Carvalho Chehab 129425188bd0SMauro Carvalho Chehab static struct linear_segments cnr_16qam_table[] = { 129525188bd0SMauro Carvalho Chehab { 5314816, 0}, 129625188bd0SMauro Carvalho Chehab { 5219072, 1000}, 129725188bd0SMauro Carvalho Chehab { 5118720, 2000}, 129825188bd0SMauro Carvalho Chehab { 4998912, 3000}, 129925188bd0SMauro Carvalho Chehab { 4875520, 4000}, 130025188bd0SMauro Carvalho Chehab { 4736000, 5000}, 130125188bd0SMauro Carvalho Chehab { 4604160, 6000}, 130225188bd0SMauro Carvalho Chehab { 4458752, 7000}, 130325188bd0SMauro Carvalho Chehab { 4300288, 8000}, 130425188bd0SMauro Carvalho Chehab { 4092928, 9000}, 130525188bd0SMauro Carvalho Chehab { 3836160, 10000}, 130625188bd0SMauro Carvalho Chehab { 3521024, 11000}, 130725188bd0SMauro Carvalho Chehab { 3155968, 12000}, 130825188bd0SMauro Carvalho Chehab { 2756864, 13000}, 130925188bd0SMauro Carvalho Chehab { 2347008, 14000}, 131025188bd0SMauro Carvalho Chehab { 1955072, 15000}, 131125188bd0SMauro Carvalho Chehab { 1593600, 16000}, 131225188bd0SMauro Carvalho Chehab { 1297920, 17000}, 131325188bd0SMauro Carvalho Chehab { 1043968, 18000}, 131425188bd0SMauro Carvalho Chehab { 839680, 19000}, 131525188bd0SMauro Carvalho Chehab { 672256, 20000}, 131625188bd0SMauro Carvalho Chehab { 523008, 21000}, 131725188bd0SMauro Carvalho Chehab { 424704, 22000}, 131825188bd0SMauro Carvalho Chehab { 345088, 23000}, 131925188bd0SMauro Carvalho Chehab { 280064, 24000}, 132025188bd0SMauro Carvalho Chehab { 221440, 25000}, 132125188bd0SMauro Carvalho Chehab { 179712, 26000}, 132225188bd0SMauro Carvalho Chehab { 151040, 27000}, 132325188bd0SMauro Carvalho Chehab { 128512, 28000}, 132425188bd0SMauro Carvalho Chehab { 110080, 29000}, 132525188bd0SMauro Carvalho Chehab { 95744, 30000}, 132625188bd0SMauro Carvalho Chehab }; 132725188bd0SMauro Carvalho Chehab 132825188bd0SMauro Carvalho Chehab struct linear_segments cnr_qpsk_table[] = { 132925188bd0SMauro Carvalho Chehab { 2834176, 0}, 133025188bd0SMauro Carvalho Chehab { 2683648, 1000}, 133125188bd0SMauro Carvalho Chehab { 2536960, 2000}, 133225188bd0SMauro Carvalho Chehab { 2391808, 3000}, 133325188bd0SMauro Carvalho Chehab { 2133248, 4000}, 133425188bd0SMauro Carvalho Chehab { 1906176, 5000}, 133525188bd0SMauro Carvalho Chehab { 1666560, 6000}, 133625188bd0SMauro Carvalho Chehab { 1422080, 7000}, 133725188bd0SMauro Carvalho Chehab { 1189632, 8000}, 133825188bd0SMauro Carvalho Chehab { 976384, 9000}, 133925188bd0SMauro Carvalho Chehab { 790272, 10000}, 134025188bd0SMauro Carvalho Chehab { 633344, 11000}, 134125188bd0SMauro Carvalho Chehab { 505600, 12000}, 134225188bd0SMauro Carvalho Chehab { 402944, 13000}, 134325188bd0SMauro Carvalho Chehab { 320768, 14000}, 134425188bd0SMauro Carvalho Chehab { 255488, 15000}, 134525188bd0SMauro Carvalho Chehab { 204032, 16000}, 134625188bd0SMauro Carvalho Chehab { 163072, 17000}, 134725188bd0SMauro Carvalho Chehab { 130304, 18000}, 134825188bd0SMauro Carvalho Chehab { 105216, 19000}, 134925188bd0SMauro Carvalho Chehab { 83456, 20000}, 135025188bd0SMauro Carvalho Chehab { 65024, 21000}, 135125188bd0SMauro Carvalho Chehab { 52480, 22000}, 135225188bd0SMauro Carvalho Chehab { 42752, 23000}, 135325188bd0SMauro Carvalho Chehab { 34560, 24000}, 135425188bd0SMauro Carvalho Chehab { 27136, 25000}, 135525188bd0SMauro Carvalho Chehab { 22016, 26000}, 135625188bd0SMauro Carvalho Chehab { 18432, 27000}, 135725188bd0SMauro Carvalho Chehab { 15616, 28000}, 135825188bd0SMauro Carvalho Chehab { 13312, 29000}, 135925188bd0SMauro Carvalho Chehab { 11520, 30000}, 136025188bd0SMauro Carvalho Chehab }; 136125188bd0SMauro Carvalho Chehab 136225188bd0SMauro Carvalho Chehab static u32 interpolate_value(u32 value, struct linear_segments *segments, 136325188bd0SMauro Carvalho Chehab unsigned len) 136425188bd0SMauro Carvalho Chehab { 136525188bd0SMauro Carvalho Chehab u64 tmp64; 136625188bd0SMauro Carvalho Chehab u32 dx, dy; 136725188bd0SMauro Carvalho Chehab int i, ret; 136825188bd0SMauro Carvalho Chehab 136925188bd0SMauro Carvalho Chehab if (value >= segments[0].x) 137025188bd0SMauro Carvalho Chehab return segments[0].y; 137125188bd0SMauro Carvalho Chehab if (value < segments[len-1].x) 137225188bd0SMauro Carvalho Chehab return segments[len-1].y; 137325188bd0SMauro Carvalho Chehab 137425188bd0SMauro Carvalho Chehab for (i = 1; i < len - 1; i++) { 137525188bd0SMauro Carvalho Chehab /* If value is identical, no need to interpolate */ 137625188bd0SMauro Carvalho Chehab if (value == segments[i].x) 137725188bd0SMauro Carvalho Chehab return segments[i].y; 137825188bd0SMauro Carvalho Chehab if (value > segments[i].x) 137925188bd0SMauro Carvalho Chehab break; 138025188bd0SMauro Carvalho Chehab } 138125188bd0SMauro Carvalho Chehab 138225188bd0SMauro Carvalho Chehab /* Linear interpolation between the two (x,y) points */ 138325188bd0SMauro Carvalho Chehab dy = segments[i].y - segments[i - 1].y; 138425188bd0SMauro Carvalho Chehab dx = segments[i - 1].x - segments[i].x; 138525188bd0SMauro Carvalho Chehab tmp64 = value - segments[i].x; 138625188bd0SMauro Carvalho Chehab tmp64 *= dy; 138725188bd0SMauro Carvalho Chehab do_div(tmp64, dx); 138825188bd0SMauro Carvalho Chehab ret = segments[i].y - tmp64; 138925188bd0SMauro Carvalho Chehab 139025188bd0SMauro Carvalho Chehab return ret; 139125188bd0SMauro Carvalho Chehab } 139225188bd0SMauro Carvalho Chehab 139325188bd0SMauro Carvalho Chehab static int mb86a20s_get_main_CNR(struct dvb_frontend *fe) 139425188bd0SMauro Carvalho Chehab { 139525188bd0SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 139625188bd0SMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 139725188bd0SMauro Carvalho Chehab u32 cnr_linear, cnr; 139825188bd0SMauro Carvalho Chehab int rc, val; 139925188bd0SMauro Carvalho Chehab 140025188bd0SMauro Carvalho Chehab /* Check if CNR is available */ 140125188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x45); 140225188bd0SMauro Carvalho Chehab if (rc < 0) 140325188bd0SMauro Carvalho Chehab return rc; 140425188bd0SMauro Carvalho Chehab 140525188bd0SMauro Carvalho Chehab if (!(rc & 0x40)) { 1406d56e326fSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n", 140725188bd0SMauro Carvalho Chehab __func__); 140825188bd0SMauro Carvalho Chehab return -EBUSY; 140925188bd0SMauro Carvalho Chehab } 141025188bd0SMauro Carvalho Chehab val = rc; 141125188bd0SMauro Carvalho Chehab 141225188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x46); 141325188bd0SMauro Carvalho Chehab if (rc < 0) 141425188bd0SMauro Carvalho Chehab return rc; 141525188bd0SMauro Carvalho Chehab cnr_linear = rc << 8; 141625188bd0SMauro Carvalho Chehab 141725188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x46); 141825188bd0SMauro Carvalho Chehab if (rc < 0) 141925188bd0SMauro Carvalho Chehab return rc; 142025188bd0SMauro Carvalho Chehab cnr_linear |= rc; 142125188bd0SMauro Carvalho Chehab 142225188bd0SMauro Carvalho Chehab cnr = interpolate_value(cnr_linear, 142325188bd0SMauro Carvalho Chehab cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table)); 142425188bd0SMauro Carvalho Chehab 142525188bd0SMauro Carvalho Chehab c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 142625188bd0SMauro Carvalho Chehab c->cnr.stat[0].svalue = cnr; 142725188bd0SMauro Carvalho Chehab 142825188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", 142925188bd0SMauro Carvalho Chehab __func__, cnr / 1000, cnr % 1000, cnr_linear); 143025188bd0SMauro Carvalho Chehab 143125188bd0SMauro Carvalho Chehab /* CNR counter reset */ 143225188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val | 0x10); 143325188bd0SMauro Carvalho Chehab if (rc < 0) 143425188bd0SMauro Carvalho Chehab return rc; 143525188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x45, val & 0x6f); 143625188bd0SMauro Carvalho Chehab 143725188bd0SMauro Carvalho Chehab return rc; 143825188bd0SMauro Carvalho Chehab } 143925188bd0SMauro Carvalho Chehab 1440593ae89aSMauro Carvalho Chehab static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe) 144125188bd0SMauro Carvalho Chehab { 144225188bd0SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 144325188bd0SMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 144425188bd0SMauro Carvalho Chehab u32 mer, cnr; 144525188bd0SMauro Carvalho Chehab int rc, val, i; 144625188bd0SMauro Carvalho Chehab struct linear_segments *segs; 144725188bd0SMauro Carvalho Chehab unsigned segs_len; 144825188bd0SMauro Carvalho Chehab 144925188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 145025188bd0SMauro Carvalho Chehab 145125188bd0SMauro Carvalho Chehab /* Check if the measures are already available */ 145225188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x5b); 145325188bd0SMauro Carvalho Chehab if (rc < 0) 145425188bd0SMauro Carvalho Chehab return rc; 145525188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 145625188bd0SMauro Carvalho Chehab if (rc < 0) 145725188bd0SMauro Carvalho Chehab return rc; 145825188bd0SMauro Carvalho Chehab 145925188bd0SMauro Carvalho Chehab /* Check if data is available */ 146025188bd0SMauro Carvalho Chehab if (!(rc & 0x01)) { 1461d56e326fSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 146225188bd0SMauro Carvalho Chehab "%s: MER measures aren't available yet.\n", __func__); 146325188bd0SMauro Carvalho Chehab return -EBUSY; 146425188bd0SMauro Carvalho Chehab } 146525188bd0SMauro Carvalho Chehab 146625188bd0SMauro Carvalho Chehab /* Read all layers */ 146725188bd0SMauro Carvalho Chehab for (i = 0; i < 3; i++) { 146825188bd0SMauro Carvalho Chehab if (!(c->isdbt_layer_enabled & (1 << i))) { 146925188bd0SMauro Carvalho Chehab c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 147025188bd0SMauro Carvalho Chehab continue; 147125188bd0SMauro Carvalho Chehab } 147225188bd0SMauro Carvalho Chehab 147325188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3); 147425188bd0SMauro Carvalho Chehab if (rc < 0) 147525188bd0SMauro Carvalho Chehab return rc; 147625188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 147725188bd0SMauro Carvalho Chehab if (rc < 0) 147825188bd0SMauro Carvalho Chehab return rc; 147925188bd0SMauro Carvalho Chehab mer = rc << 16; 148025188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3); 148125188bd0SMauro Carvalho Chehab if (rc < 0) 148225188bd0SMauro Carvalho Chehab return rc; 148325188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 148425188bd0SMauro Carvalho Chehab if (rc < 0) 148525188bd0SMauro Carvalho Chehab return rc; 148625188bd0SMauro Carvalho Chehab mer |= rc << 8; 148725188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3); 148825188bd0SMauro Carvalho Chehab if (rc < 0) 148925188bd0SMauro Carvalho Chehab return rc; 149025188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 149125188bd0SMauro Carvalho Chehab if (rc < 0) 149225188bd0SMauro Carvalho Chehab return rc; 149325188bd0SMauro Carvalho Chehab mer |= rc; 149425188bd0SMauro Carvalho Chehab 149525188bd0SMauro Carvalho Chehab switch (c->layer[i].modulation) { 149625188bd0SMauro Carvalho Chehab case DQPSK: 149725188bd0SMauro Carvalho Chehab case QPSK: 149825188bd0SMauro Carvalho Chehab segs = cnr_qpsk_table; 149925188bd0SMauro Carvalho Chehab segs_len = ARRAY_SIZE(cnr_qpsk_table); 150025188bd0SMauro Carvalho Chehab break; 150125188bd0SMauro Carvalho Chehab case QAM_16: 150225188bd0SMauro Carvalho Chehab segs = cnr_16qam_table; 150325188bd0SMauro Carvalho Chehab segs_len = ARRAY_SIZE(cnr_16qam_table); 150425188bd0SMauro Carvalho Chehab break; 150525188bd0SMauro Carvalho Chehab default: 150625188bd0SMauro Carvalho Chehab case QAM_64: 150725188bd0SMauro Carvalho Chehab segs = cnr_64qam_table; 150825188bd0SMauro Carvalho Chehab segs_len = ARRAY_SIZE(cnr_64qam_table); 150925188bd0SMauro Carvalho Chehab break; 151025188bd0SMauro Carvalho Chehab } 151125188bd0SMauro Carvalho Chehab cnr = interpolate_value(mer, segs, segs_len); 151225188bd0SMauro Carvalho Chehab 151325188bd0SMauro Carvalho Chehab c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL; 151425188bd0SMauro Carvalho Chehab c->cnr.stat[1 + i].svalue = cnr; 151525188bd0SMauro Carvalho Chehab 151625188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, 151725188bd0SMauro Carvalho Chehab "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n", 151825188bd0SMauro Carvalho Chehab __func__, 'A' + i, cnr / 1000, cnr % 1000, mer); 151925188bd0SMauro Carvalho Chehab 152025188bd0SMauro Carvalho Chehab } 152125188bd0SMauro Carvalho Chehab 152225188bd0SMauro Carvalho Chehab /* Start a new MER measurement */ 152325188bd0SMauro Carvalho Chehab /* MER counter reset */ 152425188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0x50); 152525188bd0SMauro Carvalho Chehab if (rc < 0) 152625188bd0SMauro Carvalho Chehab return rc; 152725188bd0SMauro Carvalho Chehab rc = mb86a20s_readreg(state, 0x51); 152825188bd0SMauro Carvalho Chehab if (rc < 0) 152925188bd0SMauro Carvalho Chehab return rc; 153025188bd0SMauro Carvalho Chehab val = rc; 153125188bd0SMauro Carvalho Chehab 153225188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val | 0x01); 153325188bd0SMauro Carvalho Chehab if (rc < 0) 153425188bd0SMauro Carvalho Chehab return rc; 153525188bd0SMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, val & 0x06); 153625188bd0SMauro Carvalho Chehab if (rc < 0) 153725188bd0SMauro Carvalho Chehab return rc; 153825188bd0SMauro Carvalho Chehab 153925188bd0SMauro Carvalho Chehab return 0; 154025188bd0SMauro Carvalho Chehab } 154125188bd0SMauro Carvalho Chehab 154209b6d21eSMauro Carvalho Chehab static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) 154309b6d21eSMauro Carvalho Chehab { 154409b6d21eSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 154509b6d21eSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 154609b6d21eSMauro Carvalho Chehab int i; 154709b6d21eSMauro Carvalho Chehab 154809b6d21eSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 154909b6d21eSMauro Carvalho Chehab 155009b6d21eSMauro Carvalho Chehab /* Fill the length of each status counter */ 155109b6d21eSMauro Carvalho Chehab 155209b6d21eSMauro Carvalho Chehab /* Only global stats */ 155309b6d21eSMauro Carvalho Chehab c->strength.len = 1; 155409b6d21eSMauro Carvalho Chehab 155509b6d21eSMauro Carvalho Chehab /* Per-layer stats - 3 layers + global */ 155609b6d21eSMauro Carvalho Chehab c->cnr.len = 4; 155709b6d21eSMauro Carvalho Chehab c->pre_bit_error.len = 4; 155809b6d21eSMauro Carvalho Chehab c->pre_bit_count.len = 4; 1559d9b6f08aSMauro Carvalho Chehab c->post_bit_error.len = 4; 1560d9b6f08aSMauro Carvalho Chehab c->post_bit_count.len = 4; 156109b6d21eSMauro Carvalho Chehab c->block_error.len = 4; 156209b6d21eSMauro Carvalho Chehab c->block_count.len = 4; 156309b6d21eSMauro Carvalho Chehab 156409b6d21eSMauro Carvalho Chehab /* Signal is always available */ 156509b6d21eSMauro Carvalho Chehab c->strength.stat[0].scale = FE_SCALE_RELATIVE; 156609b6d21eSMauro Carvalho Chehab c->strength.stat[0].uvalue = 0; 156709b6d21eSMauro Carvalho Chehab 156809b6d21eSMauro Carvalho Chehab /* Put all of them at FE_SCALE_NOT_AVAILABLE */ 156909b6d21eSMauro Carvalho Chehab for (i = 0; i < 4; i++) { 157009b6d21eSMauro Carvalho Chehab c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 157109b6d21eSMauro Carvalho Chehab c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 157209b6d21eSMauro Carvalho Chehab c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1573d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 1574d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 157509b6d21eSMauro Carvalho Chehab c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 157609b6d21eSMauro Carvalho Chehab c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; 157709b6d21eSMauro Carvalho Chehab } 157809b6d21eSMauro Carvalho Chehab } 157909b6d21eSMauro Carvalho Chehab 158015b1c5a0SMauro Carvalho Chehab static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr) 1581149d518aSMauro Carvalho Chehab { 1582149d518aSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1583149d518aSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1584149d518aSMauro Carvalho Chehab int rc = 0, i; 1585149d518aSMauro Carvalho Chehab u32 bit_error = 0, bit_count = 0; 1586149d518aSMauro Carvalho Chehab u32 t_pre_bit_error = 0, t_pre_bit_count = 0; 1587d9b6f08aSMauro Carvalho Chehab u32 t_post_bit_error = 0, t_post_bit_count = 0; 1588593ae89aSMauro Carvalho Chehab u32 block_error = 0, block_count = 0; 1589593ae89aSMauro Carvalho Chehab u32 t_block_error = 0, t_block_count = 0; 1590d9b6f08aSMauro Carvalho Chehab int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0; 1591d9b6f08aSMauro Carvalho Chehab int per_layers = 0; 1592149d518aSMauro Carvalho Chehab 159325188bd0SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 159425188bd0SMauro Carvalho Chehab 159525188bd0SMauro Carvalho Chehab mb86a20s_get_main_CNR(fe); 159625188bd0SMauro Carvalho Chehab 1597149d518aSMauro Carvalho Chehab /* Get per-layer stats */ 1598593ae89aSMauro Carvalho Chehab mb86a20s_get_blk_error_layer_CNR(fe); 159925188bd0SMauro Carvalho Chehab 160015b1c5a0SMauro Carvalho Chehab /* 160115b1c5a0SMauro Carvalho Chehab * At state 7, only CNR is available 160215b1c5a0SMauro Carvalho Chehab * For BER measures, state=9 is required 160315b1c5a0SMauro Carvalho Chehab * FIXME: we may get MER measures with state=8 160415b1c5a0SMauro Carvalho Chehab */ 160515b1c5a0SMauro Carvalho Chehab if (status_nr < 9) 160615b1c5a0SMauro Carvalho Chehab return 0; 160715b1c5a0SMauro Carvalho Chehab 1608149d518aSMauro Carvalho Chehab for (i = 0; i < 3; i++) { 1609149d518aSMauro Carvalho Chehab if (c->isdbt_layer_enabled & (1 << i)) { 1610149d518aSMauro Carvalho Chehab /* Layer is active and has rc segments */ 1611149d518aSMauro Carvalho Chehab active_layers++; 1612149d518aSMauro Carvalho Chehab 1613149d518aSMauro Carvalho Chehab /* Handle BER before vterbi */ 1614ad0abbf1SMauro Carvalho Chehab rc = mb86a20s_get_pre_ber(fe, i, 1615ad0abbf1SMauro Carvalho Chehab &bit_error, &bit_count); 1616149d518aSMauro Carvalho Chehab if (rc >= 0) { 1617149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1618149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[1 + i].uvalue += bit_error; 1619149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1620149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[1 + i].uvalue += bit_count; 1621149d518aSMauro Carvalho Chehab } else if (rc != -EBUSY) { 1622149d518aSMauro Carvalho Chehab /* 1623149d518aSMauro Carvalho Chehab * If an I/O error happened, 1624149d518aSMauro Carvalho Chehab * measures are now unavailable 1625149d518aSMauro Carvalho Chehab */ 1626149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1627149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1628149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1629149d518aSMauro Carvalho Chehab "%s: Can't get BER for layer %c (error %d).\n", 1630149d518aSMauro Carvalho Chehab __func__, 'A' + i, rc); 1631149d518aSMauro Carvalho Chehab } 1632149d518aSMauro Carvalho Chehab if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1633d9b6f08aSMauro Carvalho Chehab pre_ber_layers++; 1634d9b6f08aSMauro Carvalho Chehab 1635d9b6f08aSMauro Carvalho Chehab /* Handle BER post vterbi */ 1636d9b6f08aSMauro Carvalho Chehab rc = mb86a20s_get_post_ber(fe, i, 1637d9b6f08aSMauro Carvalho Chehab &bit_error, &bit_count); 1638d9b6f08aSMauro Carvalho Chehab if (rc >= 0) { 1639d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1640d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[1 + i].uvalue += bit_error; 1641d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1642d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[1 + i].uvalue += bit_count; 1643d9b6f08aSMauro Carvalho Chehab } else if (rc != -EBUSY) { 1644d9b6f08aSMauro Carvalho Chehab /* 1645d9b6f08aSMauro Carvalho Chehab * If an I/O error happened, 1646d9b6f08aSMauro Carvalho Chehab * measures are now unavailable 1647d9b6f08aSMauro Carvalho Chehab */ 1648d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1649d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1650d9b6f08aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1651d9b6f08aSMauro Carvalho Chehab "%s: Can't get BER for layer %c (error %d).\n", 1652d9b6f08aSMauro Carvalho Chehab __func__, 'A' + i, rc); 1653d9b6f08aSMauro Carvalho Chehab } 1654d9b6f08aSMauro Carvalho Chehab if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1655d9b6f08aSMauro Carvalho Chehab post_ber_layers++; 1656149d518aSMauro Carvalho Chehab 1657593ae89aSMauro Carvalho Chehab /* Handle Block errors for PER/UCB reports */ 1658593ae89aSMauro Carvalho Chehab rc = mb86a20s_get_blk_error(fe, i, 1659593ae89aSMauro Carvalho Chehab &block_error, 1660593ae89aSMauro Carvalho Chehab &block_count); 1661593ae89aSMauro Carvalho Chehab if (rc >= 0) { 1662593ae89aSMauro Carvalho Chehab c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER; 1663593ae89aSMauro Carvalho Chehab c->block_error.stat[1 + i].uvalue += block_error; 1664593ae89aSMauro Carvalho Chehab c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER; 1665593ae89aSMauro Carvalho Chehab c->block_count.stat[1 + i].uvalue += block_count; 1666593ae89aSMauro Carvalho Chehab } else if (rc != -EBUSY) { 1667593ae89aSMauro Carvalho Chehab /* 1668593ae89aSMauro Carvalho Chehab * If an I/O error happened, 1669593ae89aSMauro Carvalho Chehab * measures are now unavailable 1670593ae89aSMauro Carvalho Chehab */ 1671593ae89aSMauro Carvalho Chehab c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1672593ae89aSMauro Carvalho Chehab c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; 1673593ae89aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1674593ae89aSMauro Carvalho Chehab "%s: Can't get PER for layer %c (error %d).\n", 1675593ae89aSMauro Carvalho Chehab __func__, 'A' + i, rc); 1676593ae89aSMauro Carvalho Chehab 1677593ae89aSMauro Carvalho Chehab } 1678593ae89aSMauro Carvalho Chehab if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) 1679593ae89aSMauro Carvalho Chehab per_layers++; 1680593ae89aSMauro Carvalho Chehab 1681d9b6f08aSMauro Carvalho Chehab /* Update total preBER */ 1682149d518aSMauro Carvalho Chehab t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue; 1683149d518aSMauro Carvalho Chehab t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue; 1684593ae89aSMauro Carvalho Chehab 1685d9b6f08aSMauro Carvalho Chehab /* Update total postBER */ 1686d9b6f08aSMauro Carvalho Chehab t_post_bit_error += c->post_bit_error.stat[1 + i].uvalue; 1687d9b6f08aSMauro Carvalho Chehab t_post_bit_count += c->post_bit_count.stat[1 + i].uvalue; 1688d9b6f08aSMauro Carvalho Chehab 1689593ae89aSMauro Carvalho Chehab /* Update total PER */ 1690593ae89aSMauro Carvalho Chehab t_block_error += c->block_error.stat[1 + i].uvalue; 1691593ae89aSMauro Carvalho Chehab t_block_count += c->block_count.stat[1 + i].uvalue; 1692149d518aSMauro Carvalho Chehab } 1693149d518aSMauro Carvalho Chehab } 1694149d518aSMauro Carvalho Chehab 1695149d518aSMauro Carvalho Chehab /* 1696149d518aSMauro Carvalho Chehab * Start showing global count if at least one error count is 1697149d518aSMauro Carvalho Chehab * available. 1698149d518aSMauro Carvalho Chehab */ 1699d9b6f08aSMauro Carvalho Chehab if (pre_ber_layers) { 1700149d518aSMauro Carvalho Chehab /* 1701149d518aSMauro Carvalho Chehab * At least one per-layer BER measure was read. We can now 1702149d518aSMauro Carvalho Chehab * calculate the total BER 1703149d518aSMauro Carvalho Chehab * 1704149d518aSMauro Carvalho Chehab * Total Bit Error/Count is calculated as the sum of the 1705149d518aSMauro Carvalho Chehab * bit errors on all active layers. 1706149d518aSMauro Carvalho Chehab */ 1707149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1708149d518aSMauro Carvalho Chehab c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; 1709149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1710149d518aSMauro Carvalho Chehab c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; 1711f67102c4SMauro Carvalho Chehab } else { 1712f67102c4SMauro Carvalho Chehab c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1713f67102c4SMauro Carvalho Chehab c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1714149d518aSMauro Carvalho Chehab } 1715149d518aSMauro Carvalho Chehab 1716d9b6f08aSMauro Carvalho Chehab /* 1717d9b6f08aSMauro Carvalho Chehab * Start showing global count if at least one error count is 1718d9b6f08aSMauro Carvalho Chehab * available. 1719d9b6f08aSMauro Carvalho Chehab */ 1720d9b6f08aSMauro Carvalho Chehab if (post_ber_layers) { 1721d9b6f08aSMauro Carvalho Chehab /* 1722d9b6f08aSMauro Carvalho Chehab * At least one per-layer BER measure was read. We can now 1723d9b6f08aSMauro Carvalho Chehab * calculate the total BER 1724d9b6f08aSMauro Carvalho Chehab * 1725d9b6f08aSMauro Carvalho Chehab * Total Bit Error/Count is calculated as the sum of the 1726d9b6f08aSMauro Carvalho Chehab * bit errors on all active layers. 1727d9b6f08aSMauro Carvalho Chehab */ 1728d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1729d9b6f08aSMauro Carvalho Chehab c->post_bit_error.stat[0].uvalue = t_post_bit_error; 1730d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1731d9b6f08aSMauro Carvalho Chehab c->post_bit_count.stat[0].uvalue = t_post_bit_count; 1732f67102c4SMauro Carvalho Chehab } else { 1733f67102c4SMauro Carvalho Chehab c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1734f67102c4SMauro Carvalho Chehab c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1735d9b6f08aSMauro Carvalho Chehab } 1736d9b6f08aSMauro Carvalho Chehab 1737593ae89aSMauro Carvalho Chehab if (per_layers) { 1738593ae89aSMauro Carvalho Chehab /* 1739593ae89aSMauro Carvalho Chehab * At least one per-layer UCB measure was read. We can now 1740593ae89aSMauro Carvalho Chehab * calculate the total UCB 1741593ae89aSMauro Carvalho Chehab * 1742593ae89aSMauro Carvalho Chehab * Total block Error/Count is calculated as the sum of the 1743593ae89aSMauro Carvalho Chehab * block errors on all active layers. 1744593ae89aSMauro Carvalho Chehab */ 1745593ae89aSMauro Carvalho Chehab c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1746593ae89aSMauro Carvalho Chehab c->block_error.stat[0].uvalue = t_block_error; 1747593ae89aSMauro Carvalho Chehab c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1748593ae89aSMauro Carvalho Chehab c->block_count.stat[0].uvalue = t_block_count; 1749f67102c4SMauro Carvalho Chehab } else { 1750f67102c4SMauro Carvalho Chehab c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1751f67102c4SMauro Carvalho Chehab c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1752593ae89aSMauro Carvalho Chehab } 1753593ae89aSMauro Carvalho Chehab 1754149d518aSMauro Carvalho Chehab return rc; 1755149d518aSMauro Carvalho Chehab } 175609b6d21eSMauro Carvalho Chehab 175709b6d21eSMauro Carvalho Chehab /* 175809b6d21eSMauro Carvalho Chehab * The functions below are called via DVB callbacks, so they need to 175909b6d21eSMauro Carvalho Chehab * properly use the I2C gate control 176009b6d21eSMauro Carvalho Chehab */ 176109b6d21eSMauro Carvalho Chehab 1762dd4493efSMauro Carvalho Chehab static int mb86a20s_initfe(struct dvb_frontend *fe) 1763dd4493efSMauro Carvalho Chehab { 1764dd4493efSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1765768e6dadSMauro Carvalho Chehab u64 pll; 1766dd4493efSMauro Carvalho Chehab int rc; 1767dd4493efSMauro Carvalho Chehab u8 regD5 = 1; 1768dd4493efSMauro Carvalho Chehab 1769f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1770dd4493efSMauro Carvalho Chehab 1771dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1772dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); 1773dd4493efSMauro Carvalho Chehab 1774dd4493efSMauro Carvalho Chehab /* Initialize the frontend */ 1775768e6dadSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_init1); 1776dd4493efSMauro Carvalho Chehab if (rc < 0) 1777dd4493efSMauro Carvalho Chehab goto err; 1778dd4493efSMauro Carvalho Chehab 1779768e6dadSMauro Carvalho Chehab /* Adjust IF frequency to match tuner */ 1780768e6dadSMauro Carvalho Chehab if (fe->ops.tuner_ops.get_if_frequency) 1781768e6dadSMauro Carvalho Chehab fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq); 1782768e6dadSMauro Carvalho Chehab 1783768e6dadSMauro Carvalho Chehab if (!state->if_freq) 1784768e6dadSMauro Carvalho Chehab state->if_freq = 3300000; 1785768e6dadSMauro Carvalho Chehab 1786768e6dadSMauro Carvalho Chehab /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */ 1787768e6dadSMauro Carvalho Chehab pll = state->if_freq * 1677721600L; 1788768e6dadSMauro Carvalho Chehab do_div(pll, 1628571429L); 1789768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x28, 0x20); 1790768e6dadSMauro Carvalho Chehab if (rc < 0) 1791768e6dadSMauro Carvalho Chehab goto err; 1792768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1793768e6dadSMauro Carvalho Chehab if (rc < 0) 1794768e6dadSMauro Carvalho Chehab goto err; 1795768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1796768e6dadSMauro Carvalho Chehab if (rc < 0) 1797768e6dadSMauro Carvalho Chehab goto err; 1798768e6dadSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1799768e6dadSMauro Carvalho Chehab if (rc < 0) 1800768e6dadSMauro Carvalho Chehab goto err; 1801768e6dadSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s: IF=%d, PLL=0x%06llx\n", 1802768e6dadSMauro Carvalho Chehab __func__, state->if_freq, (long long)pll); 1803768e6dadSMauro Carvalho Chehab 1804dd4493efSMauro Carvalho Chehab if (!state->config->is_serial) { 1805dd4493efSMauro Carvalho Chehab regD5 &= ~1; 1806dd4493efSMauro Carvalho Chehab 1807dd4493efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x50, 0xd5); 1808dd4493efSMauro Carvalho Chehab if (rc < 0) 1809dd4493efSMauro Carvalho Chehab goto err; 1810dd4493efSMauro Carvalho Chehab rc = mb86a20s_writereg(state, 0x51, regD5); 1811dd4493efSMauro Carvalho Chehab if (rc < 0) 1812dd4493efSMauro Carvalho Chehab goto err; 1813dd4493efSMauro Carvalho Chehab } 1814dd4493efSMauro Carvalho Chehab 1815768e6dadSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_init2); 1816768e6dadSMauro Carvalho Chehab if (rc < 0) 1817768e6dadSMauro Carvalho Chehab goto err; 1818768e6dadSMauro Carvalho Chehab 1819768e6dadSMauro Carvalho Chehab 1820dd4493efSMauro Carvalho Chehab err: 1821dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1822dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 1823dd4493efSMauro Carvalho Chehab 1824dd4493efSMauro Carvalho Chehab if (rc < 0) { 1825dd4493efSMauro Carvalho Chehab state->need_init = true; 1826f66d81b5SMauro Carvalho Chehab dev_info(&state->i2c->dev, 1827f66d81b5SMauro Carvalho Chehab "mb86a20s: Init failed. Will try again later\n"); 1828dd4493efSMauro Carvalho Chehab } else { 1829dd4493efSMauro Carvalho Chehab state->need_init = false; 1830f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); 1831dd4493efSMauro Carvalho Chehab } 1832dd4493efSMauro Carvalho Chehab return rc; 1833dd4493efSMauro Carvalho Chehab } 1834dd4493efSMauro Carvalho Chehab 1835dd4493efSMauro Carvalho Chehab static int mb86a20s_set_frontend(struct dvb_frontend *fe) 1836dd4493efSMauro Carvalho Chehab { 1837dd4493efSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 1838768e6dadSMauro Carvalho Chehab int rc, if_freq; 1839dd4493efSMauro Carvalho Chehab #if 0 1840dd4493efSMauro Carvalho Chehab /* 1841dd4493efSMauro Carvalho Chehab * FIXME: Properly implement the set frontend properties 1842dd4493efSMauro Carvalho Chehab */ 1843dd4493efSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1844dd4493efSMauro Carvalho Chehab #endif 1845f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1846dd4493efSMauro Carvalho Chehab 1847dd4493efSMauro Carvalho Chehab /* 1848dd4493efSMauro Carvalho Chehab * Gate should already be opened, but it doesn't hurt to 1849dd4493efSMauro Carvalho Chehab * double-check 1850dd4493efSMauro Carvalho Chehab */ 1851dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1852dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 1853dd4493efSMauro Carvalho Chehab fe->ops.tuner_ops.set_params(fe); 1854dd4493efSMauro Carvalho Chehab 1855768e6dadSMauro Carvalho Chehab if (fe->ops.tuner_ops.get_if_frequency) { 1856768e6dadSMauro Carvalho Chehab fe->ops.tuner_ops.get_if_frequency(fe, &if_freq); 1857768e6dadSMauro Carvalho Chehab 1858768e6dadSMauro Carvalho Chehab /* 1859768e6dadSMauro Carvalho Chehab * If the IF frequency changed, re-initialize the 1860768e6dadSMauro Carvalho Chehab * frontend. This is needed by some drivers like tda18271, 1861768e6dadSMauro Carvalho Chehab * that only sets the IF after receiving a set_params() call 1862768e6dadSMauro Carvalho Chehab */ 1863768e6dadSMauro Carvalho Chehab if (if_freq != state->if_freq) 1864768e6dadSMauro Carvalho Chehab state->need_init = true; 1865768e6dadSMauro Carvalho Chehab } 1866768e6dadSMauro Carvalho Chehab 1867dd4493efSMauro Carvalho Chehab /* 1868dd4493efSMauro Carvalho Chehab * Make it more reliable: if, for some reason, the initial 1869dd4493efSMauro Carvalho Chehab * device initialization doesn't happen, initialize it when 1870dd4493efSMauro Carvalho Chehab * a SBTVD parameters are adjusted. 1871dd4493efSMauro Carvalho Chehab * 1872dd4493efSMauro Carvalho Chehab * Unfortunately, due to a hard to track bug at tda829x/tda18271, 1873dd4493efSMauro Carvalho Chehab * the agc callback logic is not called during DVB attach time, 1874dd4493efSMauro Carvalho Chehab * causing mb86a20s to not be initialized with Kworld SBTVD. 1875dd4493efSMauro Carvalho Chehab * So, this hack is needed, in order to make Kworld SBTVD to work. 1876768e6dadSMauro Carvalho Chehab * 1877768e6dadSMauro Carvalho Chehab * It is also needed to change the IF after the initial init. 1878dd4493efSMauro Carvalho Chehab */ 1879dd4493efSMauro Carvalho Chehab if (state->need_init) 1880dd4493efSMauro Carvalho Chehab mb86a20s_initfe(fe); 1881dd4493efSMauro Carvalho Chehab 1882dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1883dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); 1884d01a8ee3SMauro Carvalho Chehab 1885dd4493efSMauro Carvalho Chehab rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); 188609b6d21eSMauro Carvalho Chehab mb86a20s_reset_counters(fe); 1887d01a8ee3SMauro Carvalho Chehab 1888dd4493efSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1889dd4493efSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 1890dd4493efSMauro Carvalho Chehab 1891dd4493efSMauro Carvalho Chehab return rc; 1892dd4493efSMauro Carvalho Chehab } 1893dd4493efSMauro Carvalho Chehab 189409b6d21eSMauro Carvalho Chehab static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, 1895d36e418aSMauro Carvalho Chehab fe_status_t *status) 1896d36e418aSMauro Carvalho Chehab { 189709b6d21eSMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 189815b1c5a0SMauro Carvalho Chehab int rc, status_nr; 1899d36e418aSMauro Carvalho Chehab 190009b6d21eSMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 1901d36e418aSMauro Carvalho Chehab 1902d36e418aSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1903d36e418aSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0); 1904d36e418aSMauro Carvalho Chehab 190509b6d21eSMauro Carvalho Chehab /* Get lock */ 190615b1c5a0SMauro Carvalho Chehab status_nr = mb86a20s_read_status(fe, status); 190715b1c5a0SMauro Carvalho Chehab if (status_nr < 7) { 190809b6d21eSMauro Carvalho Chehab mb86a20s_stats_not_ready(fe); 190909b6d21eSMauro Carvalho Chehab mb86a20s_reset_frontend_cache(fe); 191009b6d21eSMauro Carvalho Chehab } 191115b1c5a0SMauro Carvalho Chehab if (status_nr < 0) { 1912149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1913149d518aSMauro Carvalho Chehab "%s: Can't read frontend lock status\n", __func__); 191409b6d21eSMauro Carvalho Chehab goto error; 1915149d518aSMauro Carvalho Chehab } 191609b6d21eSMauro Carvalho Chehab 191709b6d21eSMauro Carvalho Chehab /* Get signal strength */ 191809b6d21eSMauro Carvalho Chehab rc = mb86a20s_read_signal_strength(fe); 191909b6d21eSMauro Carvalho Chehab if (rc < 0) { 1920149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1921149d518aSMauro Carvalho Chehab "%s: Can't reset VBER registers.\n", __func__); 192209b6d21eSMauro Carvalho Chehab mb86a20s_stats_not_ready(fe); 192309b6d21eSMauro Carvalho Chehab mb86a20s_reset_frontend_cache(fe); 1924149d518aSMauro Carvalho Chehab 1925149d518aSMauro Carvalho Chehab rc = 0; /* Status is OK */ 192609b6d21eSMauro Carvalho Chehab goto error; 192709b6d21eSMauro Carvalho Chehab } 192809b6d21eSMauro Carvalho Chehab 192915b1c5a0SMauro Carvalho Chehab if (status_nr >= 7) { 193009b6d21eSMauro Carvalho Chehab /* Get TMCC info*/ 193109b6d21eSMauro Carvalho Chehab rc = mb86a20s_get_frontend(fe); 1932149d518aSMauro Carvalho Chehab if (rc < 0) { 1933149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1934149d518aSMauro Carvalho Chehab "%s: Can't get FE TMCC data.\n", __func__); 1935149d518aSMauro Carvalho Chehab rc = 0; /* Status is OK */ 193609b6d21eSMauro Carvalho Chehab goto error; 193709b6d21eSMauro Carvalho Chehab } 193809b6d21eSMauro Carvalho Chehab 1939149d518aSMauro Carvalho Chehab /* Get statistics */ 194015b1c5a0SMauro Carvalho Chehab rc = mb86a20s_get_stats(fe, status_nr); 1941149d518aSMauro Carvalho Chehab if (rc < 0 && rc != -EBUSY) { 1942149d518aSMauro Carvalho Chehab dev_err(&state->i2c->dev, 1943149d518aSMauro Carvalho Chehab "%s: Can't get FE statistics.\n", __func__); 1944149d518aSMauro Carvalho Chehab rc = 0; 1945149d518aSMauro Carvalho Chehab goto error; 1946149d518aSMauro Carvalho Chehab } 1947149d518aSMauro Carvalho Chehab rc = 0; /* Don't return EBUSY to userspace */ 1948149d518aSMauro Carvalho Chehab } 1949149d518aSMauro Carvalho Chehab goto ok; 1950149d518aSMauro Carvalho Chehab 1951149d518aSMauro Carvalho Chehab error: 195209b6d21eSMauro Carvalho Chehab mb86a20s_stats_not_ready(fe); 1953d36e418aSMauro Carvalho Chehab 1954149d518aSMauro Carvalho Chehab ok: 1955d36e418aSMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl) 1956d36e418aSMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 1); 1957149d518aSMauro Carvalho Chehab 195809b6d21eSMauro Carvalho Chehab return rc; 1959d36e418aSMauro Carvalho Chehab } 1960d36e418aSMauro Carvalho Chehab 196109b6d21eSMauro Carvalho Chehab static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, 196209b6d21eSMauro Carvalho Chehab u16 *strength) 196309b6d21eSMauro Carvalho Chehab { 196409b6d21eSMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache; 196509b6d21eSMauro Carvalho Chehab 196609b6d21eSMauro Carvalho Chehab 196709b6d21eSMauro Carvalho Chehab *strength = c->strength.stat[0].uvalue; 196809b6d21eSMauro Carvalho Chehab 196909b6d21eSMauro Carvalho Chehab return 0; 197009b6d21eSMauro Carvalho Chehab } 197109b6d21eSMauro Carvalho Chehab 197209b6d21eSMauro Carvalho Chehab static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe) 197309b6d21eSMauro Carvalho Chehab { 197409b6d21eSMauro Carvalho Chehab /* 197509b6d21eSMauro Carvalho Chehab * get_frontend is now handled together with other stats 197609b6d21eSMauro Carvalho Chehab * retrival, when read_status() is called, as some statistics 197709b6d21eSMauro Carvalho Chehab * will depend on the layers detection. 197809b6d21eSMauro Carvalho Chehab */ 197909b6d21eSMauro Carvalho Chehab return 0; 198009b6d21eSMauro Carvalho Chehab }; 198109b6d21eSMauro Carvalho Chehab 19829a0bf528SMauro Carvalho Chehab static int mb86a20s_tune(struct dvb_frontend *fe, 19839a0bf528SMauro Carvalho Chehab bool re_tune, 19849a0bf528SMauro Carvalho Chehab unsigned int mode_flags, 19859a0bf528SMauro Carvalho Chehab unsigned int *delay, 19869a0bf528SMauro Carvalho Chehab fe_status_t *status) 19879a0bf528SMauro Carvalho Chehab { 1988f66d81b5SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 19899a0bf528SMauro Carvalho Chehab int rc = 0; 19909a0bf528SMauro Carvalho Chehab 1991f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 19929a0bf528SMauro Carvalho Chehab 19939a0bf528SMauro Carvalho Chehab if (re_tune) 19949a0bf528SMauro Carvalho Chehab rc = mb86a20s_set_frontend(fe); 19959a0bf528SMauro Carvalho Chehab 19969a0bf528SMauro Carvalho Chehab if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) 199709b6d21eSMauro Carvalho Chehab mb86a20s_read_status_and_stats(fe, status); 19989a0bf528SMauro Carvalho Chehab 19999a0bf528SMauro Carvalho Chehab return rc; 20009a0bf528SMauro Carvalho Chehab } 20019a0bf528SMauro Carvalho Chehab 20029a0bf528SMauro Carvalho Chehab static void mb86a20s_release(struct dvb_frontend *fe) 20039a0bf528SMauro Carvalho Chehab { 20049a0bf528SMauro Carvalho Chehab struct mb86a20s_state *state = fe->demodulator_priv; 20059a0bf528SMauro Carvalho Chehab 2006f66d81b5SMauro Carvalho Chehab dev_dbg(&state->i2c->dev, "%s called.\n", __func__); 20079a0bf528SMauro Carvalho Chehab 20089a0bf528SMauro Carvalho Chehab kfree(state); 20099a0bf528SMauro Carvalho Chehab } 20109a0bf528SMauro Carvalho Chehab 20119a0bf528SMauro Carvalho Chehab static struct dvb_frontend_ops mb86a20s_ops; 20129a0bf528SMauro Carvalho Chehab 20139a0bf528SMauro Carvalho Chehab struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, 20149a0bf528SMauro Carvalho Chehab struct i2c_adapter *i2c) 20159a0bf528SMauro Carvalho Chehab { 2016f66d81b5SMauro Carvalho Chehab struct mb86a20s_state *state; 20179a0bf528SMauro Carvalho Chehab u8 rev; 20189a0bf528SMauro Carvalho Chehab 2019f167e302SMauro Carvalho Chehab dev_dbg(&i2c->dev, "%s called.\n", __func__); 2020f167e302SMauro Carvalho Chehab 20219a0bf528SMauro Carvalho Chehab /* allocate memory for the internal state */ 2022f66d81b5SMauro Carvalho Chehab state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); 20239a0bf528SMauro Carvalho Chehab if (state == NULL) { 2024f167e302SMauro Carvalho Chehab dev_err(&i2c->dev, 2025f66d81b5SMauro Carvalho Chehab "%s: unable to allocate memory for state\n", __func__); 20269a0bf528SMauro Carvalho Chehab goto error; 20279a0bf528SMauro Carvalho Chehab } 20289a0bf528SMauro Carvalho Chehab 20299a0bf528SMauro Carvalho Chehab /* setup the state */ 20309a0bf528SMauro Carvalho Chehab state->config = config; 20319a0bf528SMauro Carvalho Chehab state->i2c = i2c; 20329a0bf528SMauro Carvalho Chehab 20339a0bf528SMauro Carvalho Chehab /* create dvb_frontend */ 20349a0bf528SMauro Carvalho Chehab memcpy(&state->frontend.ops, &mb86a20s_ops, 20359a0bf528SMauro Carvalho Chehab sizeof(struct dvb_frontend_ops)); 20369a0bf528SMauro Carvalho Chehab state->frontend.demodulator_priv = state; 20379a0bf528SMauro Carvalho Chehab 20389a0bf528SMauro Carvalho Chehab /* Check if it is a mb86a20s frontend */ 20399a0bf528SMauro Carvalho Chehab rev = mb86a20s_readreg(state, 0); 20409a0bf528SMauro Carvalho Chehab 20419a0bf528SMauro Carvalho Chehab if (rev == 0x13) { 2042f167e302SMauro Carvalho Chehab dev_info(&i2c->dev, 2043f66d81b5SMauro Carvalho Chehab "Detected a Fujitsu mb86a20s frontend\n"); 20449a0bf528SMauro Carvalho Chehab } else { 2045f167e302SMauro Carvalho Chehab dev_dbg(&i2c->dev, 2046f66d81b5SMauro Carvalho Chehab "Frontend revision %d is unknown - aborting.\n", 20479a0bf528SMauro Carvalho Chehab rev); 20489a0bf528SMauro Carvalho Chehab goto error; 20499a0bf528SMauro Carvalho Chehab } 20509a0bf528SMauro Carvalho Chehab 20519a0bf528SMauro Carvalho Chehab return &state->frontend; 20529a0bf528SMauro Carvalho Chehab 20539a0bf528SMauro Carvalho Chehab error: 20549a0bf528SMauro Carvalho Chehab kfree(state); 20559a0bf528SMauro Carvalho Chehab return NULL; 20569a0bf528SMauro Carvalho Chehab } 20579a0bf528SMauro Carvalho Chehab EXPORT_SYMBOL(mb86a20s_attach); 20589a0bf528SMauro Carvalho Chehab 20599a0bf528SMauro Carvalho Chehab static struct dvb_frontend_ops mb86a20s_ops = { 20609a0bf528SMauro Carvalho Chehab .delsys = { SYS_ISDBT }, 20619a0bf528SMauro Carvalho Chehab /* Use dib8000 values per default */ 20629a0bf528SMauro Carvalho Chehab .info = { 20639a0bf528SMauro Carvalho Chehab .name = "Fujitsu mb86A20s", 20649a0bf528SMauro Carvalho Chehab .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER | 20659a0bf528SMauro Carvalho Chehab FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 20669a0bf528SMauro Carvalho Chehab FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 20679a0bf528SMauro Carvalho Chehab FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 20689a0bf528SMauro Carvalho Chehab FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | 20699a0bf528SMauro Carvalho Chehab FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 20709a0bf528SMauro Carvalho Chehab /* Actually, those values depend on the used tuner */ 20719a0bf528SMauro Carvalho Chehab .frequency_min = 45000000, 20729a0bf528SMauro Carvalho Chehab .frequency_max = 864000000, 20739a0bf528SMauro Carvalho Chehab .frequency_stepsize = 62500, 20749a0bf528SMauro Carvalho Chehab }, 20759a0bf528SMauro Carvalho Chehab 20769a0bf528SMauro Carvalho Chehab .release = mb86a20s_release, 20779a0bf528SMauro Carvalho Chehab 20789a0bf528SMauro Carvalho Chehab .init = mb86a20s_initfe, 20799a0bf528SMauro Carvalho Chehab .set_frontend = mb86a20s_set_frontend, 208009b6d21eSMauro Carvalho Chehab .get_frontend = mb86a20s_get_frontend_dummy, 208109b6d21eSMauro Carvalho Chehab .read_status = mb86a20s_read_status_and_stats, 208209b6d21eSMauro Carvalho Chehab .read_signal_strength = mb86a20s_read_signal_strength_from_cache, 20839a0bf528SMauro Carvalho Chehab .tune = mb86a20s_tune, 20849a0bf528SMauro Carvalho Chehab }; 20859a0bf528SMauro Carvalho Chehab 20869a0bf528SMauro Carvalho Chehab MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); 20879a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 20889a0bf528SMauro Carvalho Chehab MODULE_LICENSE("GPL"); 2089