1 /* 2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver 3 4 Copyright (C) Manu Abraham (abraham.manu@gmail.com) 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/slab.h> 26 27 #include "dvb_frontend.h" 28 #include "mb86a16.h" 29 #include "mb86a16_priv.h" 30 31 static unsigned int verbose = 5; 32 module_param(verbose, int, 0644); 33 34 #define ABS(x) ((x) < 0 ? (-x) : (x)) 35 36 struct mb86a16_state { 37 struct i2c_adapter *i2c_adap; 38 const struct mb86a16_config *config; 39 struct dvb_frontend frontend; 40 41 /* tuning parameters */ 42 int frequency; 43 int srate; 44 45 /* Internal stuff */ 46 int master_clk; 47 int deci; 48 int csel; 49 int rsel; 50 }; 51 52 #define MB86A16_ERROR 0 53 #define MB86A16_NOTICE 1 54 #define MB86A16_INFO 2 55 #define MB86A16_DEBUG 3 56 57 #define dprintk(x, y, z, format, arg...) do { \ 58 if (z) { \ 59 if ((x > MB86A16_ERROR) && (x > y)) \ 60 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \ 61 else if ((x > MB86A16_NOTICE) && (x > y)) \ 62 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \ 63 else if ((x > MB86A16_INFO) && (x > y)) \ 64 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \ 65 else if ((x > MB86A16_DEBUG) && (x > y)) \ 66 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \ 67 } else { \ 68 if (x > y) \ 69 printk(format, ##arg); \ 70 } \ 71 } while (0) 72 73 #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()") 74 #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->") 75 76 static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) 77 { 78 int ret; 79 u8 buf[] = { reg, val }; 80 81 struct i2c_msg msg = { 82 .addr = state->config->demod_address, 83 .flags = 0, 84 .buf = buf, 85 .len = 2 86 }; 87 88 dprintk(verbose, MB86A16_DEBUG, 1, 89 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]", 90 state->config->demod_address, buf[0], buf[1]); 91 92 ret = i2c_transfer(state->i2c_adap, &msg, 1); 93 94 return (ret != 1) ? -EREMOTEIO : 0; 95 } 96 97 static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) 98 { 99 int ret; 100 u8 b0[] = { reg }; 101 u8 b1[] = { 0 }; 102 103 struct i2c_msg msg[] = { 104 { 105 .addr = state->config->demod_address, 106 .flags = 0, 107 .buf = b0, 108 .len = 1 109 }, { 110 .addr = state->config->demod_address, 111 .flags = I2C_M_RD, 112 .buf = b1, 113 .len = 1 114 } 115 }; 116 ret = i2c_transfer(state->i2c_adap, msg, 2); 117 if (ret != 2) { 118 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)", 119 reg, ret); 120 121 if (ret < 0) 122 return ret; 123 return -EREMOTEIO; 124 } 125 *val = b1[0]; 126 127 return ret; 128 } 129 130 static int CNTM_set(struct mb86a16_state *state, 131 unsigned char timint1, 132 unsigned char timint2, 133 unsigned char cnext) 134 { 135 unsigned char val; 136 137 val = (timint1 << 4) | (timint2 << 2) | cnext; 138 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0) 139 goto err; 140 141 return 0; 142 143 err: 144 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 145 return -EREMOTEIO; 146 } 147 148 static int smrt_set(struct mb86a16_state *state, int rate) 149 { 150 int tmp ; 151 int m ; 152 unsigned char STOFS0, STOFS1; 153 154 m = 1 << state->deci; 155 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk; 156 157 STOFS0 = tmp & 0x0ff; 158 STOFS1 = (tmp & 0xf00) >> 8; 159 160 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) | 161 (state->csel << 1) | 162 state->rsel) < 0) 163 goto err; 164 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0) 165 goto err; 166 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0) 167 goto err; 168 169 return 0; 170 err: 171 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 172 return -1; 173 } 174 175 static int srst(struct mb86a16_state *state) 176 { 177 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0) 178 goto err; 179 180 return 0; 181 err: 182 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 183 return -EREMOTEIO; 184 185 } 186 187 static int afcex_data_set(struct mb86a16_state *state, 188 unsigned char AFCEX_L, 189 unsigned char AFCEX_H) 190 { 191 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0) 192 goto err; 193 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0) 194 goto err; 195 196 return 0; 197 err: 198 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 199 200 return -1; 201 } 202 203 static int afcofs_data_set(struct mb86a16_state *state, 204 unsigned char AFCEX_L, 205 unsigned char AFCEX_H) 206 { 207 if (mb86a16_write(state, 0x58, AFCEX_L) < 0) 208 goto err; 209 if (mb86a16_write(state, 0x59, AFCEX_H) < 0) 210 goto err; 211 212 return 0; 213 err: 214 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 215 return -EREMOTEIO; 216 } 217 218 static int stlp_set(struct mb86a16_state *state, 219 unsigned char STRAS, 220 unsigned char STRBS) 221 { 222 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0) 223 goto err; 224 225 return 0; 226 err: 227 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 228 return -EREMOTEIO; 229 } 230 231 static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA) 232 { 233 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0) 234 goto err; 235 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0) 236 goto err; 237 238 return 0; 239 err: 240 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 241 return -EREMOTEIO; 242 } 243 244 static int initial_set(struct mb86a16_state *state) 245 { 246 if (stlp_set(state, 5, 7)) 247 goto err; 248 249 udelay(100); 250 if (afcex_data_set(state, 0, 0)) 251 goto err; 252 253 udelay(100); 254 if (afcofs_data_set(state, 0, 0)) 255 goto err; 256 257 udelay(100); 258 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0) 259 goto err; 260 if (mb86a16_write(state, 0x2f, 0x21) < 0) 261 goto err; 262 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0) 263 goto err; 264 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0) 265 goto err; 266 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0) 267 goto err; 268 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0) 269 goto err; 270 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0) 271 goto err; 272 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0) 273 goto err; 274 if (mb86a16_write(state, 0x54, 0xff) < 0) 275 goto err; 276 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0) 277 goto err; 278 279 return 0; 280 281 err: 282 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 283 return -EREMOTEIO; 284 } 285 286 static int S01T_set(struct mb86a16_state *state, 287 unsigned char s1t, 288 unsigned s0t) 289 { 290 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0) 291 goto err; 292 293 return 0; 294 err: 295 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 296 return -EREMOTEIO; 297 } 298 299 300 static int EN_set(struct mb86a16_state *state, 301 int cren, 302 int afcen) 303 { 304 unsigned char val; 305 306 val = 0x7a | (cren << 7) | (afcen << 2); 307 if (mb86a16_write(state, 0x49, val) < 0) 308 goto err; 309 310 return 0; 311 err: 312 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 313 return -EREMOTEIO; 314 } 315 316 static int AFCEXEN_set(struct mb86a16_state *state, 317 int afcexen, 318 int smrt) 319 { 320 unsigned char AFCA ; 321 322 if (smrt > 18875) 323 AFCA = 4; 324 else if (smrt > 9375) 325 AFCA = 3; 326 else if (smrt > 2250) 327 AFCA = 2; 328 else 329 AFCA = 1; 330 331 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0) 332 goto err; 333 334 return 0; 335 336 err: 337 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 338 return -EREMOTEIO; 339 } 340 341 static int DAGC_data_set(struct mb86a16_state *state, 342 unsigned char DAGCA, 343 unsigned char DAGCW) 344 { 345 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0) 346 goto err; 347 348 return 0; 349 350 err: 351 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 352 return -EREMOTEIO; 353 } 354 355 static void smrt_info_get(struct mb86a16_state *state, int rate) 356 { 357 if (rate >= 37501) { 358 state->deci = 0; state->csel = 0; state->rsel = 0; 359 } else if (rate >= 30001) { 360 state->deci = 0; state->csel = 0; state->rsel = 1; 361 } else if (rate >= 26251) { 362 state->deci = 0; state->csel = 1; state->rsel = 0; 363 } else if (rate >= 22501) { 364 state->deci = 0; state->csel = 1; state->rsel = 1; 365 } else if (rate >= 18751) { 366 state->deci = 1; state->csel = 0; state->rsel = 0; 367 } else if (rate >= 15001) { 368 state->deci = 1; state->csel = 0; state->rsel = 1; 369 } else if (rate >= 13126) { 370 state->deci = 1; state->csel = 1; state->rsel = 0; 371 } else if (rate >= 11251) { 372 state->deci = 1; state->csel = 1; state->rsel = 1; 373 } else if (rate >= 9376) { 374 state->deci = 2; state->csel = 0; state->rsel = 0; 375 } else if (rate >= 7501) { 376 state->deci = 2; state->csel = 0; state->rsel = 1; 377 } else if (rate >= 6563) { 378 state->deci = 2; state->csel = 1; state->rsel = 0; 379 } else if (rate >= 5626) { 380 state->deci = 2; state->csel = 1; state->rsel = 1; 381 } else if (rate >= 4688) { 382 state->deci = 3; state->csel = 0; state->rsel = 0; 383 } else if (rate >= 3751) { 384 state->deci = 3; state->csel = 0; state->rsel = 1; 385 } else if (rate >= 3282) { 386 state->deci = 3; state->csel = 1; state->rsel = 0; 387 } else if (rate >= 2814) { 388 state->deci = 3; state->csel = 1; state->rsel = 1; 389 } else if (rate >= 2344) { 390 state->deci = 4; state->csel = 0; state->rsel = 0; 391 } else if (rate >= 1876) { 392 state->deci = 4; state->csel = 0; state->rsel = 1; 393 } else if (rate >= 1641) { 394 state->deci = 4; state->csel = 1; state->rsel = 0; 395 } else if (rate >= 1407) { 396 state->deci = 4; state->csel = 1; state->rsel = 1; 397 } else if (rate >= 1172) { 398 state->deci = 5; state->csel = 0; state->rsel = 0; 399 } else if (rate >= 939) { 400 state->deci = 5; state->csel = 0; state->rsel = 1; 401 } else if (rate >= 821) { 402 state->deci = 5; state->csel = 1; state->rsel = 0; 403 } else { 404 state->deci = 5; state->csel = 1; state->rsel = 1; 405 } 406 407 if (state->csel == 0) 408 state->master_clk = 92000; 409 else 410 state->master_clk = 61333; 411 412 } 413 414 static int signal_det(struct mb86a16_state *state, 415 int smrt, 416 unsigned char *SIG) 417 { 418 419 int ret ; 420 int smrtd ; 421 int wait_sym ; 422 423 u32 wait_t; 424 unsigned char S[3] ; 425 int i ; 426 427 if (*SIG > 45) { 428 if (CNTM_set(state, 2, 1, 2) < 0) { 429 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 430 return -1; 431 } 432 wait_sym = 40000; 433 } else { 434 if (CNTM_set(state, 3, 1, 2) < 0) { 435 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 436 return -1; 437 } 438 wait_sym = 80000; 439 } 440 for (i = 0; i < 3; i++) { 441 if (i == 0) 442 smrtd = smrt * 98 / 100; 443 else if (i == 1) 444 smrtd = smrt; 445 else 446 smrtd = smrt * 102 / 100; 447 smrt_info_get(state, smrtd); 448 smrt_set(state, smrtd); 449 srst(state); 450 wait_t = (wait_sym + 99 * smrtd / 100) / smrtd; 451 if (wait_t == 0) 452 wait_t = 1; 453 msleep_interruptible(10); 454 if (mb86a16_read(state, 0x37, &(S[i])) != 2) { 455 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 456 return -EREMOTEIO; 457 } 458 } 459 if ((S[1] > S[0] * 112 / 100) && 460 (S[1] > S[2] * 112 / 100)) { 461 462 ret = 1; 463 } else { 464 ret = 0; 465 } 466 *SIG = S[1]; 467 468 if (CNTM_set(state, 0, 1, 2) < 0) { 469 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 470 return -1; 471 } 472 473 return ret; 474 } 475 476 static int rf_val_set(struct mb86a16_state *state, 477 int f, 478 int smrt, 479 unsigned char R) 480 { 481 unsigned char C, F, B; 482 int M; 483 unsigned char rf_val[5]; 484 int ack = -1; 485 486 if (smrt > 37750) 487 C = 1; 488 else if (smrt > 18875) 489 C = 2; 490 else if (smrt > 5500) 491 C = 3; 492 else 493 C = 4; 494 495 if (smrt > 30500) 496 F = 3; 497 else if (smrt > 9375) 498 F = 1; 499 else if (smrt > 4625) 500 F = 0; 501 else 502 F = 2; 503 504 if (f < 1060) 505 B = 0; 506 else if (f < 1175) 507 B = 1; 508 else if (f < 1305) 509 B = 2; 510 else if (f < 1435) 511 B = 3; 512 else if (f < 1570) 513 B = 4; 514 else if (f < 1715) 515 B = 5; 516 else if (f < 1845) 517 B = 6; 518 else if (f < 1980) 519 B = 7; 520 else if (f < 2080) 521 B = 8; 522 else 523 B = 9; 524 525 M = f * (1 << R) / 2; 526 527 rf_val[0] = 0x01 | (C << 3) | (F << 1); 528 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12); 529 rf_val[2] = (M & 0x00ff0) >> 4; 530 rf_val[3] = ((M & 0x0000f) << 4) | B; 531 532 /* Frequency Set */ 533 if (mb86a16_write(state, 0x21, rf_val[0]) < 0) 534 ack = 0; 535 if (mb86a16_write(state, 0x22, rf_val[1]) < 0) 536 ack = 0; 537 if (mb86a16_write(state, 0x23, rf_val[2]) < 0) 538 ack = 0; 539 if (mb86a16_write(state, 0x24, rf_val[3]) < 0) 540 ack = 0; 541 if (mb86a16_write(state, 0x25, 0x01) < 0) 542 ack = 0; 543 if (ack == 0) { 544 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error"); 545 return -EREMOTEIO; 546 } 547 548 return 0; 549 } 550 551 static int afcerr_chk(struct mb86a16_state *state) 552 { 553 unsigned char AFCM_L, AFCM_H ; 554 int AFCM ; 555 int afcm, afcerr ; 556 557 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2) 558 goto err; 559 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2) 560 goto err; 561 562 AFCM = (AFCM_H << 8) + AFCM_L; 563 564 if (AFCM > 2048) 565 afcm = AFCM - 4096; 566 else 567 afcm = AFCM; 568 afcerr = afcm * state->master_clk / 8192; 569 570 return afcerr; 571 572 err: 573 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 574 return -EREMOTEIO; 575 } 576 577 static int dagcm_val_get(struct mb86a16_state *state) 578 { 579 int DAGCM; 580 unsigned char DAGCM_H, DAGCM_L; 581 582 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2) 583 goto err; 584 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2) 585 goto err; 586 587 DAGCM = (DAGCM_H << 8) + DAGCM_L; 588 589 return DAGCM; 590 591 err: 592 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 593 return -EREMOTEIO; 594 } 595 596 static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status) 597 { 598 u8 stat, stat2; 599 struct mb86a16_state *state = fe->demodulator_priv; 600 601 *status = 0; 602 603 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2) 604 goto err; 605 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2) 606 goto err; 607 if ((stat > 25) && (stat2 > 25)) 608 *status |= FE_HAS_SIGNAL; 609 if ((stat > 45) && (stat2 > 45)) 610 *status |= FE_HAS_CARRIER; 611 612 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2) 613 goto err; 614 615 if (stat & 0x01) 616 *status |= FE_HAS_SYNC; 617 if (stat & 0x01) 618 *status |= FE_HAS_VITERBI; 619 620 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2) 621 goto err; 622 623 if ((stat & 0x0f) && (*status & FE_HAS_VITERBI)) 624 *status |= FE_HAS_LOCK; 625 626 return 0; 627 628 err: 629 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 630 return -EREMOTEIO; 631 } 632 633 static int sync_chk(struct mb86a16_state *state, 634 unsigned char *VIRM) 635 { 636 unsigned char val; 637 int sync; 638 639 if (mb86a16_read(state, 0x0d, &val) != 2) 640 goto err; 641 642 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val); 643 sync = val & 0x01; 644 *VIRM = (val & 0x1c) >> 2; 645 646 return sync; 647 err: 648 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 649 return -EREMOTEIO; 650 651 } 652 653 static int freqerr_chk(struct mb86a16_state *state, 654 int fTP, 655 int smrt, 656 int unit) 657 { 658 unsigned char CRM, AFCML, AFCMH; 659 unsigned char temp1, temp2, temp3; 660 int crm, afcm, AFCM; 661 int crrerr, afcerr; /* kHz */ 662 int frqerr; /* MHz */ 663 int afcen, afcexen = 0; 664 int R, M, fOSC, fOSC_OFS; 665 666 if (mb86a16_read(state, 0x43, &CRM) != 2) 667 goto err; 668 669 if (CRM > 127) 670 crm = CRM - 256; 671 else 672 crm = CRM; 673 674 crrerr = smrt * crm / 256; 675 if (mb86a16_read(state, 0x49, &temp1) != 2) 676 goto err; 677 678 afcen = (temp1 & 0x04) >> 2; 679 if (afcen == 0) { 680 if (mb86a16_read(state, 0x2a, &temp1) != 2) 681 goto err; 682 afcexen = (temp1 & 0x20) >> 5; 683 } 684 685 if (afcen == 1) { 686 if (mb86a16_read(state, 0x0e, &AFCML) != 2) 687 goto err; 688 if (mb86a16_read(state, 0x0f, &AFCMH) != 2) 689 goto err; 690 } else if (afcexen == 1) { 691 if (mb86a16_read(state, 0x2b, &AFCML) != 2) 692 goto err; 693 if (mb86a16_read(state, 0x2c, &AFCMH) != 2) 694 goto err; 695 } 696 if ((afcen == 1) || (afcexen == 1)) { 697 smrt_info_get(state, smrt); 698 AFCM = ((AFCMH & 0x01) << 8) + AFCML; 699 if (AFCM > 255) 700 afcm = AFCM - 512; 701 else 702 afcm = AFCM; 703 704 afcerr = afcm * state->master_clk / 8192; 705 } else 706 afcerr = 0; 707 708 if (mb86a16_read(state, 0x22, &temp1) != 2) 709 goto err; 710 if (mb86a16_read(state, 0x23, &temp2) != 2) 711 goto err; 712 if (mb86a16_read(state, 0x24, &temp3) != 2) 713 goto err; 714 715 R = (temp1 & 0xe0) >> 5; 716 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4); 717 if (R == 0) 718 fOSC = 2 * M; 719 else 720 fOSC = M; 721 722 fOSC_OFS = fOSC - fTP; 723 724 if (unit == 0) { /* MHz */ 725 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0) 726 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000; 727 else 728 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000; 729 } else { /* kHz */ 730 frqerr = crrerr + afcerr + fOSC_OFS * 1000; 731 } 732 733 return frqerr; 734 err: 735 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 736 return -EREMOTEIO; 737 } 738 739 static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt) 740 { 741 unsigned char R; 742 743 if (smrt > 9375) 744 R = 0; 745 else 746 R = 1; 747 748 return R; 749 } 750 751 static void swp_info_get(struct mb86a16_state *state, 752 int fOSC_start, 753 int smrt, 754 int v, int R, 755 int swp_ofs, 756 int *fOSC, 757 int *afcex_freq, 758 unsigned char *AFCEX_L, 759 unsigned char *AFCEX_H) 760 { 761 int AFCEX ; 762 int crnt_swp_freq ; 763 764 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; 765 766 if (R == 0) 767 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2; 768 else 769 *fOSC = (crnt_swp_freq + 500) / 1000; 770 771 if (*fOSC >= crnt_swp_freq) 772 *afcex_freq = *fOSC * 1000 - crnt_swp_freq; 773 else 774 *afcex_freq = crnt_swp_freq - *fOSC * 1000; 775 776 AFCEX = *afcex_freq * 8192 / state->master_clk; 777 *AFCEX_L = AFCEX & 0x00ff; 778 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 779 } 780 781 782 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin, 783 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1) 784 { 785 int swp_freq ; 786 787 if ((i % 2 == 1) && (v <= vmax)) { 788 /* positive v (case 1) */ 789 if ((v - 1 == vmin) && 790 (*(V + 30 + v) >= 0) && 791 (*(V + 30 + v - 1) >= 0) && 792 (*(V + 30 + v - 1) > *(V + 30 + v)) && 793 (*(V + 30 + v - 1) > SIGMIN)) { 794 795 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 796 *SIG1 = *(V + 30 + v - 1); 797 } else if ((v == vmax) && 798 (*(V + 30 + v) >= 0) && 799 (*(V + 30 + v - 1) >= 0) && 800 (*(V + 30 + v) > *(V + 30 + v - 1)) && 801 (*(V + 30 + v) > SIGMIN)) { 802 /* (case 2) */ 803 swp_freq = fOSC * 1000 + afcex_freq; 804 *SIG1 = *(V + 30 + v); 805 } else if ((*(V + 30 + v) > 0) && 806 (*(V + 30 + v - 1) > 0) && 807 (*(V + 30 + v - 2) > 0) && 808 (*(V + 30 + v - 3) > 0) && 809 (*(V + 30 + v - 1) > *(V + 30 + v)) && 810 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) && 811 ((*(V + 30 + v - 1) > SIGMIN) || 812 (*(V + 30 + v - 2) > SIGMIN))) { 813 /* (case 3) */ 814 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) { 815 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 816 *SIG1 = *(V + 30 + v - 1); 817 } else { 818 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2; 819 *SIG1 = *(V + 30 + v - 2); 820 } 821 } else if ((v == vmax) && 822 (*(V + 30 + v) >= 0) && 823 (*(V + 30 + v - 1) >= 0) && 824 (*(V + 30 + v - 2) >= 0) && 825 (*(V + 30 + v) > *(V + 30 + v - 2)) && 826 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) && 827 ((*(V + 30 + v) > SIGMIN) || 828 (*(V + 30 + v - 1) > SIGMIN))) { 829 /* (case 4) */ 830 if (*(V + 30 + v) >= *(V + 30 + v - 1)) { 831 swp_freq = fOSC * 1000 + afcex_freq; 832 *SIG1 = *(V + 30 + v); 833 } else { 834 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 835 *SIG1 = *(V + 30 + v - 1); 836 } 837 } else { 838 swp_freq = -1 ; 839 } 840 } else if ((i % 2 == 0) && (v >= vmin)) { 841 /* Negative v (case 1) */ 842 if ((*(V + 30 + v) > 0) && 843 (*(V + 30 + v + 1) > 0) && 844 (*(V + 30 + v + 2) > 0) && 845 (*(V + 30 + v + 1) > *(V + 30 + v)) && 846 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 847 (*(V + 30 + v + 1) > SIGMIN)) { 848 849 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 850 *SIG1 = *(V + 30 + v + 1); 851 } else if ((v + 1 == vmax) && 852 (*(V + 30 + v) >= 0) && 853 (*(V + 30 + v + 1) >= 0) && 854 (*(V + 30 + v + 1) > *(V + 30 + v)) && 855 (*(V + 30 + v + 1) > SIGMIN)) { 856 /* (case 2) */ 857 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 858 *SIG1 = *(V + 30 + v); 859 } else if ((v == vmin) && 860 (*(V + 30 + v) > 0) && 861 (*(V + 30 + v + 1) > 0) && 862 (*(V + 30 + v + 2) > 0) && 863 (*(V + 30 + v) > *(V + 30 + v + 1)) && 864 (*(V + 30 + v) > *(V + 30 + v + 2)) && 865 (*(V + 30 + v) > SIGMIN)) { 866 /* (case 3) */ 867 swp_freq = fOSC * 1000 + afcex_freq; 868 *SIG1 = *(V + 30 + v); 869 } else if ((*(V + 30 + v) >= 0) && 870 (*(V + 30 + v + 1) >= 0) && 871 (*(V + 30 + v + 2) >= 0) && 872 (*(V + 30 + v + 3) >= 0) && 873 (*(V + 30 + v + 1) > *(V + 30 + v)) && 874 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) && 875 ((*(V + 30 + v + 1) > SIGMIN) || 876 (*(V + 30 + v + 2) > SIGMIN))) { 877 /* (case 4) */ 878 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 879 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 880 *SIG1 = *(V + 30 + v + 1); 881 } else { 882 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 883 *SIG1 = *(V + 30 + v + 2); 884 } 885 } else if ((*(V + 30 + v) >= 0) && 886 (*(V + 30 + v + 1) >= 0) && 887 (*(V + 30 + v + 2) >= 0) && 888 (*(V + 30 + v + 3) >= 0) && 889 (*(V + 30 + v) > *(V + 30 + v + 2)) && 890 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 891 (*(V + 30 + v) > *(V + 30 + v + 3)) && 892 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) && 893 ((*(V + 30 + v) > SIGMIN) || 894 (*(V + 30 + v + 1) > SIGMIN))) { 895 /* (case 5) */ 896 if (*(V + 30 + v) >= *(V + 30 + v + 1)) { 897 swp_freq = fOSC * 1000 + afcex_freq; 898 *SIG1 = *(V + 30 + v); 899 } else { 900 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 901 *SIG1 = *(V + 30 + v + 1); 902 } 903 } else if ((v + 2 == vmin) && 904 (*(V + 30 + v) >= 0) && 905 (*(V + 30 + v + 1) >= 0) && 906 (*(V + 30 + v + 2) >= 0) && 907 (*(V + 30 + v + 1) > *(V + 30 + v)) && 908 (*(V + 30 + v + 2) > *(V + 30 + v)) && 909 ((*(V + 30 + v + 1) > SIGMIN) || 910 (*(V + 30 + v + 2) > SIGMIN))) { 911 /* (case 6) */ 912 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 913 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 914 *SIG1 = *(V + 30 + v + 1); 915 } else { 916 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 917 *SIG1 = *(V + 30 + v + 2); 918 } 919 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) { 920 swp_freq = fOSC * 1000; 921 *SIG1 = *(V + 30 + v); 922 } else 923 swp_freq = -1; 924 } else 925 swp_freq = -1; 926 927 return swp_freq; 928 } 929 930 static void swp_info_get2(struct mb86a16_state *state, 931 int smrt, 932 int R, 933 int swp_freq, 934 int *afcex_freq, 935 int *fOSC, 936 unsigned char *AFCEX_L, 937 unsigned char *AFCEX_H) 938 { 939 int AFCEX ; 940 941 if (R == 0) 942 *fOSC = (swp_freq + 1000) / 2000 * 2; 943 else 944 *fOSC = (swp_freq + 500) / 1000; 945 946 if (*fOSC >= swp_freq) 947 *afcex_freq = *fOSC * 1000 - swp_freq; 948 else 949 *afcex_freq = swp_freq - *fOSC * 1000; 950 951 AFCEX = *afcex_freq * 8192 / state->master_clk; 952 *AFCEX_L = AFCEX & 0x00ff; 953 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 954 } 955 956 static void afcex_info_get(struct mb86a16_state *state, 957 int afcex_freq, 958 unsigned char *AFCEX_L, 959 unsigned char *AFCEX_H) 960 { 961 int AFCEX ; 962 963 AFCEX = afcex_freq * 8192 / state->master_clk; 964 *AFCEX_L = AFCEX & 0x00ff; 965 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 966 } 967 968 static int SEQ_set(struct mb86a16_state *state, unsigned char loop) 969 { 970 /* SLOCK0 = 0 */ 971 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) { 972 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 973 return -EREMOTEIO; 974 } 975 976 return 0; 977 } 978 979 static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV) 980 { 981 /* Viterbi Rate, IQ Settings */ 982 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) { 983 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 984 return -EREMOTEIO; 985 } 986 987 return 0; 988 } 989 990 static int FEC_srst(struct mb86a16_state *state) 991 { 992 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) { 993 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 994 return -EREMOTEIO; 995 } 996 997 return 0; 998 } 999 1000 static int S2T_set(struct mb86a16_state *state, unsigned char S2T) 1001 { 1002 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) { 1003 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1004 return -EREMOTEIO; 1005 } 1006 1007 return 0; 1008 } 1009 1010 static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T) 1011 { 1012 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) { 1013 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1014 return -EREMOTEIO; 1015 } 1016 1017 return 0; 1018 } 1019 1020 1021 static int mb86a16_set_fe(struct mb86a16_state *state) 1022 { 1023 u8 agcval, cnmval; 1024 1025 int i, j; 1026 int fOSC = 0; 1027 int fOSC_start = 0; 1028 int wait_t; 1029 int fcp; 1030 int swp_ofs; 1031 int V[60]; 1032 u8 SIG1MIN; 1033 1034 unsigned char CREN, AFCEN, AFCEXEN; 1035 unsigned char SIG1; 1036 unsigned char TIMINT1, TIMINT2, TIMEXT; 1037 unsigned char S0T, S1T; 1038 unsigned char S2T; 1039 /* unsigned char S2T, S3T; */ 1040 unsigned char S4T, S5T; 1041 unsigned char AFCEX_L, AFCEX_H; 1042 unsigned char R; 1043 unsigned char VIRM; 1044 unsigned char ETH, VIA; 1045 unsigned char junk; 1046 1047 int loop; 1048 int ftemp; 1049 int v, vmax, vmin; 1050 int vmax_his, vmin_his; 1051 int swp_freq, prev_swp_freq[20]; 1052 int prev_freq_num; 1053 int signal_dupl; 1054 int afcex_freq; 1055 int signal; 1056 int afcerr; 1057 int temp_freq, delta_freq; 1058 int dagcm[4]; 1059 int smrt_d; 1060 /* int freq_err; */ 1061 int n; 1062 int ret = -1; 1063 int sync; 1064 1065 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate); 1066 1067 fcp = 3000; 1068 swp_ofs = state->srate / 4; 1069 1070 for (i = 0; i < 60; i++) 1071 V[i] = -1; 1072 1073 for (i = 0; i < 20; i++) 1074 prev_swp_freq[i] = 0; 1075 1076 SIG1MIN = 25; 1077 1078 for (n = 0; ((n < 3) && (ret == -1)); n++) { 1079 SEQ_set(state, 0); 1080 iq_vt_set(state, 0); 1081 1082 CREN = 0; 1083 AFCEN = 0; 1084 AFCEXEN = 1; 1085 TIMINT1 = 0; 1086 TIMINT2 = 1; 1087 TIMEXT = 2; 1088 S1T = 0; 1089 S0T = 0; 1090 1091 if (initial_set(state) < 0) { 1092 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed"); 1093 return -1; 1094 } 1095 if (DAGC_data_set(state, 3, 2) < 0) { 1096 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1097 return -1; 1098 } 1099 if (EN_set(state, CREN, AFCEN) < 0) { 1100 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1101 return -1; /* (0, 0) */ 1102 } 1103 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1104 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1105 return -1; /* (1, smrt) = (1, symbolrate) */ 1106 } 1107 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) { 1108 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error"); 1109 return -1; /* (0, 1, 2) */ 1110 } 1111 if (S01T_set(state, S1T, S0T) < 0) { 1112 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1113 return -1; /* (0, 0) */ 1114 } 1115 smrt_info_get(state, state->srate); 1116 if (smrt_set(state, state->srate) < 0) { 1117 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error"); 1118 return -1; 1119 } 1120 1121 R = vco_dev_get(state, state->srate); 1122 if (R == 1) 1123 fOSC_start = state->frequency; 1124 1125 else if (R == 0) { 1126 if (state->frequency % 2 == 0) { 1127 fOSC_start = state->frequency; 1128 } else { 1129 fOSC_start = state->frequency + 1; 1130 if (fOSC_start > 2150) 1131 fOSC_start = state->frequency - 1; 1132 } 1133 } 1134 loop = 1; 1135 ftemp = fOSC_start * 1000; 1136 vmax = 0 ; 1137 while (loop == 1) { 1138 ftemp = ftemp + swp_ofs; 1139 vmax++; 1140 1141 /* Upper bound */ 1142 if (ftemp > 2150000) { 1143 loop = 0; 1144 vmax--; 1145 } else { 1146 if ((ftemp == 2150000) || 1147 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4)) 1148 loop = 0; 1149 } 1150 } 1151 1152 loop = 1; 1153 ftemp = fOSC_start * 1000; 1154 vmin = 0 ; 1155 while (loop == 1) { 1156 ftemp = ftemp - swp_ofs; 1157 vmin--; 1158 1159 /* Lower bound */ 1160 if (ftemp < 950000) { 1161 loop = 0; 1162 vmin++; 1163 } else { 1164 if ((ftemp == 950000) || 1165 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4)) 1166 loop = 0; 1167 } 1168 } 1169 1170 wait_t = (8000 + state->srate / 2) / state->srate; 1171 if (wait_t == 0) 1172 wait_t = 1; 1173 1174 i = 0; 1175 j = 0; 1176 prev_freq_num = 0; 1177 loop = 1; 1178 signal = 0; 1179 vmax_his = 0; 1180 vmin_his = 0; 1181 v = 0; 1182 1183 while (loop == 1) { 1184 swp_info_get(state, fOSC_start, state->srate, 1185 v, R, swp_ofs, &fOSC, 1186 &afcex_freq, &AFCEX_L, &AFCEX_H); 1187 1188 udelay(100); 1189 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1190 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1191 return -1; 1192 } 1193 udelay(100); 1194 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1195 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1196 return -1; 1197 } 1198 if (srst(state) < 0) { 1199 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1200 return -1; 1201 } 1202 msleep_interruptible(wait_t); 1203 1204 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1205 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1206 return -1; 1207 } 1208 V[30 + v] = SIG1 ; 1209 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin, 1210 SIG1MIN, fOSC, afcex_freq, 1211 swp_ofs, &SIG1); /* changed */ 1212 1213 signal_dupl = 0; 1214 for (j = 0; j < prev_freq_num; j++) { 1215 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) { 1216 signal_dupl = 1; 1217 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j); 1218 } 1219 } 1220 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) { 1221 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate); 1222 prev_swp_freq[prev_freq_num] = swp_freq; 1223 prev_freq_num++; 1224 swp_info_get2(state, state->srate, R, swp_freq, 1225 &afcex_freq, &fOSC, 1226 &AFCEX_L, &AFCEX_H); 1227 1228 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1229 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1230 return -1; 1231 } 1232 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1233 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1234 return -1; 1235 } 1236 signal = signal_det(state, state->srate, &SIG1); 1237 if (signal == 1) { 1238 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****"); 1239 loop = 0; 1240 } else { 1241 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again..."); 1242 smrt_info_get(state, state->srate); 1243 if (smrt_set(state, state->srate) < 0) { 1244 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1245 return -1; 1246 } 1247 } 1248 } 1249 if (v > vmax) 1250 vmax_his = 1 ; 1251 if (v < vmin) 1252 vmin_his = 1 ; 1253 i++; 1254 1255 if ((i % 2 == 1) && (vmax_his == 1)) 1256 i++; 1257 if ((i % 2 == 0) && (vmin_his == 1)) 1258 i++; 1259 1260 if (i % 2 == 1) 1261 v = (i + 1) / 2; 1262 else 1263 v = -i / 2; 1264 1265 if ((vmax_his == 1) && (vmin_his == 1)) 1266 loop = 0 ; 1267 } 1268 1269 if (signal == 1) { 1270 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check"); 1271 S1T = 7 ; 1272 S0T = 1 ; 1273 CREN = 0 ; 1274 AFCEN = 1 ; 1275 AFCEXEN = 0 ; 1276 1277 if (S01T_set(state, S1T, S0T) < 0) { 1278 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1279 return -1; 1280 } 1281 smrt_info_get(state, state->srate); 1282 if (smrt_set(state, state->srate) < 0) { 1283 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1284 return -1; 1285 } 1286 if (EN_set(state, CREN, AFCEN) < 0) { 1287 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1288 return -1; 1289 } 1290 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1291 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1292 return -1; 1293 } 1294 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H); 1295 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1296 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error"); 1297 return -1; 1298 } 1299 if (srst(state) < 0) { 1300 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1301 return -1; 1302 } 1303 /* delay 4~200 */ 1304 wait_t = 200000 / state->master_clk + 200000 / state->srate; 1305 msleep(wait_t); 1306 afcerr = afcerr_chk(state); 1307 if (afcerr == -1) 1308 return -1; 1309 1310 swp_freq = fOSC * 1000 + afcerr ; 1311 AFCEXEN = 1 ; 1312 if (state->srate >= 1500) 1313 smrt_d = state->srate / 3; 1314 else 1315 smrt_d = state->srate / 2; 1316 smrt_info_get(state, smrt_d); 1317 if (smrt_set(state, smrt_d) < 0) { 1318 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1319 return -1; 1320 } 1321 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) { 1322 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1323 return -1; 1324 } 1325 R = vco_dev_get(state, smrt_d); 1326 if (DAGC_data_set(state, 2, 0) < 0) { 1327 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1328 return -1; 1329 } 1330 for (i = 0; i < 3; i++) { 1331 temp_freq = swp_freq + (i - 1) * state->srate / 8; 1332 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1333 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1334 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1335 return -1; 1336 } 1337 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1338 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1339 return -1; 1340 } 1341 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1342 msleep(wait_t); 1343 dagcm[i] = dagcm_val_get(state); 1344 } 1345 if ((dagcm[0] > dagcm[1]) && 1346 (dagcm[0] > dagcm[2]) && 1347 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) { 1348 1349 temp_freq = swp_freq - 2 * state->srate / 8; 1350 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1351 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1352 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1353 return -1; 1354 } 1355 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1356 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1357 return -1; 1358 } 1359 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1360 msleep(wait_t); 1361 dagcm[3] = dagcm_val_get(state); 1362 if (dagcm[3] > dagcm[1]) 1363 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300; 1364 else 1365 delta_freq = 0; 1366 } else if ((dagcm[2] > dagcm[1]) && 1367 (dagcm[2] > dagcm[0]) && 1368 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) { 1369 1370 temp_freq = swp_freq + 2 * state->srate / 8; 1371 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1372 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1373 dprintk(verbose, MB86A16_ERROR, 1, "rf val set"); 1374 return -1; 1375 } 1376 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1377 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1378 return -1; 1379 } 1380 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1381 msleep(wait_t); 1382 dagcm[3] = dagcm_val_get(state); 1383 if (dagcm[3] > dagcm[1]) 1384 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300; 1385 else 1386 delta_freq = 0 ; 1387 1388 } else { 1389 delta_freq = 0 ; 1390 } 1391 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq); 1392 swp_freq += delta_freq; 1393 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq); 1394 if (ABS(state->frequency * 1000 - swp_freq) > 3800) { 1395 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !"); 1396 } else { 1397 1398 S1T = 0; 1399 S0T = 3; 1400 CREN = 1; 1401 AFCEN = 0; 1402 AFCEXEN = 1; 1403 1404 if (S01T_set(state, S1T, S0T) < 0) { 1405 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1406 return -1; 1407 } 1408 if (DAGC_data_set(state, 0, 0) < 0) { 1409 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1410 return -1; 1411 } 1412 R = vco_dev_get(state, state->srate); 1413 smrt_info_get(state, state->srate); 1414 if (smrt_set(state, state->srate) < 0) { 1415 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1416 return -1; 1417 } 1418 if (EN_set(state, CREN, AFCEN) < 0) { 1419 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1420 return -1; 1421 } 1422 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1423 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1424 return -1; 1425 } 1426 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1427 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1428 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1429 return -1; 1430 } 1431 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1432 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1433 return -1; 1434 } 1435 if (srst(state) < 0) { 1436 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1437 return -1; 1438 } 1439 wait_t = 7 + (10000 + state->srate / 2) / state->srate; 1440 if (wait_t == 0) 1441 wait_t = 1; 1442 msleep_interruptible(wait_t); 1443 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1444 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1445 return -EREMOTEIO; 1446 } 1447 1448 if (SIG1 > 110) { 1449 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6; 1450 wait_t = 7 + (917504 + state->srate / 2) / state->srate; 1451 } else if (SIG1 > 105) { 1452 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1453 wait_t = 7 + (1048576 + state->srate / 2) / state->srate; 1454 } else if (SIG1 > 85) { 1455 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1456 wait_t = 7 + (1310720 + state->srate / 2) / state->srate; 1457 } else if (SIG1 > 65) { 1458 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1459 wait_t = 7 + (1572864 + state->srate / 2) / state->srate; 1460 } else { 1461 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1462 wait_t = 7 + (2097152 + state->srate / 2) / state->srate; 1463 } 1464 wait_t *= 2; /* FOS */ 1465 S2T_set(state, S2T); 1466 S45T_set(state, S4T, S5T); 1467 Vi_set(state, ETH, VIA); 1468 srst(state); 1469 msleep_interruptible(wait_t); 1470 sync = sync_chk(state, &VIRM); 1471 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync); 1472 if (VIRM) { 1473 if (VIRM == 4) { 1474 /* 5/6 */ 1475 if (SIG1 > 110) 1476 wait_t = (786432 + state->srate / 2) / state->srate; 1477 else 1478 wait_t = (1572864 + state->srate / 2) / state->srate; 1479 if (state->srate < 5000) 1480 /* FIXME ! , should be a long wait ! */ 1481 msleep_interruptible(wait_t); 1482 else 1483 msleep_interruptible(wait_t); 1484 1485 if (sync_chk(state, &junk) == 0) { 1486 iq_vt_set(state, 1); 1487 FEC_srst(state); 1488 } 1489 } 1490 /* 1/2, 2/3, 3/4, 7/8 */ 1491 if (SIG1 > 110) 1492 wait_t = (786432 + state->srate / 2) / state->srate; 1493 else 1494 wait_t = (1572864 + state->srate / 2) / state->srate; 1495 msleep_interruptible(wait_t); 1496 SEQ_set(state, 1); 1497 } else { 1498 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC"); 1499 SEQ_set(state, 1); 1500 ret = -1; 1501 } 1502 } 1503 } else { 1504 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL"); 1505 ret = -1; 1506 } 1507 1508 sync = sync_chk(state, &junk); 1509 if (sync) { 1510 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******"); 1511 freqerr_chk(state, state->frequency, state->srate, 1); 1512 ret = 0; 1513 break; 1514 } 1515 } 1516 1517 mb86a16_read(state, 0x15, &agcval); 1518 mb86a16_read(state, 0x26, &cnmval); 1519 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval); 1520 1521 return ret; 1522 } 1523 1524 static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe, 1525 struct dvb_diseqc_master_cmd *cmd) 1526 { 1527 struct mb86a16_state *state = fe->demodulator_priv; 1528 int i; 1529 u8 regs; 1530 1531 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1532 goto err; 1533 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1534 goto err; 1535 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1536 goto err; 1537 1538 regs = 0x18; 1539 1540 if (cmd->msg_len > 5 || cmd->msg_len < 4) 1541 return -EINVAL; 1542 1543 for (i = 0; i < cmd->msg_len; i++) { 1544 if (mb86a16_write(state, regs, cmd->msg[i]) < 0) 1545 goto err; 1546 1547 regs++; 1548 } 1549 i += 0x90; 1550 1551 msleep_interruptible(10); 1552 1553 if (mb86a16_write(state, MB86A16_DCC1, i) < 0) 1554 goto err; 1555 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1556 goto err; 1557 1558 return 0; 1559 1560 err: 1561 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1562 return -EREMOTEIO; 1563 } 1564 1565 static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, 1566 enum fe_sec_mini_cmd burst) 1567 { 1568 struct mb86a16_state *state = fe->demodulator_priv; 1569 1570 switch (burst) { 1571 case SEC_MINI_A: 1572 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1573 MB86A16_DCC1_TBEN | 1574 MB86A16_DCC1_TBO) < 0) 1575 goto err; 1576 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1577 goto err; 1578 break; 1579 case SEC_MINI_B: 1580 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1581 MB86A16_DCC1_TBEN) < 0) 1582 goto err; 1583 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1584 goto err; 1585 break; 1586 } 1587 1588 return 0; 1589 err: 1590 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1591 return -EREMOTEIO; 1592 } 1593 1594 static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 1595 { 1596 struct mb86a16_state *state = fe->demodulator_priv; 1597 1598 switch (tone) { 1599 case SEC_TONE_ON: 1600 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0) 1601 goto err; 1602 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1603 MB86A16_DCC1_CTOE) < 0) 1604 1605 goto err; 1606 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1607 goto err; 1608 break; 1609 case SEC_TONE_OFF: 1610 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1611 goto err; 1612 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1613 goto err; 1614 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1615 goto err; 1616 break; 1617 default: 1618 return -EINVAL; 1619 } 1620 return 0; 1621 1622 err: 1623 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1624 return -EREMOTEIO; 1625 } 1626 1627 static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe) 1628 { 1629 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1630 struct mb86a16_state *state = fe->demodulator_priv; 1631 1632 state->frequency = p->frequency / 1000; 1633 state->srate = p->symbol_rate / 1000; 1634 1635 if (!mb86a16_set_fe(state)) { 1636 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK"); 1637 return DVBFE_ALGO_SEARCH_SUCCESS; 1638 } 1639 1640 dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!"); 1641 return DVBFE_ALGO_SEARCH_FAILED; 1642 } 1643 1644 static void mb86a16_release(struct dvb_frontend *fe) 1645 { 1646 struct mb86a16_state *state = fe->demodulator_priv; 1647 kfree(state); 1648 } 1649 1650 static int mb86a16_init(struct dvb_frontend *fe) 1651 { 1652 return 0; 1653 } 1654 1655 static int mb86a16_sleep(struct dvb_frontend *fe) 1656 { 1657 return 0; 1658 } 1659 1660 static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber) 1661 { 1662 u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst; 1663 u32 timer; 1664 1665 struct mb86a16_state *state = fe->demodulator_priv; 1666 1667 *ber = 0; 1668 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2) 1669 goto err; 1670 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2) 1671 goto err; 1672 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2) 1673 goto err; 1674 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2) 1675 goto err; 1676 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2) 1677 goto err; 1678 /* BER monitor invalid when BER_EN = 0 */ 1679 if (ber_mon & 0x04) { 1680 /* coarse, fast calculation */ 1681 *ber = ber_tab & 0x1f; 1682 dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber); 1683 if (ber_mon & 0x01) { 1684 /* 1685 * BER_SEL = 1, The monitored BER is the estimated 1686 * value with a Reed-Solomon decoder error amount at 1687 * the deinterleaver output. 1688 * monitored BER is expressed as a 20 bit output in total 1689 */ 1690 ber_rst = ber_mon >> 3; 1691 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1692 if (ber_rst == 0) 1693 timer = 12500000; 1694 if (ber_rst == 1) 1695 timer = 25000000; 1696 if (ber_rst == 2) 1697 timer = 50000000; 1698 if (ber_rst == 3) 1699 timer = 100000000; 1700 1701 *ber /= timer; 1702 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1703 } else { 1704 /* 1705 * BER_SEL = 0, The monitored BER is the estimated 1706 * value with a Viterbi decoder error amount at the 1707 * QPSK demodulator output. 1708 * monitored BER is expressed as a 24 bit output in total 1709 */ 1710 ber_tim = ber_mon >> 1; 1711 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1712 if (ber_tim == 0) 1713 timer = 16; 1714 if (ber_tim == 1) 1715 timer = 24; 1716 1717 *ber /= 2 ^ timer; 1718 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1719 } 1720 } 1721 return 0; 1722 err: 1723 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1724 return -EREMOTEIO; 1725 } 1726 1727 static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1728 { 1729 u8 agcm = 0; 1730 struct mb86a16_state *state = fe->demodulator_priv; 1731 1732 *strength = 0; 1733 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) { 1734 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1735 return -EREMOTEIO; 1736 } 1737 1738 *strength = ((0xff - agcm) * 100) / 256; 1739 dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength); 1740 *strength = (0xffff - 0xff) + agcm; 1741 1742 return 0; 1743 } 1744 1745 struct cnr { 1746 u8 cn_reg; 1747 u8 cn_val; 1748 }; 1749 1750 static const struct cnr cnr_tab[] = { 1751 { 35, 2 }, 1752 { 40, 3 }, 1753 { 50, 4 }, 1754 { 60, 5 }, 1755 { 70, 6 }, 1756 { 80, 7 }, 1757 { 92, 8 }, 1758 { 103, 9 }, 1759 { 115, 10 }, 1760 { 138, 12 }, 1761 { 162, 15 }, 1762 { 180, 18 }, 1763 { 185, 19 }, 1764 { 189, 20 }, 1765 { 195, 22 }, 1766 { 199, 24 }, 1767 { 201, 25 }, 1768 { 202, 26 }, 1769 { 203, 27 }, 1770 { 205, 28 }, 1771 { 208, 30 } 1772 }; 1773 1774 static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr) 1775 { 1776 struct mb86a16_state *state = fe->demodulator_priv; 1777 int i = 0; 1778 int low_tide = 2, high_tide = 30, q_level; 1779 u8 cn; 1780 1781 *snr = 0; 1782 if (mb86a16_read(state, 0x26, &cn) != 2) { 1783 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1784 return -EREMOTEIO; 1785 } 1786 1787 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) { 1788 if (cn < cnr_tab[i].cn_reg) { 1789 *snr = cnr_tab[i].cn_val; 1790 break; 1791 } 1792 } 1793 q_level = (*snr * 100) / (high_tide - low_tide); 1794 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level); 1795 *snr = (0xffff - 0xff) + *snr; 1796 1797 return 0; 1798 } 1799 1800 static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1801 { 1802 u8 dist; 1803 struct mb86a16_state *state = fe->demodulator_priv; 1804 1805 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) { 1806 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1807 return -EREMOTEIO; 1808 } 1809 *ucblocks = dist; 1810 1811 return 0; 1812 } 1813 1814 static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe) 1815 { 1816 return DVBFE_ALGO_CUSTOM; 1817 } 1818 1819 static struct dvb_frontend_ops mb86a16_ops = { 1820 .delsys = { SYS_DVBS }, 1821 .info = { 1822 .name = "Fujitsu MB86A16 DVB-S", 1823 .frequency_min = 950000, 1824 .frequency_max = 2150000, 1825 .frequency_stepsize = 3000, 1826 .frequency_tolerance = 0, 1827 .symbol_rate_min = 1000000, 1828 .symbol_rate_max = 45000000, 1829 .symbol_rate_tolerance = 500, 1830 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 1831 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | 1832 FE_CAN_FEC_7_8 | FE_CAN_QPSK | 1833 FE_CAN_FEC_AUTO 1834 }, 1835 .release = mb86a16_release, 1836 1837 .get_frontend_algo = mb86a16_frontend_algo, 1838 .search = mb86a16_search, 1839 .init = mb86a16_init, 1840 .sleep = mb86a16_sleep, 1841 .read_status = mb86a16_read_status, 1842 1843 .read_ber = mb86a16_read_ber, 1844 .read_signal_strength = mb86a16_read_signal_strength, 1845 .read_snr = mb86a16_read_snr, 1846 .read_ucblocks = mb86a16_read_ucblocks, 1847 1848 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg, 1849 .diseqc_send_burst = mb86a16_send_diseqc_burst, 1850 .set_tone = mb86a16_set_tone, 1851 }; 1852 1853 struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, 1854 struct i2c_adapter *i2c_adap) 1855 { 1856 u8 dev_id = 0; 1857 struct mb86a16_state *state = NULL; 1858 1859 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL); 1860 if (state == NULL) 1861 goto error; 1862 1863 state->config = config; 1864 state->i2c_adap = i2c_adap; 1865 1866 mb86a16_read(state, 0x7f, &dev_id); 1867 if (dev_id != 0xfe) 1868 goto error; 1869 1870 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops)); 1871 state->frontend.demodulator_priv = state; 1872 state->frontend.ops.set_voltage = state->config->set_voltage; 1873 1874 return &state->frontend; 1875 error: 1876 kfree(state); 1877 return NULL; 1878 } 1879 EXPORT_SYMBOL(mb86a16_attach); 1880 MODULE_LICENSE("GPL"); 1881 MODULE_AUTHOR("Manu Abraham"); 1882