1 /* 2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver 3 4 Copyright (C) Manu Abraham (abraham.manu@gmail.com) 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/slab.h> 26 27 #include "dvb_frontend.h" 28 #include "mb86a16.h" 29 #include "mb86a16_priv.h" 30 31 static unsigned int verbose = 5; 32 module_param(verbose, int, 0644); 33 34 #define ABS(x) ((x) < 0 ? (-x) : (x)) 35 36 struct mb86a16_state { 37 struct i2c_adapter *i2c_adap; 38 const struct mb86a16_config *config; 39 struct dvb_frontend frontend; 40 41 /* tuning parameters */ 42 int frequency; 43 int srate; 44 45 /* Internal stuff */ 46 int master_clk; 47 int deci; 48 int csel; 49 int rsel; 50 }; 51 52 #define MB86A16_ERROR 0 53 #define MB86A16_NOTICE 1 54 #define MB86A16_INFO 2 55 #define MB86A16_DEBUG 3 56 57 #define dprintk(x, y, z, format, arg...) do { \ 58 if (z) { \ 59 if ((x > MB86A16_ERROR) && (x > y)) \ 60 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \ 61 else if ((x > MB86A16_NOTICE) && (x > y)) \ 62 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \ 63 else if ((x > MB86A16_INFO) && (x > y)) \ 64 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \ 65 else if ((x > MB86A16_DEBUG) && (x > y)) \ 66 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \ 67 } else { \ 68 if (x > y) \ 69 printk(format, ##arg); \ 70 } \ 71 } while (0) 72 73 #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()") 74 #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->") 75 76 static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) 77 { 78 int ret; 79 u8 buf[] = { reg, val }; 80 81 struct i2c_msg msg = { 82 .addr = state->config->demod_address, 83 .flags = 0, 84 .buf = buf, 85 .len = 2 86 }; 87 88 dprintk(verbose, MB86A16_DEBUG, 1, 89 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]", 90 state->config->demod_address, buf[0], buf[1]); 91 92 ret = i2c_transfer(state->i2c_adap, &msg, 1); 93 94 return (ret != 1) ? -EREMOTEIO : 0; 95 } 96 97 static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) 98 { 99 int ret; 100 u8 b0[] = { reg }; 101 u8 b1[] = { 0 }; 102 103 struct i2c_msg msg[] = { 104 { 105 .addr = state->config->demod_address, 106 .flags = 0, 107 .buf = b0, 108 .len = 1 109 }, { 110 .addr = state->config->demod_address, 111 .flags = I2C_M_RD, 112 .buf = b1, 113 .len = 1 114 } 115 }; 116 ret = i2c_transfer(state->i2c_adap, msg, 2); 117 if (ret != 2) { 118 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)", 119 reg, ret); 120 121 return -EREMOTEIO; 122 } 123 *val = b1[0]; 124 125 return ret; 126 } 127 128 static int CNTM_set(struct mb86a16_state *state, 129 unsigned char timint1, 130 unsigned char timint2, 131 unsigned char cnext) 132 { 133 unsigned char val; 134 135 val = (timint1 << 4) | (timint2 << 2) | cnext; 136 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0) 137 goto err; 138 139 return 0; 140 141 err: 142 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 143 return -EREMOTEIO; 144 } 145 146 static int smrt_set(struct mb86a16_state *state, int rate) 147 { 148 int tmp ; 149 int m ; 150 unsigned char STOFS0, STOFS1; 151 152 m = 1 << state->deci; 153 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk; 154 155 STOFS0 = tmp & 0x0ff; 156 STOFS1 = (tmp & 0xf00) >> 8; 157 158 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) | 159 (state->csel << 1) | 160 state->rsel) < 0) 161 goto err; 162 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0) 163 goto err; 164 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0) 165 goto err; 166 167 return 0; 168 err: 169 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 170 return -1; 171 } 172 173 static int srst(struct mb86a16_state *state) 174 { 175 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0) 176 goto err; 177 178 return 0; 179 err: 180 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 181 return -EREMOTEIO; 182 183 } 184 185 static int afcex_data_set(struct mb86a16_state *state, 186 unsigned char AFCEX_L, 187 unsigned char AFCEX_H) 188 { 189 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0) 190 goto err; 191 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0) 192 goto err; 193 194 return 0; 195 err: 196 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 197 198 return -1; 199 } 200 201 static int afcofs_data_set(struct mb86a16_state *state, 202 unsigned char AFCEX_L, 203 unsigned char AFCEX_H) 204 { 205 if (mb86a16_write(state, 0x58, AFCEX_L) < 0) 206 goto err; 207 if (mb86a16_write(state, 0x59, AFCEX_H) < 0) 208 goto err; 209 210 return 0; 211 err: 212 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 213 return -EREMOTEIO; 214 } 215 216 static int stlp_set(struct mb86a16_state *state, 217 unsigned char STRAS, 218 unsigned char STRBS) 219 { 220 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0) 221 goto err; 222 223 return 0; 224 err: 225 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 226 return -EREMOTEIO; 227 } 228 229 static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA) 230 { 231 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0) 232 goto err; 233 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0) 234 goto err; 235 236 return 0; 237 err: 238 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 239 return -EREMOTEIO; 240 } 241 242 static int initial_set(struct mb86a16_state *state) 243 { 244 if (stlp_set(state, 5, 7)) 245 goto err; 246 247 udelay(100); 248 if (afcex_data_set(state, 0, 0)) 249 goto err; 250 251 udelay(100); 252 if (afcofs_data_set(state, 0, 0)) 253 goto err; 254 255 udelay(100); 256 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0) 257 goto err; 258 if (mb86a16_write(state, 0x2f, 0x21) < 0) 259 goto err; 260 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0) 261 goto err; 262 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0) 263 goto err; 264 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0) 265 goto err; 266 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0) 267 goto err; 268 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0) 269 goto err; 270 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0) 271 goto err; 272 if (mb86a16_write(state, 0x54, 0xff) < 0) 273 goto err; 274 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0) 275 goto err; 276 277 return 0; 278 279 err: 280 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 281 return -EREMOTEIO; 282 } 283 284 static int S01T_set(struct mb86a16_state *state, 285 unsigned char s1t, 286 unsigned s0t) 287 { 288 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0) 289 goto err; 290 291 return 0; 292 err: 293 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 294 return -EREMOTEIO; 295 } 296 297 298 static int EN_set(struct mb86a16_state *state, 299 int cren, 300 int afcen) 301 { 302 unsigned char val; 303 304 val = 0x7a | (cren << 7) | (afcen << 2); 305 if (mb86a16_write(state, 0x49, val) < 0) 306 goto err; 307 308 return 0; 309 err: 310 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 311 return -EREMOTEIO; 312 } 313 314 static int AFCEXEN_set(struct mb86a16_state *state, 315 int afcexen, 316 int smrt) 317 { 318 unsigned char AFCA ; 319 320 if (smrt > 18875) 321 AFCA = 4; 322 else if (smrt > 9375) 323 AFCA = 3; 324 else if (smrt > 2250) 325 AFCA = 2; 326 else 327 AFCA = 1; 328 329 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0) 330 goto err; 331 332 return 0; 333 334 err: 335 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 336 return -EREMOTEIO; 337 } 338 339 static int DAGC_data_set(struct mb86a16_state *state, 340 unsigned char DAGCA, 341 unsigned char DAGCW) 342 { 343 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0) 344 goto err; 345 346 return 0; 347 348 err: 349 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 350 return -EREMOTEIO; 351 } 352 353 static void smrt_info_get(struct mb86a16_state *state, int rate) 354 { 355 if (rate >= 37501) { 356 state->deci = 0; state->csel = 0; state->rsel = 0; 357 } else if (rate >= 30001) { 358 state->deci = 0; state->csel = 0; state->rsel = 1; 359 } else if (rate >= 26251) { 360 state->deci = 0; state->csel = 1; state->rsel = 0; 361 } else if (rate >= 22501) { 362 state->deci = 0; state->csel = 1; state->rsel = 1; 363 } else if (rate >= 18751) { 364 state->deci = 1; state->csel = 0; state->rsel = 0; 365 } else if (rate >= 15001) { 366 state->deci = 1; state->csel = 0; state->rsel = 1; 367 } else if (rate >= 13126) { 368 state->deci = 1; state->csel = 1; state->rsel = 0; 369 } else if (rate >= 11251) { 370 state->deci = 1; state->csel = 1; state->rsel = 1; 371 } else if (rate >= 9376) { 372 state->deci = 2; state->csel = 0; state->rsel = 0; 373 } else if (rate >= 7501) { 374 state->deci = 2; state->csel = 0; state->rsel = 1; 375 } else if (rate >= 6563) { 376 state->deci = 2; state->csel = 1; state->rsel = 0; 377 } else if (rate >= 5626) { 378 state->deci = 2; state->csel = 1; state->rsel = 1; 379 } else if (rate >= 4688) { 380 state->deci = 3; state->csel = 0; state->rsel = 0; 381 } else if (rate >= 3751) { 382 state->deci = 3; state->csel = 0; state->rsel = 1; 383 } else if (rate >= 3282) { 384 state->deci = 3; state->csel = 1; state->rsel = 0; 385 } else if (rate >= 2814) { 386 state->deci = 3; state->csel = 1; state->rsel = 1; 387 } else if (rate >= 2344) { 388 state->deci = 4; state->csel = 0; state->rsel = 0; 389 } else if (rate >= 1876) { 390 state->deci = 4; state->csel = 0; state->rsel = 1; 391 } else if (rate >= 1641) { 392 state->deci = 4; state->csel = 1; state->rsel = 0; 393 } else if (rate >= 1407) { 394 state->deci = 4; state->csel = 1; state->rsel = 1; 395 } else if (rate >= 1172) { 396 state->deci = 5; state->csel = 0; state->rsel = 0; 397 } else if (rate >= 939) { 398 state->deci = 5; state->csel = 0; state->rsel = 1; 399 } else if (rate >= 821) { 400 state->deci = 5; state->csel = 1; state->rsel = 0; 401 } else { 402 state->deci = 5; state->csel = 1; state->rsel = 1; 403 } 404 405 if (state->csel == 0) 406 state->master_clk = 92000; 407 else 408 state->master_clk = 61333; 409 410 } 411 412 static int signal_det(struct mb86a16_state *state, 413 int smrt, 414 unsigned char *SIG) 415 { 416 417 int ret ; 418 int smrtd ; 419 int wait_sym ; 420 421 u32 wait_t; 422 unsigned char S[3] ; 423 int i ; 424 425 if (*SIG > 45) { 426 if (CNTM_set(state, 2, 1, 2) < 0) { 427 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 428 return -1; 429 } 430 wait_sym = 40000; 431 } else { 432 if (CNTM_set(state, 3, 1, 2) < 0) { 433 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 434 return -1; 435 } 436 wait_sym = 80000; 437 } 438 for (i = 0; i < 3; i++) { 439 if (i == 0) 440 smrtd = smrt * 98 / 100; 441 else if (i == 1) 442 smrtd = smrt; 443 else 444 smrtd = smrt * 102 / 100; 445 smrt_info_get(state, smrtd); 446 smrt_set(state, smrtd); 447 srst(state); 448 wait_t = (wait_sym + 99 * smrtd / 100) / smrtd; 449 if (wait_t == 0) 450 wait_t = 1; 451 msleep_interruptible(10); 452 if (mb86a16_read(state, 0x37, &(S[i])) != 2) { 453 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 454 return -EREMOTEIO; 455 } 456 } 457 if ((S[1] > S[0] * 112 / 100) && 458 (S[1] > S[2] * 112 / 100)) { 459 460 ret = 1; 461 } else { 462 ret = 0; 463 } 464 *SIG = S[1]; 465 466 if (CNTM_set(state, 0, 1, 2) < 0) { 467 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 468 return -1; 469 } 470 471 return ret; 472 } 473 474 static int rf_val_set(struct mb86a16_state *state, 475 int f, 476 int smrt, 477 unsigned char R) 478 { 479 unsigned char C, F, B; 480 int M; 481 unsigned char rf_val[5]; 482 int ack = -1; 483 484 if (smrt > 37750) 485 C = 1; 486 else if (smrt > 18875) 487 C = 2; 488 else if (smrt > 5500) 489 C = 3; 490 else 491 C = 4; 492 493 if (smrt > 30500) 494 F = 3; 495 else if (smrt > 9375) 496 F = 1; 497 else if (smrt > 4625) 498 F = 0; 499 else 500 F = 2; 501 502 if (f < 1060) 503 B = 0; 504 else if (f < 1175) 505 B = 1; 506 else if (f < 1305) 507 B = 2; 508 else if (f < 1435) 509 B = 3; 510 else if (f < 1570) 511 B = 4; 512 else if (f < 1715) 513 B = 5; 514 else if (f < 1845) 515 B = 6; 516 else if (f < 1980) 517 B = 7; 518 else if (f < 2080) 519 B = 8; 520 else 521 B = 9; 522 523 M = f * (1 << R) / 2; 524 525 rf_val[0] = 0x01 | (C << 3) | (F << 1); 526 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12); 527 rf_val[2] = (M & 0x00ff0) >> 4; 528 rf_val[3] = ((M & 0x0000f) << 4) | B; 529 530 /* Frequency Set */ 531 if (mb86a16_write(state, 0x21, rf_val[0]) < 0) 532 ack = 0; 533 if (mb86a16_write(state, 0x22, rf_val[1]) < 0) 534 ack = 0; 535 if (mb86a16_write(state, 0x23, rf_val[2]) < 0) 536 ack = 0; 537 if (mb86a16_write(state, 0x24, rf_val[3]) < 0) 538 ack = 0; 539 if (mb86a16_write(state, 0x25, 0x01) < 0) 540 ack = 0; 541 if (ack == 0) { 542 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error"); 543 return -EREMOTEIO; 544 } 545 546 return 0; 547 } 548 549 static int afcerr_chk(struct mb86a16_state *state) 550 { 551 unsigned char AFCM_L, AFCM_H ; 552 int AFCM ; 553 int afcm, afcerr ; 554 555 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2) 556 goto err; 557 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2) 558 goto err; 559 560 AFCM = (AFCM_H << 8) + AFCM_L; 561 562 if (AFCM > 2048) 563 afcm = AFCM - 4096; 564 else 565 afcm = AFCM; 566 afcerr = afcm * state->master_clk / 8192; 567 568 return afcerr; 569 570 err: 571 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 572 return -EREMOTEIO; 573 } 574 575 static int dagcm_val_get(struct mb86a16_state *state) 576 { 577 int DAGCM; 578 unsigned char DAGCM_H, DAGCM_L; 579 580 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2) 581 goto err; 582 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2) 583 goto err; 584 585 DAGCM = (DAGCM_H << 8) + DAGCM_L; 586 587 return DAGCM; 588 589 err: 590 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 591 return -EREMOTEIO; 592 } 593 594 static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status) 595 { 596 u8 stat, stat2; 597 struct mb86a16_state *state = fe->demodulator_priv; 598 599 *status = 0; 600 601 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2) 602 goto err; 603 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2) 604 goto err; 605 if ((stat > 25) && (stat2 > 25)) 606 *status |= FE_HAS_SIGNAL; 607 if ((stat > 45) && (stat2 > 45)) 608 *status |= FE_HAS_CARRIER; 609 610 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2) 611 goto err; 612 613 if (stat & 0x01) 614 *status |= FE_HAS_SYNC; 615 if (stat & 0x01) 616 *status |= FE_HAS_VITERBI; 617 618 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2) 619 goto err; 620 621 if ((stat & 0x0f) && (*status & FE_HAS_VITERBI)) 622 *status |= FE_HAS_LOCK; 623 624 return 0; 625 626 err: 627 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 628 return -EREMOTEIO; 629 } 630 631 static int sync_chk(struct mb86a16_state *state, 632 unsigned char *VIRM) 633 { 634 unsigned char val; 635 int sync; 636 637 if (mb86a16_read(state, 0x0d, &val) != 2) 638 goto err; 639 640 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val); 641 sync = val & 0x01; 642 *VIRM = (val & 0x1c) >> 2; 643 644 return sync; 645 err: 646 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 647 return -EREMOTEIO; 648 649 } 650 651 static int freqerr_chk(struct mb86a16_state *state, 652 int fTP, 653 int smrt, 654 int unit) 655 { 656 unsigned char CRM, AFCML, AFCMH; 657 unsigned char temp1, temp2, temp3; 658 int crm, afcm, AFCM; 659 int crrerr, afcerr; /* kHz */ 660 int frqerr; /* MHz */ 661 int afcen, afcexen = 0; 662 int R, M, fOSC, fOSC_OFS; 663 664 if (mb86a16_read(state, 0x43, &CRM) != 2) 665 goto err; 666 667 if (CRM > 127) 668 crm = CRM - 256; 669 else 670 crm = CRM; 671 672 crrerr = smrt * crm / 256; 673 if (mb86a16_read(state, 0x49, &temp1) != 2) 674 goto err; 675 676 afcen = (temp1 & 0x04) >> 2; 677 if (afcen == 0) { 678 if (mb86a16_read(state, 0x2a, &temp1) != 2) 679 goto err; 680 afcexen = (temp1 & 0x20) >> 5; 681 } 682 683 if (afcen == 1) { 684 if (mb86a16_read(state, 0x0e, &AFCML) != 2) 685 goto err; 686 if (mb86a16_read(state, 0x0f, &AFCMH) != 2) 687 goto err; 688 } else if (afcexen == 1) { 689 if (mb86a16_read(state, 0x2b, &AFCML) != 2) 690 goto err; 691 if (mb86a16_read(state, 0x2c, &AFCMH) != 2) 692 goto err; 693 } 694 if ((afcen == 1) || (afcexen == 1)) { 695 smrt_info_get(state, smrt); 696 AFCM = ((AFCMH & 0x01) << 8) + AFCML; 697 if (AFCM > 255) 698 afcm = AFCM - 512; 699 else 700 afcm = AFCM; 701 702 afcerr = afcm * state->master_clk / 8192; 703 } else 704 afcerr = 0; 705 706 if (mb86a16_read(state, 0x22, &temp1) != 2) 707 goto err; 708 if (mb86a16_read(state, 0x23, &temp2) != 2) 709 goto err; 710 if (mb86a16_read(state, 0x24, &temp3) != 2) 711 goto err; 712 713 R = (temp1 & 0xe0) >> 5; 714 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4); 715 if (R == 0) 716 fOSC = 2 * M; 717 else 718 fOSC = M; 719 720 fOSC_OFS = fOSC - fTP; 721 722 if (unit == 0) { /* MHz */ 723 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0) 724 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000; 725 else 726 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000; 727 } else { /* kHz */ 728 frqerr = crrerr + afcerr + fOSC_OFS * 1000; 729 } 730 731 return frqerr; 732 err: 733 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 734 return -EREMOTEIO; 735 } 736 737 static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt) 738 { 739 unsigned char R; 740 741 if (smrt > 9375) 742 R = 0; 743 else 744 R = 1; 745 746 return R; 747 } 748 749 static void swp_info_get(struct mb86a16_state *state, 750 int fOSC_start, 751 int smrt, 752 int v, int R, 753 int swp_ofs, 754 int *fOSC, 755 int *afcex_freq, 756 unsigned char *AFCEX_L, 757 unsigned char *AFCEX_H) 758 { 759 int AFCEX ; 760 int crnt_swp_freq ; 761 762 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; 763 764 if (R == 0) 765 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2; 766 else 767 *fOSC = (crnt_swp_freq + 500) / 1000; 768 769 if (*fOSC >= crnt_swp_freq) 770 *afcex_freq = *fOSC * 1000 - crnt_swp_freq; 771 else 772 *afcex_freq = crnt_swp_freq - *fOSC * 1000; 773 774 AFCEX = *afcex_freq * 8192 / state->master_clk; 775 *AFCEX_L = AFCEX & 0x00ff; 776 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 777 } 778 779 780 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin, 781 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1) 782 { 783 int swp_freq ; 784 785 if ((i % 2 == 1) && (v <= vmax)) { 786 /* positive v (case 1) */ 787 if ((v - 1 == vmin) && 788 (*(V + 30 + v) >= 0) && 789 (*(V + 30 + v - 1) >= 0) && 790 (*(V + 30 + v - 1) > *(V + 30 + v)) && 791 (*(V + 30 + v - 1) > SIGMIN)) { 792 793 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 794 *SIG1 = *(V + 30 + v - 1); 795 } else if ((v == vmax) && 796 (*(V + 30 + v) >= 0) && 797 (*(V + 30 + v - 1) >= 0) && 798 (*(V + 30 + v) > *(V + 30 + v - 1)) && 799 (*(V + 30 + v) > SIGMIN)) { 800 /* (case 2) */ 801 swp_freq = fOSC * 1000 + afcex_freq; 802 *SIG1 = *(V + 30 + v); 803 } else if ((*(V + 30 + v) > 0) && 804 (*(V + 30 + v - 1) > 0) && 805 (*(V + 30 + v - 2) > 0) && 806 (*(V + 30 + v - 3) > 0) && 807 (*(V + 30 + v - 1) > *(V + 30 + v)) && 808 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) && 809 ((*(V + 30 + v - 1) > SIGMIN) || 810 (*(V + 30 + v - 2) > SIGMIN))) { 811 /* (case 3) */ 812 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) { 813 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 814 *SIG1 = *(V + 30 + v - 1); 815 } else { 816 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2; 817 *SIG1 = *(V + 30 + v - 2); 818 } 819 } else if ((v == vmax) && 820 (*(V + 30 + v) >= 0) && 821 (*(V + 30 + v - 1) >= 0) && 822 (*(V + 30 + v - 2) >= 0) && 823 (*(V + 30 + v) > *(V + 30 + v - 2)) && 824 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) && 825 ((*(V + 30 + v) > SIGMIN) || 826 (*(V + 30 + v - 1) > SIGMIN))) { 827 /* (case 4) */ 828 if (*(V + 30 + v) >= *(V + 30 + v - 1)) { 829 swp_freq = fOSC * 1000 + afcex_freq; 830 *SIG1 = *(V + 30 + v); 831 } else { 832 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 833 *SIG1 = *(V + 30 + v - 1); 834 } 835 } else { 836 swp_freq = -1 ; 837 } 838 } else if ((i % 2 == 0) && (v >= vmin)) { 839 /* Negative v (case 1) */ 840 if ((*(V + 30 + v) > 0) && 841 (*(V + 30 + v + 1) > 0) && 842 (*(V + 30 + v + 2) > 0) && 843 (*(V + 30 + v + 1) > *(V + 30 + v)) && 844 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 845 (*(V + 30 + v + 1) > SIGMIN)) { 846 847 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 848 *SIG1 = *(V + 30 + v + 1); 849 } else if ((v + 1 == vmax) && 850 (*(V + 30 + v) >= 0) && 851 (*(V + 30 + v + 1) >= 0) && 852 (*(V + 30 + v + 1) > *(V + 30 + v)) && 853 (*(V + 30 + v + 1) > SIGMIN)) { 854 /* (case 2) */ 855 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 856 *SIG1 = *(V + 30 + v); 857 } else if ((v == vmin) && 858 (*(V + 30 + v) > 0) && 859 (*(V + 30 + v + 1) > 0) && 860 (*(V + 30 + v + 2) > 0) && 861 (*(V + 30 + v) > *(V + 30 + v + 1)) && 862 (*(V + 30 + v) > *(V + 30 + v + 2)) && 863 (*(V + 30 + v) > SIGMIN)) { 864 /* (case 3) */ 865 swp_freq = fOSC * 1000 + afcex_freq; 866 *SIG1 = *(V + 30 + v); 867 } else if ((*(V + 30 + v) >= 0) && 868 (*(V + 30 + v + 1) >= 0) && 869 (*(V + 30 + v + 2) >= 0) && 870 (*(V + 30 + v + 3) >= 0) && 871 (*(V + 30 + v + 1) > *(V + 30 + v)) && 872 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) && 873 ((*(V + 30 + v + 1) > SIGMIN) || 874 (*(V + 30 + v + 2) > SIGMIN))) { 875 /* (case 4) */ 876 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 877 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 878 *SIG1 = *(V + 30 + v + 1); 879 } else { 880 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 881 *SIG1 = *(V + 30 + v + 2); 882 } 883 } else if ((*(V + 30 + v) >= 0) && 884 (*(V + 30 + v + 1) >= 0) && 885 (*(V + 30 + v + 2) >= 0) && 886 (*(V + 30 + v + 3) >= 0) && 887 (*(V + 30 + v) > *(V + 30 + v + 2)) && 888 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 889 (*(V + 30 + v) > *(V + 30 + v + 3)) && 890 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) && 891 ((*(V + 30 + v) > SIGMIN) || 892 (*(V + 30 + v + 1) > SIGMIN))) { 893 /* (case 5) */ 894 if (*(V + 30 + v) >= *(V + 30 + v + 1)) { 895 swp_freq = fOSC * 1000 + afcex_freq; 896 *SIG1 = *(V + 30 + v); 897 } else { 898 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 899 *SIG1 = *(V + 30 + v + 1); 900 } 901 } else if ((v + 2 == vmin) && 902 (*(V + 30 + v) >= 0) && 903 (*(V + 30 + v + 1) >= 0) && 904 (*(V + 30 + v + 2) >= 0) && 905 (*(V + 30 + v + 1) > *(V + 30 + v)) && 906 (*(V + 30 + v + 2) > *(V + 30 + v)) && 907 ((*(V + 30 + v + 1) > SIGMIN) || 908 (*(V + 30 + v + 2) > SIGMIN))) { 909 /* (case 6) */ 910 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 911 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 912 *SIG1 = *(V + 30 + v + 1); 913 } else { 914 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 915 *SIG1 = *(V + 30 + v + 2); 916 } 917 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) { 918 swp_freq = fOSC * 1000; 919 *SIG1 = *(V + 30 + v); 920 } else 921 swp_freq = -1; 922 } else 923 swp_freq = -1; 924 925 return swp_freq; 926 } 927 928 static void swp_info_get2(struct mb86a16_state *state, 929 int smrt, 930 int R, 931 int swp_freq, 932 int *afcex_freq, 933 int *fOSC, 934 unsigned char *AFCEX_L, 935 unsigned char *AFCEX_H) 936 { 937 int AFCEX ; 938 939 if (R == 0) 940 *fOSC = (swp_freq + 1000) / 2000 * 2; 941 else 942 *fOSC = (swp_freq + 500) / 1000; 943 944 if (*fOSC >= swp_freq) 945 *afcex_freq = *fOSC * 1000 - swp_freq; 946 else 947 *afcex_freq = swp_freq - *fOSC * 1000; 948 949 AFCEX = *afcex_freq * 8192 / state->master_clk; 950 *AFCEX_L = AFCEX & 0x00ff; 951 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 952 } 953 954 static void afcex_info_get(struct mb86a16_state *state, 955 int afcex_freq, 956 unsigned char *AFCEX_L, 957 unsigned char *AFCEX_H) 958 { 959 int AFCEX ; 960 961 AFCEX = afcex_freq * 8192 / state->master_clk; 962 *AFCEX_L = AFCEX & 0x00ff; 963 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 964 } 965 966 static int SEQ_set(struct mb86a16_state *state, unsigned char loop) 967 { 968 /* SLOCK0 = 0 */ 969 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) { 970 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 971 return -EREMOTEIO; 972 } 973 974 return 0; 975 } 976 977 static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV) 978 { 979 /* Viterbi Rate, IQ Settings */ 980 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) { 981 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 982 return -EREMOTEIO; 983 } 984 985 return 0; 986 } 987 988 static int FEC_srst(struct mb86a16_state *state) 989 { 990 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) { 991 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 992 return -EREMOTEIO; 993 } 994 995 return 0; 996 } 997 998 static int S2T_set(struct mb86a16_state *state, unsigned char S2T) 999 { 1000 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) { 1001 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1002 return -EREMOTEIO; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T) 1009 { 1010 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) { 1011 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1012 return -EREMOTEIO; 1013 } 1014 1015 return 0; 1016 } 1017 1018 1019 static int mb86a16_set_fe(struct mb86a16_state *state) 1020 { 1021 u8 agcval, cnmval; 1022 1023 int i, j; 1024 int fOSC = 0; 1025 int fOSC_start = 0; 1026 int wait_t; 1027 int fcp; 1028 int swp_ofs; 1029 int V[60]; 1030 u8 SIG1MIN; 1031 1032 unsigned char CREN, AFCEN, AFCEXEN; 1033 unsigned char SIG1; 1034 unsigned char TIMINT1, TIMINT2, TIMEXT; 1035 unsigned char S0T, S1T; 1036 unsigned char S2T; 1037 /* unsigned char S2T, S3T; */ 1038 unsigned char S4T, S5T; 1039 unsigned char AFCEX_L, AFCEX_H; 1040 unsigned char R; 1041 unsigned char VIRM; 1042 unsigned char ETH, VIA; 1043 unsigned char junk; 1044 1045 int loop; 1046 int ftemp; 1047 int v, vmax, vmin; 1048 int vmax_his, vmin_his; 1049 int swp_freq, prev_swp_freq[20]; 1050 int prev_freq_num; 1051 int signal_dupl; 1052 int afcex_freq; 1053 int signal; 1054 int afcerr; 1055 int temp_freq, delta_freq; 1056 int dagcm[4]; 1057 int smrt_d; 1058 /* int freq_err; */ 1059 int n; 1060 int ret = -1; 1061 int sync; 1062 1063 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate); 1064 1065 fcp = 3000; 1066 swp_ofs = state->srate / 4; 1067 1068 for (i = 0; i < 60; i++) 1069 V[i] = -1; 1070 1071 for (i = 0; i < 20; i++) 1072 prev_swp_freq[i] = 0; 1073 1074 SIG1MIN = 25; 1075 1076 for (n = 0; ((n < 3) && (ret == -1)); n++) { 1077 SEQ_set(state, 0); 1078 iq_vt_set(state, 0); 1079 1080 CREN = 0; 1081 AFCEN = 0; 1082 AFCEXEN = 1; 1083 TIMINT1 = 0; 1084 TIMINT2 = 1; 1085 TIMEXT = 2; 1086 S1T = 0; 1087 S0T = 0; 1088 1089 if (initial_set(state) < 0) { 1090 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed"); 1091 return -1; 1092 } 1093 if (DAGC_data_set(state, 3, 2) < 0) { 1094 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1095 return -1; 1096 } 1097 if (EN_set(state, CREN, AFCEN) < 0) { 1098 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1099 return -1; /* (0, 0) */ 1100 } 1101 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1102 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1103 return -1; /* (1, smrt) = (1, symbolrate) */ 1104 } 1105 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) { 1106 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error"); 1107 return -1; /* (0, 1, 2) */ 1108 } 1109 if (S01T_set(state, S1T, S0T) < 0) { 1110 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1111 return -1; /* (0, 0) */ 1112 } 1113 smrt_info_get(state, state->srate); 1114 if (smrt_set(state, state->srate) < 0) { 1115 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error"); 1116 return -1; 1117 } 1118 1119 R = vco_dev_get(state, state->srate); 1120 if (R == 1) 1121 fOSC_start = state->frequency; 1122 1123 else if (R == 0) { 1124 if (state->frequency % 2 == 0) { 1125 fOSC_start = state->frequency; 1126 } else { 1127 fOSC_start = state->frequency + 1; 1128 if (fOSC_start > 2150) 1129 fOSC_start = state->frequency - 1; 1130 } 1131 } 1132 loop = 1; 1133 ftemp = fOSC_start * 1000; 1134 vmax = 0 ; 1135 while (loop == 1) { 1136 ftemp = ftemp + swp_ofs; 1137 vmax++; 1138 1139 /* Upper bound */ 1140 if (ftemp > 2150000) { 1141 loop = 0; 1142 vmax--; 1143 } else { 1144 if ((ftemp == 2150000) || 1145 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4)) 1146 loop = 0; 1147 } 1148 } 1149 1150 loop = 1; 1151 ftemp = fOSC_start * 1000; 1152 vmin = 0 ; 1153 while (loop == 1) { 1154 ftemp = ftemp - swp_ofs; 1155 vmin--; 1156 1157 /* Lower bound */ 1158 if (ftemp < 950000) { 1159 loop = 0; 1160 vmin++; 1161 } else { 1162 if ((ftemp == 950000) || 1163 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4)) 1164 loop = 0; 1165 } 1166 } 1167 1168 wait_t = (8000 + state->srate / 2) / state->srate; 1169 if (wait_t == 0) 1170 wait_t = 1; 1171 1172 i = 0; 1173 j = 0; 1174 prev_freq_num = 0; 1175 loop = 1; 1176 signal = 0; 1177 vmax_his = 0; 1178 vmin_his = 0; 1179 v = 0; 1180 1181 while (loop == 1) { 1182 swp_info_get(state, fOSC_start, state->srate, 1183 v, R, swp_ofs, &fOSC, 1184 &afcex_freq, &AFCEX_L, &AFCEX_H); 1185 1186 udelay(100); 1187 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1188 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1189 return -1; 1190 } 1191 udelay(100); 1192 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1193 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1194 return -1; 1195 } 1196 if (srst(state) < 0) { 1197 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1198 return -1; 1199 } 1200 msleep_interruptible(wait_t); 1201 1202 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1203 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1204 return -1; 1205 } 1206 V[30 + v] = SIG1 ; 1207 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin, 1208 SIG1MIN, fOSC, afcex_freq, 1209 swp_ofs, &SIG1); /* changed */ 1210 1211 signal_dupl = 0; 1212 for (j = 0; j < prev_freq_num; j++) { 1213 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) { 1214 signal_dupl = 1; 1215 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j); 1216 } 1217 } 1218 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) { 1219 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate); 1220 prev_swp_freq[prev_freq_num] = swp_freq; 1221 prev_freq_num++; 1222 swp_info_get2(state, state->srate, R, swp_freq, 1223 &afcex_freq, &fOSC, 1224 &AFCEX_L, &AFCEX_H); 1225 1226 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1227 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1228 return -1; 1229 } 1230 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1231 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1232 return -1; 1233 } 1234 signal = signal_det(state, state->srate, &SIG1); 1235 if (signal == 1) { 1236 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****"); 1237 loop = 0; 1238 } else { 1239 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again..."); 1240 smrt_info_get(state, state->srate); 1241 if (smrt_set(state, state->srate) < 0) { 1242 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1243 return -1; 1244 } 1245 } 1246 } 1247 if (v > vmax) 1248 vmax_his = 1 ; 1249 if (v < vmin) 1250 vmin_his = 1 ; 1251 i++; 1252 1253 if ((i % 2 == 1) && (vmax_his == 1)) 1254 i++; 1255 if ((i % 2 == 0) && (vmin_his == 1)) 1256 i++; 1257 1258 if (i % 2 == 1) 1259 v = (i + 1) / 2; 1260 else 1261 v = -i / 2; 1262 1263 if ((vmax_his == 1) && (vmin_his == 1)) 1264 loop = 0 ; 1265 } 1266 1267 if (signal == 1) { 1268 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check"); 1269 S1T = 7 ; 1270 S0T = 1 ; 1271 CREN = 0 ; 1272 AFCEN = 1 ; 1273 AFCEXEN = 0 ; 1274 1275 if (S01T_set(state, S1T, S0T) < 0) { 1276 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1277 return -1; 1278 } 1279 smrt_info_get(state, state->srate); 1280 if (smrt_set(state, state->srate) < 0) { 1281 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1282 return -1; 1283 } 1284 if (EN_set(state, CREN, AFCEN) < 0) { 1285 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1286 return -1; 1287 } 1288 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1289 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1290 return -1; 1291 } 1292 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H); 1293 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1294 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error"); 1295 return -1; 1296 } 1297 if (srst(state) < 0) { 1298 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1299 return -1; 1300 } 1301 /* delay 4~200 */ 1302 wait_t = 200000 / state->master_clk + 200000 / state->srate; 1303 msleep(wait_t); 1304 afcerr = afcerr_chk(state); 1305 if (afcerr == -1) 1306 return -1; 1307 1308 swp_freq = fOSC * 1000 + afcerr ; 1309 AFCEXEN = 1 ; 1310 if (state->srate >= 1500) 1311 smrt_d = state->srate / 3; 1312 else 1313 smrt_d = state->srate / 2; 1314 smrt_info_get(state, smrt_d); 1315 if (smrt_set(state, smrt_d) < 0) { 1316 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1317 return -1; 1318 } 1319 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) { 1320 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1321 return -1; 1322 } 1323 R = vco_dev_get(state, smrt_d); 1324 if (DAGC_data_set(state, 2, 0) < 0) { 1325 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1326 return -1; 1327 } 1328 for (i = 0; i < 3; i++) { 1329 temp_freq = swp_freq + (i - 1) * state->srate / 8; 1330 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1331 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1332 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1333 return -1; 1334 } 1335 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1336 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1337 return -1; 1338 } 1339 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1340 msleep(wait_t); 1341 dagcm[i] = dagcm_val_get(state); 1342 } 1343 if ((dagcm[0] > dagcm[1]) && 1344 (dagcm[0] > dagcm[2]) && 1345 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) { 1346 1347 temp_freq = swp_freq - 2 * state->srate / 8; 1348 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1349 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1350 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1351 return -1; 1352 } 1353 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1354 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1355 return -1; 1356 } 1357 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1358 msleep(wait_t); 1359 dagcm[3] = dagcm_val_get(state); 1360 if (dagcm[3] > dagcm[1]) 1361 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300; 1362 else 1363 delta_freq = 0; 1364 } else if ((dagcm[2] > dagcm[1]) && 1365 (dagcm[2] > dagcm[0]) && 1366 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) { 1367 1368 temp_freq = swp_freq + 2 * state->srate / 8; 1369 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1370 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1371 dprintk(verbose, MB86A16_ERROR, 1, "rf val set"); 1372 return -1; 1373 } 1374 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1375 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1376 return -1; 1377 } 1378 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1379 msleep(wait_t); 1380 dagcm[3] = dagcm_val_get(state); 1381 if (dagcm[3] > dagcm[1]) 1382 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300; 1383 else 1384 delta_freq = 0 ; 1385 1386 } else { 1387 delta_freq = 0 ; 1388 } 1389 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq); 1390 swp_freq += delta_freq; 1391 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq); 1392 if (ABS(state->frequency * 1000 - swp_freq) > 3800) { 1393 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !"); 1394 } else { 1395 1396 S1T = 0; 1397 S0T = 3; 1398 CREN = 1; 1399 AFCEN = 0; 1400 AFCEXEN = 1; 1401 1402 if (S01T_set(state, S1T, S0T) < 0) { 1403 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1404 return -1; 1405 } 1406 if (DAGC_data_set(state, 0, 0) < 0) { 1407 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1408 return -1; 1409 } 1410 R = vco_dev_get(state, state->srate); 1411 smrt_info_get(state, state->srate); 1412 if (smrt_set(state, state->srate) < 0) { 1413 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1414 return -1; 1415 } 1416 if (EN_set(state, CREN, AFCEN) < 0) { 1417 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1418 return -1; 1419 } 1420 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1421 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1422 return -1; 1423 } 1424 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1425 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1426 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1427 return -1; 1428 } 1429 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1430 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1431 return -1; 1432 } 1433 if (srst(state) < 0) { 1434 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1435 return -1; 1436 } 1437 wait_t = 7 + (10000 + state->srate / 2) / state->srate; 1438 if (wait_t == 0) 1439 wait_t = 1; 1440 msleep_interruptible(wait_t); 1441 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1442 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1443 return -EREMOTEIO; 1444 } 1445 1446 if (SIG1 > 110) { 1447 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6; 1448 wait_t = 7 + (917504 + state->srate / 2) / state->srate; 1449 } else if (SIG1 > 105) { 1450 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1451 wait_t = 7 + (1048576 + state->srate / 2) / state->srate; 1452 } else if (SIG1 > 85) { 1453 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1454 wait_t = 7 + (1310720 + state->srate / 2) / state->srate; 1455 } else if (SIG1 > 65) { 1456 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1457 wait_t = 7 + (1572864 + state->srate / 2) / state->srate; 1458 } else { 1459 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1460 wait_t = 7 + (2097152 + state->srate / 2) / state->srate; 1461 } 1462 wait_t *= 2; /* FOS */ 1463 S2T_set(state, S2T); 1464 S45T_set(state, S4T, S5T); 1465 Vi_set(state, ETH, VIA); 1466 srst(state); 1467 msleep_interruptible(wait_t); 1468 sync = sync_chk(state, &VIRM); 1469 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync); 1470 if (VIRM) { 1471 if (VIRM == 4) { 1472 /* 5/6 */ 1473 if (SIG1 > 110) 1474 wait_t = (786432 + state->srate / 2) / state->srate; 1475 else 1476 wait_t = (1572864 + state->srate / 2) / state->srate; 1477 if (state->srate < 5000) 1478 /* FIXME ! , should be a long wait ! */ 1479 msleep_interruptible(wait_t); 1480 else 1481 msleep_interruptible(wait_t); 1482 1483 if (sync_chk(state, &junk) == 0) { 1484 iq_vt_set(state, 1); 1485 FEC_srst(state); 1486 } 1487 } 1488 /* 1/2, 2/3, 3/4, 7/8 */ 1489 if (SIG1 > 110) 1490 wait_t = (786432 + state->srate / 2) / state->srate; 1491 else 1492 wait_t = (1572864 + state->srate / 2) / state->srate; 1493 msleep_interruptible(wait_t); 1494 SEQ_set(state, 1); 1495 } else { 1496 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC"); 1497 SEQ_set(state, 1); 1498 ret = -1; 1499 } 1500 } 1501 } else { 1502 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL"); 1503 ret = -1; 1504 } 1505 1506 sync = sync_chk(state, &junk); 1507 if (sync) { 1508 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******"); 1509 freqerr_chk(state, state->frequency, state->srate, 1); 1510 ret = 0; 1511 break; 1512 } 1513 } 1514 1515 mb86a16_read(state, 0x15, &agcval); 1516 mb86a16_read(state, 0x26, &cnmval); 1517 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval); 1518 1519 return ret; 1520 } 1521 1522 static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe, 1523 struct dvb_diseqc_master_cmd *cmd) 1524 { 1525 struct mb86a16_state *state = fe->demodulator_priv; 1526 int i; 1527 u8 regs; 1528 1529 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1530 goto err; 1531 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1532 goto err; 1533 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1534 goto err; 1535 1536 regs = 0x18; 1537 1538 if (cmd->msg_len > 5 || cmd->msg_len < 4) 1539 return -EINVAL; 1540 1541 for (i = 0; i < cmd->msg_len; i++) { 1542 if (mb86a16_write(state, regs, cmd->msg[i]) < 0) 1543 goto err; 1544 1545 regs++; 1546 } 1547 i += 0x90; 1548 1549 msleep_interruptible(10); 1550 1551 if (mb86a16_write(state, MB86A16_DCC1, i) < 0) 1552 goto err; 1553 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1554 goto err; 1555 1556 return 0; 1557 1558 err: 1559 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1560 return -EREMOTEIO; 1561 } 1562 1563 static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) 1564 { 1565 struct mb86a16_state *state = fe->demodulator_priv; 1566 1567 switch (burst) { 1568 case SEC_MINI_A: 1569 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1570 MB86A16_DCC1_TBEN | 1571 MB86A16_DCC1_TBO) < 0) 1572 goto err; 1573 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1574 goto err; 1575 break; 1576 case SEC_MINI_B: 1577 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1578 MB86A16_DCC1_TBEN) < 0) 1579 goto err; 1580 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1581 goto err; 1582 break; 1583 } 1584 1585 return 0; 1586 err: 1587 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1588 return -EREMOTEIO; 1589 } 1590 1591 static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 1592 { 1593 struct mb86a16_state *state = fe->demodulator_priv; 1594 1595 switch (tone) { 1596 case SEC_TONE_ON: 1597 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0) 1598 goto err; 1599 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1600 MB86A16_DCC1_CTOE) < 0) 1601 1602 goto err; 1603 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1604 goto err; 1605 break; 1606 case SEC_TONE_OFF: 1607 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1608 goto err; 1609 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1610 goto err; 1611 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1612 goto err; 1613 break; 1614 default: 1615 return -EINVAL; 1616 } 1617 return 0; 1618 1619 err: 1620 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1621 return -EREMOTEIO; 1622 } 1623 1624 static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe) 1625 { 1626 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1627 struct mb86a16_state *state = fe->demodulator_priv; 1628 1629 state->frequency = p->frequency / 1000; 1630 state->srate = p->symbol_rate / 1000; 1631 1632 if (!mb86a16_set_fe(state)) { 1633 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK"); 1634 return DVBFE_ALGO_SEARCH_SUCCESS; 1635 } 1636 1637 dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!"); 1638 return DVBFE_ALGO_SEARCH_FAILED; 1639 } 1640 1641 static void mb86a16_release(struct dvb_frontend *fe) 1642 { 1643 struct mb86a16_state *state = fe->demodulator_priv; 1644 kfree(state); 1645 } 1646 1647 static int mb86a16_init(struct dvb_frontend *fe) 1648 { 1649 return 0; 1650 } 1651 1652 static int mb86a16_sleep(struct dvb_frontend *fe) 1653 { 1654 return 0; 1655 } 1656 1657 static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber) 1658 { 1659 u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst; 1660 u32 timer; 1661 1662 struct mb86a16_state *state = fe->demodulator_priv; 1663 1664 *ber = 0; 1665 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2) 1666 goto err; 1667 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2) 1668 goto err; 1669 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2) 1670 goto err; 1671 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2) 1672 goto err; 1673 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2) 1674 goto err; 1675 /* BER monitor invalid when BER_EN = 0 */ 1676 if (ber_mon & 0x04) { 1677 /* coarse, fast calculation */ 1678 *ber = ber_tab & 0x1f; 1679 dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber); 1680 if (ber_mon & 0x01) { 1681 /* 1682 * BER_SEL = 1, The monitored BER is the estimated 1683 * value with a Reed-Solomon decoder error amount at 1684 * the deinterleaver output. 1685 * monitored BER is expressed as a 20 bit output in total 1686 */ 1687 ber_rst = ber_mon >> 3; 1688 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1689 if (ber_rst == 0) 1690 timer = 12500000; 1691 if (ber_rst == 1) 1692 timer = 25000000; 1693 if (ber_rst == 2) 1694 timer = 50000000; 1695 if (ber_rst == 3) 1696 timer = 100000000; 1697 1698 *ber /= timer; 1699 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1700 } else { 1701 /* 1702 * BER_SEL = 0, The monitored BER is the estimated 1703 * value with a Viterbi decoder error amount at the 1704 * QPSK demodulator output. 1705 * monitored BER is expressed as a 24 bit output in total 1706 */ 1707 ber_tim = ber_mon >> 1; 1708 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1709 if (ber_tim == 0) 1710 timer = 16; 1711 if (ber_tim == 1) 1712 timer = 24; 1713 1714 *ber /= 2 ^ timer; 1715 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1716 } 1717 } 1718 return 0; 1719 err: 1720 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1721 return -EREMOTEIO; 1722 } 1723 1724 static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1725 { 1726 u8 agcm = 0; 1727 struct mb86a16_state *state = fe->demodulator_priv; 1728 1729 *strength = 0; 1730 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) { 1731 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1732 return -EREMOTEIO; 1733 } 1734 1735 *strength = ((0xff - agcm) * 100) / 256; 1736 dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength); 1737 *strength = (0xffff - 0xff) + agcm; 1738 1739 return 0; 1740 } 1741 1742 struct cnr { 1743 u8 cn_reg; 1744 u8 cn_val; 1745 }; 1746 1747 static const struct cnr cnr_tab[] = { 1748 { 35, 2 }, 1749 { 40, 3 }, 1750 { 50, 4 }, 1751 { 60, 5 }, 1752 { 70, 6 }, 1753 { 80, 7 }, 1754 { 92, 8 }, 1755 { 103, 9 }, 1756 { 115, 10 }, 1757 { 138, 12 }, 1758 { 162, 15 }, 1759 { 180, 18 }, 1760 { 185, 19 }, 1761 { 189, 20 }, 1762 { 195, 22 }, 1763 { 199, 24 }, 1764 { 201, 25 }, 1765 { 202, 26 }, 1766 { 203, 27 }, 1767 { 205, 28 }, 1768 { 208, 30 } 1769 }; 1770 1771 static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr) 1772 { 1773 struct mb86a16_state *state = fe->demodulator_priv; 1774 int i = 0; 1775 int low_tide = 2, high_tide = 30, q_level; 1776 u8 cn; 1777 1778 *snr = 0; 1779 if (mb86a16_read(state, 0x26, &cn) != 2) { 1780 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1781 return -EREMOTEIO; 1782 } 1783 1784 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) { 1785 if (cn < cnr_tab[i].cn_reg) { 1786 *snr = cnr_tab[i].cn_val; 1787 break; 1788 } 1789 } 1790 q_level = (*snr * 100) / (high_tide - low_tide); 1791 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level); 1792 *snr = (0xffff - 0xff) + *snr; 1793 1794 return 0; 1795 } 1796 1797 static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1798 { 1799 u8 dist; 1800 struct mb86a16_state *state = fe->demodulator_priv; 1801 1802 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) { 1803 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1804 return -EREMOTEIO; 1805 } 1806 *ucblocks = dist; 1807 1808 return 0; 1809 } 1810 1811 static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe) 1812 { 1813 return DVBFE_ALGO_CUSTOM; 1814 } 1815 1816 static struct dvb_frontend_ops mb86a16_ops = { 1817 .delsys = { SYS_DVBS }, 1818 .info = { 1819 .name = "Fujitsu MB86A16 DVB-S", 1820 .frequency_min = 950000, 1821 .frequency_max = 2150000, 1822 .frequency_stepsize = 3000, 1823 .frequency_tolerance = 0, 1824 .symbol_rate_min = 1000000, 1825 .symbol_rate_max = 45000000, 1826 .symbol_rate_tolerance = 500, 1827 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 1828 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | 1829 FE_CAN_FEC_7_8 | FE_CAN_QPSK | 1830 FE_CAN_FEC_AUTO 1831 }, 1832 .release = mb86a16_release, 1833 1834 .get_frontend_algo = mb86a16_frontend_algo, 1835 .search = mb86a16_search, 1836 .init = mb86a16_init, 1837 .sleep = mb86a16_sleep, 1838 .read_status = mb86a16_read_status, 1839 1840 .read_ber = mb86a16_read_ber, 1841 .read_signal_strength = mb86a16_read_signal_strength, 1842 .read_snr = mb86a16_read_snr, 1843 .read_ucblocks = mb86a16_read_ucblocks, 1844 1845 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg, 1846 .diseqc_send_burst = mb86a16_send_diseqc_burst, 1847 .set_tone = mb86a16_set_tone, 1848 }; 1849 1850 struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, 1851 struct i2c_adapter *i2c_adap) 1852 { 1853 u8 dev_id = 0; 1854 struct mb86a16_state *state = NULL; 1855 1856 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL); 1857 if (state == NULL) 1858 goto error; 1859 1860 state->config = config; 1861 state->i2c_adap = i2c_adap; 1862 1863 mb86a16_read(state, 0x7f, &dev_id); 1864 if (dev_id != 0xfe) 1865 goto error; 1866 1867 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops)); 1868 state->frontend.demodulator_priv = state; 1869 state->frontend.ops.set_voltage = state->config->set_voltage; 1870 1871 return &state->frontend; 1872 error: 1873 kfree(state); 1874 return NULL; 1875 } 1876 EXPORT_SYMBOL(mb86a16_attach); 1877 MODULE_LICENSE("GPL"); 1878 MODULE_AUTHOR("Manu Abraham"); 1879