1 /* 2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver 3 4 Copyright (C) Manu Abraham (abraham.manu@gmail.com) 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/slab.h> 26 27 #include <media/dvb_frontend.h> 28 #include "mb86a16.h" 29 #include "mb86a16_priv.h" 30 31 static unsigned int verbose = 5; 32 module_param(verbose, int, 0644); 33 34 struct mb86a16_state { 35 struct i2c_adapter *i2c_adap; 36 const struct mb86a16_config *config; 37 struct dvb_frontend frontend; 38 39 /* tuning parameters */ 40 int frequency; 41 int srate; 42 43 /* Internal stuff */ 44 int master_clk; 45 int deci; 46 int csel; 47 int rsel; 48 }; 49 50 #define MB86A16_ERROR 0 51 #define MB86A16_NOTICE 1 52 #define MB86A16_INFO 2 53 #define MB86A16_DEBUG 3 54 55 #define dprintk(x, y, z, format, arg...) do { \ 56 if (z) { \ 57 if ((x > MB86A16_ERROR) && (x > y)) \ 58 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \ 59 else if ((x > MB86A16_NOTICE) && (x > y)) \ 60 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \ 61 else if ((x > MB86A16_INFO) && (x > y)) \ 62 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \ 63 else if ((x > MB86A16_DEBUG) && (x > y)) \ 64 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \ 65 } else { \ 66 if (x > y) \ 67 printk(format, ##arg); \ 68 } \ 69 } while (0) 70 71 #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()") 72 #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->") 73 74 static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) 75 { 76 int ret; 77 u8 buf[] = { reg, val }; 78 79 struct i2c_msg msg = { 80 .addr = state->config->demod_address, 81 .flags = 0, 82 .buf = buf, 83 .len = 2 84 }; 85 86 dprintk(verbose, MB86A16_DEBUG, 1, 87 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]", 88 state->config->demod_address, buf[0], buf[1]); 89 90 ret = i2c_transfer(state->i2c_adap, &msg, 1); 91 92 return (ret != 1) ? -EREMOTEIO : 0; 93 } 94 95 static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) 96 { 97 int ret; 98 u8 b0[] = { reg }; 99 u8 b1[] = { 0 }; 100 101 struct i2c_msg msg[] = { 102 { 103 .addr = state->config->demod_address, 104 .flags = 0, 105 .buf = b0, 106 .len = 1 107 }, { 108 .addr = state->config->demod_address, 109 .flags = I2C_M_RD, 110 .buf = b1, 111 .len = 1 112 } 113 }; 114 ret = i2c_transfer(state->i2c_adap, msg, 2); 115 if (ret != 2) { 116 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)", 117 reg, ret); 118 119 if (ret < 0) 120 return ret; 121 return -EREMOTEIO; 122 } 123 *val = b1[0]; 124 125 return ret; 126 } 127 128 static int CNTM_set(struct mb86a16_state *state, 129 unsigned char timint1, 130 unsigned char timint2, 131 unsigned char cnext) 132 { 133 unsigned char val; 134 135 val = (timint1 << 4) | (timint2 << 2) | cnext; 136 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0) 137 goto err; 138 139 return 0; 140 141 err: 142 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 143 return -EREMOTEIO; 144 } 145 146 static int smrt_set(struct mb86a16_state *state, int rate) 147 { 148 int tmp ; 149 int m ; 150 unsigned char STOFS0, STOFS1; 151 152 m = 1 << state->deci; 153 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk; 154 155 STOFS0 = tmp & 0x0ff; 156 STOFS1 = (tmp & 0xf00) >> 8; 157 158 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) | 159 (state->csel << 1) | 160 state->rsel) < 0) 161 goto err; 162 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0) 163 goto err; 164 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0) 165 goto err; 166 167 return 0; 168 err: 169 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 170 return -1; 171 } 172 173 static int srst(struct mb86a16_state *state) 174 { 175 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0) 176 goto err; 177 178 return 0; 179 err: 180 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 181 return -EREMOTEIO; 182 183 } 184 185 static int afcex_data_set(struct mb86a16_state *state, 186 unsigned char AFCEX_L, 187 unsigned char AFCEX_H) 188 { 189 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0) 190 goto err; 191 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0) 192 goto err; 193 194 return 0; 195 err: 196 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 197 198 return -1; 199 } 200 201 static int afcofs_data_set(struct mb86a16_state *state, 202 unsigned char AFCEX_L, 203 unsigned char AFCEX_H) 204 { 205 if (mb86a16_write(state, 0x58, AFCEX_L) < 0) 206 goto err; 207 if (mb86a16_write(state, 0x59, AFCEX_H) < 0) 208 goto err; 209 210 return 0; 211 err: 212 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 213 return -EREMOTEIO; 214 } 215 216 static int stlp_set(struct mb86a16_state *state, 217 unsigned char STRAS, 218 unsigned char STRBS) 219 { 220 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0) 221 goto err; 222 223 return 0; 224 err: 225 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 226 return -EREMOTEIO; 227 } 228 229 static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA) 230 { 231 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0) 232 goto err; 233 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0) 234 goto err; 235 236 return 0; 237 err: 238 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 239 return -EREMOTEIO; 240 } 241 242 static int initial_set(struct mb86a16_state *state) 243 { 244 if (stlp_set(state, 5, 7)) 245 goto err; 246 247 udelay(100); 248 if (afcex_data_set(state, 0, 0)) 249 goto err; 250 251 udelay(100); 252 if (afcofs_data_set(state, 0, 0)) 253 goto err; 254 255 udelay(100); 256 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0) 257 goto err; 258 if (mb86a16_write(state, 0x2f, 0x21) < 0) 259 goto err; 260 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0) 261 goto err; 262 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0) 263 goto err; 264 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0) 265 goto err; 266 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0) 267 goto err; 268 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0) 269 goto err; 270 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0) 271 goto err; 272 if (mb86a16_write(state, 0x54, 0xff) < 0) 273 goto err; 274 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0) 275 goto err; 276 277 return 0; 278 279 err: 280 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 281 return -EREMOTEIO; 282 } 283 284 static int S01T_set(struct mb86a16_state *state, 285 unsigned char s1t, 286 unsigned s0t) 287 { 288 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0) 289 goto err; 290 291 return 0; 292 err: 293 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 294 return -EREMOTEIO; 295 } 296 297 298 static int EN_set(struct mb86a16_state *state, 299 int cren, 300 int afcen) 301 { 302 unsigned char val; 303 304 val = 0x7a | (cren << 7) | (afcen << 2); 305 if (mb86a16_write(state, 0x49, val) < 0) 306 goto err; 307 308 return 0; 309 err: 310 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 311 return -EREMOTEIO; 312 } 313 314 static int AFCEXEN_set(struct mb86a16_state *state, 315 int afcexen, 316 int smrt) 317 { 318 unsigned char AFCA ; 319 320 if (smrt > 18875) 321 AFCA = 4; 322 else if (smrt > 9375) 323 AFCA = 3; 324 else if (smrt > 2250) 325 AFCA = 2; 326 else 327 AFCA = 1; 328 329 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0) 330 goto err; 331 332 return 0; 333 334 err: 335 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 336 return -EREMOTEIO; 337 } 338 339 static int DAGC_data_set(struct mb86a16_state *state, 340 unsigned char DAGCA, 341 unsigned char DAGCW) 342 { 343 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0) 344 goto err; 345 346 return 0; 347 348 err: 349 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 350 return -EREMOTEIO; 351 } 352 353 static void smrt_info_get(struct mb86a16_state *state, int rate) 354 { 355 if (rate >= 37501) { 356 state->deci = 0; state->csel = 0; state->rsel = 0; 357 } else if (rate >= 30001) { 358 state->deci = 0; state->csel = 0; state->rsel = 1; 359 } else if (rate >= 26251) { 360 state->deci = 0; state->csel = 1; state->rsel = 0; 361 } else if (rate >= 22501) { 362 state->deci = 0; state->csel = 1; state->rsel = 1; 363 } else if (rate >= 18751) { 364 state->deci = 1; state->csel = 0; state->rsel = 0; 365 } else if (rate >= 15001) { 366 state->deci = 1; state->csel = 0; state->rsel = 1; 367 } else if (rate >= 13126) { 368 state->deci = 1; state->csel = 1; state->rsel = 0; 369 } else if (rate >= 11251) { 370 state->deci = 1; state->csel = 1; state->rsel = 1; 371 } else if (rate >= 9376) { 372 state->deci = 2; state->csel = 0; state->rsel = 0; 373 } else if (rate >= 7501) { 374 state->deci = 2; state->csel = 0; state->rsel = 1; 375 } else if (rate >= 6563) { 376 state->deci = 2; state->csel = 1; state->rsel = 0; 377 } else if (rate >= 5626) { 378 state->deci = 2; state->csel = 1; state->rsel = 1; 379 } else if (rate >= 4688) { 380 state->deci = 3; state->csel = 0; state->rsel = 0; 381 } else if (rate >= 3751) { 382 state->deci = 3; state->csel = 0; state->rsel = 1; 383 } else if (rate >= 3282) { 384 state->deci = 3; state->csel = 1; state->rsel = 0; 385 } else if (rate >= 2814) { 386 state->deci = 3; state->csel = 1; state->rsel = 1; 387 } else if (rate >= 2344) { 388 state->deci = 4; state->csel = 0; state->rsel = 0; 389 } else if (rate >= 1876) { 390 state->deci = 4; state->csel = 0; state->rsel = 1; 391 } else if (rate >= 1641) { 392 state->deci = 4; state->csel = 1; state->rsel = 0; 393 } else if (rate >= 1407) { 394 state->deci = 4; state->csel = 1; state->rsel = 1; 395 } else if (rate >= 1172) { 396 state->deci = 5; state->csel = 0; state->rsel = 0; 397 } else if (rate >= 939) { 398 state->deci = 5; state->csel = 0; state->rsel = 1; 399 } else if (rate >= 821) { 400 state->deci = 5; state->csel = 1; state->rsel = 0; 401 } else { 402 state->deci = 5; state->csel = 1; state->rsel = 1; 403 } 404 405 if (state->csel == 0) 406 state->master_clk = 92000; 407 else 408 state->master_clk = 61333; 409 410 } 411 412 static int signal_det(struct mb86a16_state *state, 413 int smrt, 414 unsigned char *SIG) 415 { 416 int ret; 417 int smrtd; 418 unsigned char S[3]; 419 int i; 420 421 if (*SIG > 45) { 422 if (CNTM_set(state, 2, 1, 2) < 0) { 423 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 424 return -1; 425 } 426 } else { 427 if (CNTM_set(state, 3, 1, 2) < 0) { 428 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 429 return -1; 430 } 431 } 432 for (i = 0; i < 3; i++) { 433 if (i == 0) 434 smrtd = smrt * 98 / 100; 435 else if (i == 1) 436 smrtd = smrt; 437 else 438 smrtd = smrt * 102 / 100; 439 smrt_info_get(state, smrtd); 440 smrt_set(state, smrtd); 441 srst(state); 442 msleep_interruptible(10); 443 if (mb86a16_read(state, 0x37, &(S[i])) != 2) { 444 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 445 return -EREMOTEIO; 446 } 447 } 448 if ((S[1] > S[0] * 112 / 100) && (S[1] > S[2] * 112 / 100)) 449 ret = 1; 450 else 451 ret = 0; 452 453 *SIG = S[1]; 454 455 if (CNTM_set(state, 0, 1, 2) < 0) { 456 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 457 return -1; 458 } 459 460 return ret; 461 } 462 463 static int rf_val_set(struct mb86a16_state *state, 464 int f, 465 int smrt, 466 unsigned char R) 467 { 468 unsigned char C, F, B; 469 int M; 470 unsigned char rf_val[5]; 471 int ack = -1; 472 473 if (smrt > 37750) 474 C = 1; 475 else if (smrt > 18875) 476 C = 2; 477 else if (smrt > 5500) 478 C = 3; 479 else 480 C = 4; 481 482 if (smrt > 30500) 483 F = 3; 484 else if (smrt > 9375) 485 F = 1; 486 else if (smrt > 4625) 487 F = 0; 488 else 489 F = 2; 490 491 if (f < 1060) 492 B = 0; 493 else if (f < 1175) 494 B = 1; 495 else if (f < 1305) 496 B = 2; 497 else if (f < 1435) 498 B = 3; 499 else if (f < 1570) 500 B = 4; 501 else if (f < 1715) 502 B = 5; 503 else if (f < 1845) 504 B = 6; 505 else if (f < 1980) 506 B = 7; 507 else if (f < 2080) 508 B = 8; 509 else 510 B = 9; 511 512 M = f * (1 << R) / 2; 513 514 rf_val[0] = 0x01 | (C << 3) | (F << 1); 515 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12); 516 rf_val[2] = (M & 0x00ff0) >> 4; 517 rf_val[3] = ((M & 0x0000f) << 4) | B; 518 519 /* Frequency Set */ 520 if (mb86a16_write(state, 0x21, rf_val[0]) < 0) 521 ack = 0; 522 if (mb86a16_write(state, 0x22, rf_val[1]) < 0) 523 ack = 0; 524 if (mb86a16_write(state, 0x23, rf_val[2]) < 0) 525 ack = 0; 526 if (mb86a16_write(state, 0x24, rf_val[3]) < 0) 527 ack = 0; 528 if (mb86a16_write(state, 0x25, 0x01) < 0) 529 ack = 0; 530 if (ack == 0) { 531 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error"); 532 return -EREMOTEIO; 533 } 534 535 return 0; 536 } 537 538 static int afcerr_chk(struct mb86a16_state *state) 539 { 540 unsigned char AFCM_L, AFCM_H ; 541 int AFCM ; 542 int afcm, afcerr ; 543 544 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2) 545 goto err; 546 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2) 547 goto err; 548 549 AFCM = (AFCM_H << 8) + AFCM_L; 550 551 if (AFCM > 2048) 552 afcm = AFCM - 4096; 553 else 554 afcm = AFCM; 555 afcerr = afcm * state->master_clk / 8192; 556 557 return afcerr; 558 559 err: 560 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 561 return -EREMOTEIO; 562 } 563 564 static int dagcm_val_get(struct mb86a16_state *state) 565 { 566 int DAGCM; 567 unsigned char DAGCM_H, DAGCM_L; 568 569 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2) 570 goto err; 571 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2) 572 goto err; 573 574 DAGCM = (DAGCM_H << 8) + DAGCM_L; 575 576 return DAGCM; 577 578 err: 579 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 580 return -EREMOTEIO; 581 } 582 583 static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status) 584 { 585 u8 stat, stat2; 586 struct mb86a16_state *state = fe->demodulator_priv; 587 588 *status = 0; 589 590 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2) 591 goto err; 592 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2) 593 goto err; 594 if ((stat > 25) && (stat2 > 25)) 595 *status |= FE_HAS_SIGNAL; 596 if ((stat > 45) && (stat2 > 45)) 597 *status |= FE_HAS_CARRIER; 598 599 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2) 600 goto err; 601 602 if (stat & 0x01) 603 *status |= FE_HAS_SYNC; 604 if (stat & 0x01) 605 *status |= FE_HAS_VITERBI; 606 607 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2) 608 goto err; 609 610 if ((stat & 0x0f) && (*status & FE_HAS_VITERBI)) 611 *status |= FE_HAS_LOCK; 612 613 return 0; 614 615 err: 616 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 617 return -EREMOTEIO; 618 } 619 620 static int sync_chk(struct mb86a16_state *state, 621 unsigned char *VIRM) 622 { 623 unsigned char val; 624 int sync; 625 626 if (mb86a16_read(state, 0x0d, &val) != 2) 627 goto err; 628 629 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val); 630 sync = val & 0x01; 631 *VIRM = (val & 0x1c) >> 2; 632 633 return sync; 634 err: 635 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 636 *VIRM = 0; 637 return -EREMOTEIO; 638 639 } 640 641 static int freqerr_chk(struct mb86a16_state *state, 642 int fTP, 643 int smrt, 644 int unit) 645 { 646 unsigned char CRM, AFCML, AFCMH; 647 unsigned char temp1, temp2, temp3; 648 int crm, afcm, AFCM; 649 int crrerr, afcerr; /* kHz */ 650 int frqerr; /* MHz */ 651 int afcen, afcexen = 0; 652 int R, M, fOSC, fOSC_OFS; 653 654 if (mb86a16_read(state, 0x43, &CRM) != 2) 655 goto err; 656 657 if (CRM > 127) 658 crm = CRM - 256; 659 else 660 crm = CRM; 661 662 crrerr = smrt * crm / 256; 663 if (mb86a16_read(state, 0x49, &temp1) != 2) 664 goto err; 665 666 afcen = (temp1 & 0x04) >> 2; 667 if (afcen == 0) { 668 if (mb86a16_read(state, 0x2a, &temp1) != 2) 669 goto err; 670 afcexen = (temp1 & 0x20) >> 5; 671 } 672 673 if (afcen == 1) { 674 if (mb86a16_read(state, 0x0e, &AFCML) != 2) 675 goto err; 676 if (mb86a16_read(state, 0x0f, &AFCMH) != 2) 677 goto err; 678 } else if (afcexen == 1) { 679 if (mb86a16_read(state, 0x2b, &AFCML) != 2) 680 goto err; 681 if (mb86a16_read(state, 0x2c, &AFCMH) != 2) 682 goto err; 683 } 684 if ((afcen == 1) || (afcexen == 1)) { 685 smrt_info_get(state, smrt); 686 AFCM = ((AFCMH & 0x01) << 8) + AFCML; 687 if (AFCM > 255) 688 afcm = AFCM - 512; 689 else 690 afcm = AFCM; 691 692 afcerr = afcm * state->master_clk / 8192; 693 } else 694 afcerr = 0; 695 696 if (mb86a16_read(state, 0x22, &temp1) != 2) 697 goto err; 698 if (mb86a16_read(state, 0x23, &temp2) != 2) 699 goto err; 700 if (mb86a16_read(state, 0x24, &temp3) != 2) 701 goto err; 702 703 R = (temp1 & 0xe0) >> 5; 704 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4); 705 if (R == 0) 706 fOSC = 2 * M; 707 else 708 fOSC = M; 709 710 fOSC_OFS = fOSC - fTP; 711 712 if (unit == 0) { /* MHz */ 713 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0) 714 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000; 715 else 716 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000; 717 } else { /* kHz */ 718 frqerr = crrerr + afcerr + fOSC_OFS * 1000; 719 } 720 721 return frqerr; 722 err: 723 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 724 return -EREMOTEIO; 725 } 726 727 static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt) 728 { 729 unsigned char R; 730 731 if (smrt > 9375) 732 R = 0; 733 else 734 R = 1; 735 736 return R; 737 } 738 739 static void swp_info_get(struct mb86a16_state *state, 740 int fOSC_start, 741 int smrt, 742 int v, int R, 743 int swp_ofs, 744 int *fOSC, 745 int *afcex_freq, 746 unsigned char *AFCEX_L, 747 unsigned char *AFCEX_H) 748 { 749 int AFCEX ; 750 int crnt_swp_freq ; 751 752 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; 753 754 if (R == 0) 755 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2; 756 else 757 *fOSC = (crnt_swp_freq + 500) / 1000; 758 759 if (*fOSC >= crnt_swp_freq) 760 *afcex_freq = *fOSC * 1000 - crnt_swp_freq; 761 else 762 *afcex_freq = crnt_swp_freq - *fOSC * 1000; 763 764 AFCEX = *afcex_freq * 8192 / state->master_clk; 765 *AFCEX_L = AFCEX & 0x00ff; 766 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 767 } 768 769 770 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin, 771 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1) 772 { 773 int swp_freq ; 774 775 if ((i % 2 == 1) && (v <= vmax)) { 776 /* positive v (case 1) */ 777 if ((v - 1 == vmin) && 778 (*(V + 30 + v) >= 0) && 779 (*(V + 30 + v - 1) >= 0) && 780 (*(V + 30 + v - 1) > *(V + 30 + v)) && 781 (*(V + 30 + v - 1) > SIGMIN)) { 782 783 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 784 *SIG1 = *(V + 30 + v - 1); 785 } else if ((v == vmax) && 786 (*(V + 30 + v) >= 0) && 787 (*(V + 30 + v - 1) >= 0) && 788 (*(V + 30 + v) > *(V + 30 + v - 1)) && 789 (*(V + 30 + v) > SIGMIN)) { 790 /* (case 2) */ 791 swp_freq = fOSC * 1000 + afcex_freq; 792 *SIG1 = *(V + 30 + v); 793 } else if ((*(V + 30 + v) > 0) && 794 (*(V + 30 + v - 1) > 0) && 795 (*(V + 30 + v - 2) > 0) && 796 (*(V + 30 + v - 3) > 0) && 797 (*(V + 30 + v - 1) > *(V + 30 + v)) && 798 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) && 799 ((*(V + 30 + v - 1) > SIGMIN) || 800 (*(V + 30 + v - 2) > SIGMIN))) { 801 /* (case 3) */ 802 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) { 803 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 804 *SIG1 = *(V + 30 + v - 1); 805 } else { 806 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2; 807 *SIG1 = *(V + 30 + v - 2); 808 } 809 } else if ((v == vmax) && 810 (*(V + 30 + v) >= 0) && 811 (*(V + 30 + v - 1) >= 0) && 812 (*(V + 30 + v - 2) >= 0) && 813 (*(V + 30 + v) > *(V + 30 + v - 2)) && 814 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) && 815 ((*(V + 30 + v) > SIGMIN) || 816 (*(V + 30 + v - 1) > SIGMIN))) { 817 /* (case 4) */ 818 if (*(V + 30 + v) >= *(V + 30 + v - 1)) { 819 swp_freq = fOSC * 1000 + afcex_freq; 820 *SIG1 = *(V + 30 + v); 821 } else { 822 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 823 *SIG1 = *(V + 30 + v - 1); 824 } 825 } else { 826 swp_freq = -1 ; 827 } 828 } else if ((i % 2 == 0) && (v >= vmin)) { 829 /* Negative v (case 1) */ 830 if ((*(V + 30 + v) > 0) && 831 (*(V + 30 + v + 1) > 0) && 832 (*(V + 30 + v + 2) > 0) && 833 (*(V + 30 + v + 1) > *(V + 30 + v)) && 834 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 835 (*(V + 30 + v + 1) > SIGMIN)) { 836 837 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 838 *SIG1 = *(V + 30 + v + 1); 839 } else if ((v + 1 == vmax) && 840 (*(V + 30 + v) >= 0) && 841 (*(V + 30 + v + 1) >= 0) && 842 (*(V + 30 + v + 1) > *(V + 30 + v)) && 843 (*(V + 30 + v + 1) > SIGMIN)) { 844 /* (case 2) */ 845 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 846 *SIG1 = *(V + 30 + v); 847 } else if ((v == vmin) && 848 (*(V + 30 + v) > 0) && 849 (*(V + 30 + v + 1) > 0) && 850 (*(V + 30 + v + 2) > 0) && 851 (*(V + 30 + v) > *(V + 30 + v + 1)) && 852 (*(V + 30 + v) > *(V + 30 + v + 2)) && 853 (*(V + 30 + v) > SIGMIN)) { 854 /* (case 3) */ 855 swp_freq = fOSC * 1000 + afcex_freq; 856 *SIG1 = *(V + 30 + v); 857 } else if ((*(V + 30 + v) >= 0) && 858 (*(V + 30 + v + 1) >= 0) && 859 (*(V + 30 + v + 2) >= 0) && 860 (*(V + 30 + v + 3) >= 0) && 861 (*(V + 30 + v + 1) > *(V + 30 + v)) && 862 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) && 863 ((*(V + 30 + v + 1) > SIGMIN) || 864 (*(V + 30 + v + 2) > SIGMIN))) { 865 /* (case 4) */ 866 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 867 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 868 *SIG1 = *(V + 30 + v + 1); 869 } else { 870 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 871 *SIG1 = *(V + 30 + v + 2); 872 } 873 } else if ((*(V + 30 + v) >= 0) && 874 (*(V + 30 + v + 1) >= 0) && 875 (*(V + 30 + v + 2) >= 0) && 876 (*(V + 30 + v + 3) >= 0) && 877 (*(V + 30 + v) > *(V + 30 + v + 2)) && 878 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 879 (*(V + 30 + v) > *(V + 30 + v + 3)) && 880 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) && 881 ((*(V + 30 + v) > SIGMIN) || 882 (*(V + 30 + v + 1) > SIGMIN))) { 883 /* (case 5) */ 884 if (*(V + 30 + v) >= *(V + 30 + v + 1)) { 885 swp_freq = fOSC * 1000 + afcex_freq; 886 *SIG1 = *(V + 30 + v); 887 } else { 888 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 889 *SIG1 = *(V + 30 + v + 1); 890 } 891 } else if ((v + 2 == vmin) && 892 (*(V + 30 + v) >= 0) && 893 (*(V + 30 + v + 1) >= 0) && 894 (*(V + 30 + v + 2) >= 0) && 895 (*(V + 30 + v + 1) > *(V + 30 + v)) && 896 (*(V + 30 + v + 2) > *(V + 30 + v)) && 897 ((*(V + 30 + v + 1) > SIGMIN) || 898 (*(V + 30 + v + 2) > SIGMIN))) { 899 /* (case 6) */ 900 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 901 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 902 *SIG1 = *(V + 30 + v + 1); 903 } else { 904 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 905 *SIG1 = *(V + 30 + v + 2); 906 } 907 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) { 908 swp_freq = fOSC * 1000; 909 *SIG1 = *(V + 30 + v); 910 } else 911 swp_freq = -1; 912 } else 913 swp_freq = -1; 914 915 return swp_freq; 916 } 917 918 static void swp_info_get2(struct mb86a16_state *state, 919 int smrt, 920 int R, 921 int swp_freq, 922 int *afcex_freq, 923 int *fOSC, 924 unsigned char *AFCEX_L, 925 unsigned char *AFCEX_H) 926 { 927 int AFCEX ; 928 929 if (R == 0) 930 *fOSC = (swp_freq + 1000) / 2000 * 2; 931 else 932 *fOSC = (swp_freq + 500) / 1000; 933 934 if (*fOSC >= swp_freq) 935 *afcex_freq = *fOSC * 1000 - swp_freq; 936 else 937 *afcex_freq = swp_freq - *fOSC * 1000; 938 939 AFCEX = *afcex_freq * 8192 / state->master_clk; 940 *AFCEX_L = AFCEX & 0x00ff; 941 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 942 } 943 944 static void afcex_info_get(struct mb86a16_state *state, 945 int afcex_freq, 946 unsigned char *AFCEX_L, 947 unsigned char *AFCEX_H) 948 { 949 int AFCEX ; 950 951 AFCEX = afcex_freq * 8192 / state->master_clk; 952 *AFCEX_L = AFCEX & 0x00ff; 953 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 954 } 955 956 static int SEQ_set(struct mb86a16_state *state, unsigned char loop) 957 { 958 /* SLOCK0 = 0 */ 959 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) { 960 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 961 return -EREMOTEIO; 962 } 963 964 return 0; 965 } 966 967 static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV) 968 { 969 /* Viterbi Rate, IQ Settings */ 970 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) { 971 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 972 return -EREMOTEIO; 973 } 974 975 return 0; 976 } 977 978 static int FEC_srst(struct mb86a16_state *state) 979 { 980 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) { 981 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 982 return -EREMOTEIO; 983 } 984 985 return 0; 986 } 987 988 static int S2T_set(struct mb86a16_state *state, unsigned char S2T) 989 { 990 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) { 991 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 992 return -EREMOTEIO; 993 } 994 995 return 0; 996 } 997 998 static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T) 999 { 1000 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) { 1001 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1002 return -EREMOTEIO; 1003 } 1004 1005 return 0; 1006 } 1007 1008 1009 static int mb86a16_set_fe(struct mb86a16_state *state) 1010 { 1011 u8 agcval, cnmval; 1012 1013 int i, j; 1014 int fOSC = 0; 1015 int fOSC_start = 0; 1016 int wait_t; 1017 int fcp; 1018 int swp_ofs; 1019 int V[60]; 1020 u8 SIG1MIN; 1021 1022 unsigned char CREN, AFCEN, AFCEXEN; 1023 unsigned char SIG1; 1024 unsigned char TIMINT1, TIMINT2, TIMEXT; 1025 unsigned char S0T, S1T; 1026 unsigned char S2T; 1027 /* unsigned char S2T, S3T; */ 1028 unsigned char S4T, S5T; 1029 unsigned char AFCEX_L, AFCEX_H; 1030 unsigned char R; 1031 unsigned char VIRM; 1032 unsigned char ETH, VIA; 1033 unsigned char junk; 1034 1035 int loop; 1036 int ftemp; 1037 int v, vmax, vmin; 1038 int vmax_his, vmin_his; 1039 int swp_freq, prev_swp_freq[20]; 1040 int prev_freq_num; 1041 int signal_dupl; 1042 int afcex_freq; 1043 int signal; 1044 int afcerr; 1045 int temp_freq, delta_freq; 1046 int dagcm[4]; 1047 int smrt_d; 1048 /* int freq_err; */ 1049 int n; 1050 int ret = -1; 1051 int sync; 1052 1053 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate); 1054 1055 fcp = 3000; 1056 swp_ofs = state->srate / 4; 1057 1058 for (i = 0; i < 60; i++) 1059 V[i] = -1; 1060 1061 for (i = 0; i < 20; i++) 1062 prev_swp_freq[i] = 0; 1063 1064 SIG1MIN = 25; 1065 1066 for (n = 0; ((n < 3) && (ret == -1)); n++) { 1067 SEQ_set(state, 0); 1068 iq_vt_set(state, 0); 1069 1070 CREN = 0; 1071 AFCEN = 0; 1072 AFCEXEN = 1; 1073 TIMINT1 = 0; 1074 TIMINT2 = 1; 1075 TIMEXT = 2; 1076 S1T = 0; 1077 S0T = 0; 1078 1079 if (initial_set(state) < 0) { 1080 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed"); 1081 return -1; 1082 } 1083 if (DAGC_data_set(state, 3, 2) < 0) { 1084 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1085 return -1; 1086 } 1087 if (EN_set(state, CREN, AFCEN) < 0) { 1088 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1089 return -1; /* (0, 0) */ 1090 } 1091 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1092 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1093 return -1; /* (1, smrt) = (1, symbolrate) */ 1094 } 1095 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) { 1096 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error"); 1097 return -1; /* (0, 1, 2) */ 1098 } 1099 if (S01T_set(state, S1T, S0T) < 0) { 1100 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1101 return -1; /* (0, 0) */ 1102 } 1103 smrt_info_get(state, state->srate); 1104 if (smrt_set(state, state->srate) < 0) { 1105 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error"); 1106 return -1; 1107 } 1108 1109 R = vco_dev_get(state, state->srate); 1110 if (R == 1) 1111 fOSC_start = state->frequency; 1112 1113 else if (R == 0) { 1114 if (state->frequency % 2 == 0) { 1115 fOSC_start = state->frequency; 1116 } else { 1117 fOSC_start = state->frequency + 1; 1118 if (fOSC_start > 2150) 1119 fOSC_start = state->frequency - 1; 1120 } 1121 } 1122 loop = 1; 1123 ftemp = fOSC_start * 1000; 1124 vmax = 0 ; 1125 while (loop == 1) { 1126 ftemp = ftemp + swp_ofs; 1127 vmax++; 1128 1129 /* Upper bound */ 1130 if (ftemp > 2150000) { 1131 loop = 0; 1132 vmax--; 1133 } else { 1134 if ((ftemp == 2150000) || 1135 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4)) 1136 loop = 0; 1137 } 1138 } 1139 1140 loop = 1; 1141 ftemp = fOSC_start * 1000; 1142 vmin = 0 ; 1143 while (loop == 1) { 1144 ftemp = ftemp - swp_ofs; 1145 vmin--; 1146 1147 /* Lower bound */ 1148 if (ftemp < 950000) { 1149 loop = 0; 1150 vmin++; 1151 } else { 1152 if ((ftemp == 950000) || 1153 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4)) 1154 loop = 0; 1155 } 1156 } 1157 1158 wait_t = (8000 + state->srate / 2) / state->srate; 1159 if (wait_t == 0) 1160 wait_t = 1; 1161 1162 i = 0; 1163 j = 0; 1164 prev_freq_num = 0; 1165 loop = 1; 1166 signal = 0; 1167 vmax_his = 0; 1168 vmin_his = 0; 1169 v = 0; 1170 1171 while (loop == 1) { 1172 swp_info_get(state, fOSC_start, state->srate, 1173 v, R, swp_ofs, &fOSC, 1174 &afcex_freq, &AFCEX_L, &AFCEX_H); 1175 1176 udelay(100); 1177 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1178 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1179 return -1; 1180 } 1181 udelay(100); 1182 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1183 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1184 return -1; 1185 } 1186 if (srst(state) < 0) { 1187 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1188 return -1; 1189 } 1190 msleep_interruptible(wait_t); 1191 1192 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1193 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1194 return -1; 1195 } 1196 V[30 + v] = SIG1 ; 1197 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin, 1198 SIG1MIN, fOSC, afcex_freq, 1199 swp_ofs, &SIG1); /* changed */ 1200 1201 signal_dupl = 0; 1202 for (j = 0; j < prev_freq_num; j++) { 1203 if ((abs(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) { 1204 signal_dupl = 1; 1205 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j); 1206 } 1207 } 1208 if ((signal_dupl == 0) && (swp_freq > 0) && (abs(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) { 1209 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate); 1210 prev_swp_freq[prev_freq_num] = swp_freq; 1211 prev_freq_num++; 1212 swp_info_get2(state, state->srate, R, swp_freq, 1213 &afcex_freq, &fOSC, 1214 &AFCEX_L, &AFCEX_H); 1215 1216 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1217 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1218 return -1; 1219 } 1220 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1221 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1222 return -1; 1223 } 1224 signal = signal_det(state, state->srate, &SIG1); 1225 if (signal == 1) { 1226 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****"); 1227 loop = 0; 1228 } else { 1229 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again..."); 1230 smrt_info_get(state, state->srate); 1231 if (smrt_set(state, state->srate) < 0) { 1232 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1233 return -1; 1234 } 1235 } 1236 } 1237 if (v > vmax) 1238 vmax_his = 1 ; 1239 if (v < vmin) 1240 vmin_his = 1 ; 1241 i++; 1242 1243 if ((i % 2 == 1) && (vmax_his == 1)) 1244 i++; 1245 if ((i % 2 == 0) && (vmin_his == 1)) 1246 i++; 1247 1248 if (i % 2 == 1) 1249 v = (i + 1) / 2; 1250 else 1251 v = -i / 2; 1252 1253 if ((vmax_his == 1) && (vmin_his == 1)) 1254 loop = 0 ; 1255 } 1256 1257 if (signal == 1) { 1258 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check"); 1259 S1T = 7 ; 1260 S0T = 1 ; 1261 CREN = 0 ; 1262 AFCEN = 1 ; 1263 AFCEXEN = 0 ; 1264 1265 if (S01T_set(state, S1T, S0T) < 0) { 1266 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1267 return -1; 1268 } 1269 smrt_info_get(state, state->srate); 1270 if (smrt_set(state, state->srate) < 0) { 1271 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1272 return -1; 1273 } 1274 if (EN_set(state, CREN, AFCEN) < 0) { 1275 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1276 return -1; 1277 } 1278 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1279 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1280 return -1; 1281 } 1282 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H); 1283 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1284 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error"); 1285 return -1; 1286 } 1287 if (srst(state) < 0) { 1288 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1289 return -1; 1290 } 1291 /* delay 4~200 */ 1292 wait_t = 200000 / state->master_clk + 200000 / state->srate; 1293 msleep(wait_t); 1294 afcerr = afcerr_chk(state); 1295 if (afcerr == -1) 1296 return -1; 1297 1298 swp_freq = fOSC * 1000 + afcerr ; 1299 AFCEXEN = 1 ; 1300 if (state->srate >= 1500) 1301 smrt_d = state->srate / 3; 1302 else 1303 smrt_d = state->srate / 2; 1304 smrt_info_get(state, smrt_d); 1305 if (smrt_set(state, smrt_d) < 0) { 1306 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1307 return -1; 1308 } 1309 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) { 1310 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1311 return -1; 1312 } 1313 R = vco_dev_get(state, smrt_d); 1314 if (DAGC_data_set(state, 2, 0) < 0) { 1315 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1316 return -1; 1317 } 1318 for (i = 0; i < 3; i++) { 1319 temp_freq = swp_freq + (i - 1) * state->srate / 8; 1320 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1321 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1322 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1323 return -1; 1324 } 1325 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1326 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1327 return -1; 1328 } 1329 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1330 msleep(wait_t); 1331 dagcm[i] = dagcm_val_get(state); 1332 } 1333 if ((dagcm[0] > dagcm[1]) && 1334 (dagcm[0] > dagcm[2]) && 1335 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) { 1336 1337 temp_freq = swp_freq - 2 * state->srate / 8; 1338 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1339 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1340 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1341 return -1; 1342 } 1343 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1344 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1345 return -1; 1346 } 1347 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1348 msleep(wait_t); 1349 dagcm[3] = dagcm_val_get(state); 1350 if (dagcm[3] > dagcm[1]) 1351 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300; 1352 else 1353 delta_freq = 0; 1354 } else if ((dagcm[2] > dagcm[1]) && 1355 (dagcm[2] > dagcm[0]) && 1356 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) { 1357 1358 temp_freq = swp_freq + 2 * state->srate / 8; 1359 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1360 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1361 dprintk(verbose, MB86A16_ERROR, 1, "rf val set"); 1362 return -1; 1363 } 1364 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1365 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1366 return -1; 1367 } 1368 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1369 msleep(wait_t); 1370 dagcm[3] = dagcm_val_get(state); 1371 if (dagcm[3] > dagcm[1]) 1372 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300; 1373 else 1374 delta_freq = 0 ; 1375 1376 } else { 1377 delta_freq = 0 ; 1378 } 1379 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq); 1380 swp_freq += delta_freq; 1381 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq); 1382 if (abs(state->frequency * 1000 - swp_freq) > 3800) { 1383 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !"); 1384 } else { 1385 1386 S1T = 0; 1387 S0T = 3; 1388 CREN = 1; 1389 AFCEN = 0; 1390 AFCEXEN = 1; 1391 1392 if (S01T_set(state, S1T, S0T) < 0) { 1393 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1394 return -1; 1395 } 1396 if (DAGC_data_set(state, 0, 0) < 0) { 1397 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1398 return -1; 1399 } 1400 R = vco_dev_get(state, state->srate); 1401 smrt_info_get(state, state->srate); 1402 if (smrt_set(state, state->srate) < 0) { 1403 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1404 return -1; 1405 } 1406 if (EN_set(state, CREN, AFCEN) < 0) { 1407 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1408 return -1; 1409 } 1410 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1411 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1412 return -1; 1413 } 1414 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1415 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1416 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1417 return -1; 1418 } 1419 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1420 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1421 return -1; 1422 } 1423 if (srst(state) < 0) { 1424 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1425 return -1; 1426 } 1427 wait_t = 7 + (10000 + state->srate / 2) / state->srate; 1428 if (wait_t == 0) 1429 wait_t = 1; 1430 msleep_interruptible(wait_t); 1431 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1432 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1433 return -EREMOTEIO; 1434 } 1435 1436 if (SIG1 > 110) { 1437 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6; 1438 wait_t = 7 + (917504 + state->srate / 2) / state->srate; 1439 } else if (SIG1 > 105) { 1440 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1441 wait_t = 7 + (1048576 + state->srate / 2) / state->srate; 1442 } else if (SIG1 > 85) { 1443 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1444 wait_t = 7 + (1310720 + state->srate / 2) / state->srate; 1445 } else if (SIG1 > 65) { 1446 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1447 wait_t = 7 + (1572864 + state->srate / 2) / state->srate; 1448 } else { 1449 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1450 wait_t = 7 + (2097152 + state->srate / 2) / state->srate; 1451 } 1452 wait_t *= 2; /* FOS */ 1453 S2T_set(state, S2T); 1454 S45T_set(state, S4T, S5T); 1455 Vi_set(state, ETH, VIA); 1456 srst(state); 1457 msleep_interruptible(wait_t); 1458 sync = sync_chk(state, &VIRM); 1459 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync); 1460 if (VIRM) { 1461 if (VIRM == 4) { 1462 /* 5/6 */ 1463 if (SIG1 > 110) 1464 wait_t = (786432 + state->srate / 2) / state->srate; 1465 else 1466 wait_t = (1572864 + state->srate / 2) / state->srate; 1467 if (state->srate < 5000) 1468 /* FIXME ! , should be a long wait ! */ 1469 msleep_interruptible(wait_t); 1470 else 1471 msleep_interruptible(wait_t); 1472 1473 if (sync_chk(state, &junk) == 0) { 1474 iq_vt_set(state, 1); 1475 FEC_srst(state); 1476 } 1477 } 1478 /* 1/2, 2/3, 3/4, 7/8 */ 1479 if (SIG1 > 110) 1480 wait_t = (786432 + state->srate / 2) / state->srate; 1481 else 1482 wait_t = (1572864 + state->srate / 2) / state->srate; 1483 msleep_interruptible(wait_t); 1484 SEQ_set(state, 1); 1485 } else { 1486 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC"); 1487 SEQ_set(state, 1); 1488 ret = -1; 1489 } 1490 } 1491 } else { 1492 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL"); 1493 ret = -1; 1494 } 1495 1496 sync = sync_chk(state, &junk); 1497 if (sync) { 1498 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******"); 1499 freqerr_chk(state, state->frequency, state->srate, 1); 1500 ret = 0; 1501 break; 1502 } 1503 } 1504 1505 mb86a16_read(state, 0x15, &agcval); 1506 mb86a16_read(state, 0x26, &cnmval); 1507 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval); 1508 1509 return ret; 1510 } 1511 1512 static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe, 1513 struct dvb_diseqc_master_cmd *cmd) 1514 { 1515 struct mb86a16_state *state = fe->demodulator_priv; 1516 int i; 1517 u8 regs; 1518 1519 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1520 goto err; 1521 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1522 goto err; 1523 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1524 goto err; 1525 1526 regs = 0x18; 1527 1528 if (cmd->msg_len > 5 || cmd->msg_len < 4) 1529 return -EINVAL; 1530 1531 for (i = 0; i < cmd->msg_len; i++) { 1532 if (mb86a16_write(state, regs, cmd->msg[i]) < 0) 1533 goto err; 1534 1535 regs++; 1536 } 1537 i += 0x90; 1538 1539 msleep_interruptible(10); 1540 1541 if (mb86a16_write(state, MB86A16_DCC1, i) < 0) 1542 goto err; 1543 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1544 goto err; 1545 1546 return 0; 1547 1548 err: 1549 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1550 return -EREMOTEIO; 1551 } 1552 1553 static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, 1554 enum fe_sec_mini_cmd burst) 1555 { 1556 struct mb86a16_state *state = fe->demodulator_priv; 1557 1558 switch (burst) { 1559 case SEC_MINI_A: 1560 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1561 MB86A16_DCC1_TBEN | 1562 MB86A16_DCC1_TBO) < 0) 1563 goto err; 1564 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1565 goto err; 1566 break; 1567 case SEC_MINI_B: 1568 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1569 MB86A16_DCC1_TBEN) < 0) 1570 goto err; 1571 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1572 goto err; 1573 break; 1574 } 1575 1576 return 0; 1577 err: 1578 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1579 return -EREMOTEIO; 1580 } 1581 1582 static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 1583 { 1584 struct mb86a16_state *state = fe->demodulator_priv; 1585 1586 switch (tone) { 1587 case SEC_TONE_ON: 1588 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0) 1589 goto err; 1590 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1591 MB86A16_DCC1_CTOE) < 0) 1592 1593 goto err; 1594 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1595 goto err; 1596 break; 1597 case SEC_TONE_OFF: 1598 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1599 goto err; 1600 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1601 goto err; 1602 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1603 goto err; 1604 break; 1605 default: 1606 return -EINVAL; 1607 } 1608 return 0; 1609 1610 err: 1611 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1612 return -EREMOTEIO; 1613 } 1614 1615 static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe) 1616 { 1617 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1618 struct mb86a16_state *state = fe->demodulator_priv; 1619 1620 state->frequency = p->frequency / 1000; 1621 state->srate = p->symbol_rate / 1000; 1622 1623 if (!mb86a16_set_fe(state)) { 1624 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK"); 1625 return DVBFE_ALGO_SEARCH_SUCCESS; 1626 } 1627 1628 dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!"); 1629 return DVBFE_ALGO_SEARCH_FAILED; 1630 } 1631 1632 static void mb86a16_release(struct dvb_frontend *fe) 1633 { 1634 struct mb86a16_state *state = fe->demodulator_priv; 1635 kfree(state); 1636 } 1637 1638 static int mb86a16_init(struct dvb_frontend *fe) 1639 { 1640 return 0; 1641 } 1642 1643 static int mb86a16_sleep(struct dvb_frontend *fe) 1644 { 1645 return 0; 1646 } 1647 1648 static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber) 1649 { 1650 u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst; 1651 u32 timer; 1652 1653 struct mb86a16_state *state = fe->demodulator_priv; 1654 1655 *ber = 0; 1656 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2) 1657 goto err; 1658 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2) 1659 goto err; 1660 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2) 1661 goto err; 1662 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2) 1663 goto err; 1664 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2) 1665 goto err; 1666 /* BER monitor invalid when BER_EN = 0 */ 1667 if (ber_mon & 0x04) { 1668 /* coarse, fast calculation */ 1669 *ber = ber_tab & 0x1f; 1670 dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber); 1671 if (ber_mon & 0x01) { 1672 /* 1673 * BER_SEL = 1, The monitored BER is the estimated 1674 * value with a Reed-Solomon decoder error amount at 1675 * the deinterleaver output. 1676 * monitored BER is expressed as a 20 bit output in total 1677 */ 1678 ber_rst = (ber_mon >> 3) & 0x03; 1679 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1680 if (ber_rst == 0) 1681 timer = 12500000; 1682 else if (ber_rst == 1) 1683 timer = 25000000; 1684 else if (ber_rst == 2) 1685 timer = 50000000; 1686 else /* ber_rst == 3 */ 1687 timer = 100000000; 1688 1689 *ber /= timer; 1690 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1691 } else { 1692 /* 1693 * BER_SEL = 0, The monitored BER is the estimated 1694 * value with a Viterbi decoder error amount at the 1695 * QPSK demodulator output. 1696 * monitored BER is expressed as a 24 bit output in total 1697 */ 1698 ber_tim = (ber_mon >> 1) & 0x01; 1699 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1700 if (ber_tim == 0) 1701 timer = 16; 1702 else /* ber_tim == 1 */ 1703 timer = 24; 1704 1705 *ber /= 2 ^ timer; 1706 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1707 } 1708 } 1709 return 0; 1710 err: 1711 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1712 return -EREMOTEIO; 1713 } 1714 1715 static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1716 { 1717 u8 agcm = 0; 1718 struct mb86a16_state *state = fe->demodulator_priv; 1719 1720 *strength = 0; 1721 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) { 1722 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1723 return -EREMOTEIO; 1724 } 1725 1726 *strength = ((0xff - agcm) * 100) / 256; 1727 dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength); 1728 *strength = (0xffff - 0xff) + agcm; 1729 1730 return 0; 1731 } 1732 1733 struct cnr { 1734 u8 cn_reg; 1735 u8 cn_val; 1736 }; 1737 1738 static const struct cnr cnr_tab[] = { 1739 { 35, 2 }, 1740 { 40, 3 }, 1741 { 50, 4 }, 1742 { 60, 5 }, 1743 { 70, 6 }, 1744 { 80, 7 }, 1745 { 92, 8 }, 1746 { 103, 9 }, 1747 { 115, 10 }, 1748 { 138, 12 }, 1749 { 162, 15 }, 1750 { 180, 18 }, 1751 { 185, 19 }, 1752 { 189, 20 }, 1753 { 195, 22 }, 1754 { 199, 24 }, 1755 { 201, 25 }, 1756 { 202, 26 }, 1757 { 203, 27 }, 1758 { 205, 28 }, 1759 { 208, 30 } 1760 }; 1761 1762 static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr) 1763 { 1764 struct mb86a16_state *state = fe->demodulator_priv; 1765 int i = 0; 1766 int low_tide = 2, high_tide = 30, q_level; 1767 u8 cn; 1768 1769 *snr = 0; 1770 if (mb86a16_read(state, 0x26, &cn) != 2) { 1771 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1772 return -EREMOTEIO; 1773 } 1774 1775 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) { 1776 if (cn < cnr_tab[i].cn_reg) { 1777 *snr = cnr_tab[i].cn_val; 1778 break; 1779 } 1780 } 1781 q_level = (*snr * 100) / (high_tide - low_tide); 1782 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level); 1783 *snr = (0xffff - 0xff) + *snr; 1784 1785 return 0; 1786 } 1787 1788 static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1789 { 1790 u8 dist; 1791 struct mb86a16_state *state = fe->demodulator_priv; 1792 1793 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) { 1794 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1795 return -EREMOTEIO; 1796 } 1797 *ucblocks = dist; 1798 1799 return 0; 1800 } 1801 1802 static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe) 1803 { 1804 return DVBFE_ALGO_CUSTOM; 1805 } 1806 1807 static const struct dvb_frontend_ops mb86a16_ops = { 1808 .delsys = { SYS_DVBS }, 1809 .info = { 1810 .name = "Fujitsu MB86A16 DVB-S", 1811 .frequency_min = 950000, 1812 .frequency_max = 2150000, 1813 .frequency_stepsize = 3000, 1814 .frequency_tolerance = 0, 1815 .symbol_rate_min = 1000000, 1816 .symbol_rate_max = 45000000, 1817 .symbol_rate_tolerance = 500, 1818 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 1819 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | 1820 FE_CAN_FEC_7_8 | FE_CAN_QPSK | 1821 FE_CAN_FEC_AUTO 1822 }, 1823 .release = mb86a16_release, 1824 1825 .get_frontend_algo = mb86a16_frontend_algo, 1826 .search = mb86a16_search, 1827 .init = mb86a16_init, 1828 .sleep = mb86a16_sleep, 1829 .read_status = mb86a16_read_status, 1830 1831 .read_ber = mb86a16_read_ber, 1832 .read_signal_strength = mb86a16_read_signal_strength, 1833 .read_snr = mb86a16_read_snr, 1834 .read_ucblocks = mb86a16_read_ucblocks, 1835 1836 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg, 1837 .diseqc_send_burst = mb86a16_send_diseqc_burst, 1838 .set_tone = mb86a16_set_tone, 1839 }; 1840 1841 struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, 1842 struct i2c_adapter *i2c_adap) 1843 { 1844 u8 dev_id = 0; 1845 struct mb86a16_state *state = NULL; 1846 1847 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL); 1848 if (state == NULL) 1849 goto error; 1850 1851 state->config = config; 1852 state->i2c_adap = i2c_adap; 1853 1854 mb86a16_read(state, 0x7f, &dev_id); 1855 if (dev_id != 0xfe) 1856 goto error; 1857 1858 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops)); 1859 state->frontend.demodulator_priv = state; 1860 state->frontend.ops.set_voltage = state->config->set_voltage; 1861 1862 return &state->frontend; 1863 error: 1864 kfree(state); 1865 return NULL; 1866 } 1867 EXPORT_SYMBOL(mb86a16_attach); 1868 MODULE_LICENSE("GPL"); 1869 MODULE_AUTHOR("Manu Abraham"); 1870