1 /* 2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver 3 4 Copyright (C) Manu Abraham (abraham.manu@gmail.com) 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/slab.h> 26 27 #include "dvb_frontend.h" 28 #include "mb86a16.h" 29 #include "mb86a16_priv.h" 30 31 static unsigned int verbose = 5; 32 module_param(verbose, int, 0644); 33 34 #define ABS(x) ((x) < 0 ? (-x) : (x)) 35 36 struct mb86a16_state { 37 struct i2c_adapter *i2c_adap; 38 const struct mb86a16_config *config; 39 struct dvb_frontend frontend; 40 41 /* tuning parameters */ 42 int frequency; 43 int srate; 44 45 /* Internal stuff */ 46 int master_clk; 47 int deci; 48 int csel; 49 int rsel; 50 }; 51 52 #define MB86A16_ERROR 0 53 #define MB86A16_NOTICE 1 54 #define MB86A16_INFO 2 55 #define MB86A16_DEBUG 3 56 57 #define dprintk(x, y, z, format, arg...) do { \ 58 if (z) { \ 59 if ((x > MB86A16_ERROR) && (x > y)) \ 60 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \ 61 else if ((x > MB86A16_NOTICE) && (x > y)) \ 62 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \ 63 else if ((x > MB86A16_INFO) && (x > y)) \ 64 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \ 65 else if ((x > MB86A16_DEBUG) && (x > y)) \ 66 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \ 67 } else { \ 68 if (x > y) \ 69 printk(format, ##arg); \ 70 } \ 71 } while (0) 72 73 #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()") 74 #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->") 75 76 static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) 77 { 78 int ret; 79 u8 buf[] = { reg, val }; 80 81 struct i2c_msg msg = { 82 .addr = state->config->demod_address, 83 .flags = 0, 84 .buf = buf, 85 .len = 2 86 }; 87 88 dprintk(verbose, MB86A16_DEBUG, 1, 89 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]", 90 state->config->demod_address, buf[0], buf[1]); 91 92 ret = i2c_transfer(state->i2c_adap, &msg, 1); 93 94 return (ret != 1) ? -EREMOTEIO : 0; 95 } 96 97 static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) 98 { 99 int ret; 100 u8 b0[] = { reg }; 101 u8 b1[] = { 0 }; 102 103 struct i2c_msg msg[] = { 104 { 105 .addr = state->config->demod_address, 106 .flags = 0, 107 .buf = b0, 108 .len = 1 109 }, { 110 .addr = state->config->demod_address, 111 .flags = I2C_M_RD, 112 .buf = b1, 113 .len = 1 114 } 115 }; 116 ret = i2c_transfer(state->i2c_adap, msg, 2); 117 if (ret != 2) { 118 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)", 119 reg, ret); 120 121 if (ret < 0) 122 return ret; 123 return -EREMOTEIO; 124 } 125 *val = b1[0]; 126 127 return ret; 128 } 129 130 static int CNTM_set(struct mb86a16_state *state, 131 unsigned char timint1, 132 unsigned char timint2, 133 unsigned char cnext) 134 { 135 unsigned char val; 136 137 val = (timint1 << 4) | (timint2 << 2) | cnext; 138 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0) 139 goto err; 140 141 return 0; 142 143 err: 144 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 145 return -EREMOTEIO; 146 } 147 148 static int smrt_set(struct mb86a16_state *state, int rate) 149 { 150 int tmp ; 151 int m ; 152 unsigned char STOFS0, STOFS1; 153 154 m = 1 << state->deci; 155 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk; 156 157 STOFS0 = tmp & 0x0ff; 158 STOFS1 = (tmp & 0xf00) >> 8; 159 160 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) | 161 (state->csel << 1) | 162 state->rsel) < 0) 163 goto err; 164 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0) 165 goto err; 166 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0) 167 goto err; 168 169 return 0; 170 err: 171 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 172 return -1; 173 } 174 175 static int srst(struct mb86a16_state *state) 176 { 177 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0) 178 goto err; 179 180 return 0; 181 err: 182 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 183 return -EREMOTEIO; 184 185 } 186 187 static int afcex_data_set(struct mb86a16_state *state, 188 unsigned char AFCEX_L, 189 unsigned char AFCEX_H) 190 { 191 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0) 192 goto err; 193 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0) 194 goto err; 195 196 return 0; 197 err: 198 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 199 200 return -1; 201 } 202 203 static int afcofs_data_set(struct mb86a16_state *state, 204 unsigned char AFCEX_L, 205 unsigned char AFCEX_H) 206 { 207 if (mb86a16_write(state, 0x58, AFCEX_L) < 0) 208 goto err; 209 if (mb86a16_write(state, 0x59, AFCEX_H) < 0) 210 goto err; 211 212 return 0; 213 err: 214 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 215 return -EREMOTEIO; 216 } 217 218 static int stlp_set(struct mb86a16_state *state, 219 unsigned char STRAS, 220 unsigned char STRBS) 221 { 222 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0) 223 goto err; 224 225 return 0; 226 err: 227 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 228 return -EREMOTEIO; 229 } 230 231 static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA) 232 { 233 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0) 234 goto err; 235 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0) 236 goto err; 237 238 return 0; 239 err: 240 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 241 return -EREMOTEIO; 242 } 243 244 static int initial_set(struct mb86a16_state *state) 245 { 246 if (stlp_set(state, 5, 7)) 247 goto err; 248 249 udelay(100); 250 if (afcex_data_set(state, 0, 0)) 251 goto err; 252 253 udelay(100); 254 if (afcofs_data_set(state, 0, 0)) 255 goto err; 256 257 udelay(100); 258 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0) 259 goto err; 260 if (mb86a16_write(state, 0x2f, 0x21) < 0) 261 goto err; 262 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0) 263 goto err; 264 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0) 265 goto err; 266 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0) 267 goto err; 268 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0) 269 goto err; 270 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0) 271 goto err; 272 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0) 273 goto err; 274 if (mb86a16_write(state, 0x54, 0xff) < 0) 275 goto err; 276 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0) 277 goto err; 278 279 return 0; 280 281 err: 282 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 283 return -EREMOTEIO; 284 } 285 286 static int S01T_set(struct mb86a16_state *state, 287 unsigned char s1t, 288 unsigned s0t) 289 { 290 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0) 291 goto err; 292 293 return 0; 294 err: 295 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 296 return -EREMOTEIO; 297 } 298 299 300 static int EN_set(struct mb86a16_state *state, 301 int cren, 302 int afcen) 303 { 304 unsigned char val; 305 306 val = 0x7a | (cren << 7) | (afcen << 2); 307 if (mb86a16_write(state, 0x49, val) < 0) 308 goto err; 309 310 return 0; 311 err: 312 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 313 return -EREMOTEIO; 314 } 315 316 static int AFCEXEN_set(struct mb86a16_state *state, 317 int afcexen, 318 int smrt) 319 { 320 unsigned char AFCA ; 321 322 if (smrt > 18875) 323 AFCA = 4; 324 else if (smrt > 9375) 325 AFCA = 3; 326 else if (smrt > 2250) 327 AFCA = 2; 328 else 329 AFCA = 1; 330 331 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0) 332 goto err; 333 334 return 0; 335 336 err: 337 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 338 return -EREMOTEIO; 339 } 340 341 static int DAGC_data_set(struct mb86a16_state *state, 342 unsigned char DAGCA, 343 unsigned char DAGCW) 344 { 345 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0) 346 goto err; 347 348 return 0; 349 350 err: 351 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 352 return -EREMOTEIO; 353 } 354 355 static void smrt_info_get(struct mb86a16_state *state, int rate) 356 { 357 if (rate >= 37501) { 358 state->deci = 0; state->csel = 0; state->rsel = 0; 359 } else if (rate >= 30001) { 360 state->deci = 0; state->csel = 0; state->rsel = 1; 361 } else if (rate >= 26251) { 362 state->deci = 0; state->csel = 1; state->rsel = 0; 363 } else if (rate >= 22501) { 364 state->deci = 0; state->csel = 1; state->rsel = 1; 365 } else if (rate >= 18751) { 366 state->deci = 1; state->csel = 0; state->rsel = 0; 367 } else if (rate >= 15001) { 368 state->deci = 1; state->csel = 0; state->rsel = 1; 369 } else if (rate >= 13126) { 370 state->deci = 1; state->csel = 1; state->rsel = 0; 371 } else if (rate >= 11251) { 372 state->deci = 1; state->csel = 1; state->rsel = 1; 373 } else if (rate >= 9376) { 374 state->deci = 2; state->csel = 0; state->rsel = 0; 375 } else if (rate >= 7501) { 376 state->deci = 2; state->csel = 0; state->rsel = 1; 377 } else if (rate >= 6563) { 378 state->deci = 2; state->csel = 1; state->rsel = 0; 379 } else if (rate >= 5626) { 380 state->deci = 2; state->csel = 1; state->rsel = 1; 381 } else if (rate >= 4688) { 382 state->deci = 3; state->csel = 0; state->rsel = 0; 383 } else if (rate >= 3751) { 384 state->deci = 3; state->csel = 0; state->rsel = 1; 385 } else if (rate >= 3282) { 386 state->deci = 3; state->csel = 1; state->rsel = 0; 387 } else if (rate >= 2814) { 388 state->deci = 3; state->csel = 1; state->rsel = 1; 389 } else if (rate >= 2344) { 390 state->deci = 4; state->csel = 0; state->rsel = 0; 391 } else if (rate >= 1876) { 392 state->deci = 4; state->csel = 0; state->rsel = 1; 393 } else if (rate >= 1641) { 394 state->deci = 4; state->csel = 1; state->rsel = 0; 395 } else if (rate >= 1407) { 396 state->deci = 4; state->csel = 1; state->rsel = 1; 397 } else if (rate >= 1172) { 398 state->deci = 5; state->csel = 0; state->rsel = 0; 399 } else if (rate >= 939) { 400 state->deci = 5; state->csel = 0; state->rsel = 1; 401 } else if (rate >= 821) { 402 state->deci = 5; state->csel = 1; state->rsel = 0; 403 } else { 404 state->deci = 5; state->csel = 1; state->rsel = 1; 405 } 406 407 if (state->csel == 0) 408 state->master_clk = 92000; 409 else 410 state->master_clk = 61333; 411 412 } 413 414 static int signal_det(struct mb86a16_state *state, 415 int smrt, 416 unsigned char *SIG) 417 { 418 int ret; 419 int smrtd; 420 unsigned char S[3]; 421 int i; 422 423 if (*SIG > 45) { 424 if (CNTM_set(state, 2, 1, 2) < 0) { 425 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 426 return -1; 427 } 428 } else { 429 if (CNTM_set(state, 3, 1, 2) < 0) { 430 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 431 return -1; 432 } 433 } 434 for (i = 0; i < 3; i++) { 435 if (i == 0) 436 smrtd = smrt * 98 / 100; 437 else if (i == 1) 438 smrtd = smrt; 439 else 440 smrtd = smrt * 102 / 100; 441 smrt_info_get(state, smrtd); 442 smrt_set(state, smrtd); 443 srst(state); 444 msleep_interruptible(10); 445 if (mb86a16_read(state, 0x37, &(S[i])) != 2) { 446 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 447 return -EREMOTEIO; 448 } 449 } 450 if ((S[1] > S[0] * 112 / 100) && (S[1] > S[2] * 112 / 100)) 451 ret = 1; 452 else 453 ret = 0; 454 455 *SIG = S[1]; 456 457 if (CNTM_set(state, 0, 1, 2) < 0) { 458 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 459 return -1; 460 } 461 462 return ret; 463 } 464 465 static int rf_val_set(struct mb86a16_state *state, 466 int f, 467 int smrt, 468 unsigned char R) 469 { 470 unsigned char C, F, B; 471 int M; 472 unsigned char rf_val[5]; 473 int ack = -1; 474 475 if (smrt > 37750) 476 C = 1; 477 else if (smrt > 18875) 478 C = 2; 479 else if (smrt > 5500) 480 C = 3; 481 else 482 C = 4; 483 484 if (smrt > 30500) 485 F = 3; 486 else if (smrt > 9375) 487 F = 1; 488 else if (smrt > 4625) 489 F = 0; 490 else 491 F = 2; 492 493 if (f < 1060) 494 B = 0; 495 else if (f < 1175) 496 B = 1; 497 else if (f < 1305) 498 B = 2; 499 else if (f < 1435) 500 B = 3; 501 else if (f < 1570) 502 B = 4; 503 else if (f < 1715) 504 B = 5; 505 else if (f < 1845) 506 B = 6; 507 else if (f < 1980) 508 B = 7; 509 else if (f < 2080) 510 B = 8; 511 else 512 B = 9; 513 514 M = f * (1 << R) / 2; 515 516 rf_val[0] = 0x01 | (C << 3) | (F << 1); 517 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12); 518 rf_val[2] = (M & 0x00ff0) >> 4; 519 rf_val[3] = ((M & 0x0000f) << 4) | B; 520 521 /* Frequency Set */ 522 if (mb86a16_write(state, 0x21, rf_val[0]) < 0) 523 ack = 0; 524 if (mb86a16_write(state, 0x22, rf_val[1]) < 0) 525 ack = 0; 526 if (mb86a16_write(state, 0x23, rf_val[2]) < 0) 527 ack = 0; 528 if (mb86a16_write(state, 0x24, rf_val[3]) < 0) 529 ack = 0; 530 if (mb86a16_write(state, 0x25, 0x01) < 0) 531 ack = 0; 532 if (ack == 0) { 533 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error"); 534 return -EREMOTEIO; 535 } 536 537 return 0; 538 } 539 540 static int afcerr_chk(struct mb86a16_state *state) 541 { 542 unsigned char AFCM_L, AFCM_H ; 543 int AFCM ; 544 int afcm, afcerr ; 545 546 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2) 547 goto err; 548 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2) 549 goto err; 550 551 AFCM = (AFCM_H << 8) + AFCM_L; 552 553 if (AFCM > 2048) 554 afcm = AFCM - 4096; 555 else 556 afcm = AFCM; 557 afcerr = afcm * state->master_clk / 8192; 558 559 return afcerr; 560 561 err: 562 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 563 return -EREMOTEIO; 564 } 565 566 static int dagcm_val_get(struct mb86a16_state *state) 567 { 568 int DAGCM; 569 unsigned char DAGCM_H, DAGCM_L; 570 571 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2) 572 goto err; 573 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2) 574 goto err; 575 576 DAGCM = (DAGCM_H << 8) + DAGCM_L; 577 578 return DAGCM; 579 580 err: 581 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 582 return -EREMOTEIO; 583 } 584 585 static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status) 586 { 587 u8 stat, stat2; 588 struct mb86a16_state *state = fe->demodulator_priv; 589 590 *status = 0; 591 592 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2) 593 goto err; 594 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2) 595 goto err; 596 if ((stat > 25) && (stat2 > 25)) 597 *status |= FE_HAS_SIGNAL; 598 if ((stat > 45) && (stat2 > 45)) 599 *status |= FE_HAS_CARRIER; 600 601 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2) 602 goto err; 603 604 if (stat & 0x01) 605 *status |= FE_HAS_SYNC; 606 if (stat & 0x01) 607 *status |= FE_HAS_VITERBI; 608 609 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2) 610 goto err; 611 612 if ((stat & 0x0f) && (*status & FE_HAS_VITERBI)) 613 *status |= FE_HAS_LOCK; 614 615 return 0; 616 617 err: 618 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 619 return -EREMOTEIO; 620 } 621 622 static int sync_chk(struct mb86a16_state *state, 623 unsigned char *VIRM) 624 { 625 unsigned char val; 626 int sync; 627 628 if (mb86a16_read(state, 0x0d, &val) != 2) 629 goto err; 630 631 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val); 632 sync = val & 0x01; 633 *VIRM = (val & 0x1c) >> 2; 634 635 return sync; 636 err: 637 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 638 return -EREMOTEIO; 639 640 } 641 642 static int freqerr_chk(struct mb86a16_state *state, 643 int fTP, 644 int smrt, 645 int unit) 646 { 647 unsigned char CRM, AFCML, AFCMH; 648 unsigned char temp1, temp2, temp3; 649 int crm, afcm, AFCM; 650 int crrerr, afcerr; /* kHz */ 651 int frqerr; /* MHz */ 652 int afcen, afcexen = 0; 653 int R, M, fOSC, fOSC_OFS; 654 655 if (mb86a16_read(state, 0x43, &CRM) != 2) 656 goto err; 657 658 if (CRM > 127) 659 crm = CRM - 256; 660 else 661 crm = CRM; 662 663 crrerr = smrt * crm / 256; 664 if (mb86a16_read(state, 0x49, &temp1) != 2) 665 goto err; 666 667 afcen = (temp1 & 0x04) >> 2; 668 if (afcen == 0) { 669 if (mb86a16_read(state, 0x2a, &temp1) != 2) 670 goto err; 671 afcexen = (temp1 & 0x20) >> 5; 672 } 673 674 if (afcen == 1) { 675 if (mb86a16_read(state, 0x0e, &AFCML) != 2) 676 goto err; 677 if (mb86a16_read(state, 0x0f, &AFCMH) != 2) 678 goto err; 679 } else if (afcexen == 1) { 680 if (mb86a16_read(state, 0x2b, &AFCML) != 2) 681 goto err; 682 if (mb86a16_read(state, 0x2c, &AFCMH) != 2) 683 goto err; 684 } 685 if ((afcen == 1) || (afcexen == 1)) { 686 smrt_info_get(state, smrt); 687 AFCM = ((AFCMH & 0x01) << 8) + AFCML; 688 if (AFCM > 255) 689 afcm = AFCM - 512; 690 else 691 afcm = AFCM; 692 693 afcerr = afcm * state->master_clk / 8192; 694 } else 695 afcerr = 0; 696 697 if (mb86a16_read(state, 0x22, &temp1) != 2) 698 goto err; 699 if (mb86a16_read(state, 0x23, &temp2) != 2) 700 goto err; 701 if (mb86a16_read(state, 0x24, &temp3) != 2) 702 goto err; 703 704 R = (temp1 & 0xe0) >> 5; 705 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4); 706 if (R == 0) 707 fOSC = 2 * M; 708 else 709 fOSC = M; 710 711 fOSC_OFS = fOSC - fTP; 712 713 if (unit == 0) { /* MHz */ 714 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0) 715 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000; 716 else 717 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000; 718 } else { /* kHz */ 719 frqerr = crrerr + afcerr + fOSC_OFS * 1000; 720 } 721 722 return frqerr; 723 err: 724 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 725 return -EREMOTEIO; 726 } 727 728 static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt) 729 { 730 unsigned char R; 731 732 if (smrt > 9375) 733 R = 0; 734 else 735 R = 1; 736 737 return R; 738 } 739 740 static void swp_info_get(struct mb86a16_state *state, 741 int fOSC_start, 742 int smrt, 743 int v, int R, 744 int swp_ofs, 745 int *fOSC, 746 int *afcex_freq, 747 unsigned char *AFCEX_L, 748 unsigned char *AFCEX_H) 749 { 750 int AFCEX ; 751 int crnt_swp_freq ; 752 753 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; 754 755 if (R == 0) 756 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2; 757 else 758 *fOSC = (crnt_swp_freq + 500) / 1000; 759 760 if (*fOSC >= crnt_swp_freq) 761 *afcex_freq = *fOSC * 1000 - crnt_swp_freq; 762 else 763 *afcex_freq = crnt_swp_freq - *fOSC * 1000; 764 765 AFCEX = *afcex_freq * 8192 / state->master_clk; 766 *AFCEX_L = AFCEX & 0x00ff; 767 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 768 } 769 770 771 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin, 772 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1) 773 { 774 int swp_freq ; 775 776 if ((i % 2 == 1) && (v <= vmax)) { 777 /* positive v (case 1) */ 778 if ((v - 1 == vmin) && 779 (*(V + 30 + v) >= 0) && 780 (*(V + 30 + v - 1) >= 0) && 781 (*(V + 30 + v - 1) > *(V + 30 + v)) && 782 (*(V + 30 + v - 1) > SIGMIN)) { 783 784 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 785 *SIG1 = *(V + 30 + v - 1); 786 } else if ((v == vmax) && 787 (*(V + 30 + v) >= 0) && 788 (*(V + 30 + v - 1) >= 0) && 789 (*(V + 30 + v) > *(V + 30 + v - 1)) && 790 (*(V + 30 + v) > SIGMIN)) { 791 /* (case 2) */ 792 swp_freq = fOSC * 1000 + afcex_freq; 793 *SIG1 = *(V + 30 + v); 794 } else if ((*(V + 30 + v) > 0) && 795 (*(V + 30 + v - 1) > 0) && 796 (*(V + 30 + v - 2) > 0) && 797 (*(V + 30 + v - 3) > 0) && 798 (*(V + 30 + v - 1) > *(V + 30 + v)) && 799 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) && 800 ((*(V + 30 + v - 1) > SIGMIN) || 801 (*(V + 30 + v - 2) > SIGMIN))) { 802 /* (case 3) */ 803 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) { 804 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 805 *SIG1 = *(V + 30 + v - 1); 806 } else { 807 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2; 808 *SIG1 = *(V + 30 + v - 2); 809 } 810 } else if ((v == vmax) && 811 (*(V + 30 + v) >= 0) && 812 (*(V + 30 + v - 1) >= 0) && 813 (*(V + 30 + v - 2) >= 0) && 814 (*(V + 30 + v) > *(V + 30 + v - 2)) && 815 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) && 816 ((*(V + 30 + v) > SIGMIN) || 817 (*(V + 30 + v - 1) > SIGMIN))) { 818 /* (case 4) */ 819 if (*(V + 30 + v) >= *(V + 30 + v - 1)) { 820 swp_freq = fOSC * 1000 + afcex_freq; 821 *SIG1 = *(V + 30 + v); 822 } else { 823 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 824 *SIG1 = *(V + 30 + v - 1); 825 } 826 } else { 827 swp_freq = -1 ; 828 } 829 } else if ((i % 2 == 0) && (v >= vmin)) { 830 /* Negative v (case 1) */ 831 if ((*(V + 30 + v) > 0) && 832 (*(V + 30 + v + 1) > 0) && 833 (*(V + 30 + v + 2) > 0) && 834 (*(V + 30 + v + 1) > *(V + 30 + v)) && 835 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 836 (*(V + 30 + v + 1) > SIGMIN)) { 837 838 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 839 *SIG1 = *(V + 30 + v + 1); 840 } else if ((v + 1 == vmax) && 841 (*(V + 30 + v) >= 0) && 842 (*(V + 30 + v + 1) >= 0) && 843 (*(V + 30 + v + 1) > *(V + 30 + v)) && 844 (*(V + 30 + v + 1) > SIGMIN)) { 845 /* (case 2) */ 846 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 847 *SIG1 = *(V + 30 + v); 848 } else if ((v == vmin) && 849 (*(V + 30 + v) > 0) && 850 (*(V + 30 + v + 1) > 0) && 851 (*(V + 30 + v + 2) > 0) && 852 (*(V + 30 + v) > *(V + 30 + v + 1)) && 853 (*(V + 30 + v) > *(V + 30 + v + 2)) && 854 (*(V + 30 + v) > SIGMIN)) { 855 /* (case 3) */ 856 swp_freq = fOSC * 1000 + afcex_freq; 857 *SIG1 = *(V + 30 + v); 858 } else if ((*(V + 30 + v) >= 0) && 859 (*(V + 30 + v + 1) >= 0) && 860 (*(V + 30 + v + 2) >= 0) && 861 (*(V + 30 + v + 3) >= 0) && 862 (*(V + 30 + v + 1) > *(V + 30 + v)) && 863 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) && 864 ((*(V + 30 + v + 1) > SIGMIN) || 865 (*(V + 30 + v + 2) > SIGMIN))) { 866 /* (case 4) */ 867 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 868 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 869 *SIG1 = *(V + 30 + v + 1); 870 } else { 871 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 872 *SIG1 = *(V + 30 + v + 2); 873 } 874 } else if ((*(V + 30 + v) >= 0) && 875 (*(V + 30 + v + 1) >= 0) && 876 (*(V + 30 + v + 2) >= 0) && 877 (*(V + 30 + v + 3) >= 0) && 878 (*(V + 30 + v) > *(V + 30 + v + 2)) && 879 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 880 (*(V + 30 + v) > *(V + 30 + v + 3)) && 881 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) && 882 ((*(V + 30 + v) > SIGMIN) || 883 (*(V + 30 + v + 1) > SIGMIN))) { 884 /* (case 5) */ 885 if (*(V + 30 + v) >= *(V + 30 + v + 1)) { 886 swp_freq = fOSC * 1000 + afcex_freq; 887 *SIG1 = *(V + 30 + v); 888 } else { 889 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 890 *SIG1 = *(V + 30 + v + 1); 891 } 892 } else if ((v + 2 == vmin) && 893 (*(V + 30 + v) >= 0) && 894 (*(V + 30 + v + 1) >= 0) && 895 (*(V + 30 + v + 2) >= 0) && 896 (*(V + 30 + v + 1) > *(V + 30 + v)) && 897 (*(V + 30 + v + 2) > *(V + 30 + v)) && 898 ((*(V + 30 + v + 1) > SIGMIN) || 899 (*(V + 30 + v + 2) > SIGMIN))) { 900 /* (case 6) */ 901 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 902 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 903 *SIG1 = *(V + 30 + v + 1); 904 } else { 905 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 906 *SIG1 = *(V + 30 + v + 2); 907 } 908 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) { 909 swp_freq = fOSC * 1000; 910 *SIG1 = *(V + 30 + v); 911 } else 912 swp_freq = -1; 913 } else 914 swp_freq = -1; 915 916 return swp_freq; 917 } 918 919 static void swp_info_get2(struct mb86a16_state *state, 920 int smrt, 921 int R, 922 int swp_freq, 923 int *afcex_freq, 924 int *fOSC, 925 unsigned char *AFCEX_L, 926 unsigned char *AFCEX_H) 927 { 928 int AFCEX ; 929 930 if (R == 0) 931 *fOSC = (swp_freq + 1000) / 2000 * 2; 932 else 933 *fOSC = (swp_freq + 500) / 1000; 934 935 if (*fOSC >= swp_freq) 936 *afcex_freq = *fOSC * 1000 - swp_freq; 937 else 938 *afcex_freq = swp_freq - *fOSC * 1000; 939 940 AFCEX = *afcex_freq * 8192 / state->master_clk; 941 *AFCEX_L = AFCEX & 0x00ff; 942 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 943 } 944 945 static void afcex_info_get(struct mb86a16_state *state, 946 int afcex_freq, 947 unsigned char *AFCEX_L, 948 unsigned char *AFCEX_H) 949 { 950 int AFCEX ; 951 952 AFCEX = afcex_freq * 8192 / state->master_clk; 953 *AFCEX_L = AFCEX & 0x00ff; 954 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 955 } 956 957 static int SEQ_set(struct mb86a16_state *state, unsigned char loop) 958 { 959 /* SLOCK0 = 0 */ 960 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) { 961 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 962 return -EREMOTEIO; 963 } 964 965 return 0; 966 } 967 968 static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV) 969 { 970 /* Viterbi Rate, IQ Settings */ 971 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) { 972 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 973 return -EREMOTEIO; 974 } 975 976 return 0; 977 } 978 979 static int FEC_srst(struct mb86a16_state *state) 980 { 981 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) { 982 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 983 return -EREMOTEIO; 984 } 985 986 return 0; 987 } 988 989 static int S2T_set(struct mb86a16_state *state, unsigned char S2T) 990 { 991 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) { 992 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 993 return -EREMOTEIO; 994 } 995 996 return 0; 997 } 998 999 static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T) 1000 { 1001 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) { 1002 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1003 return -EREMOTEIO; 1004 } 1005 1006 return 0; 1007 } 1008 1009 1010 static int mb86a16_set_fe(struct mb86a16_state *state) 1011 { 1012 u8 agcval, cnmval; 1013 1014 int i, j; 1015 int fOSC = 0; 1016 int fOSC_start = 0; 1017 int wait_t; 1018 int fcp; 1019 int swp_ofs; 1020 int V[60]; 1021 u8 SIG1MIN; 1022 1023 unsigned char CREN, AFCEN, AFCEXEN; 1024 unsigned char SIG1; 1025 unsigned char TIMINT1, TIMINT2, TIMEXT; 1026 unsigned char S0T, S1T; 1027 unsigned char S2T; 1028 /* unsigned char S2T, S3T; */ 1029 unsigned char S4T, S5T; 1030 unsigned char AFCEX_L, AFCEX_H; 1031 unsigned char R; 1032 unsigned char VIRM; 1033 unsigned char ETH, VIA; 1034 unsigned char junk; 1035 1036 int loop; 1037 int ftemp; 1038 int v, vmax, vmin; 1039 int vmax_his, vmin_his; 1040 int swp_freq, prev_swp_freq[20]; 1041 int prev_freq_num; 1042 int signal_dupl; 1043 int afcex_freq; 1044 int signal; 1045 int afcerr; 1046 int temp_freq, delta_freq; 1047 int dagcm[4]; 1048 int smrt_d; 1049 /* int freq_err; */ 1050 int n; 1051 int ret = -1; 1052 int sync; 1053 1054 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate); 1055 1056 fcp = 3000; 1057 swp_ofs = state->srate / 4; 1058 1059 for (i = 0; i < 60; i++) 1060 V[i] = -1; 1061 1062 for (i = 0; i < 20; i++) 1063 prev_swp_freq[i] = 0; 1064 1065 SIG1MIN = 25; 1066 1067 for (n = 0; ((n < 3) && (ret == -1)); n++) { 1068 SEQ_set(state, 0); 1069 iq_vt_set(state, 0); 1070 1071 CREN = 0; 1072 AFCEN = 0; 1073 AFCEXEN = 1; 1074 TIMINT1 = 0; 1075 TIMINT2 = 1; 1076 TIMEXT = 2; 1077 S1T = 0; 1078 S0T = 0; 1079 1080 if (initial_set(state) < 0) { 1081 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed"); 1082 return -1; 1083 } 1084 if (DAGC_data_set(state, 3, 2) < 0) { 1085 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1086 return -1; 1087 } 1088 if (EN_set(state, CREN, AFCEN) < 0) { 1089 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1090 return -1; /* (0, 0) */ 1091 } 1092 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1093 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1094 return -1; /* (1, smrt) = (1, symbolrate) */ 1095 } 1096 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) { 1097 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error"); 1098 return -1; /* (0, 1, 2) */ 1099 } 1100 if (S01T_set(state, S1T, S0T) < 0) { 1101 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1102 return -1; /* (0, 0) */ 1103 } 1104 smrt_info_get(state, state->srate); 1105 if (smrt_set(state, state->srate) < 0) { 1106 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error"); 1107 return -1; 1108 } 1109 1110 R = vco_dev_get(state, state->srate); 1111 if (R == 1) 1112 fOSC_start = state->frequency; 1113 1114 else if (R == 0) { 1115 if (state->frequency % 2 == 0) { 1116 fOSC_start = state->frequency; 1117 } else { 1118 fOSC_start = state->frequency + 1; 1119 if (fOSC_start > 2150) 1120 fOSC_start = state->frequency - 1; 1121 } 1122 } 1123 loop = 1; 1124 ftemp = fOSC_start * 1000; 1125 vmax = 0 ; 1126 while (loop == 1) { 1127 ftemp = ftemp + swp_ofs; 1128 vmax++; 1129 1130 /* Upper bound */ 1131 if (ftemp > 2150000) { 1132 loop = 0; 1133 vmax--; 1134 } else { 1135 if ((ftemp == 2150000) || 1136 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4)) 1137 loop = 0; 1138 } 1139 } 1140 1141 loop = 1; 1142 ftemp = fOSC_start * 1000; 1143 vmin = 0 ; 1144 while (loop == 1) { 1145 ftemp = ftemp - swp_ofs; 1146 vmin--; 1147 1148 /* Lower bound */ 1149 if (ftemp < 950000) { 1150 loop = 0; 1151 vmin++; 1152 } else { 1153 if ((ftemp == 950000) || 1154 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4)) 1155 loop = 0; 1156 } 1157 } 1158 1159 wait_t = (8000 + state->srate / 2) / state->srate; 1160 if (wait_t == 0) 1161 wait_t = 1; 1162 1163 i = 0; 1164 j = 0; 1165 prev_freq_num = 0; 1166 loop = 1; 1167 signal = 0; 1168 vmax_his = 0; 1169 vmin_his = 0; 1170 v = 0; 1171 1172 while (loop == 1) { 1173 swp_info_get(state, fOSC_start, state->srate, 1174 v, R, swp_ofs, &fOSC, 1175 &afcex_freq, &AFCEX_L, &AFCEX_H); 1176 1177 udelay(100); 1178 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1179 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1180 return -1; 1181 } 1182 udelay(100); 1183 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1184 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1185 return -1; 1186 } 1187 if (srst(state) < 0) { 1188 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1189 return -1; 1190 } 1191 msleep_interruptible(wait_t); 1192 1193 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1194 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1195 return -1; 1196 } 1197 V[30 + v] = SIG1 ; 1198 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin, 1199 SIG1MIN, fOSC, afcex_freq, 1200 swp_ofs, &SIG1); /* changed */ 1201 1202 signal_dupl = 0; 1203 for (j = 0; j < prev_freq_num; j++) { 1204 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) { 1205 signal_dupl = 1; 1206 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j); 1207 } 1208 } 1209 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) { 1210 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate); 1211 prev_swp_freq[prev_freq_num] = swp_freq; 1212 prev_freq_num++; 1213 swp_info_get2(state, state->srate, R, swp_freq, 1214 &afcex_freq, &fOSC, 1215 &AFCEX_L, &AFCEX_H); 1216 1217 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1218 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1219 return -1; 1220 } 1221 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1222 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1223 return -1; 1224 } 1225 signal = signal_det(state, state->srate, &SIG1); 1226 if (signal == 1) { 1227 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****"); 1228 loop = 0; 1229 } else { 1230 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again..."); 1231 smrt_info_get(state, state->srate); 1232 if (smrt_set(state, state->srate) < 0) { 1233 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1234 return -1; 1235 } 1236 } 1237 } 1238 if (v > vmax) 1239 vmax_his = 1 ; 1240 if (v < vmin) 1241 vmin_his = 1 ; 1242 i++; 1243 1244 if ((i % 2 == 1) && (vmax_his == 1)) 1245 i++; 1246 if ((i % 2 == 0) && (vmin_his == 1)) 1247 i++; 1248 1249 if (i % 2 == 1) 1250 v = (i + 1) / 2; 1251 else 1252 v = -i / 2; 1253 1254 if ((vmax_his == 1) && (vmin_his == 1)) 1255 loop = 0 ; 1256 } 1257 1258 if (signal == 1) { 1259 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check"); 1260 S1T = 7 ; 1261 S0T = 1 ; 1262 CREN = 0 ; 1263 AFCEN = 1 ; 1264 AFCEXEN = 0 ; 1265 1266 if (S01T_set(state, S1T, S0T) < 0) { 1267 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1268 return -1; 1269 } 1270 smrt_info_get(state, state->srate); 1271 if (smrt_set(state, state->srate) < 0) { 1272 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1273 return -1; 1274 } 1275 if (EN_set(state, CREN, AFCEN) < 0) { 1276 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1277 return -1; 1278 } 1279 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1280 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1281 return -1; 1282 } 1283 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H); 1284 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1285 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error"); 1286 return -1; 1287 } 1288 if (srst(state) < 0) { 1289 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1290 return -1; 1291 } 1292 /* delay 4~200 */ 1293 wait_t = 200000 / state->master_clk + 200000 / state->srate; 1294 msleep(wait_t); 1295 afcerr = afcerr_chk(state); 1296 if (afcerr == -1) 1297 return -1; 1298 1299 swp_freq = fOSC * 1000 + afcerr ; 1300 AFCEXEN = 1 ; 1301 if (state->srate >= 1500) 1302 smrt_d = state->srate / 3; 1303 else 1304 smrt_d = state->srate / 2; 1305 smrt_info_get(state, smrt_d); 1306 if (smrt_set(state, smrt_d) < 0) { 1307 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1308 return -1; 1309 } 1310 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) { 1311 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1312 return -1; 1313 } 1314 R = vco_dev_get(state, smrt_d); 1315 if (DAGC_data_set(state, 2, 0) < 0) { 1316 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1317 return -1; 1318 } 1319 for (i = 0; i < 3; i++) { 1320 temp_freq = swp_freq + (i - 1) * state->srate / 8; 1321 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1322 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1323 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1324 return -1; 1325 } 1326 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1327 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1328 return -1; 1329 } 1330 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1331 msleep(wait_t); 1332 dagcm[i] = dagcm_val_get(state); 1333 } 1334 if ((dagcm[0] > dagcm[1]) && 1335 (dagcm[0] > dagcm[2]) && 1336 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) { 1337 1338 temp_freq = swp_freq - 2 * state->srate / 8; 1339 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1340 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1341 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1342 return -1; 1343 } 1344 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1345 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1346 return -1; 1347 } 1348 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1349 msleep(wait_t); 1350 dagcm[3] = dagcm_val_get(state); 1351 if (dagcm[3] > dagcm[1]) 1352 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300; 1353 else 1354 delta_freq = 0; 1355 } else if ((dagcm[2] > dagcm[1]) && 1356 (dagcm[2] > dagcm[0]) && 1357 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) { 1358 1359 temp_freq = swp_freq + 2 * state->srate / 8; 1360 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1361 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1362 dprintk(verbose, MB86A16_ERROR, 1, "rf val set"); 1363 return -1; 1364 } 1365 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1366 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1367 return -1; 1368 } 1369 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1370 msleep(wait_t); 1371 dagcm[3] = dagcm_val_get(state); 1372 if (dagcm[3] > dagcm[1]) 1373 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300; 1374 else 1375 delta_freq = 0 ; 1376 1377 } else { 1378 delta_freq = 0 ; 1379 } 1380 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq); 1381 swp_freq += delta_freq; 1382 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq); 1383 if (ABS(state->frequency * 1000 - swp_freq) > 3800) { 1384 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !"); 1385 } else { 1386 1387 S1T = 0; 1388 S0T = 3; 1389 CREN = 1; 1390 AFCEN = 0; 1391 AFCEXEN = 1; 1392 1393 if (S01T_set(state, S1T, S0T) < 0) { 1394 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1395 return -1; 1396 } 1397 if (DAGC_data_set(state, 0, 0) < 0) { 1398 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1399 return -1; 1400 } 1401 R = vco_dev_get(state, state->srate); 1402 smrt_info_get(state, state->srate); 1403 if (smrt_set(state, state->srate) < 0) { 1404 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1405 return -1; 1406 } 1407 if (EN_set(state, CREN, AFCEN) < 0) { 1408 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1409 return -1; 1410 } 1411 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1412 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1413 return -1; 1414 } 1415 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1416 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1417 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1418 return -1; 1419 } 1420 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1421 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1422 return -1; 1423 } 1424 if (srst(state) < 0) { 1425 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1426 return -1; 1427 } 1428 wait_t = 7 + (10000 + state->srate / 2) / state->srate; 1429 if (wait_t == 0) 1430 wait_t = 1; 1431 msleep_interruptible(wait_t); 1432 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1433 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1434 return -EREMOTEIO; 1435 } 1436 1437 if (SIG1 > 110) { 1438 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6; 1439 wait_t = 7 + (917504 + state->srate / 2) / state->srate; 1440 } else if (SIG1 > 105) { 1441 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1442 wait_t = 7 + (1048576 + state->srate / 2) / state->srate; 1443 } else if (SIG1 > 85) { 1444 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1445 wait_t = 7 + (1310720 + state->srate / 2) / state->srate; 1446 } else if (SIG1 > 65) { 1447 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1448 wait_t = 7 + (1572864 + state->srate / 2) / state->srate; 1449 } else { 1450 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1451 wait_t = 7 + (2097152 + state->srate / 2) / state->srate; 1452 } 1453 wait_t *= 2; /* FOS */ 1454 S2T_set(state, S2T); 1455 S45T_set(state, S4T, S5T); 1456 Vi_set(state, ETH, VIA); 1457 srst(state); 1458 msleep_interruptible(wait_t); 1459 sync = sync_chk(state, &VIRM); 1460 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync); 1461 if (VIRM) { 1462 if (VIRM == 4) { 1463 /* 5/6 */ 1464 if (SIG1 > 110) 1465 wait_t = (786432 + state->srate / 2) / state->srate; 1466 else 1467 wait_t = (1572864 + state->srate / 2) / state->srate; 1468 if (state->srate < 5000) 1469 /* FIXME ! , should be a long wait ! */ 1470 msleep_interruptible(wait_t); 1471 else 1472 msleep_interruptible(wait_t); 1473 1474 if (sync_chk(state, &junk) == 0) { 1475 iq_vt_set(state, 1); 1476 FEC_srst(state); 1477 } 1478 } 1479 /* 1/2, 2/3, 3/4, 7/8 */ 1480 if (SIG1 > 110) 1481 wait_t = (786432 + state->srate / 2) / state->srate; 1482 else 1483 wait_t = (1572864 + state->srate / 2) / state->srate; 1484 msleep_interruptible(wait_t); 1485 SEQ_set(state, 1); 1486 } else { 1487 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC"); 1488 SEQ_set(state, 1); 1489 ret = -1; 1490 } 1491 } 1492 } else { 1493 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL"); 1494 ret = -1; 1495 } 1496 1497 sync = sync_chk(state, &junk); 1498 if (sync) { 1499 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******"); 1500 freqerr_chk(state, state->frequency, state->srate, 1); 1501 ret = 0; 1502 break; 1503 } 1504 } 1505 1506 mb86a16_read(state, 0x15, &agcval); 1507 mb86a16_read(state, 0x26, &cnmval); 1508 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval); 1509 1510 return ret; 1511 } 1512 1513 static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe, 1514 struct dvb_diseqc_master_cmd *cmd) 1515 { 1516 struct mb86a16_state *state = fe->demodulator_priv; 1517 int i; 1518 u8 regs; 1519 1520 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1521 goto err; 1522 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1523 goto err; 1524 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1525 goto err; 1526 1527 regs = 0x18; 1528 1529 if (cmd->msg_len > 5 || cmd->msg_len < 4) 1530 return -EINVAL; 1531 1532 for (i = 0; i < cmd->msg_len; i++) { 1533 if (mb86a16_write(state, regs, cmd->msg[i]) < 0) 1534 goto err; 1535 1536 regs++; 1537 } 1538 i += 0x90; 1539 1540 msleep_interruptible(10); 1541 1542 if (mb86a16_write(state, MB86A16_DCC1, i) < 0) 1543 goto err; 1544 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1545 goto err; 1546 1547 return 0; 1548 1549 err: 1550 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1551 return -EREMOTEIO; 1552 } 1553 1554 static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, 1555 enum fe_sec_mini_cmd burst) 1556 { 1557 struct mb86a16_state *state = fe->demodulator_priv; 1558 1559 switch (burst) { 1560 case SEC_MINI_A: 1561 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1562 MB86A16_DCC1_TBEN | 1563 MB86A16_DCC1_TBO) < 0) 1564 goto err; 1565 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1566 goto err; 1567 break; 1568 case SEC_MINI_B: 1569 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1570 MB86A16_DCC1_TBEN) < 0) 1571 goto err; 1572 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1573 goto err; 1574 break; 1575 } 1576 1577 return 0; 1578 err: 1579 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1580 return -EREMOTEIO; 1581 } 1582 1583 static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 1584 { 1585 struct mb86a16_state *state = fe->demodulator_priv; 1586 1587 switch (tone) { 1588 case SEC_TONE_ON: 1589 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0) 1590 goto err; 1591 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1592 MB86A16_DCC1_CTOE) < 0) 1593 1594 goto err; 1595 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1596 goto err; 1597 break; 1598 case SEC_TONE_OFF: 1599 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1600 goto err; 1601 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1602 goto err; 1603 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1604 goto err; 1605 break; 1606 default: 1607 return -EINVAL; 1608 } 1609 return 0; 1610 1611 err: 1612 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1613 return -EREMOTEIO; 1614 } 1615 1616 static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe) 1617 { 1618 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1619 struct mb86a16_state *state = fe->demodulator_priv; 1620 1621 state->frequency = p->frequency / 1000; 1622 state->srate = p->symbol_rate / 1000; 1623 1624 if (!mb86a16_set_fe(state)) { 1625 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK"); 1626 return DVBFE_ALGO_SEARCH_SUCCESS; 1627 } 1628 1629 dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!"); 1630 return DVBFE_ALGO_SEARCH_FAILED; 1631 } 1632 1633 static void mb86a16_release(struct dvb_frontend *fe) 1634 { 1635 struct mb86a16_state *state = fe->demodulator_priv; 1636 kfree(state); 1637 } 1638 1639 static int mb86a16_init(struct dvb_frontend *fe) 1640 { 1641 return 0; 1642 } 1643 1644 static int mb86a16_sleep(struct dvb_frontend *fe) 1645 { 1646 return 0; 1647 } 1648 1649 static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber) 1650 { 1651 u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst; 1652 u32 timer; 1653 1654 struct mb86a16_state *state = fe->demodulator_priv; 1655 1656 *ber = 0; 1657 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2) 1658 goto err; 1659 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2) 1660 goto err; 1661 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2) 1662 goto err; 1663 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2) 1664 goto err; 1665 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2) 1666 goto err; 1667 /* BER monitor invalid when BER_EN = 0 */ 1668 if (ber_mon & 0x04) { 1669 /* coarse, fast calculation */ 1670 *ber = ber_tab & 0x1f; 1671 dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber); 1672 if (ber_mon & 0x01) { 1673 /* 1674 * BER_SEL = 1, The monitored BER is the estimated 1675 * value with a Reed-Solomon decoder error amount at 1676 * the deinterleaver output. 1677 * monitored BER is expressed as a 20 bit output in total 1678 */ 1679 ber_rst = ber_mon >> 3; 1680 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1681 if (ber_rst == 0) 1682 timer = 12500000; 1683 if (ber_rst == 1) 1684 timer = 25000000; 1685 if (ber_rst == 2) 1686 timer = 50000000; 1687 if (ber_rst == 3) 1688 timer = 100000000; 1689 1690 *ber /= timer; 1691 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1692 } else { 1693 /* 1694 * BER_SEL = 0, The monitored BER is the estimated 1695 * value with a Viterbi decoder error amount at the 1696 * QPSK demodulator output. 1697 * monitored BER is expressed as a 24 bit output in total 1698 */ 1699 ber_tim = ber_mon >> 1; 1700 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1701 if (ber_tim == 0) 1702 timer = 16; 1703 if (ber_tim == 1) 1704 timer = 24; 1705 1706 *ber /= 2 ^ timer; 1707 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1708 } 1709 } 1710 return 0; 1711 err: 1712 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1713 return -EREMOTEIO; 1714 } 1715 1716 static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1717 { 1718 u8 agcm = 0; 1719 struct mb86a16_state *state = fe->demodulator_priv; 1720 1721 *strength = 0; 1722 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) { 1723 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1724 return -EREMOTEIO; 1725 } 1726 1727 *strength = ((0xff - agcm) * 100) / 256; 1728 dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength); 1729 *strength = (0xffff - 0xff) + agcm; 1730 1731 return 0; 1732 } 1733 1734 struct cnr { 1735 u8 cn_reg; 1736 u8 cn_val; 1737 }; 1738 1739 static const struct cnr cnr_tab[] = { 1740 { 35, 2 }, 1741 { 40, 3 }, 1742 { 50, 4 }, 1743 { 60, 5 }, 1744 { 70, 6 }, 1745 { 80, 7 }, 1746 { 92, 8 }, 1747 { 103, 9 }, 1748 { 115, 10 }, 1749 { 138, 12 }, 1750 { 162, 15 }, 1751 { 180, 18 }, 1752 { 185, 19 }, 1753 { 189, 20 }, 1754 { 195, 22 }, 1755 { 199, 24 }, 1756 { 201, 25 }, 1757 { 202, 26 }, 1758 { 203, 27 }, 1759 { 205, 28 }, 1760 { 208, 30 } 1761 }; 1762 1763 static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr) 1764 { 1765 struct mb86a16_state *state = fe->demodulator_priv; 1766 int i = 0; 1767 int low_tide = 2, high_tide = 30, q_level; 1768 u8 cn; 1769 1770 *snr = 0; 1771 if (mb86a16_read(state, 0x26, &cn) != 2) { 1772 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1773 return -EREMOTEIO; 1774 } 1775 1776 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) { 1777 if (cn < cnr_tab[i].cn_reg) { 1778 *snr = cnr_tab[i].cn_val; 1779 break; 1780 } 1781 } 1782 q_level = (*snr * 100) / (high_tide - low_tide); 1783 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level); 1784 *snr = (0xffff - 0xff) + *snr; 1785 1786 return 0; 1787 } 1788 1789 static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1790 { 1791 u8 dist; 1792 struct mb86a16_state *state = fe->demodulator_priv; 1793 1794 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) { 1795 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1796 return -EREMOTEIO; 1797 } 1798 *ucblocks = dist; 1799 1800 return 0; 1801 } 1802 1803 static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe) 1804 { 1805 return DVBFE_ALGO_CUSTOM; 1806 } 1807 1808 static const struct dvb_frontend_ops mb86a16_ops = { 1809 .delsys = { SYS_DVBS }, 1810 .info = { 1811 .name = "Fujitsu MB86A16 DVB-S", 1812 .frequency_min = 950000, 1813 .frequency_max = 2150000, 1814 .frequency_stepsize = 3000, 1815 .frequency_tolerance = 0, 1816 .symbol_rate_min = 1000000, 1817 .symbol_rate_max = 45000000, 1818 .symbol_rate_tolerance = 500, 1819 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 1820 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | 1821 FE_CAN_FEC_7_8 | FE_CAN_QPSK | 1822 FE_CAN_FEC_AUTO 1823 }, 1824 .release = mb86a16_release, 1825 1826 .get_frontend_algo = mb86a16_frontend_algo, 1827 .search = mb86a16_search, 1828 .init = mb86a16_init, 1829 .sleep = mb86a16_sleep, 1830 .read_status = mb86a16_read_status, 1831 1832 .read_ber = mb86a16_read_ber, 1833 .read_signal_strength = mb86a16_read_signal_strength, 1834 .read_snr = mb86a16_read_snr, 1835 .read_ucblocks = mb86a16_read_ucblocks, 1836 1837 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg, 1838 .diseqc_send_burst = mb86a16_send_diseqc_burst, 1839 .set_tone = mb86a16_set_tone, 1840 }; 1841 1842 struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, 1843 struct i2c_adapter *i2c_adap) 1844 { 1845 u8 dev_id = 0; 1846 struct mb86a16_state *state = NULL; 1847 1848 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL); 1849 if (state == NULL) 1850 goto error; 1851 1852 state->config = config; 1853 state->i2c_adap = i2c_adap; 1854 1855 mb86a16_read(state, 0x7f, &dev_id); 1856 if (dev_id != 0xfe) 1857 goto error; 1858 1859 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops)); 1860 state->frontend.demodulator_priv = state; 1861 state->frontend.ops.set_voltage = state->config->set_voltage; 1862 1863 return &state->frontend; 1864 error: 1865 kfree(state); 1866 return NULL; 1867 } 1868 EXPORT_SYMBOL(mb86a16_attach); 1869 MODULE_LICENSE("GPL"); 1870 MODULE_AUTHOR("Manu Abraham"); 1871