1 /* 2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver 3 4 Copyright (C) Manu Abraham (abraham.manu@gmail.com) 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/slab.h> 26 27 #include <media/dvb_frontend.h> 28 #include "mb86a16.h" 29 #include "mb86a16_priv.h" 30 31 static unsigned int verbose = 5; 32 module_param(verbose, int, 0644); 33 34 #define ABS(x) ((x) < 0 ? (-x) : (x)) 35 36 struct mb86a16_state { 37 struct i2c_adapter *i2c_adap; 38 const struct mb86a16_config *config; 39 struct dvb_frontend frontend; 40 41 /* tuning parameters */ 42 int frequency; 43 int srate; 44 45 /* Internal stuff */ 46 int master_clk; 47 int deci; 48 int csel; 49 int rsel; 50 }; 51 52 #define MB86A16_ERROR 0 53 #define MB86A16_NOTICE 1 54 #define MB86A16_INFO 2 55 #define MB86A16_DEBUG 3 56 57 #define dprintk(x, y, z, format, arg...) do { \ 58 if (z) { \ 59 if ((x > MB86A16_ERROR) && (x > y)) \ 60 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \ 61 else if ((x > MB86A16_NOTICE) && (x > y)) \ 62 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \ 63 else if ((x > MB86A16_INFO) && (x > y)) \ 64 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \ 65 else if ((x > MB86A16_DEBUG) && (x > y)) \ 66 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \ 67 } else { \ 68 if (x > y) \ 69 printk(format, ##arg); \ 70 } \ 71 } while (0) 72 73 #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()") 74 #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->") 75 76 static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) 77 { 78 int ret; 79 u8 buf[] = { reg, val }; 80 81 struct i2c_msg msg = { 82 .addr = state->config->demod_address, 83 .flags = 0, 84 .buf = buf, 85 .len = 2 86 }; 87 88 dprintk(verbose, MB86A16_DEBUG, 1, 89 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]", 90 state->config->demod_address, buf[0], buf[1]); 91 92 ret = i2c_transfer(state->i2c_adap, &msg, 1); 93 94 return (ret != 1) ? -EREMOTEIO : 0; 95 } 96 97 static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) 98 { 99 int ret; 100 u8 b0[] = { reg }; 101 u8 b1[] = { 0 }; 102 103 struct i2c_msg msg[] = { 104 { 105 .addr = state->config->demod_address, 106 .flags = 0, 107 .buf = b0, 108 .len = 1 109 }, { 110 .addr = state->config->demod_address, 111 .flags = I2C_M_RD, 112 .buf = b1, 113 .len = 1 114 } 115 }; 116 ret = i2c_transfer(state->i2c_adap, msg, 2); 117 if (ret != 2) { 118 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)", 119 reg, ret); 120 121 if (ret < 0) 122 return ret; 123 return -EREMOTEIO; 124 } 125 *val = b1[0]; 126 127 return ret; 128 } 129 130 static int CNTM_set(struct mb86a16_state *state, 131 unsigned char timint1, 132 unsigned char timint2, 133 unsigned char cnext) 134 { 135 unsigned char val; 136 137 val = (timint1 << 4) | (timint2 << 2) | cnext; 138 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0) 139 goto err; 140 141 return 0; 142 143 err: 144 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 145 return -EREMOTEIO; 146 } 147 148 static int smrt_set(struct mb86a16_state *state, int rate) 149 { 150 int tmp ; 151 int m ; 152 unsigned char STOFS0, STOFS1; 153 154 m = 1 << state->deci; 155 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk; 156 157 STOFS0 = tmp & 0x0ff; 158 STOFS1 = (tmp & 0xf00) >> 8; 159 160 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) | 161 (state->csel << 1) | 162 state->rsel) < 0) 163 goto err; 164 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0) 165 goto err; 166 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0) 167 goto err; 168 169 return 0; 170 err: 171 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 172 return -1; 173 } 174 175 static int srst(struct mb86a16_state *state) 176 { 177 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0) 178 goto err; 179 180 return 0; 181 err: 182 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 183 return -EREMOTEIO; 184 185 } 186 187 static int afcex_data_set(struct mb86a16_state *state, 188 unsigned char AFCEX_L, 189 unsigned char AFCEX_H) 190 { 191 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0) 192 goto err; 193 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0) 194 goto err; 195 196 return 0; 197 err: 198 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 199 200 return -1; 201 } 202 203 static int afcofs_data_set(struct mb86a16_state *state, 204 unsigned char AFCEX_L, 205 unsigned char AFCEX_H) 206 { 207 if (mb86a16_write(state, 0x58, AFCEX_L) < 0) 208 goto err; 209 if (mb86a16_write(state, 0x59, AFCEX_H) < 0) 210 goto err; 211 212 return 0; 213 err: 214 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 215 return -EREMOTEIO; 216 } 217 218 static int stlp_set(struct mb86a16_state *state, 219 unsigned char STRAS, 220 unsigned char STRBS) 221 { 222 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0) 223 goto err; 224 225 return 0; 226 err: 227 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 228 return -EREMOTEIO; 229 } 230 231 static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA) 232 { 233 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0) 234 goto err; 235 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0) 236 goto err; 237 238 return 0; 239 err: 240 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 241 return -EREMOTEIO; 242 } 243 244 static int initial_set(struct mb86a16_state *state) 245 { 246 if (stlp_set(state, 5, 7)) 247 goto err; 248 249 udelay(100); 250 if (afcex_data_set(state, 0, 0)) 251 goto err; 252 253 udelay(100); 254 if (afcofs_data_set(state, 0, 0)) 255 goto err; 256 257 udelay(100); 258 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0) 259 goto err; 260 if (mb86a16_write(state, 0x2f, 0x21) < 0) 261 goto err; 262 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0) 263 goto err; 264 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0) 265 goto err; 266 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0) 267 goto err; 268 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0) 269 goto err; 270 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0) 271 goto err; 272 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0) 273 goto err; 274 if (mb86a16_write(state, 0x54, 0xff) < 0) 275 goto err; 276 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0) 277 goto err; 278 279 return 0; 280 281 err: 282 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 283 return -EREMOTEIO; 284 } 285 286 static int S01T_set(struct mb86a16_state *state, 287 unsigned char s1t, 288 unsigned s0t) 289 { 290 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0) 291 goto err; 292 293 return 0; 294 err: 295 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 296 return -EREMOTEIO; 297 } 298 299 300 static int EN_set(struct mb86a16_state *state, 301 int cren, 302 int afcen) 303 { 304 unsigned char val; 305 306 val = 0x7a | (cren << 7) | (afcen << 2); 307 if (mb86a16_write(state, 0x49, val) < 0) 308 goto err; 309 310 return 0; 311 err: 312 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 313 return -EREMOTEIO; 314 } 315 316 static int AFCEXEN_set(struct mb86a16_state *state, 317 int afcexen, 318 int smrt) 319 { 320 unsigned char AFCA ; 321 322 if (smrt > 18875) 323 AFCA = 4; 324 else if (smrt > 9375) 325 AFCA = 3; 326 else if (smrt > 2250) 327 AFCA = 2; 328 else 329 AFCA = 1; 330 331 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0) 332 goto err; 333 334 return 0; 335 336 err: 337 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 338 return -EREMOTEIO; 339 } 340 341 static int DAGC_data_set(struct mb86a16_state *state, 342 unsigned char DAGCA, 343 unsigned char DAGCW) 344 { 345 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0) 346 goto err; 347 348 return 0; 349 350 err: 351 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 352 return -EREMOTEIO; 353 } 354 355 static void smrt_info_get(struct mb86a16_state *state, int rate) 356 { 357 if (rate >= 37501) { 358 state->deci = 0; state->csel = 0; state->rsel = 0; 359 } else if (rate >= 30001) { 360 state->deci = 0; state->csel = 0; state->rsel = 1; 361 } else if (rate >= 26251) { 362 state->deci = 0; state->csel = 1; state->rsel = 0; 363 } else if (rate >= 22501) { 364 state->deci = 0; state->csel = 1; state->rsel = 1; 365 } else if (rate >= 18751) { 366 state->deci = 1; state->csel = 0; state->rsel = 0; 367 } else if (rate >= 15001) { 368 state->deci = 1; state->csel = 0; state->rsel = 1; 369 } else if (rate >= 13126) { 370 state->deci = 1; state->csel = 1; state->rsel = 0; 371 } else if (rate >= 11251) { 372 state->deci = 1; state->csel = 1; state->rsel = 1; 373 } else if (rate >= 9376) { 374 state->deci = 2; state->csel = 0; state->rsel = 0; 375 } else if (rate >= 7501) { 376 state->deci = 2; state->csel = 0; state->rsel = 1; 377 } else if (rate >= 6563) { 378 state->deci = 2; state->csel = 1; state->rsel = 0; 379 } else if (rate >= 5626) { 380 state->deci = 2; state->csel = 1; state->rsel = 1; 381 } else if (rate >= 4688) { 382 state->deci = 3; state->csel = 0; state->rsel = 0; 383 } else if (rate >= 3751) { 384 state->deci = 3; state->csel = 0; state->rsel = 1; 385 } else if (rate >= 3282) { 386 state->deci = 3; state->csel = 1; state->rsel = 0; 387 } else if (rate >= 2814) { 388 state->deci = 3; state->csel = 1; state->rsel = 1; 389 } else if (rate >= 2344) { 390 state->deci = 4; state->csel = 0; state->rsel = 0; 391 } else if (rate >= 1876) { 392 state->deci = 4; state->csel = 0; state->rsel = 1; 393 } else if (rate >= 1641) { 394 state->deci = 4; state->csel = 1; state->rsel = 0; 395 } else if (rate >= 1407) { 396 state->deci = 4; state->csel = 1; state->rsel = 1; 397 } else if (rate >= 1172) { 398 state->deci = 5; state->csel = 0; state->rsel = 0; 399 } else if (rate >= 939) { 400 state->deci = 5; state->csel = 0; state->rsel = 1; 401 } else if (rate >= 821) { 402 state->deci = 5; state->csel = 1; state->rsel = 0; 403 } else { 404 state->deci = 5; state->csel = 1; state->rsel = 1; 405 } 406 407 if (state->csel == 0) 408 state->master_clk = 92000; 409 else 410 state->master_clk = 61333; 411 412 } 413 414 static int signal_det(struct mb86a16_state *state, 415 int smrt, 416 unsigned char *SIG) 417 { 418 int ret; 419 int smrtd; 420 unsigned char S[3]; 421 int i; 422 423 if (*SIG > 45) { 424 if (CNTM_set(state, 2, 1, 2) < 0) { 425 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 426 return -1; 427 } 428 } else { 429 if (CNTM_set(state, 3, 1, 2) < 0) { 430 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 431 return -1; 432 } 433 } 434 for (i = 0; i < 3; i++) { 435 if (i == 0) 436 smrtd = smrt * 98 / 100; 437 else if (i == 1) 438 smrtd = smrt; 439 else 440 smrtd = smrt * 102 / 100; 441 smrt_info_get(state, smrtd); 442 smrt_set(state, smrtd); 443 srst(state); 444 msleep_interruptible(10); 445 if (mb86a16_read(state, 0x37, &(S[i])) != 2) { 446 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 447 return -EREMOTEIO; 448 } 449 } 450 if ((S[1] > S[0] * 112 / 100) && (S[1] > S[2] * 112 / 100)) 451 ret = 1; 452 else 453 ret = 0; 454 455 *SIG = S[1]; 456 457 if (CNTM_set(state, 0, 1, 2) < 0) { 458 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error"); 459 return -1; 460 } 461 462 return ret; 463 } 464 465 static int rf_val_set(struct mb86a16_state *state, 466 int f, 467 int smrt, 468 unsigned char R) 469 { 470 unsigned char C, F, B; 471 int M; 472 unsigned char rf_val[5]; 473 int ack = -1; 474 475 if (smrt > 37750) 476 C = 1; 477 else if (smrt > 18875) 478 C = 2; 479 else if (smrt > 5500) 480 C = 3; 481 else 482 C = 4; 483 484 if (smrt > 30500) 485 F = 3; 486 else if (smrt > 9375) 487 F = 1; 488 else if (smrt > 4625) 489 F = 0; 490 else 491 F = 2; 492 493 if (f < 1060) 494 B = 0; 495 else if (f < 1175) 496 B = 1; 497 else if (f < 1305) 498 B = 2; 499 else if (f < 1435) 500 B = 3; 501 else if (f < 1570) 502 B = 4; 503 else if (f < 1715) 504 B = 5; 505 else if (f < 1845) 506 B = 6; 507 else if (f < 1980) 508 B = 7; 509 else if (f < 2080) 510 B = 8; 511 else 512 B = 9; 513 514 M = f * (1 << R) / 2; 515 516 rf_val[0] = 0x01 | (C << 3) | (F << 1); 517 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12); 518 rf_val[2] = (M & 0x00ff0) >> 4; 519 rf_val[3] = ((M & 0x0000f) << 4) | B; 520 521 /* Frequency Set */ 522 if (mb86a16_write(state, 0x21, rf_val[0]) < 0) 523 ack = 0; 524 if (mb86a16_write(state, 0x22, rf_val[1]) < 0) 525 ack = 0; 526 if (mb86a16_write(state, 0x23, rf_val[2]) < 0) 527 ack = 0; 528 if (mb86a16_write(state, 0x24, rf_val[3]) < 0) 529 ack = 0; 530 if (mb86a16_write(state, 0x25, 0x01) < 0) 531 ack = 0; 532 if (ack == 0) { 533 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error"); 534 return -EREMOTEIO; 535 } 536 537 return 0; 538 } 539 540 static int afcerr_chk(struct mb86a16_state *state) 541 { 542 unsigned char AFCM_L, AFCM_H ; 543 int AFCM ; 544 int afcm, afcerr ; 545 546 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2) 547 goto err; 548 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2) 549 goto err; 550 551 AFCM = (AFCM_H << 8) + AFCM_L; 552 553 if (AFCM > 2048) 554 afcm = AFCM - 4096; 555 else 556 afcm = AFCM; 557 afcerr = afcm * state->master_clk / 8192; 558 559 return afcerr; 560 561 err: 562 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 563 return -EREMOTEIO; 564 } 565 566 static int dagcm_val_get(struct mb86a16_state *state) 567 { 568 int DAGCM; 569 unsigned char DAGCM_H, DAGCM_L; 570 571 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2) 572 goto err; 573 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2) 574 goto err; 575 576 DAGCM = (DAGCM_H << 8) + DAGCM_L; 577 578 return DAGCM; 579 580 err: 581 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 582 return -EREMOTEIO; 583 } 584 585 static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status) 586 { 587 u8 stat, stat2; 588 struct mb86a16_state *state = fe->demodulator_priv; 589 590 *status = 0; 591 592 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2) 593 goto err; 594 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2) 595 goto err; 596 if ((stat > 25) && (stat2 > 25)) 597 *status |= FE_HAS_SIGNAL; 598 if ((stat > 45) && (stat2 > 45)) 599 *status |= FE_HAS_CARRIER; 600 601 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2) 602 goto err; 603 604 if (stat & 0x01) 605 *status |= FE_HAS_SYNC; 606 if (stat & 0x01) 607 *status |= FE_HAS_VITERBI; 608 609 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2) 610 goto err; 611 612 if ((stat & 0x0f) && (*status & FE_HAS_VITERBI)) 613 *status |= FE_HAS_LOCK; 614 615 return 0; 616 617 err: 618 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 619 return -EREMOTEIO; 620 } 621 622 static int sync_chk(struct mb86a16_state *state, 623 unsigned char *VIRM) 624 { 625 unsigned char val; 626 int sync; 627 628 if (mb86a16_read(state, 0x0d, &val) != 2) 629 goto err; 630 631 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val); 632 sync = val & 0x01; 633 *VIRM = (val & 0x1c) >> 2; 634 635 return sync; 636 err: 637 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 638 *VIRM = 0; 639 return -EREMOTEIO; 640 641 } 642 643 static int freqerr_chk(struct mb86a16_state *state, 644 int fTP, 645 int smrt, 646 int unit) 647 { 648 unsigned char CRM, AFCML, AFCMH; 649 unsigned char temp1, temp2, temp3; 650 int crm, afcm, AFCM; 651 int crrerr, afcerr; /* kHz */ 652 int frqerr; /* MHz */ 653 int afcen, afcexen = 0; 654 int R, M, fOSC, fOSC_OFS; 655 656 if (mb86a16_read(state, 0x43, &CRM) != 2) 657 goto err; 658 659 if (CRM > 127) 660 crm = CRM - 256; 661 else 662 crm = CRM; 663 664 crrerr = smrt * crm / 256; 665 if (mb86a16_read(state, 0x49, &temp1) != 2) 666 goto err; 667 668 afcen = (temp1 & 0x04) >> 2; 669 if (afcen == 0) { 670 if (mb86a16_read(state, 0x2a, &temp1) != 2) 671 goto err; 672 afcexen = (temp1 & 0x20) >> 5; 673 } 674 675 if (afcen == 1) { 676 if (mb86a16_read(state, 0x0e, &AFCML) != 2) 677 goto err; 678 if (mb86a16_read(state, 0x0f, &AFCMH) != 2) 679 goto err; 680 } else if (afcexen == 1) { 681 if (mb86a16_read(state, 0x2b, &AFCML) != 2) 682 goto err; 683 if (mb86a16_read(state, 0x2c, &AFCMH) != 2) 684 goto err; 685 } 686 if ((afcen == 1) || (afcexen == 1)) { 687 smrt_info_get(state, smrt); 688 AFCM = ((AFCMH & 0x01) << 8) + AFCML; 689 if (AFCM > 255) 690 afcm = AFCM - 512; 691 else 692 afcm = AFCM; 693 694 afcerr = afcm * state->master_clk / 8192; 695 } else 696 afcerr = 0; 697 698 if (mb86a16_read(state, 0x22, &temp1) != 2) 699 goto err; 700 if (mb86a16_read(state, 0x23, &temp2) != 2) 701 goto err; 702 if (mb86a16_read(state, 0x24, &temp3) != 2) 703 goto err; 704 705 R = (temp1 & 0xe0) >> 5; 706 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4); 707 if (R == 0) 708 fOSC = 2 * M; 709 else 710 fOSC = M; 711 712 fOSC_OFS = fOSC - fTP; 713 714 if (unit == 0) { /* MHz */ 715 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0) 716 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000; 717 else 718 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000; 719 } else { /* kHz */ 720 frqerr = crrerr + afcerr + fOSC_OFS * 1000; 721 } 722 723 return frqerr; 724 err: 725 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 726 return -EREMOTEIO; 727 } 728 729 static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt) 730 { 731 unsigned char R; 732 733 if (smrt > 9375) 734 R = 0; 735 else 736 R = 1; 737 738 return R; 739 } 740 741 static void swp_info_get(struct mb86a16_state *state, 742 int fOSC_start, 743 int smrt, 744 int v, int R, 745 int swp_ofs, 746 int *fOSC, 747 int *afcex_freq, 748 unsigned char *AFCEX_L, 749 unsigned char *AFCEX_H) 750 { 751 int AFCEX ; 752 int crnt_swp_freq ; 753 754 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; 755 756 if (R == 0) 757 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2; 758 else 759 *fOSC = (crnt_swp_freq + 500) / 1000; 760 761 if (*fOSC >= crnt_swp_freq) 762 *afcex_freq = *fOSC * 1000 - crnt_swp_freq; 763 else 764 *afcex_freq = crnt_swp_freq - *fOSC * 1000; 765 766 AFCEX = *afcex_freq * 8192 / state->master_clk; 767 *AFCEX_L = AFCEX & 0x00ff; 768 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 769 } 770 771 772 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin, 773 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1) 774 { 775 int swp_freq ; 776 777 if ((i % 2 == 1) && (v <= vmax)) { 778 /* positive v (case 1) */ 779 if ((v - 1 == vmin) && 780 (*(V + 30 + v) >= 0) && 781 (*(V + 30 + v - 1) >= 0) && 782 (*(V + 30 + v - 1) > *(V + 30 + v)) && 783 (*(V + 30 + v - 1) > SIGMIN)) { 784 785 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 786 *SIG1 = *(V + 30 + v - 1); 787 } else if ((v == vmax) && 788 (*(V + 30 + v) >= 0) && 789 (*(V + 30 + v - 1) >= 0) && 790 (*(V + 30 + v) > *(V + 30 + v - 1)) && 791 (*(V + 30 + v) > SIGMIN)) { 792 /* (case 2) */ 793 swp_freq = fOSC * 1000 + afcex_freq; 794 *SIG1 = *(V + 30 + v); 795 } else if ((*(V + 30 + v) > 0) && 796 (*(V + 30 + v - 1) > 0) && 797 (*(V + 30 + v - 2) > 0) && 798 (*(V + 30 + v - 3) > 0) && 799 (*(V + 30 + v - 1) > *(V + 30 + v)) && 800 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) && 801 ((*(V + 30 + v - 1) > SIGMIN) || 802 (*(V + 30 + v - 2) > SIGMIN))) { 803 /* (case 3) */ 804 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) { 805 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 806 *SIG1 = *(V + 30 + v - 1); 807 } else { 808 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2; 809 *SIG1 = *(V + 30 + v - 2); 810 } 811 } else if ((v == vmax) && 812 (*(V + 30 + v) >= 0) && 813 (*(V + 30 + v - 1) >= 0) && 814 (*(V + 30 + v - 2) >= 0) && 815 (*(V + 30 + v) > *(V + 30 + v - 2)) && 816 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) && 817 ((*(V + 30 + v) > SIGMIN) || 818 (*(V + 30 + v - 1) > SIGMIN))) { 819 /* (case 4) */ 820 if (*(V + 30 + v) >= *(V + 30 + v - 1)) { 821 swp_freq = fOSC * 1000 + afcex_freq; 822 *SIG1 = *(V + 30 + v); 823 } else { 824 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs; 825 *SIG1 = *(V + 30 + v - 1); 826 } 827 } else { 828 swp_freq = -1 ; 829 } 830 } else if ((i % 2 == 0) && (v >= vmin)) { 831 /* Negative v (case 1) */ 832 if ((*(V + 30 + v) > 0) && 833 (*(V + 30 + v + 1) > 0) && 834 (*(V + 30 + v + 2) > 0) && 835 (*(V + 30 + v + 1) > *(V + 30 + v)) && 836 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 837 (*(V + 30 + v + 1) > SIGMIN)) { 838 839 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 840 *SIG1 = *(V + 30 + v + 1); 841 } else if ((v + 1 == vmax) && 842 (*(V + 30 + v) >= 0) && 843 (*(V + 30 + v + 1) >= 0) && 844 (*(V + 30 + v + 1) > *(V + 30 + v)) && 845 (*(V + 30 + v + 1) > SIGMIN)) { 846 /* (case 2) */ 847 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 848 *SIG1 = *(V + 30 + v); 849 } else if ((v == vmin) && 850 (*(V + 30 + v) > 0) && 851 (*(V + 30 + v + 1) > 0) && 852 (*(V + 30 + v + 2) > 0) && 853 (*(V + 30 + v) > *(V + 30 + v + 1)) && 854 (*(V + 30 + v) > *(V + 30 + v + 2)) && 855 (*(V + 30 + v) > SIGMIN)) { 856 /* (case 3) */ 857 swp_freq = fOSC * 1000 + afcex_freq; 858 *SIG1 = *(V + 30 + v); 859 } else if ((*(V + 30 + v) >= 0) && 860 (*(V + 30 + v + 1) >= 0) && 861 (*(V + 30 + v + 2) >= 0) && 862 (*(V + 30 + v + 3) >= 0) && 863 (*(V + 30 + v + 1) > *(V + 30 + v)) && 864 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) && 865 ((*(V + 30 + v + 1) > SIGMIN) || 866 (*(V + 30 + v + 2) > SIGMIN))) { 867 /* (case 4) */ 868 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 869 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 870 *SIG1 = *(V + 30 + v + 1); 871 } else { 872 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 873 *SIG1 = *(V + 30 + v + 2); 874 } 875 } else if ((*(V + 30 + v) >= 0) && 876 (*(V + 30 + v + 1) >= 0) && 877 (*(V + 30 + v + 2) >= 0) && 878 (*(V + 30 + v + 3) >= 0) && 879 (*(V + 30 + v) > *(V + 30 + v + 2)) && 880 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) && 881 (*(V + 30 + v) > *(V + 30 + v + 3)) && 882 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) && 883 ((*(V + 30 + v) > SIGMIN) || 884 (*(V + 30 + v + 1) > SIGMIN))) { 885 /* (case 5) */ 886 if (*(V + 30 + v) >= *(V + 30 + v + 1)) { 887 swp_freq = fOSC * 1000 + afcex_freq; 888 *SIG1 = *(V + 30 + v); 889 } else { 890 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 891 *SIG1 = *(V + 30 + v + 1); 892 } 893 } else if ((v + 2 == vmin) && 894 (*(V + 30 + v) >= 0) && 895 (*(V + 30 + v + 1) >= 0) && 896 (*(V + 30 + v + 2) >= 0) && 897 (*(V + 30 + v + 1) > *(V + 30 + v)) && 898 (*(V + 30 + v + 2) > *(V + 30 + v)) && 899 ((*(V + 30 + v + 1) > SIGMIN) || 900 (*(V + 30 + v + 2) > SIGMIN))) { 901 /* (case 6) */ 902 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) { 903 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs; 904 *SIG1 = *(V + 30 + v + 1); 905 } else { 906 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2; 907 *SIG1 = *(V + 30 + v + 2); 908 } 909 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) { 910 swp_freq = fOSC * 1000; 911 *SIG1 = *(V + 30 + v); 912 } else 913 swp_freq = -1; 914 } else 915 swp_freq = -1; 916 917 return swp_freq; 918 } 919 920 static void swp_info_get2(struct mb86a16_state *state, 921 int smrt, 922 int R, 923 int swp_freq, 924 int *afcex_freq, 925 int *fOSC, 926 unsigned char *AFCEX_L, 927 unsigned char *AFCEX_H) 928 { 929 int AFCEX ; 930 931 if (R == 0) 932 *fOSC = (swp_freq + 1000) / 2000 * 2; 933 else 934 *fOSC = (swp_freq + 500) / 1000; 935 936 if (*fOSC >= swp_freq) 937 *afcex_freq = *fOSC * 1000 - swp_freq; 938 else 939 *afcex_freq = swp_freq - *fOSC * 1000; 940 941 AFCEX = *afcex_freq * 8192 / state->master_clk; 942 *AFCEX_L = AFCEX & 0x00ff; 943 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 944 } 945 946 static void afcex_info_get(struct mb86a16_state *state, 947 int afcex_freq, 948 unsigned char *AFCEX_L, 949 unsigned char *AFCEX_H) 950 { 951 int AFCEX ; 952 953 AFCEX = afcex_freq * 8192 / state->master_clk; 954 *AFCEX_L = AFCEX & 0x00ff; 955 *AFCEX_H = (AFCEX & 0x0f00) >> 8; 956 } 957 958 static int SEQ_set(struct mb86a16_state *state, unsigned char loop) 959 { 960 /* SLOCK0 = 0 */ 961 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) { 962 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 963 return -EREMOTEIO; 964 } 965 966 return 0; 967 } 968 969 static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV) 970 { 971 /* Viterbi Rate, IQ Settings */ 972 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) { 973 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 974 return -EREMOTEIO; 975 } 976 977 return 0; 978 } 979 980 static int FEC_srst(struct mb86a16_state *state) 981 { 982 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) { 983 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 984 return -EREMOTEIO; 985 } 986 987 return 0; 988 } 989 990 static int S2T_set(struct mb86a16_state *state, unsigned char S2T) 991 { 992 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) { 993 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 994 return -EREMOTEIO; 995 } 996 997 return 0; 998 } 999 1000 static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T) 1001 { 1002 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) { 1003 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1004 return -EREMOTEIO; 1005 } 1006 1007 return 0; 1008 } 1009 1010 1011 static int mb86a16_set_fe(struct mb86a16_state *state) 1012 { 1013 u8 agcval, cnmval; 1014 1015 int i, j; 1016 int fOSC = 0; 1017 int fOSC_start = 0; 1018 int wait_t; 1019 int fcp; 1020 int swp_ofs; 1021 int V[60]; 1022 u8 SIG1MIN; 1023 1024 unsigned char CREN, AFCEN, AFCEXEN; 1025 unsigned char SIG1; 1026 unsigned char TIMINT1, TIMINT2, TIMEXT; 1027 unsigned char S0T, S1T; 1028 unsigned char S2T; 1029 /* unsigned char S2T, S3T; */ 1030 unsigned char S4T, S5T; 1031 unsigned char AFCEX_L, AFCEX_H; 1032 unsigned char R; 1033 unsigned char VIRM; 1034 unsigned char ETH, VIA; 1035 unsigned char junk; 1036 1037 int loop; 1038 int ftemp; 1039 int v, vmax, vmin; 1040 int vmax_his, vmin_his; 1041 int swp_freq, prev_swp_freq[20]; 1042 int prev_freq_num; 1043 int signal_dupl; 1044 int afcex_freq; 1045 int signal; 1046 int afcerr; 1047 int temp_freq, delta_freq; 1048 int dagcm[4]; 1049 int smrt_d; 1050 /* int freq_err; */ 1051 int n; 1052 int ret = -1; 1053 int sync; 1054 1055 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate); 1056 1057 fcp = 3000; 1058 swp_ofs = state->srate / 4; 1059 1060 for (i = 0; i < 60; i++) 1061 V[i] = -1; 1062 1063 for (i = 0; i < 20; i++) 1064 prev_swp_freq[i] = 0; 1065 1066 SIG1MIN = 25; 1067 1068 for (n = 0; ((n < 3) && (ret == -1)); n++) { 1069 SEQ_set(state, 0); 1070 iq_vt_set(state, 0); 1071 1072 CREN = 0; 1073 AFCEN = 0; 1074 AFCEXEN = 1; 1075 TIMINT1 = 0; 1076 TIMINT2 = 1; 1077 TIMEXT = 2; 1078 S1T = 0; 1079 S0T = 0; 1080 1081 if (initial_set(state) < 0) { 1082 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed"); 1083 return -1; 1084 } 1085 if (DAGC_data_set(state, 3, 2) < 0) { 1086 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1087 return -1; 1088 } 1089 if (EN_set(state, CREN, AFCEN) < 0) { 1090 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1091 return -1; /* (0, 0) */ 1092 } 1093 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1094 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1095 return -1; /* (1, smrt) = (1, symbolrate) */ 1096 } 1097 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) { 1098 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error"); 1099 return -1; /* (0, 1, 2) */ 1100 } 1101 if (S01T_set(state, S1T, S0T) < 0) { 1102 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1103 return -1; /* (0, 0) */ 1104 } 1105 smrt_info_get(state, state->srate); 1106 if (smrt_set(state, state->srate) < 0) { 1107 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error"); 1108 return -1; 1109 } 1110 1111 R = vco_dev_get(state, state->srate); 1112 if (R == 1) 1113 fOSC_start = state->frequency; 1114 1115 else if (R == 0) { 1116 if (state->frequency % 2 == 0) { 1117 fOSC_start = state->frequency; 1118 } else { 1119 fOSC_start = state->frequency + 1; 1120 if (fOSC_start > 2150) 1121 fOSC_start = state->frequency - 1; 1122 } 1123 } 1124 loop = 1; 1125 ftemp = fOSC_start * 1000; 1126 vmax = 0 ; 1127 while (loop == 1) { 1128 ftemp = ftemp + swp_ofs; 1129 vmax++; 1130 1131 /* Upper bound */ 1132 if (ftemp > 2150000) { 1133 loop = 0; 1134 vmax--; 1135 } else { 1136 if ((ftemp == 2150000) || 1137 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4)) 1138 loop = 0; 1139 } 1140 } 1141 1142 loop = 1; 1143 ftemp = fOSC_start * 1000; 1144 vmin = 0 ; 1145 while (loop == 1) { 1146 ftemp = ftemp - swp_ofs; 1147 vmin--; 1148 1149 /* Lower bound */ 1150 if (ftemp < 950000) { 1151 loop = 0; 1152 vmin++; 1153 } else { 1154 if ((ftemp == 950000) || 1155 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4)) 1156 loop = 0; 1157 } 1158 } 1159 1160 wait_t = (8000 + state->srate / 2) / state->srate; 1161 if (wait_t == 0) 1162 wait_t = 1; 1163 1164 i = 0; 1165 j = 0; 1166 prev_freq_num = 0; 1167 loop = 1; 1168 signal = 0; 1169 vmax_his = 0; 1170 vmin_his = 0; 1171 v = 0; 1172 1173 while (loop == 1) { 1174 swp_info_get(state, fOSC_start, state->srate, 1175 v, R, swp_ofs, &fOSC, 1176 &afcex_freq, &AFCEX_L, &AFCEX_H); 1177 1178 udelay(100); 1179 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1180 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1181 return -1; 1182 } 1183 udelay(100); 1184 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1185 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1186 return -1; 1187 } 1188 if (srst(state) < 0) { 1189 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1190 return -1; 1191 } 1192 msleep_interruptible(wait_t); 1193 1194 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1195 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1196 return -1; 1197 } 1198 V[30 + v] = SIG1 ; 1199 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin, 1200 SIG1MIN, fOSC, afcex_freq, 1201 swp_ofs, &SIG1); /* changed */ 1202 1203 signal_dupl = 0; 1204 for (j = 0; j < prev_freq_num; j++) { 1205 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) { 1206 signal_dupl = 1; 1207 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j); 1208 } 1209 } 1210 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) { 1211 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate); 1212 prev_swp_freq[prev_freq_num] = swp_freq; 1213 prev_freq_num++; 1214 swp_info_get2(state, state->srate, R, swp_freq, 1215 &afcex_freq, &fOSC, 1216 &AFCEX_L, &AFCEX_H); 1217 1218 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1219 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1220 return -1; 1221 } 1222 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1223 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1224 return -1; 1225 } 1226 signal = signal_det(state, state->srate, &SIG1); 1227 if (signal == 1) { 1228 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****"); 1229 loop = 0; 1230 } else { 1231 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again..."); 1232 smrt_info_get(state, state->srate); 1233 if (smrt_set(state, state->srate) < 0) { 1234 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1235 return -1; 1236 } 1237 } 1238 } 1239 if (v > vmax) 1240 vmax_his = 1 ; 1241 if (v < vmin) 1242 vmin_his = 1 ; 1243 i++; 1244 1245 if ((i % 2 == 1) && (vmax_his == 1)) 1246 i++; 1247 if ((i % 2 == 0) && (vmin_his == 1)) 1248 i++; 1249 1250 if (i % 2 == 1) 1251 v = (i + 1) / 2; 1252 else 1253 v = -i / 2; 1254 1255 if ((vmax_his == 1) && (vmin_his == 1)) 1256 loop = 0 ; 1257 } 1258 1259 if (signal == 1) { 1260 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check"); 1261 S1T = 7 ; 1262 S0T = 1 ; 1263 CREN = 0 ; 1264 AFCEN = 1 ; 1265 AFCEXEN = 0 ; 1266 1267 if (S01T_set(state, S1T, S0T) < 0) { 1268 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1269 return -1; 1270 } 1271 smrt_info_get(state, state->srate); 1272 if (smrt_set(state, state->srate) < 0) { 1273 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1274 return -1; 1275 } 1276 if (EN_set(state, CREN, AFCEN) < 0) { 1277 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1278 return -1; 1279 } 1280 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1281 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1282 return -1; 1283 } 1284 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H); 1285 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1286 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error"); 1287 return -1; 1288 } 1289 if (srst(state) < 0) { 1290 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1291 return -1; 1292 } 1293 /* delay 4~200 */ 1294 wait_t = 200000 / state->master_clk + 200000 / state->srate; 1295 msleep(wait_t); 1296 afcerr = afcerr_chk(state); 1297 if (afcerr == -1) 1298 return -1; 1299 1300 swp_freq = fOSC * 1000 + afcerr ; 1301 AFCEXEN = 1 ; 1302 if (state->srate >= 1500) 1303 smrt_d = state->srate / 3; 1304 else 1305 smrt_d = state->srate / 2; 1306 smrt_info_get(state, smrt_d); 1307 if (smrt_set(state, smrt_d) < 0) { 1308 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1309 return -1; 1310 } 1311 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) { 1312 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1313 return -1; 1314 } 1315 R = vco_dev_get(state, smrt_d); 1316 if (DAGC_data_set(state, 2, 0) < 0) { 1317 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1318 return -1; 1319 } 1320 for (i = 0; i < 3; i++) { 1321 temp_freq = swp_freq + (i - 1) * state->srate / 8; 1322 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1323 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1324 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1325 return -1; 1326 } 1327 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1328 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1329 return -1; 1330 } 1331 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1332 msleep(wait_t); 1333 dagcm[i] = dagcm_val_get(state); 1334 } 1335 if ((dagcm[0] > dagcm[1]) && 1336 (dagcm[0] > dagcm[2]) && 1337 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) { 1338 1339 temp_freq = swp_freq - 2 * state->srate / 8; 1340 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1341 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1342 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1343 return -1; 1344 } 1345 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1346 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1347 return -1; 1348 } 1349 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1350 msleep(wait_t); 1351 dagcm[3] = dagcm_val_get(state); 1352 if (dagcm[3] > dagcm[1]) 1353 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300; 1354 else 1355 delta_freq = 0; 1356 } else if ((dagcm[2] > dagcm[1]) && 1357 (dagcm[2] > dagcm[0]) && 1358 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) { 1359 1360 temp_freq = swp_freq + 2 * state->srate / 8; 1361 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1362 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { 1363 dprintk(verbose, MB86A16_ERROR, 1, "rf val set"); 1364 return -1; 1365 } 1366 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1367 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set"); 1368 return -1; 1369 } 1370 wait_t = 200000 / state->master_clk + 40000 / smrt_d; 1371 msleep(wait_t); 1372 dagcm[3] = dagcm_val_get(state); 1373 if (dagcm[3] > dagcm[1]) 1374 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300; 1375 else 1376 delta_freq = 0 ; 1377 1378 } else { 1379 delta_freq = 0 ; 1380 } 1381 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq); 1382 swp_freq += delta_freq; 1383 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq); 1384 if (ABS(state->frequency * 1000 - swp_freq) > 3800) { 1385 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !"); 1386 } else { 1387 1388 S1T = 0; 1389 S0T = 3; 1390 CREN = 1; 1391 AFCEN = 0; 1392 AFCEXEN = 1; 1393 1394 if (S01T_set(state, S1T, S0T) < 0) { 1395 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error"); 1396 return -1; 1397 } 1398 if (DAGC_data_set(state, 0, 0) < 0) { 1399 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error"); 1400 return -1; 1401 } 1402 R = vco_dev_get(state, state->srate); 1403 smrt_info_get(state, state->srate); 1404 if (smrt_set(state, state->srate) < 0) { 1405 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error"); 1406 return -1; 1407 } 1408 if (EN_set(state, CREN, AFCEN) < 0) { 1409 dprintk(verbose, MB86A16_ERROR, 1, "EN set error"); 1410 return -1; 1411 } 1412 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { 1413 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error"); 1414 return -1; 1415 } 1416 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); 1417 if (rf_val_set(state, fOSC, state->srate, R) < 0) { 1418 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error"); 1419 return -1; 1420 } 1421 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { 1422 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error"); 1423 return -1; 1424 } 1425 if (srst(state) < 0) { 1426 dprintk(verbose, MB86A16_ERROR, 1, "srst error"); 1427 return -1; 1428 } 1429 wait_t = 7 + (10000 + state->srate / 2) / state->srate; 1430 if (wait_t == 0) 1431 wait_t = 1; 1432 msleep_interruptible(wait_t); 1433 if (mb86a16_read(state, 0x37, &SIG1) != 2) { 1434 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1435 return -EREMOTEIO; 1436 } 1437 1438 if (SIG1 > 110) { 1439 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6; 1440 wait_t = 7 + (917504 + state->srate / 2) / state->srate; 1441 } else if (SIG1 > 105) { 1442 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1443 wait_t = 7 + (1048576 + state->srate / 2) / state->srate; 1444 } else if (SIG1 > 85) { 1445 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1446 wait_t = 7 + (1310720 + state->srate / 2) / state->srate; 1447 } else if (SIG1 > 65) { 1448 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1449 wait_t = 7 + (1572864 + state->srate / 2) / state->srate; 1450 } else { 1451 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2; 1452 wait_t = 7 + (2097152 + state->srate / 2) / state->srate; 1453 } 1454 wait_t *= 2; /* FOS */ 1455 S2T_set(state, S2T); 1456 S45T_set(state, S4T, S5T); 1457 Vi_set(state, ETH, VIA); 1458 srst(state); 1459 msleep_interruptible(wait_t); 1460 sync = sync_chk(state, &VIRM); 1461 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync); 1462 if (VIRM) { 1463 if (VIRM == 4) { 1464 /* 5/6 */ 1465 if (SIG1 > 110) 1466 wait_t = (786432 + state->srate / 2) / state->srate; 1467 else 1468 wait_t = (1572864 + state->srate / 2) / state->srate; 1469 if (state->srate < 5000) 1470 /* FIXME ! , should be a long wait ! */ 1471 msleep_interruptible(wait_t); 1472 else 1473 msleep_interruptible(wait_t); 1474 1475 if (sync_chk(state, &junk) == 0) { 1476 iq_vt_set(state, 1); 1477 FEC_srst(state); 1478 } 1479 } 1480 /* 1/2, 2/3, 3/4, 7/8 */ 1481 if (SIG1 > 110) 1482 wait_t = (786432 + state->srate / 2) / state->srate; 1483 else 1484 wait_t = (1572864 + state->srate / 2) / state->srate; 1485 msleep_interruptible(wait_t); 1486 SEQ_set(state, 1); 1487 } else { 1488 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC"); 1489 SEQ_set(state, 1); 1490 ret = -1; 1491 } 1492 } 1493 } else { 1494 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL"); 1495 ret = -1; 1496 } 1497 1498 sync = sync_chk(state, &junk); 1499 if (sync) { 1500 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******"); 1501 freqerr_chk(state, state->frequency, state->srate, 1); 1502 ret = 0; 1503 break; 1504 } 1505 } 1506 1507 mb86a16_read(state, 0x15, &agcval); 1508 mb86a16_read(state, 0x26, &cnmval); 1509 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval); 1510 1511 return ret; 1512 } 1513 1514 static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe, 1515 struct dvb_diseqc_master_cmd *cmd) 1516 { 1517 struct mb86a16_state *state = fe->demodulator_priv; 1518 int i; 1519 u8 regs; 1520 1521 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1522 goto err; 1523 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1524 goto err; 1525 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1526 goto err; 1527 1528 regs = 0x18; 1529 1530 if (cmd->msg_len > 5 || cmd->msg_len < 4) 1531 return -EINVAL; 1532 1533 for (i = 0; i < cmd->msg_len; i++) { 1534 if (mb86a16_write(state, regs, cmd->msg[i]) < 0) 1535 goto err; 1536 1537 regs++; 1538 } 1539 i += 0x90; 1540 1541 msleep_interruptible(10); 1542 1543 if (mb86a16_write(state, MB86A16_DCC1, i) < 0) 1544 goto err; 1545 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1546 goto err; 1547 1548 return 0; 1549 1550 err: 1551 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1552 return -EREMOTEIO; 1553 } 1554 1555 static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, 1556 enum fe_sec_mini_cmd burst) 1557 { 1558 struct mb86a16_state *state = fe->demodulator_priv; 1559 1560 switch (burst) { 1561 case SEC_MINI_A: 1562 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1563 MB86A16_DCC1_TBEN | 1564 MB86A16_DCC1_TBO) < 0) 1565 goto err; 1566 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1567 goto err; 1568 break; 1569 case SEC_MINI_B: 1570 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1571 MB86A16_DCC1_TBEN) < 0) 1572 goto err; 1573 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1574 goto err; 1575 break; 1576 } 1577 1578 return 0; 1579 err: 1580 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1581 return -EREMOTEIO; 1582 } 1583 1584 static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 1585 { 1586 struct mb86a16_state *state = fe->demodulator_priv; 1587 1588 switch (tone) { 1589 case SEC_TONE_ON: 1590 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0) 1591 goto err; 1592 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | 1593 MB86A16_DCC1_CTOE) < 0) 1594 1595 goto err; 1596 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) 1597 goto err; 1598 break; 1599 case SEC_TONE_OFF: 1600 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) 1601 goto err; 1602 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) 1603 goto err; 1604 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) 1605 goto err; 1606 break; 1607 default: 1608 return -EINVAL; 1609 } 1610 return 0; 1611 1612 err: 1613 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1614 return -EREMOTEIO; 1615 } 1616 1617 static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe) 1618 { 1619 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1620 struct mb86a16_state *state = fe->demodulator_priv; 1621 1622 state->frequency = p->frequency / 1000; 1623 state->srate = p->symbol_rate / 1000; 1624 1625 if (!mb86a16_set_fe(state)) { 1626 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK"); 1627 return DVBFE_ALGO_SEARCH_SUCCESS; 1628 } 1629 1630 dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!"); 1631 return DVBFE_ALGO_SEARCH_FAILED; 1632 } 1633 1634 static void mb86a16_release(struct dvb_frontend *fe) 1635 { 1636 struct mb86a16_state *state = fe->demodulator_priv; 1637 kfree(state); 1638 } 1639 1640 static int mb86a16_init(struct dvb_frontend *fe) 1641 { 1642 return 0; 1643 } 1644 1645 static int mb86a16_sleep(struct dvb_frontend *fe) 1646 { 1647 return 0; 1648 } 1649 1650 static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber) 1651 { 1652 u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst; 1653 u32 timer; 1654 1655 struct mb86a16_state *state = fe->demodulator_priv; 1656 1657 *ber = 0; 1658 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2) 1659 goto err; 1660 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2) 1661 goto err; 1662 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2) 1663 goto err; 1664 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2) 1665 goto err; 1666 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2) 1667 goto err; 1668 /* BER monitor invalid when BER_EN = 0 */ 1669 if (ber_mon & 0x04) { 1670 /* coarse, fast calculation */ 1671 *ber = ber_tab & 0x1f; 1672 dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber); 1673 if (ber_mon & 0x01) { 1674 /* 1675 * BER_SEL = 1, The monitored BER is the estimated 1676 * value with a Reed-Solomon decoder error amount at 1677 * the deinterleaver output. 1678 * monitored BER is expressed as a 20 bit output in total 1679 */ 1680 ber_rst = (ber_mon >> 3) & 0x03; 1681 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1682 if (ber_rst == 0) 1683 timer = 12500000; 1684 else if (ber_rst == 1) 1685 timer = 25000000; 1686 else if (ber_rst == 2) 1687 timer = 50000000; 1688 else /* ber_rst == 3 */ 1689 timer = 100000000; 1690 1691 *ber /= timer; 1692 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1693 } else { 1694 /* 1695 * BER_SEL = 0, The monitored BER is the estimated 1696 * value with a Viterbi decoder error amount at the 1697 * QPSK demodulator output. 1698 * monitored BER is expressed as a 24 bit output in total 1699 */ 1700 ber_tim = (ber_mon >> 1) & 0x01; 1701 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb; 1702 if (ber_tim == 0) 1703 timer = 16; 1704 else /* ber_tim == 1 */ 1705 timer = 24; 1706 1707 *ber /= 2 ^ timer; 1708 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber); 1709 } 1710 } 1711 return 0; 1712 err: 1713 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1714 return -EREMOTEIO; 1715 } 1716 1717 static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1718 { 1719 u8 agcm = 0; 1720 struct mb86a16_state *state = fe->demodulator_priv; 1721 1722 *strength = 0; 1723 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) { 1724 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1725 return -EREMOTEIO; 1726 } 1727 1728 *strength = ((0xff - agcm) * 100) / 256; 1729 dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength); 1730 *strength = (0xffff - 0xff) + agcm; 1731 1732 return 0; 1733 } 1734 1735 struct cnr { 1736 u8 cn_reg; 1737 u8 cn_val; 1738 }; 1739 1740 static const struct cnr cnr_tab[] = { 1741 { 35, 2 }, 1742 { 40, 3 }, 1743 { 50, 4 }, 1744 { 60, 5 }, 1745 { 70, 6 }, 1746 { 80, 7 }, 1747 { 92, 8 }, 1748 { 103, 9 }, 1749 { 115, 10 }, 1750 { 138, 12 }, 1751 { 162, 15 }, 1752 { 180, 18 }, 1753 { 185, 19 }, 1754 { 189, 20 }, 1755 { 195, 22 }, 1756 { 199, 24 }, 1757 { 201, 25 }, 1758 { 202, 26 }, 1759 { 203, 27 }, 1760 { 205, 28 }, 1761 { 208, 30 } 1762 }; 1763 1764 static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr) 1765 { 1766 struct mb86a16_state *state = fe->demodulator_priv; 1767 int i = 0; 1768 int low_tide = 2, high_tide = 30, q_level; 1769 u8 cn; 1770 1771 *snr = 0; 1772 if (mb86a16_read(state, 0x26, &cn) != 2) { 1773 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1774 return -EREMOTEIO; 1775 } 1776 1777 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) { 1778 if (cn < cnr_tab[i].cn_reg) { 1779 *snr = cnr_tab[i].cn_val; 1780 break; 1781 } 1782 } 1783 q_level = (*snr * 100) / (high_tide - low_tide); 1784 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level); 1785 *snr = (0xffff - 0xff) + *snr; 1786 1787 return 0; 1788 } 1789 1790 static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1791 { 1792 u8 dist; 1793 struct mb86a16_state *state = fe->demodulator_priv; 1794 1795 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) { 1796 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error"); 1797 return -EREMOTEIO; 1798 } 1799 *ucblocks = dist; 1800 1801 return 0; 1802 } 1803 1804 static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe) 1805 { 1806 return DVBFE_ALGO_CUSTOM; 1807 } 1808 1809 static const struct dvb_frontend_ops mb86a16_ops = { 1810 .delsys = { SYS_DVBS }, 1811 .info = { 1812 .name = "Fujitsu MB86A16 DVB-S", 1813 .frequency_min = 950000, 1814 .frequency_max = 2150000, 1815 .frequency_stepsize = 3000, 1816 .frequency_tolerance = 0, 1817 .symbol_rate_min = 1000000, 1818 .symbol_rate_max = 45000000, 1819 .symbol_rate_tolerance = 500, 1820 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 1821 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | 1822 FE_CAN_FEC_7_8 | FE_CAN_QPSK | 1823 FE_CAN_FEC_AUTO 1824 }, 1825 .release = mb86a16_release, 1826 1827 .get_frontend_algo = mb86a16_frontend_algo, 1828 .search = mb86a16_search, 1829 .init = mb86a16_init, 1830 .sleep = mb86a16_sleep, 1831 .read_status = mb86a16_read_status, 1832 1833 .read_ber = mb86a16_read_ber, 1834 .read_signal_strength = mb86a16_read_signal_strength, 1835 .read_snr = mb86a16_read_snr, 1836 .read_ucblocks = mb86a16_read_ucblocks, 1837 1838 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg, 1839 .diseqc_send_burst = mb86a16_send_diseqc_burst, 1840 .set_tone = mb86a16_set_tone, 1841 }; 1842 1843 struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, 1844 struct i2c_adapter *i2c_adap) 1845 { 1846 u8 dev_id = 0; 1847 struct mb86a16_state *state = NULL; 1848 1849 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL); 1850 if (state == NULL) 1851 goto error; 1852 1853 state->config = config; 1854 state->i2c_adap = i2c_adap; 1855 1856 mb86a16_read(state, 0x7f, &dev_id); 1857 if (dev_id != 0xfe) 1858 goto error; 1859 1860 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops)); 1861 state->frontend.demodulator_priv = state; 1862 state->frontend.ops.set_voltage = state->config->set_voltage; 1863 1864 return &state->frontend; 1865 error: 1866 kfree(state); 1867 return NULL; 1868 } 1869 EXPORT_SYMBOL(mb86a16_attach); 1870 MODULE_LICENSE("GPL"); 1871 MODULE_AUTHOR("Manu Abraham"); 1872