174ba9207SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
29a0bf528SMauro Carvalho Chehab /*
39a0bf528SMauro Carvalho Chehab Legend Silicon LGS-8GL5 DMB-TH OFDM demodulator driver
49a0bf528SMauro Carvalho Chehab
59a0bf528SMauro Carvalho Chehab Copyright (C) 2008 Sirius International (Hong Kong) Limited
69a0bf528SMauro Carvalho Chehab Timothy Lee <timothy.lee@siriushk.com>
79a0bf528SMauro Carvalho Chehab
89a0bf528SMauro Carvalho Chehab
99a0bf528SMauro Carvalho Chehab */
109a0bf528SMauro Carvalho Chehab
119a0bf528SMauro Carvalho Chehab #include <linux/kernel.h>
129a0bf528SMauro Carvalho Chehab #include <linux/init.h>
139a0bf528SMauro Carvalho Chehab #include <linux/module.h>
149a0bf528SMauro Carvalho Chehab #include <linux/string.h>
159a0bf528SMauro Carvalho Chehab #include <linux/slab.h>
16fada1935SMauro Carvalho Chehab #include <media/dvb_frontend.h>
179a0bf528SMauro Carvalho Chehab #include "lgs8gl5.h"
189a0bf528SMauro Carvalho Chehab
199a0bf528SMauro Carvalho Chehab
209a0bf528SMauro Carvalho Chehab #define REG_RESET 0x02
219a0bf528SMauro Carvalho Chehab #define REG_RESET_OFF 0x01
229a0bf528SMauro Carvalho Chehab #define REG_03 0x03
239a0bf528SMauro Carvalho Chehab #define REG_04 0x04
249a0bf528SMauro Carvalho Chehab #define REG_07 0x07
259a0bf528SMauro Carvalho Chehab #define REG_09 0x09
269a0bf528SMauro Carvalho Chehab #define REG_0A 0x0a
279a0bf528SMauro Carvalho Chehab #define REG_0B 0x0b
289a0bf528SMauro Carvalho Chehab #define REG_0C 0x0c
299a0bf528SMauro Carvalho Chehab #define REG_37 0x37
309a0bf528SMauro Carvalho Chehab #define REG_STRENGTH 0x4b
319a0bf528SMauro Carvalho Chehab #define REG_STRENGTH_MASK 0x7f
329a0bf528SMauro Carvalho Chehab #define REG_STRENGTH_CARRIER 0x80
339a0bf528SMauro Carvalho Chehab #define REG_INVERSION 0x7c
349a0bf528SMauro Carvalho Chehab #define REG_INVERSION_ON 0x80
359a0bf528SMauro Carvalho Chehab #define REG_7D 0x7d
369a0bf528SMauro Carvalho Chehab #define REG_7E 0x7e
379a0bf528SMauro Carvalho Chehab #define REG_A2 0xa2
389a0bf528SMauro Carvalho Chehab #define REG_STATUS 0xa4
399a0bf528SMauro Carvalho Chehab #define REG_STATUS_SYNC 0x04
409a0bf528SMauro Carvalho Chehab #define REG_STATUS_LOCK 0x01
419a0bf528SMauro Carvalho Chehab
429a0bf528SMauro Carvalho Chehab
439a0bf528SMauro Carvalho Chehab struct lgs8gl5_state {
449a0bf528SMauro Carvalho Chehab struct i2c_adapter *i2c;
459a0bf528SMauro Carvalho Chehab const struct lgs8gl5_config *config;
469a0bf528SMauro Carvalho Chehab struct dvb_frontend frontend;
479a0bf528SMauro Carvalho Chehab };
489a0bf528SMauro Carvalho Chehab
499a0bf528SMauro Carvalho Chehab
509a0bf528SMauro Carvalho Chehab static int debug;
519a0bf528SMauro Carvalho Chehab #define dprintk(args...) \
529a0bf528SMauro Carvalho Chehab do { \
539a0bf528SMauro Carvalho Chehab if (debug) \
549a0bf528SMauro Carvalho Chehab printk(KERN_DEBUG "lgs8gl5: " args); \
559a0bf528SMauro Carvalho Chehab } while (0)
569a0bf528SMauro Carvalho Chehab
579a0bf528SMauro Carvalho Chehab
589a0bf528SMauro Carvalho Chehab /* Writes into demod's register */
599a0bf528SMauro Carvalho Chehab static int
lgs8gl5_write_reg(struct lgs8gl5_state * state,u8 reg,u8 data)609a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
619a0bf528SMauro Carvalho Chehab {
629a0bf528SMauro Carvalho Chehab int ret;
639a0bf528SMauro Carvalho Chehab u8 buf[] = {reg, data};
649a0bf528SMauro Carvalho Chehab struct i2c_msg msg = {
659a0bf528SMauro Carvalho Chehab .addr = state->config->demod_address,
669a0bf528SMauro Carvalho Chehab .flags = 0,
679a0bf528SMauro Carvalho Chehab .buf = buf,
689a0bf528SMauro Carvalho Chehab .len = 2
699a0bf528SMauro Carvalho Chehab };
709a0bf528SMauro Carvalho Chehab
719a0bf528SMauro Carvalho Chehab ret = i2c_transfer(state->i2c, &msg, 1);
729a0bf528SMauro Carvalho Chehab if (ret != 1)
739a0bf528SMauro Carvalho Chehab dprintk("%s: error (reg=0x%02x, val=0x%02x, ret=%i)\n",
749a0bf528SMauro Carvalho Chehab __func__, reg, data, ret);
759a0bf528SMauro Carvalho Chehab return (ret != 1) ? -1 : 0;
769a0bf528SMauro Carvalho Chehab }
779a0bf528SMauro Carvalho Chehab
789a0bf528SMauro Carvalho Chehab
799a0bf528SMauro Carvalho Chehab /* Reads from demod's register */
809a0bf528SMauro Carvalho Chehab static int
lgs8gl5_read_reg(struct lgs8gl5_state * state,u8 reg)819a0bf528SMauro Carvalho Chehab lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg)
829a0bf528SMauro Carvalho Chehab {
839a0bf528SMauro Carvalho Chehab int ret;
849a0bf528SMauro Carvalho Chehab u8 b0[] = {reg};
859a0bf528SMauro Carvalho Chehab u8 b1[] = {0};
869a0bf528SMauro Carvalho Chehab struct i2c_msg msg[2] = {
879a0bf528SMauro Carvalho Chehab {
889a0bf528SMauro Carvalho Chehab .addr = state->config->demod_address,
899a0bf528SMauro Carvalho Chehab .flags = 0,
909a0bf528SMauro Carvalho Chehab .buf = b0,
919a0bf528SMauro Carvalho Chehab .len = 1
929a0bf528SMauro Carvalho Chehab },
939a0bf528SMauro Carvalho Chehab {
949a0bf528SMauro Carvalho Chehab .addr = state->config->demod_address,
959a0bf528SMauro Carvalho Chehab .flags = I2C_M_RD,
969a0bf528SMauro Carvalho Chehab .buf = b1,
979a0bf528SMauro Carvalho Chehab .len = 1
989a0bf528SMauro Carvalho Chehab }
999a0bf528SMauro Carvalho Chehab };
1009a0bf528SMauro Carvalho Chehab
1019a0bf528SMauro Carvalho Chehab ret = i2c_transfer(state->i2c, msg, 2);
1029a0bf528SMauro Carvalho Chehab if (ret != 2)
1039a0bf528SMauro Carvalho Chehab return -EIO;
1049a0bf528SMauro Carvalho Chehab
1059a0bf528SMauro Carvalho Chehab return b1[0];
1069a0bf528SMauro Carvalho Chehab }
1079a0bf528SMauro Carvalho Chehab
1089a0bf528SMauro Carvalho Chehab
1099a0bf528SMauro Carvalho Chehab static int
lgs8gl5_update_reg(struct lgs8gl5_state * state,u8 reg,u8 data)1109a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
1119a0bf528SMauro Carvalho Chehab {
1129a0bf528SMauro Carvalho Chehab lgs8gl5_read_reg(state, reg);
1139a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, reg, data);
1149a0bf528SMauro Carvalho Chehab return 0;
1159a0bf528SMauro Carvalho Chehab }
1169a0bf528SMauro Carvalho Chehab
1179a0bf528SMauro Carvalho Chehab
1189a0bf528SMauro Carvalho Chehab /* Writes into alternate device's register */
1199a0bf528SMauro Carvalho Chehab /* TODO: Find out what that device is for! */
1209a0bf528SMauro Carvalho Chehab static int
lgs8gl5_update_alt_reg(struct lgs8gl5_state * state,u8 reg,u8 data)1219a0bf528SMauro Carvalho Chehab lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
1229a0bf528SMauro Carvalho Chehab {
1239a0bf528SMauro Carvalho Chehab int ret;
1249a0bf528SMauro Carvalho Chehab u8 b0[] = {reg};
1259a0bf528SMauro Carvalho Chehab u8 b1[] = {0};
1269a0bf528SMauro Carvalho Chehab u8 b2[] = {reg, data};
1279a0bf528SMauro Carvalho Chehab struct i2c_msg msg[3] = {
1289a0bf528SMauro Carvalho Chehab {
1299a0bf528SMauro Carvalho Chehab .addr = state->config->demod_address + 2,
1309a0bf528SMauro Carvalho Chehab .flags = 0,
1319a0bf528SMauro Carvalho Chehab .buf = b0,
1329a0bf528SMauro Carvalho Chehab .len = 1
1339a0bf528SMauro Carvalho Chehab },
1349a0bf528SMauro Carvalho Chehab {
1359a0bf528SMauro Carvalho Chehab .addr = state->config->demod_address + 2,
1369a0bf528SMauro Carvalho Chehab .flags = I2C_M_RD,
1379a0bf528SMauro Carvalho Chehab .buf = b1,
1389a0bf528SMauro Carvalho Chehab .len = 1
1399a0bf528SMauro Carvalho Chehab },
1409a0bf528SMauro Carvalho Chehab {
1419a0bf528SMauro Carvalho Chehab .addr = state->config->demod_address + 2,
1429a0bf528SMauro Carvalho Chehab .flags = 0,
1439a0bf528SMauro Carvalho Chehab .buf = b2,
1449a0bf528SMauro Carvalho Chehab .len = 2
1459a0bf528SMauro Carvalho Chehab },
1469a0bf528SMauro Carvalho Chehab };
1479a0bf528SMauro Carvalho Chehab
1489a0bf528SMauro Carvalho Chehab ret = i2c_transfer(state->i2c, msg, 3);
1499a0bf528SMauro Carvalho Chehab return (ret != 3) ? -1 : 0;
1509a0bf528SMauro Carvalho Chehab }
1519a0bf528SMauro Carvalho Chehab
1529a0bf528SMauro Carvalho Chehab
1539a0bf528SMauro Carvalho Chehab static void
lgs8gl5_soft_reset(struct lgs8gl5_state * state)1549a0bf528SMauro Carvalho Chehab lgs8gl5_soft_reset(struct lgs8gl5_state *state)
1559a0bf528SMauro Carvalho Chehab {
1569a0bf528SMauro Carvalho Chehab u8 val;
1579a0bf528SMauro Carvalho Chehab
1589a0bf528SMauro Carvalho Chehab dprintk("%s\n", __func__);
1599a0bf528SMauro Carvalho Chehab
1609a0bf528SMauro Carvalho Chehab val = lgs8gl5_read_reg(state, REG_RESET);
1619a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF);
1629a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF);
1639a0bf528SMauro Carvalho Chehab msleep(5);
1649a0bf528SMauro Carvalho Chehab }
1659a0bf528SMauro Carvalho Chehab
1669a0bf528SMauro Carvalho Chehab
1679a0bf528SMauro Carvalho Chehab /* Starts demodulation */
1689a0bf528SMauro Carvalho Chehab static void
lgs8gl5_start_demod(struct lgs8gl5_state * state)1699a0bf528SMauro Carvalho Chehab lgs8gl5_start_demod(struct lgs8gl5_state *state)
1709a0bf528SMauro Carvalho Chehab {
1719a0bf528SMauro Carvalho Chehab u8 val;
1729a0bf528SMauro Carvalho Chehab int n;
1739a0bf528SMauro Carvalho Chehab
1749a0bf528SMauro Carvalho Chehab dprintk("%s\n", __func__);
1759a0bf528SMauro Carvalho Chehab
1769a0bf528SMauro Carvalho Chehab lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
1779a0bf528SMauro Carvalho Chehab lgs8gl5_soft_reset(state);
1789a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_07, 0x10);
1799a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_07, 0x10);
1809a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_09, 0x0e);
1819a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_0A, 0xe5);
1829a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_0B, 0x35);
1839a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_0C, 0x30);
1849a0bf528SMauro Carvalho Chehab
1859a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_03, 0x00);
1869a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_7E, 0x01);
1879a0bf528SMauro Carvalho Chehab lgs8gl5_update_alt_reg(state, 0xc5, 0x00);
1889a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_04, 0x02);
1899a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_37, 0x01);
1909a0bf528SMauro Carvalho Chehab lgs8gl5_soft_reset(state);
1919a0bf528SMauro Carvalho Chehab
1929a0bf528SMauro Carvalho Chehab /* Wait for carrier */
1939a0bf528SMauro Carvalho Chehab for (n = 0; n < 10; n++) {
1949a0bf528SMauro Carvalho Chehab val = lgs8gl5_read_reg(state, REG_STRENGTH);
1959a0bf528SMauro Carvalho Chehab dprintk("Wait for carrier[%d] 0x%02X\n", n, val);
1969a0bf528SMauro Carvalho Chehab if (val & REG_STRENGTH_CARRIER)
1979a0bf528SMauro Carvalho Chehab break;
1989a0bf528SMauro Carvalho Chehab msleep(4);
1999a0bf528SMauro Carvalho Chehab }
2009a0bf528SMauro Carvalho Chehab if (!(val & REG_STRENGTH_CARRIER))
2019a0bf528SMauro Carvalho Chehab return;
2029a0bf528SMauro Carvalho Chehab
2039a0bf528SMauro Carvalho Chehab /* Wait for lock */
2049a0bf528SMauro Carvalho Chehab for (n = 0; n < 20; n++) {
2059a0bf528SMauro Carvalho Chehab val = lgs8gl5_read_reg(state, REG_STATUS);
2069a0bf528SMauro Carvalho Chehab dprintk("Wait for lock[%d] 0x%02X\n", n, val);
2079a0bf528SMauro Carvalho Chehab if (val & REG_STATUS_LOCK)
2089a0bf528SMauro Carvalho Chehab break;
2099a0bf528SMauro Carvalho Chehab msleep(12);
2109a0bf528SMauro Carvalho Chehab }
2119a0bf528SMauro Carvalho Chehab if (!(val & REG_STATUS_LOCK))
2129a0bf528SMauro Carvalho Chehab return;
2139a0bf528SMauro Carvalho Chehab
2149a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2));
2159a0bf528SMauro Carvalho Chehab lgs8gl5_soft_reset(state);
2169a0bf528SMauro Carvalho Chehab }
2179a0bf528SMauro Carvalho Chehab
2189a0bf528SMauro Carvalho Chehab
2199a0bf528SMauro Carvalho Chehab static int
lgs8gl5_init(struct dvb_frontend * fe)2209a0bf528SMauro Carvalho Chehab lgs8gl5_init(struct dvb_frontend *fe)
2219a0bf528SMauro Carvalho Chehab {
2229a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = fe->demodulator_priv;
2239a0bf528SMauro Carvalho Chehab
2249a0bf528SMauro Carvalho Chehab dprintk("%s\n", __func__);
2259a0bf528SMauro Carvalho Chehab
2269a0bf528SMauro Carvalho Chehab lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
2279a0bf528SMauro Carvalho Chehab lgs8gl5_soft_reset(state);
2289a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_07, 0x10);
2299a0bf528SMauro Carvalho Chehab lgs8gl5_update_reg(state, REG_07, 0x10);
2309a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_09, 0x0e);
2319a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_0A, 0xe5);
2329a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_0B, 0x35);
2339a0bf528SMauro Carvalho Chehab lgs8gl5_write_reg(state, REG_0C, 0x30);
2349a0bf528SMauro Carvalho Chehab
2359a0bf528SMauro Carvalho Chehab return 0;
2369a0bf528SMauro Carvalho Chehab }
2379a0bf528SMauro Carvalho Chehab
2389a0bf528SMauro Carvalho Chehab
2399a0bf528SMauro Carvalho Chehab static int
lgs8gl5_read_status(struct dvb_frontend * fe,enum fe_status * status)2400df289a2SMauro Carvalho Chehab lgs8gl5_read_status(struct dvb_frontend *fe, enum fe_status *status)
2419a0bf528SMauro Carvalho Chehab {
2429a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = fe->demodulator_priv;
2439a0bf528SMauro Carvalho Chehab u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
2449a0bf528SMauro Carvalho Chehab u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
2459a0bf528SMauro Carvalho Chehab
2469a0bf528SMauro Carvalho Chehab *status = 0;
2479a0bf528SMauro Carvalho Chehab
2489a0bf528SMauro Carvalho Chehab if ((level & REG_STRENGTH_MASK) > 0)
2499a0bf528SMauro Carvalho Chehab *status |= FE_HAS_SIGNAL;
2509a0bf528SMauro Carvalho Chehab if (level & REG_STRENGTH_CARRIER)
2519a0bf528SMauro Carvalho Chehab *status |= FE_HAS_CARRIER;
2529a0bf528SMauro Carvalho Chehab if (flags & REG_STATUS_SYNC)
2539a0bf528SMauro Carvalho Chehab *status |= FE_HAS_SYNC;
2549a0bf528SMauro Carvalho Chehab if (flags & REG_STATUS_LOCK)
2559a0bf528SMauro Carvalho Chehab *status |= FE_HAS_LOCK;
2569a0bf528SMauro Carvalho Chehab
2579a0bf528SMauro Carvalho Chehab return 0;
2589a0bf528SMauro Carvalho Chehab }
2599a0bf528SMauro Carvalho Chehab
2609a0bf528SMauro Carvalho Chehab
2619a0bf528SMauro Carvalho Chehab static int
lgs8gl5_read_ber(struct dvb_frontend * fe,u32 * ber)2629a0bf528SMauro Carvalho Chehab lgs8gl5_read_ber(struct dvb_frontend *fe, u32 *ber)
2639a0bf528SMauro Carvalho Chehab {
2649a0bf528SMauro Carvalho Chehab *ber = 0;
2659a0bf528SMauro Carvalho Chehab
2669a0bf528SMauro Carvalho Chehab return 0;
2679a0bf528SMauro Carvalho Chehab }
2689a0bf528SMauro Carvalho Chehab
2699a0bf528SMauro Carvalho Chehab
2709a0bf528SMauro Carvalho Chehab static int
lgs8gl5_read_signal_strength(struct dvb_frontend * fe,u16 * signal_strength)2719a0bf528SMauro Carvalho Chehab lgs8gl5_read_signal_strength(struct dvb_frontend *fe, u16 *signal_strength)
2729a0bf528SMauro Carvalho Chehab {
2739a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = fe->demodulator_priv;
2749a0bf528SMauro Carvalho Chehab u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
2759a0bf528SMauro Carvalho Chehab *signal_strength = (level & REG_STRENGTH_MASK) << 8;
2769a0bf528SMauro Carvalho Chehab
2779a0bf528SMauro Carvalho Chehab return 0;
2789a0bf528SMauro Carvalho Chehab }
2799a0bf528SMauro Carvalho Chehab
2809a0bf528SMauro Carvalho Chehab
2819a0bf528SMauro Carvalho Chehab static int
lgs8gl5_read_snr(struct dvb_frontend * fe,u16 * snr)2829a0bf528SMauro Carvalho Chehab lgs8gl5_read_snr(struct dvb_frontend *fe, u16 *snr)
2839a0bf528SMauro Carvalho Chehab {
2849a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = fe->demodulator_priv;
2859a0bf528SMauro Carvalho Chehab u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
2869a0bf528SMauro Carvalho Chehab *snr = (level & REG_STRENGTH_MASK) << 8;
2879a0bf528SMauro Carvalho Chehab
2889a0bf528SMauro Carvalho Chehab return 0;
2899a0bf528SMauro Carvalho Chehab }
2909a0bf528SMauro Carvalho Chehab
2919a0bf528SMauro Carvalho Chehab
2929a0bf528SMauro Carvalho Chehab static int
lgs8gl5_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)2939a0bf528SMauro Carvalho Chehab lgs8gl5_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
2949a0bf528SMauro Carvalho Chehab {
2959a0bf528SMauro Carvalho Chehab *ucblocks = 0;
2969a0bf528SMauro Carvalho Chehab
2979a0bf528SMauro Carvalho Chehab return 0;
2989a0bf528SMauro Carvalho Chehab }
2999a0bf528SMauro Carvalho Chehab
3009a0bf528SMauro Carvalho Chehab
3019a0bf528SMauro Carvalho Chehab static int
lgs8gl5_set_frontend(struct dvb_frontend * fe)3029a0bf528SMauro Carvalho Chehab lgs8gl5_set_frontend(struct dvb_frontend *fe)
3039a0bf528SMauro Carvalho Chehab {
3049a0bf528SMauro Carvalho Chehab struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3059a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = fe->demodulator_priv;
3069a0bf528SMauro Carvalho Chehab
3079a0bf528SMauro Carvalho Chehab dprintk("%s\n", __func__);
3089a0bf528SMauro Carvalho Chehab
3099a0bf528SMauro Carvalho Chehab if (p->bandwidth_hz != 8000000)
3109a0bf528SMauro Carvalho Chehab return -EINVAL;
3119a0bf528SMauro Carvalho Chehab
3129a0bf528SMauro Carvalho Chehab if (fe->ops.tuner_ops.set_params) {
3139a0bf528SMauro Carvalho Chehab fe->ops.tuner_ops.set_params(fe);
3149a0bf528SMauro Carvalho Chehab if (fe->ops.i2c_gate_ctrl)
3159a0bf528SMauro Carvalho Chehab fe->ops.i2c_gate_ctrl(fe, 0);
3169a0bf528SMauro Carvalho Chehab }
3179a0bf528SMauro Carvalho Chehab
3189a0bf528SMauro Carvalho Chehab /* lgs8gl5_set_inversion(state, p->inversion); */
3199a0bf528SMauro Carvalho Chehab
3209a0bf528SMauro Carvalho Chehab lgs8gl5_start_demod(state);
3219a0bf528SMauro Carvalho Chehab
3229a0bf528SMauro Carvalho Chehab return 0;
3239a0bf528SMauro Carvalho Chehab }
3249a0bf528SMauro Carvalho Chehab
3259a0bf528SMauro Carvalho Chehab
3269a0bf528SMauro Carvalho Chehab static int
lgs8gl5_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)3277e3e68bcSMauro Carvalho Chehab lgs8gl5_get_frontend(struct dvb_frontend *fe,
3287e3e68bcSMauro Carvalho Chehab struct dtv_frontend_properties *p)
3299a0bf528SMauro Carvalho Chehab {
3309a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = fe->demodulator_priv;
3317e3e68bcSMauro Carvalho Chehab
3329a0bf528SMauro Carvalho Chehab u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
3339a0bf528SMauro Carvalho Chehab
3349a0bf528SMauro Carvalho Chehab p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF;
3359a0bf528SMauro Carvalho Chehab
3369a0bf528SMauro Carvalho Chehab p->code_rate_HP = FEC_1_2;
3379a0bf528SMauro Carvalho Chehab p->code_rate_LP = FEC_7_8;
3389a0bf528SMauro Carvalho Chehab p->guard_interval = GUARD_INTERVAL_1_32;
3399a0bf528SMauro Carvalho Chehab p->transmission_mode = TRANSMISSION_MODE_2K;
3409a0bf528SMauro Carvalho Chehab p->modulation = QAM_64;
3419a0bf528SMauro Carvalho Chehab p->hierarchy = HIERARCHY_NONE;
3429a0bf528SMauro Carvalho Chehab p->bandwidth_hz = 8000000;
3439a0bf528SMauro Carvalho Chehab
3449a0bf528SMauro Carvalho Chehab return 0;
3459a0bf528SMauro Carvalho Chehab }
3469a0bf528SMauro Carvalho Chehab
3479a0bf528SMauro Carvalho Chehab
3489a0bf528SMauro Carvalho Chehab static int
lgs8gl5_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fesettings)3499a0bf528SMauro Carvalho Chehab lgs8gl5_get_tune_settings(struct dvb_frontend *fe,
3509a0bf528SMauro Carvalho Chehab struct dvb_frontend_tune_settings *fesettings)
3519a0bf528SMauro Carvalho Chehab {
3529a0bf528SMauro Carvalho Chehab fesettings->min_delay_ms = 240;
3539a0bf528SMauro Carvalho Chehab fesettings->step_size = 0;
3549a0bf528SMauro Carvalho Chehab fesettings->max_drift = 0;
3559a0bf528SMauro Carvalho Chehab return 0;
3569a0bf528SMauro Carvalho Chehab }
3579a0bf528SMauro Carvalho Chehab
3589a0bf528SMauro Carvalho Chehab
3599a0bf528SMauro Carvalho Chehab static void
lgs8gl5_release(struct dvb_frontend * fe)3609a0bf528SMauro Carvalho Chehab lgs8gl5_release(struct dvb_frontend *fe)
3619a0bf528SMauro Carvalho Chehab {
3629a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = fe->demodulator_priv;
3639a0bf528SMauro Carvalho Chehab kfree(state);
3649a0bf528SMauro Carvalho Chehab }
3659a0bf528SMauro Carvalho Chehab
3669a0bf528SMauro Carvalho Chehab
367bd336e63SMax Kellermann static const struct dvb_frontend_ops lgs8gl5_ops;
3689a0bf528SMauro Carvalho Chehab
3699a0bf528SMauro Carvalho Chehab
3709a0bf528SMauro Carvalho Chehab struct dvb_frontend*
lgs8gl5_attach(const struct lgs8gl5_config * config,struct i2c_adapter * i2c)3719a0bf528SMauro Carvalho Chehab lgs8gl5_attach(const struct lgs8gl5_config *config, struct i2c_adapter *i2c)
3729a0bf528SMauro Carvalho Chehab {
3739a0bf528SMauro Carvalho Chehab struct lgs8gl5_state *state = NULL;
3749a0bf528SMauro Carvalho Chehab
3759a0bf528SMauro Carvalho Chehab dprintk("%s\n", __func__);
3769a0bf528SMauro Carvalho Chehab
3779a0bf528SMauro Carvalho Chehab /* Allocate memory for the internal state */
3789a0bf528SMauro Carvalho Chehab state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL);
3799a0bf528SMauro Carvalho Chehab if (state == NULL)
3809a0bf528SMauro Carvalho Chehab goto error;
3819a0bf528SMauro Carvalho Chehab
3829a0bf528SMauro Carvalho Chehab /* Setup the state */
3839a0bf528SMauro Carvalho Chehab state->config = config;
3849a0bf528SMauro Carvalho Chehab state->i2c = i2c;
3859a0bf528SMauro Carvalho Chehab
3869a0bf528SMauro Carvalho Chehab /* Check if the demod is there */
3879a0bf528SMauro Carvalho Chehab if (lgs8gl5_read_reg(state, REG_RESET) < 0)
3889a0bf528SMauro Carvalho Chehab goto error;
3899a0bf528SMauro Carvalho Chehab
3909a0bf528SMauro Carvalho Chehab /* Create dvb_frontend */
3919a0bf528SMauro Carvalho Chehab memcpy(&state->frontend.ops, &lgs8gl5_ops,
3929a0bf528SMauro Carvalho Chehab sizeof(struct dvb_frontend_ops));
3939a0bf528SMauro Carvalho Chehab state->frontend.demodulator_priv = state;
3949a0bf528SMauro Carvalho Chehab return &state->frontend;
3959a0bf528SMauro Carvalho Chehab
3969a0bf528SMauro Carvalho Chehab error:
3979a0bf528SMauro Carvalho Chehab kfree(state);
3989a0bf528SMauro Carvalho Chehab return NULL;
3999a0bf528SMauro Carvalho Chehab }
4009a0bf528SMauro Carvalho Chehab EXPORT_SYMBOL(lgs8gl5_attach);
4019a0bf528SMauro Carvalho Chehab
4029a0bf528SMauro Carvalho Chehab
403bd336e63SMax Kellermann static const struct dvb_frontend_ops lgs8gl5_ops = {
4049a0bf528SMauro Carvalho Chehab .delsys = { SYS_DTMB },
4059a0bf528SMauro Carvalho Chehab .info = {
4069a0bf528SMauro Carvalho Chehab .name = "Legend Silicon LGS-8GL5 DMB-TH",
407f1b1eabfSMauro Carvalho Chehab .frequency_min_hz = 474 * MHz,
408f1b1eabfSMauro Carvalho Chehab .frequency_max_hz = 858 * MHz,
409f1b1eabfSMauro Carvalho Chehab .frequency_stepsize_hz = 10 * kHz,
4109a0bf528SMauro Carvalho Chehab .caps = FE_CAN_FEC_AUTO |
4119a0bf528SMauro Carvalho Chehab FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
4129a0bf528SMauro Carvalho Chehab FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
4139a0bf528SMauro Carvalho Chehab FE_CAN_TRANSMISSION_MODE_AUTO |
4149a0bf528SMauro Carvalho Chehab FE_CAN_BANDWIDTH_AUTO |
4159a0bf528SMauro Carvalho Chehab FE_CAN_GUARD_INTERVAL_AUTO |
4169a0bf528SMauro Carvalho Chehab FE_CAN_HIERARCHY_AUTO |
4179a0bf528SMauro Carvalho Chehab FE_CAN_RECOVER
4189a0bf528SMauro Carvalho Chehab },
4199a0bf528SMauro Carvalho Chehab
4209a0bf528SMauro Carvalho Chehab .release = lgs8gl5_release,
4219a0bf528SMauro Carvalho Chehab
4229a0bf528SMauro Carvalho Chehab .init = lgs8gl5_init,
4239a0bf528SMauro Carvalho Chehab
4249a0bf528SMauro Carvalho Chehab .set_frontend = lgs8gl5_set_frontend,
4259a0bf528SMauro Carvalho Chehab .get_frontend = lgs8gl5_get_frontend,
4269a0bf528SMauro Carvalho Chehab .get_tune_settings = lgs8gl5_get_tune_settings,
4279a0bf528SMauro Carvalho Chehab
4289a0bf528SMauro Carvalho Chehab .read_status = lgs8gl5_read_status,
4299a0bf528SMauro Carvalho Chehab .read_ber = lgs8gl5_read_ber,
4309a0bf528SMauro Carvalho Chehab .read_signal_strength = lgs8gl5_read_signal_strength,
4319a0bf528SMauro Carvalho Chehab .read_snr = lgs8gl5_read_snr,
4329a0bf528SMauro Carvalho Chehab .read_ucblocks = lgs8gl5_read_ucblocks,
4339a0bf528SMauro Carvalho Chehab };
4349a0bf528SMauro Carvalho Chehab
4359a0bf528SMauro Carvalho Chehab
4369a0bf528SMauro Carvalho Chehab module_param(debug, int, 0644);
4379a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
4389a0bf528SMauro Carvalho Chehab
4399a0bf528SMauro Carvalho Chehab MODULE_DESCRIPTION("Legend Silicon LGS-8GL5 DMB-TH Demodulator driver");
4409a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Timothy Lee");
4419a0bf528SMauro Carvalho Chehab MODULE_LICENSE("GPL");
442