1 /* 2 * Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM 3 * 4 * Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org> 5 * 6 * LGDT3304 support by Jarod Wilson <jarod@redhat.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #include <asm/div64.h> 21 #include <linux/dvb/frontend.h> 22 #include <linux/slab.h> 23 #include "dvb_math.h" 24 #include "lgdt3305.h" 25 26 static int debug; 27 module_param(debug, int, 0644); 28 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))"); 29 30 #define DBG_INFO 1 31 #define DBG_REG 2 32 33 #define lg_printk(kern, fmt, arg...) \ 34 printk(kern "%s: " fmt, __func__, ##arg) 35 36 #define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg) 37 #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg) 38 #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg) 39 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \ 40 lg_printk(KERN_DEBUG, fmt, ##arg) 41 #define lg_reg(fmt, arg...) if (debug & DBG_REG) \ 42 lg_printk(KERN_DEBUG, fmt, ##arg) 43 44 #define lg_fail(ret) \ 45 ({ \ 46 int __ret; \ 47 __ret = (ret < 0); \ 48 if (__ret) \ 49 lg_err("error %d on line %d\n", ret, __LINE__); \ 50 __ret; \ 51 }) 52 53 struct lgdt3305_state { 54 struct i2c_adapter *i2c_adap; 55 const struct lgdt3305_config *cfg; 56 57 struct dvb_frontend frontend; 58 59 enum fe_modulation current_modulation; 60 u32 current_frequency; 61 u32 snr; 62 }; 63 64 /* ------------------------------------------------------------------------ */ 65 66 /* FIXME: verify & document the LGDT3304 registers */ 67 68 #define LGDT3305_GEN_CTRL_1 0x0000 69 #define LGDT3305_GEN_CTRL_2 0x0001 70 #define LGDT3305_GEN_CTRL_3 0x0002 71 #define LGDT3305_GEN_STATUS 0x0003 72 #define LGDT3305_GEN_CONTROL 0x0007 73 #define LGDT3305_GEN_CTRL_4 0x000a 74 #define LGDT3305_DGTL_AGC_REF_1 0x0012 75 #define LGDT3305_DGTL_AGC_REF_2 0x0013 76 #define LGDT3305_CR_CTR_FREQ_1 0x0106 77 #define LGDT3305_CR_CTR_FREQ_2 0x0107 78 #define LGDT3305_CR_CTR_FREQ_3 0x0108 79 #define LGDT3305_CR_CTR_FREQ_4 0x0109 80 #define LGDT3305_CR_MSE_1 0x011b 81 #define LGDT3305_CR_MSE_2 0x011c 82 #define LGDT3305_CR_LOCK_STATUS 0x011d 83 #define LGDT3305_CR_CTRL_7 0x0126 84 #define LGDT3305_AGC_POWER_REF_1 0x0300 85 #define LGDT3305_AGC_POWER_REF_2 0x0301 86 #define LGDT3305_AGC_DELAY_PT_1 0x0302 87 #define LGDT3305_AGC_DELAY_PT_2 0x0303 88 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306 89 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307 90 #define LGDT3305_IFBW_1 0x0308 91 #define LGDT3305_IFBW_2 0x0309 92 #define LGDT3305_AGC_CTRL_1 0x030c 93 #define LGDT3305_AGC_CTRL_4 0x0314 94 #define LGDT3305_EQ_MSE_1 0x0413 95 #define LGDT3305_EQ_MSE_2 0x0414 96 #define LGDT3305_EQ_MSE_3 0x0415 97 #define LGDT3305_PT_MSE_1 0x0417 98 #define LGDT3305_PT_MSE_2 0x0418 99 #define LGDT3305_PT_MSE_3 0x0419 100 #define LGDT3305_FEC_BLOCK_CTRL 0x0504 101 #define LGDT3305_FEC_LOCK_STATUS 0x050a 102 #define LGDT3305_FEC_PKT_ERR_1 0x050c 103 #define LGDT3305_FEC_PKT_ERR_2 0x050d 104 #define LGDT3305_TP_CTRL_1 0x050e 105 #define LGDT3305_BERT_PERIOD 0x0801 106 #define LGDT3305_BERT_ERROR_COUNT_1 0x080a 107 #define LGDT3305_BERT_ERROR_COUNT_2 0x080b 108 #define LGDT3305_BERT_ERROR_COUNT_3 0x080c 109 #define LGDT3305_BERT_ERROR_COUNT_4 0x080d 110 111 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val) 112 { 113 int ret; 114 u8 buf[] = { reg >> 8, reg & 0xff, val }; 115 struct i2c_msg msg = { 116 .addr = state->cfg->i2c_addr, .flags = 0, 117 .buf = buf, .len = 3, 118 }; 119 120 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); 121 122 ret = i2c_transfer(state->i2c_adap, &msg, 1); 123 124 if (ret != 1) { 125 lg_err("error (addr %02x %02x <- %02x, err = %i)\n", 126 msg.buf[0], msg.buf[1], msg.buf[2], ret); 127 if (ret < 0) 128 return ret; 129 else 130 return -EREMOTEIO; 131 } 132 return 0; 133 } 134 135 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val) 136 { 137 int ret; 138 u8 reg_buf[] = { reg >> 8, reg & 0xff }; 139 struct i2c_msg msg[] = { 140 { .addr = state->cfg->i2c_addr, 141 .flags = 0, .buf = reg_buf, .len = 2 }, 142 { .addr = state->cfg->i2c_addr, 143 .flags = I2C_M_RD, .buf = val, .len = 1 }, 144 }; 145 146 lg_reg("reg: 0x%04x\n", reg); 147 148 ret = i2c_transfer(state->i2c_adap, msg, 2); 149 150 if (ret != 2) { 151 lg_err("error (addr %02x reg %04x error (ret == %i)\n", 152 state->cfg->i2c_addr, reg, ret); 153 if (ret < 0) 154 return ret; 155 else 156 return -EREMOTEIO; 157 } 158 return 0; 159 } 160 161 #define read_reg(state, reg) \ 162 ({ \ 163 u8 __val; \ 164 int ret = lgdt3305_read_reg(state, reg, &__val); \ 165 if (lg_fail(ret)) \ 166 __val = 0; \ 167 __val; \ 168 }) 169 170 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state, 171 u16 reg, int bit, int onoff) 172 { 173 u8 val; 174 int ret; 175 176 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); 177 178 ret = lgdt3305_read_reg(state, reg, &val); 179 if (lg_fail(ret)) 180 goto fail; 181 182 val &= ~(1 << bit); 183 val |= (onoff & 1) << bit; 184 185 ret = lgdt3305_write_reg(state, reg, val); 186 fail: 187 return ret; 188 } 189 190 struct lgdt3305_reg { 191 u16 reg; 192 u8 val; 193 }; 194 195 static int lgdt3305_write_regs(struct lgdt3305_state *state, 196 struct lgdt3305_reg *regs, int len) 197 { 198 int i, ret; 199 200 lg_reg("writing %d registers...\n", len); 201 202 for (i = 0; i < len - 1; i++) { 203 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val); 204 if (lg_fail(ret)) 205 return ret; 206 } 207 return 0; 208 } 209 210 /* ------------------------------------------------------------------------ */ 211 212 static int lgdt3305_soft_reset(struct lgdt3305_state *state) 213 { 214 int ret; 215 216 lg_dbg("\n"); 217 218 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0); 219 if (lg_fail(ret)) 220 goto fail; 221 222 msleep(20); 223 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1); 224 fail: 225 return ret; 226 } 227 228 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state, 229 enum lgdt3305_mpeg_mode mode) 230 { 231 lg_dbg("(%d)\n", mode); 232 return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode); 233 } 234 235 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state) 236 { 237 u8 val; 238 int ret; 239 enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge; 240 enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode; 241 enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity; 242 243 lg_dbg("edge = %d, valid = %d\n", edge, valid); 244 245 ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val); 246 if (lg_fail(ret)) 247 goto fail; 248 249 val &= ~0x09; 250 251 if (edge) 252 val |= 0x08; 253 if (mode) 254 val |= 0x40; 255 if (valid) 256 val |= 0x01; 257 258 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val); 259 if (lg_fail(ret)) 260 goto fail; 261 262 ret = lgdt3305_soft_reset(state); 263 fail: 264 return ret; 265 } 266 267 static int lgdt3305_set_modulation(struct lgdt3305_state *state, 268 struct dtv_frontend_properties *p) 269 { 270 u8 opermode; 271 int ret; 272 273 lg_dbg("\n"); 274 275 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode); 276 if (lg_fail(ret)) 277 goto fail; 278 279 opermode &= ~0x03; 280 281 switch (p->modulation) { 282 case VSB_8: 283 opermode |= 0x03; 284 break; 285 case QAM_64: 286 opermode |= 0x00; 287 break; 288 case QAM_256: 289 opermode |= 0x01; 290 break; 291 default: 292 return -EINVAL; 293 } 294 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode); 295 fail: 296 return ret; 297 } 298 299 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state, 300 struct dtv_frontend_properties *p) 301 { 302 int val; 303 304 switch (p->modulation) { 305 case VSB_8: 306 val = 0; 307 break; 308 case QAM_64: 309 case QAM_256: 310 val = 1; 311 break; 312 default: 313 return -EINVAL; 314 } 315 lg_dbg("val = %d\n", val); 316 317 return lgdt3305_set_reg_bit(state, 0x043f, 2, val); 318 } 319 320 /* ------------------------------------------------------------------------ */ 321 322 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state, 323 struct dtv_frontend_properties *p) 324 { 325 u16 agc_ref; 326 327 switch (p->modulation) { 328 case VSB_8: 329 agc_ref = 0x32c4; 330 break; 331 case QAM_64: 332 agc_ref = 0x2a00; 333 break; 334 case QAM_256: 335 agc_ref = 0x2a80; 336 break; 337 default: 338 return -EINVAL; 339 } 340 341 lg_dbg("agc ref: 0x%04x\n", agc_ref); 342 343 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8); 344 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff); 345 346 return 0; 347 } 348 349 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state, 350 struct dtv_frontend_properties *p) 351 { 352 u16 ifbw, rfbw, agcdelay; 353 354 switch (p->modulation) { 355 case VSB_8: 356 agcdelay = 0x04c0; 357 rfbw = 0x8000; 358 ifbw = 0x8000; 359 break; 360 case QAM_64: 361 case QAM_256: 362 agcdelay = 0x046b; 363 rfbw = 0x8889; 364 /* FIXME: investigate optimal ifbw & rfbw values for the 365 * DT3304 and re-write this switch..case block */ 366 if (state->cfg->demod_chip == LGDT3304) 367 ifbw = 0x6666; 368 else /* (state->cfg->demod_chip == LGDT3305) */ 369 ifbw = 0x8888; 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 if (state->cfg->rf_agc_loop) { 376 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw); 377 378 /* rf agc loop filter bandwidth */ 379 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1, 380 agcdelay >> 8); 381 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2, 382 agcdelay & 0xff); 383 384 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1, 385 rfbw >> 8); 386 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2, 387 rfbw & 0xff); 388 } else { 389 lg_dbg("ifbw: 0x%04x\n", ifbw); 390 391 /* if agc loop filter bandwidth */ 392 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8); 393 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff); 394 } 395 396 return 0; 397 } 398 399 static int lgdt3305_agc_setup(struct lgdt3305_state *state, 400 struct dtv_frontend_properties *p) 401 { 402 int lockdten, acqen; 403 404 switch (p->modulation) { 405 case VSB_8: 406 lockdten = 0; 407 acqen = 0; 408 break; 409 case QAM_64: 410 case QAM_256: 411 lockdten = 1; 412 acqen = 1; 413 break; 414 default: 415 return -EINVAL; 416 } 417 418 lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen); 419 420 /* control agc function */ 421 switch (state->cfg->demod_chip) { 422 case LGDT3304: 423 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1); 424 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen); 425 break; 426 case LGDT3305: 427 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1); 428 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen); 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return lgdt3305_rfagc_loop(state, p); 435 } 436 437 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state, 438 struct dtv_frontend_properties *p) 439 { 440 u16 usref = 0; 441 442 switch (p->modulation) { 443 case VSB_8: 444 if (state->cfg->usref_8vsb) 445 usref = state->cfg->usref_8vsb; 446 break; 447 case QAM_64: 448 if (state->cfg->usref_qam64) 449 usref = state->cfg->usref_qam64; 450 break; 451 case QAM_256: 452 if (state->cfg->usref_qam256) 453 usref = state->cfg->usref_qam256; 454 break; 455 default: 456 return -EINVAL; 457 } 458 459 if (usref) { 460 lg_dbg("set manual mode: 0x%04x\n", usref); 461 462 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1); 463 464 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1, 465 0xff & (usref >> 8)); 466 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2, 467 0xff & (usref >> 0)); 468 } 469 return 0; 470 } 471 472 /* ------------------------------------------------------------------------ */ 473 474 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state, 475 struct dtv_frontend_properties *p, 476 int inversion) 477 { 478 int ret; 479 480 lg_dbg("(%d)\n", inversion); 481 482 switch (p->modulation) { 483 case VSB_8: 484 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7, 485 inversion ? 0xf9 : 0x79); 486 break; 487 case QAM_64: 488 case QAM_256: 489 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL, 490 inversion ? 0xfd : 0xff); 491 break; 492 default: 493 ret = -EINVAL; 494 } 495 return ret; 496 } 497 498 static int lgdt3305_set_if(struct lgdt3305_state *state, 499 struct dtv_frontend_properties *p) 500 { 501 u16 if_freq_khz; 502 u8 nco1, nco2, nco3, nco4; 503 u64 nco; 504 505 switch (p->modulation) { 506 case VSB_8: 507 if_freq_khz = state->cfg->vsb_if_khz; 508 break; 509 case QAM_64: 510 case QAM_256: 511 if_freq_khz = state->cfg->qam_if_khz; 512 break; 513 default: 514 return -EINVAL; 515 } 516 517 nco = if_freq_khz / 10; 518 519 switch (p->modulation) { 520 case VSB_8: 521 nco <<= 24; 522 do_div(nco, 625); 523 break; 524 case QAM_64: 525 case QAM_256: 526 nco <<= 28; 527 do_div(nco, 625); 528 break; 529 default: 530 return -EINVAL; 531 } 532 533 nco1 = (nco >> 24) & 0x3f; 534 nco1 |= 0x40; 535 nco2 = (nco >> 16) & 0xff; 536 nco3 = (nco >> 8) & 0xff; 537 nco4 = nco & 0xff; 538 539 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1); 540 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2); 541 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3); 542 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4); 543 544 lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n", 545 if_freq_khz, nco1, nco2, nco3, nco4); 546 547 return 0; 548 } 549 550 /* ------------------------------------------------------------------------ */ 551 552 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 553 { 554 struct lgdt3305_state *state = fe->demodulator_priv; 555 556 if (state->cfg->deny_i2c_rptr) 557 return 0; 558 559 lg_dbg("(%d)\n", enable); 560 561 return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5, 562 enable ? 0 : 1); 563 } 564 565 static int lgdt3305_sleep(struct dvb_frontend *fe) 566 { 567 struct lgdt3305_state *state = fe->demodulator_priv; 568 u8 gen_ctrl_3, gen_ctrl_4; 569 570 lg_dbg("\n"); 571 572 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3); 573 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4); 574 575 /* hold in software reset while sleeping */ 576 gen_ctrl_3 &= ~0x01; 577 /* tristate the IF-AGC pin */ 578 gen_ctrl_3 |= 0x02; 579 /* tristate the RF-AGC pin */ 580 gen_ctrl_3 |= 0x04; 581 582 /* disable vsb/qam module */ 583 gen_ctrl_4 &= ~0x01; 584 /* disable adc module */ 585 gen_ctrl_4 &= ~0x02; 586 587 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3); 588 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4); 589 590 return 0; 591 } 592 593 static int lgdt3305_init(struct dvb_frontend *fe) 594 { 595 struct lgdt3305_state *state = fe->demodulator_priv; 596 int ret; 597 598 static struct lgdt3305_reg lgdt3304_init_data[] = { 599 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, 600 { .reg = 0x000d, .val = 0x02, }, 601 { .reg = 0x000e, .val = 0x02, }, 602 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, 603 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, 604 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, 605 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, 606 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, 607 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, 608 { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, }, 609 { .reg = 0x0112, .val = 0x17, }, 610 { .reg = 0x0113, .val = 0x15, }, 611 { .reg = 0x0114, .val = 0x18, }, 612 { .reg = 0x0115, .val = 0xff, }, 613 { .reg = 0x0116, .val = 0x3c, }, 614 { .reg = 0x0214, .val = 0x67, }, 615 { .reg = 0x0424, .val = 0x8d, }, 616 { .reg = 0x0427, .val = 0x12, }, 617 { .reg = 0x0428, .val = 0x4f, }, 618 { .reg = LGDT3305_IFBW_1, .val = 0x80, }, 619 { .reg = LGDT3305_IFBW_2, .val = 0x00, }, 620 { .reg = 0x030a, .val = 0x08, }, 621 { .reg = 0x030b, .val = 0x9b, }, 622 { .reg = 0x030d, .val = 0x00, }, 623 { .reg = 0x030e, .val = 0x1c, }, 624 { .reg = 0x0314, .val = 0xe1, }, 625 { .reg = 0x000d, .val = 0x82, }, 626 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, 627 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, 628 }; 629 630 static struct lgdt3305_reg lgdt3305_init_data[] = { 631 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, 632 { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, }, 633 { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, }, 634 { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, }, 635 { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, }, 636 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, 637 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, 638 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, 639 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, 640 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, 641 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, 642 { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, }, 643 { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, }, 644 { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, }, 645 { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, }, 646 { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, }, 647 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, }, 648 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, }, 649 { .reg = LGDT3305_IFBW_1, .val = 0x80, }, 650 { .reg = LGDT3305_IFBW_2, .val = 0x00, }, 651 { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, }, 652 { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, }, 653 { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, }, 654 { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, }, 655 }; 656 657 lg_dbg("\n"); 658 659 switch (state->cfg->demod_chip) { 660 case LGDT3304: 661 ret = lgdt3305_write_regs(state, lgdt3304_init_data, 662 ARRAY_SIZE(lgdt3304_init_data)); 663 break; 664 case LGDT3305: 665 ret = lgdt3305_write_regs(state, lgdt3305_init_data, 666 ARRAY_SIZE(lgdt3305_init_data)); 667 break; 668 default: 669 ret = -EINVAL; 670 } 671 if (lg_fail(ret)) 672 goto fail; 673 674 ret = lgdt3305_soft_reset(state); 675 fail: 676 return ret; 677 } 678 679 static int lgdt3304_set_parameters(struct dvb_frontend *fe) 680 { 681 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 682 struct lgdt3305_state *state = fe->demodulator_priv; 683 int ret; 684 685 lg_dbg("(%d, %d)\n", p->frequency, p->modulation); 686 687 if (fe->ops.tuner_ops.set_params) { 688 ret = fe->ops.tuner_ops.set_params(fe); 689 if (fe->ops.i2c_gate_ctrl) 690 fe->ops.i2c_gate_ctrl(fe, 0); 691 if (lg_fail(ret)) 692 goto fail; 693 state->current_frequency = p->frequency; 694 } 695 696 ret = lgdt3305_set_modulation(state, p); 697 if (lg_fail(ret)) 698 goto fail; 699 700 ret = lgdt3305_passband_digital_agc(state, p); 701 if (lg_fail(ret)) 702 goto fail; 703 704 ret = lgdt3305_agc_setup(state, p); 705 if (lg_fail(ret)) 706 goto fail; 707 708 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */ 709 switch (p->modulation) { 710 case VSB_8: 711 lgdt3305_write_reg(state, 0x030d, 0x00); 712 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f); 713 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c); 714 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac); 715 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba); 716 break; 717 case QAM_64: 718 case QAM_256: 719 lgdt3305_write_reg(state, 0x030d, 0x14); 720 ret = lgdt3305_set_if(state, p); 721 if (lg_fail(ret)) 722 goto fail; 723 break; 724 default: 725 return -EINVAL; 726 } 727 728 729 ret = lgdt3305_spectral_inversion(state, p, 730 state->cfg->spectral_inversion 731 ? 1 : 0); 732 if (lg_fail(ret)) 733 goto fail; 734 735 state->current_modulation = p->modulation; 736 737 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); 738 if (lg_fail(ret)) 739 goto fail; 740 741 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */ 742 ret = lgdt3305_mpeg_mode_polarity(state); 743 fail: 744 return ret; 745 } 746 747 static int lgdt3305_set_parameters(struct dvb_frontend *fe) 748 { 749 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 750 struct lgdt3305_state *state = fe->demodulator_priv; 751 int ret; 752 753 lg_dbg("(%d, %d)\n", p->frequency, p->modulation); 754 755 if (fe->ops.tuner_ops.set_params) { 756 ret = fe->ops.tuner_ops.set_params(fe); 757 if (fe->ops.i2c_gate_ctrl) 758 fe->ops.i2c_gate_ctrl(fe, 0); 759 if (lg_fail(ret)) 760 goto fail; 761 state->current_frequency = p->frequency; 762 } 763 764 ret = lgdt3305_set_modulation(state, p); 765 if (lg_fail(ret)) 766 goto fail; 767 768 ret = lgdt3305_passband_digital_agc(state, p); 769 if (lg_fail(ret)) 770 goto fail; 771 ret = lgdt3305_set_agc_power_ref(state, p); 772 if (lg_fail(ret)) 773 goto fail; 774 ret = lgdt3305_agc_setup(state, p); 775 if (lg_fail(ret)) 776 goto fail; 777 778 /* low if */ 779 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f); 780 if (lg_fail(ret)) 781 goto fail; 782 ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1); 783 if (lg_fail(ret)) 784 goto fail; 785 786 ret = lgdt3305_set_if(state, p); 787 if (lg_fail(ret)) 788 goto fail; 789 ret = lgdt3305_spectral_inversion(state, p, 790 state->cfg->spectral_inversion 791 ? 1 : 0); 792 if (lg_fail(ret)) 793 goto fail; 794 795 ret = lgdt3305_set_filter_extension(state, p); 796 if (lg_fail(ret)) 797 goto fail; 798 799 state->current_modulation = p->modulation; 800 801 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); 802 if (lg_fail(ret)) 803 goto fail; 804 805 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */ 806 ret = lgdt3305_mpeg_mode_polarity(state); 807 fail: 808 return ret; 809 } 810 811 static int lgdt3305_get_frontend(struct dvb_frontend *fe, 812 struct dtv_frontend_properties *p) 813 { 814 struct lgdt3305_state *state = fe->demodulator_priv; 815 816 lg_dbg("\n"); 817 818 p->modulation = state->current_modulation; 819 p->frequency = state->current_frequency; 820 return 0; 821 } 822 823 /* ------------------------------------------------------------------------ */ 824 825 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state, 826 int *locked) 827 { 828 u8 val; 829 int ret; 830 char *cr_lock_state = ""; 831 832 *locked = 0; 833 834 ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val); 835 if (lg_fail(ret)) 836 goto fail; 837 838 switch (state->current_modulation) { 839 case QAM_256: 840 case QAM_64: 841 if (val & (1 << 1)) 842 *locked = 1; 843 844 switch (val & 0x07) { 845 case 0: 846 cr_lock_state = "QAM UNLOCK"; 847 break; 848 case 4: 849 cr_lock_state = "QAM 1stLock"; 850 break; 851 case 6: 852 cr_lock_state = "QAM 2ndLock"; 853 break; 854 case 7: 855 cr_lock_state = "QAM FinalLock"; 856 break; 857 default: 858 cr_lock_state = "CLOCKQAM-INVALID!"; 859 break; 860 } 861 break; 862 case VSB_8: 863 if (val & (1 << 7)) { 864 *locked = 1; 865 cr_lock_state = "CLOCKVSB"; 866 } 867 break; 868 default: 869 ret = -EINVAL; 870 } 871 lg_dbg("(%d) %s\n", *locked, cr_lock_state); 872 fail: 873 return ret; 874 } 875 876 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state, 877 int *locked) 878 { 879 u8 val; 880 int ret, mpeg_lock, fec_lock, viterbi_lock; 881 882 *locked = 0; 883 884 switch (state->current_modulation) { 885 case QAM_256: 886 case QAM_64: 887 ret = lgdt3305_read_reg(state, 888 LGDT3305_FEC_LOCK_STATUS, &val); 889 if (lg_fail(ret)) 890 goto fail; 891 892 mpeg_lock = (val & (1 << 0)) ? 1 : 0; 893 fec_lock = (val & (1 << 2)) ? 1 : 0; 894 viterbi_lock = (val & (1 << 3)) ? 1 : 0; 895 896 *locked = mpeg_lock && fec_lock && viterbi_lock; 897 898 lg_dbg("(%d) %s%s%s\n", *locked, 899 mpeg_lock ? "mpeg lock " : "", 900 fec_lock ? "fec lock " : "", 901 viterbi_lock ? "viterbi lock" : ""); 902 break; 903 case VSB_8: 904 default: 905 ret = -EINVAL; 906 } 907 fail: 908 return ret; 909 } 910 911 static int lgdt3305_read_status(struct dvb_frontend *fe, enum fe_status *status) 912 { 913 struct lgdt3305_state *state = fe->demodulator_priv; 914 u8 val; 915 int ret, signal, inlock, nofecerr, snrgood, 916 cr_lock, fec_lock, sync_lock; 917 918 *status = 0; 919 920 ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val); 921 if (lg_fail(ret)) 922 goto fail; 923 924 signal = (val & (1 << 4)) ? 1 : 0; 925 inlock = (val & (1 << 3)) ? 0 : 1; 926 sync_lock = (val & (1 << 2)) ? 1 : 0; 927 nofecerr = (val & (1 << 1)) ? 1 : 0; 928 snrgood = (val & (1 << 0)) ? 1 : 0; 929 930 lg_dbg("%s%s%s%s%s\n", 931 signal ? "SIGNALEXIST " : "", 932 inlock ? "INLOCK " : "", 933 sync_lock ? "SYNCLOCK " : "", 934 nofecerr ? "NOFECERR " : "", 935 snrgood ? "SNRGOOD " : ""); 936 937 ret = lgdt3305_read_cr_lock_status(state, &cr_lock); 938 if (lg_fail(ret)) 939 goto fail; 940 941 if (signal) 942 *status |= FE_HAS_SIGNAL; 943 if (cr_lock) 944 *status |= FE_HAS_CARRIER; 945 if (nofecerr) 946 *status |= FE_HAS_VITERBI; 947 if (sync_lock) 948 *status |= FE_HAS_SYNC; 949 950 switch (state->current_modulation) { 951 case QAM_256: 952 case QAM_64: 953 /* signal bit is unreliable on the DT3304 in QAM mode */ 954 if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock)) 955 *status |= FE_HAS_SIGNAL; 956 957 ret = lgdt3305_read_fec_lock_status(state, &fec_lock); 958 if (lg_fail(ret)) 959 goto fail; 960 961 if (fec_lock) 962 *status |= FE_HAS_LOCK; 963 break; 964 case VSB_8: 965 if (inlock) 966 *status |= FE_HAS_LOCK; 967 break; 968 default: 969 ret = -EINVAL; 970 } 971 fail: 972 return ret; 973 } 974 975 /* ------------------------------------------------------------------------ */ 976 977 /* borrowed from lgdt330x.c */ 978 static u32 calculate_snr(u32 mse, u32 c) 979 { 980 if (mse == 0) /* no signal */ 981 return 0; 982 983 mse = intlog10(mse); 984 if (mse > c) { 985 /* Negative SNR, which is possible, but realisticly the 986 demod will lose lock before the signal gets this bad. The 987 API only allows for unsigned values, so just return 0 */ 988 return 0; 989 } 990 return 10*(c - mse); 991 } 992 993 static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr) 994 { 995 struct lgdt3305_state *state = fe->demodulator_priv; 996 u32 noise; /* noise value */ 997 u32 c; /* per-modulation SNR calculation constant */ 998 999 switch (state->current_modulation) { 1000 case VSB_8: 1001 #ifdef USE_PTMSE 1002 /* Use Phase Tracker Mean-Square Error Register */ 1003 /* SNR for ranges from -13.11 to +44.08 */ 1004 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) | 1005 (read_reg(state, LGDT3305_PT_MSE_2) << 8) | 1006 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff); 1007 c = 73957994; /* log10(25*32^2)*2^24 */ 1008 #else 1009 /* Use Equalizer Mean-Square Error Register */ 1010 /* SNR for ranges from -16.12 to +44.08 */ 1011 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) | 1012 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) | 1013 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff); 1014 c = 73957994; /* log10(25*32^2)*2^24 */ 1015 #endif 1016 break; 1017 case QAM_64: 1018 case QAM_256: 1019 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) | 1020 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff); 1021 1022 c = (state->current_modulation == QAM_64) ? 1023 97939837 : 98026066; 1024 /* log10(688128)*2^24 and log10(696320)*2^24 */ 1025 break; 1026 default: 1027 return -EINVAL; 1028 } 1029 state->snr = calculate_snr(noise, c); 1030 /* report SNR in dB * 10 */ 1031 *snr = (state->snr / ((1 << 24) / 10)); 1032 lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise, 1033 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16); 1034 1035 return 0; 1036 } 1037 1038 static int lgdt3305_read_signal_strength(struct dvb_frontend *fe, 1039 u16 *strength) 1040 { 1041 /* borrowed from lgdt330x.c 1042 * 1043 * Calculate strength from SNR up to 35dB 1044 * Even though the SNR can go higher than 35dB, 1045 * there is some comfort factor in having a range of 1046 * strong signals that can show at 100% 1047 */ 1048 struct lgdt3305_state *state = fe->demodulator_priv; 1049 u16 snr; 1050 int ret; 1051 1052 *strength = 0; 1053 1054 ret = fe->ops.read_snr(fe, &snr); 1055 if (lg_fail(ret)) 1056 goto fail; 1057 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ 1058 /* scale the range 0 - 35*2^24 into 0 - 65535 */ 1059 if (state->snr >= 8960 * 0x10000) 1060 *strength = 0xffff; 1061 else 1062 *strength = state->snr / 8960; 1063 fail: 1064 return ret; 1065 } 1066 1067 /* ------------------------------------------------------------------------ */ 1068 1069 static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber) 1070 { 1071 *ber = 0; 1072 return 0; 1073 } 1074 1075 static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1076 { 1077 struct lgdt3305_state *state = fe->demodulator_priv; 1078 1079 *ucblocks = 1080 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) | 1081 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff); 1082 1083 return 0; 1084 } 1085 1086 static int lgdt3305_get_tune_settings(struct dvb_frontend *fe, 1087 struct dvb_frontend_tune_settings 1088 *fe_tune_settings) 1089 { 1090 fe_tune_settings->min_delay_ms = 500; 1091 lg_dbg("\n"); 1092 return 0; 1093 } 1094 1095 static void lgdt3305_release(struct dvb_frontend *fe) 1096 { 1097 struct lgdt3305_state *state = fe->demodulator_priv; 1098 lg_dbg("\n"); 1099 kfree(state); 1100 } 1101 1102 static const struct dvb_frontend_ops lgdt3304_ops; 1103 static const struct dvb_frontend_ops lgdt3305_ops; 1104 1105 struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config, 1106 struct i2c_adapter *i2c_adap) 1107 { 1108 struct lgdt3305_state *state = NULL; 1109 int ret; 1110 u8 val; 1111 1112 lg_dbg("(%d-%04x)\n", 1113 i2c_adap ? i2c_adapter_id(i2c_adap) : 0, 1114 config ? config->i2c_addr : 0); 1115 1116 state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL); 1117 if (state == NULL) 1118 goto fail; 1119 1120 state->cfg = config; 1121 state->i2c_adap = i2c_adap; 1122 1123 switch (config->demod_chip) { 1124 case LGDT3304: 1125 memcpy(&state->frontend.ops, &lgdt3304_ops, 1126 sizeof(struct dvb_frontend_ops)); 1127 break; 1128 case LGDT3305: 1129 memcpy(&state->frontend.ops, &lgdt3305_ops, 1130 sizeof(struct dvb_frontend_ops)); 1131 break; 1132 default: 1133 goto fail; 1134 } 1135 state->frontend.demodulator_priv = state; 1136 1137 /* verify that we're talking to a lg dt3304/5 */ 1138 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val); 1139 if ((lg_fail(ret)) | (val == 0)) 1140 goto fail; 1141 ret = lgdt3305_write_reg(state, 0x0808, 0x80); 1142 if (lg_fail(ret)) 1143 goto fail; 1144 ret = lgdt3305_read_reg(state, 0x0808, &val); 1145 if ((lg_fail(ret)) | (val != 0x80)) 1146 goto fail; 1147 ret = lgdt3305_write_reg(state, 0x0808, 0x00); 1148 if (lg_fail(ret)) 1149 goto fail; 1150 1151 state->current_frequency = -1; 1152 state->current_modulation = -1; 1153 1154 return &state->frontend; 1155 fail: 1156 lg_warn("unable to detect %s hardware\n", 1157 config->demod_chip ? "LGDT3304" : "LGDT3305"); 1158 kfree(state); 1159 return NULL; 1160 } 1161 EXPORT_SYMBOL(lgdt3305_attach); 1162 1163 static const struct dvb_frontend_ops lgdt3304_ops = { 1164 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 1165 .info = { 1166 .name = "LG Electronics LGDT3304 VSB/QAM Frontend", 1167 .frequency_min = 54000000, 1168 .frequency_max = 858000000, 1169 .frequency_stepsize = 62500, 1170 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 1171 }, 1172 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl, 1173 .init = lgdt3305_init, 1174 .sleep = lgdt3305_sleep, 1175 .set_frontend = lgdt3304_set_parameters, 1176 .get_frontend = lgdt3305_get_frontend, 1177 .get_tune_settings = lgdt3305_get_tune_settings, 1178 .read_status = lgdt3305_read_status, 1179 .read_ber = lgdt3305_read_ber, 1180 .read_signal_strength = lgdt3305_read_signal_strength, 1181 .read_snr = lgdt3305_read_snr, 1182 .read_ucblocks = lgdt3305_read_ucblocks, 1183 .release = lgdt3305_release, 1184 }; 1185 1186 static const struct dvb_frontend_ops lgdt3305_ops = { 1187 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 1188 .info = { 1189 .name = "LG Electronics LGDT3305 VSB/QAM Frontend", 1190 .frequency_min = 54000000, 1191 .frequency_max = 858000000, 1192 .frequency_stepsize = 62500, 1193 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 1194 }, 1195 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl, 1196 .init = lgdt3305_init, 1197 .sleep = lgdt3305_sleep, 1198 .set_frontend = lgdt3305_set_parameters, 1199 .get_frontend = lgdt3305_get_frontend, 1200 .get_tune_settings = lgdt3305_get_tune_settings, 1201 .read_status = lgdt3305_read_status, 1202 .read_ber = lgdt3305_read_ber, 1203 .read_signal_strength = lgdt3305_read_signal_strength, 1204 .read_snr = lgdt3305_read_snr, 1205 .read_ucblocks = lgdt3305_read_ucblocks, 1206 .release = lgdt3305_release, 1207 }; 1208 1209 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver"); 1210 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>"); 1211 MODULE_LICENSE("GPL"); 1212 MODULE_VERSION("0.2"); 1213