1 /*
2     driver for LSI L64781 COFDM demodulator
3 
4     Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH
5 		       Marko Kohtala <marko.kohtala@luukku.com>
6 
7     This program is free software; you can redistribute it and/or modify
8     it under the terms of the GNU General Public License as published by
9     the Free Software Foundation; either version 2 of the License, or
10     (at your option) any later version.
11 
12     This program is distributed in the hope that it will be useful,
13     but WITHOUT ANY WARRANTY; without even the implied warranty of
14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15     GNU General Public License for more details.
16 
17     You should have received a copy of the GNU General Public License
18     along with this program; if not, write to the Free Software
19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
21 */
22 
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <media/dvb_frontend.h>
29 #include "l64781.h"
30 
31 
32 struct l64781_state {
33 	struct i2c_adapter* i2c;
34 	const struct l64781_config* config;
35 	struct dvb_frontend frontend;
36 
37 	/* private demodulator data */
38 	unsigned int first:1;
39 };
40 
41 #define dprintk(args...) \
42 	do { \
43 		if (debug) printk(KERN_DEBUG "l64781: " args); \
44 	} while (0)
45 
46 static int debug;
47 
48 module_param(debug, int, 0644);
49 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
50 
51 
52 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
53 {
54 	int ret;
55 	u8 buf [] = { reg, data };
56 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
57 
58 	if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
59 		dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
60 			 __func__, reg, ret);
61 
62 	return (ret != 1) ? -1 : 0;
63 }
64 
65 static int l64781_readreg (struct l64781_state* state, u8 reg)
66 {
67 	int ret;
68 	u8 b0 [] = { reg };
69 	u8 b1 [] = { 0 };
70 	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
71 			   { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
72 
73 	ret = i2c_transfer(state->i2c, msg, 2);
74 
75 	if (ret != 2) return ret;
76 
77 	return b1[0];
78 }
79 
80 static void apply_tps (struct l64781_state* state)
81 {
82 	l64781_writereg (state, 0x2a, 0x00);
83 	l64781_writereg (state, 0x2a, 0x01);
84 
85 	/* This here is a little bit questionable because it enables
86 	   the automatic update of TPS registers. I think we'd need to
87 	   handle the IRQ from FE to update some other registers as
88 	   well, or at least implement some magic to tuning to correct
89 	   to the TPS received from transmission. */
90 	l64781_writereg (state, 0x2a, 0x02);
91 }
92 
93 
94 static void reset_afc (struct l64781_state* state)
95 {
96 	/* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
97 	   timing offset */
98 	l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
99 	l64781_writereg (state, 0x08, 0);    /* AFC INIT FREQ */
100 	l64781_writereg (state, 0x09, 0);
101 	l64781_writereg (state, 0x0a, 0);
102 	l64781_writereg (state, 0x07, 0x8e);
103 	l64781_writereg (state, 0x0e, 0);    /* AGC gain to zero in beginning */
104 	l64781_writereg (state, 0x11, 0x80); /* stall TIM */
105 	l64781_writereg (state, 0x10, 0);    /* TIM_OFFSET_LSB */
106 	l64781_writereg (state, 0x12, 0);
107 	l64781_writereg (state, 0x13, 0);
108 	l64781_writereg (state, 0x11, 0x00);
109 }
110 
111 static int reset_and_configure (struct l64781_state* state)
112 {
113 	u8 buf [] = { 0x06 };
114 	struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
115 	// NOTE: this is correct in writing to address 0x00
116 
117 	return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
118 }
119 
120 static int apply_frontend_param(struct dvb_frontend *fe)
121 {
122 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
123 	struct l64781_state* state = fe->demodulator_priv;
124 	/* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
125 	static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
126 	/* QPSK, QAM_16, QAM_64 */
127 	static const u8 qam_tab [] = { 2, 4, 0, 6 };
128 	static const u8 guard_tab [] = { 1, 2, 4, 8 };
129 	/* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
130 	static const u32 ppm = 8000;
131 	u32 ddfs_offset_fixed;
132 /*	u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
133 /*			bw_tab[p->bandWidth]<<10)/15625; */
134 	u32 init_freq;
135 	u32 spi_bias;
136 	u8 val0x04;
137 	u8 val0x05;
138 	u8 val0x06;
139 	int bw;
140 
141 	switch (p->bandwidth_hz) {
142 	case 8000000:
143 		bw = 8;
144 		break;
145 	case 7000000:
146 		bw = 7;
147 		break;
148 	case 6000000:
149 		bw = 6;
150 		break;
151 	default:
152 		return -EINVAL;
153 	}
154 
155 	if (fe->ops.tuner_ops.set_params) {
156 		fe->ops.tuner_ops.set_params(fe);
157 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
158 	}
159 
160 	if (p->inversion != INVERSION_ON &&
161 	    p->inversion != INVERSION_OFF)
162 		return -EINVAL;
163 
164 	if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
165 	    p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
166 	    p->code_rate_HP != FEC_7_8)
167 		return -EINVAL;
168 
169 	if (p->hierarchy != HIERARCHY_NONE &&
170 	    (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
171 	     p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
172 	     p->code_rate_LP != FEC_7_8))
173 		return -EINVAL;
174 
175 	if (p->modulation != QPSK && p->modulation != QAM_16 &&
176 	    p->modulation != QAM_64)
177 		return -EINVAL;
178 
179 	if (p->transmission_mode != TRANSMISSION_MODE_2K &&
180 	    p->transmission_mode != TRANSMISSION_MODE_8K)
181 		return -EINVAL;
182 
183 	if ((int)p->guard_interval < GUARD_INTERVAL_1_32 ||
184 	    p->guard_interval > GUARD_INTERVAL_1_4)
185 		return -EINVAL;
186 
187 	if ((int)p->hierarchy < HIERARCHY_NONE ||
188 	    p->hierarchy > HIERARCHY_4)
189 		return -EINVAL;
190 
191 	ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000;
192 
193 	/* This works up to 20000 ppm, it overflows if too large ppm! */
194 	init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
195 			bw & 0xFFFFFF);
196 
197 	/* SPI bias calculation is slightly modified to fit in 32bit */
198 	/* will work for high ppm only... */
199 	spi_bias = 378 * (1 << 10);
200 	spi_bias *= 16;
201 	spi_bias *= bw;
202 	spi_bias *= qam_tab[p->modulation];
203 	spi_bias /= p->code_rate_HP + 1;
204 	spi_bias /= (guard_tab[p->guard_interval] + 32);
205 	spi_bias *= 1000;
206 	spi_bias /= 1000 + ppm/1000;
207 	spi_bias *= p->code_rate_HP;
208 
209 	val0x04 = (p->transmission_mode << 2) | p->guard_interval;
210 	val0x05 = fec_tab[p->code_rate_HP];
211 
212 	if (p->hierarchy != HIERARCHY_NONE)
213 		val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
214 
215 	val0x06 = (p->hierarchy << 2) | p->modulation;
216 
217 	l64781_writereg (state, 0x04, val0x04);
218 	l64781_writereg (state, 0x05, val0x05);
219 	l64781_writereg (state, 0x06, val0x06);
220 
221 	reset_afc (state);
222 
223 	/* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
224 	l64781_writereg (state, 0x15,
225 			 p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
226 	l64781_writereg (state, 0x16, init_freq & 0xff);
227 	l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
228 	l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
229 
230 	l64781_writereg (state, 0x1b, spi_bias & 0xff);
231 	l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
232 	l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
233 		(p->inversion == INVERSION_ON ? 0x80 : 0x00));
234 
235 	l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
236 	l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
237 
238 	l64781_readreg (state, 0x00);  /*  clear interrupt registers... */
239 	l64781_readreg (state, 0x01);  /*  dto. */
240 
241 	apply_tps (state);
242 
243 	return 0;
244 }
245 
246 static int get_frontend(struct dvb_frontend *fe,
247 			struct dtv_frontend_properties *p)
248 {
249 	struct l64781_state* state = fe->demodulator_priv;
250 	int tmp;
251 
252 
253 	tmp = l64781_readreg(state, 0x04);
254 	switch(tmp & 3) {
255 	case 0:
256 		p->guard_interval = GUARD_INTERVAL_1_32;
257 		break;
258 	case 1:
259 		p->guard_interval = GUARD_INTERVAL_1_16;
260 		break;
261 	case 2:
262 		p->guard_interval = GUARD_INTERVAL_1_8;
263 		break;
264 	case 3:
265 		p->guard_interval = GUARD_INTERVAL_1_4;
266 		break;
267 	}
268 	switch((tmp >> 2) & 3) {
269 	case 0:
270 		p->transmission_mode = TRANSMISSION_MODE_2K;
271 		break;
272 	case 1:
273 		p->transmission_mode = TRANSMISSION_MODE_8K;
274 		break;
275 	default:
276 		printk(KERN_WARNING "Unexpected value for transmission_mode\n");
277 	}
278 
279 	tmp = l64781_readreg(state, 0x05);
280 	switch(tmp & 7) {
281 	case 0:
282 		p->code_rate_HP = FEC_1_2;
283 		break;
284 	case 1:
285 		p->code_rate_HP = FEC_2_3;
286 		break;
287 	case 2:
288 		p->code_rate_HP = FEC_3_4;
289 		break;
290 	case 3:
291 		p->code_rate_HP = FEC_5_6;
292 		break;
293 	case 4:
294 		p->code_rate_HP = FEC_7_8;
295 		break;
296 	default:
297 		printk("Unexpected value for code_rate_HP\n");
298 	}
299 	switch((tmp >> 3) & 7) {
300 	case 0:
301 		p->code_rate_LP = FEC_1_2;
302 		break;
303 	case 1:
304 		p->code_rate_LP = FEC_2_3;
305 		break;
306 	case 2:
307 		p->code_rate_LP = FEC_3_4;
308 		break;
309 	case 3:
310 		p->code_rate_LP = FEC_5_6;
311 		break;
312 	case 4:
313 		p->code_rate_LP = FEC_7_8;
314 		break;
315 	default:
316 		printk("Unexpected value for code_rate_LP\n");
317 	}
318 
319 	tmp = l64781_readreg(state, 0x06);
320 	switch(tmp & 3) {
321 	case 0:
322 		p->modulation = QPSK;
323 		break;
324 	case 1:
325 		p->modulation = QAM_16;
326 		break;
327 	case 2:
328 		p->modulation = QAM_64;
329 		break;
330 	default:
331 		printk(KERN_WARNING "Unexpected value for modulation\n");
332 	}
333 	switch((tmp >> 2) & 7) {
334 	case 0:
335 		p->hierarchy = HIERARCHY_NONE;
336 		break;
337 	case 1:
338 		p->hierarchy = HIERARCHY_1;
339 		break;
340 	case 2:
341 		p->hierarchy = HIERARCHY_2;
342 		break;
343 	case 3:
344 		p->hierarchy = HIERARCHY_4;
345 		break;
346 	default:
347 		printk("Unexpected value for hierarchy\n");
348 	}
349 
350 
351 	tmp = l64781_readreg (state, 0x1d);
352 	p->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
353 
354 	tmp = (int) (l64781_readreg (state, 0x08) |
355 		     (l64781_readreg (state, 0x09) << 8) |
356 		     (l64781_readreg (state, 0x0a) << 16));
357 	p->frequency += tmp;
358 
359 	return 0;
360 }
361 
362 static int l64781_read_status(struct dvb_frontend *fe, enum fe_status *status)
363 {
364 	struct l64781_state* state = fe->demodulator_priv;
365 	int sync = l64781_readreg (state, 0x32);
366 	int gain = l64781_readreg (state, 0x0e);
367 
368 	l64781_readreg (state, 0x00);  /*  clear interrupt registers... */
369 	l64781_readreg (state, 0x01);  /*  dto. */
370 
371 	*status = 0;
372 
373 	if (gain > 5)
374 		*status |= FE_HAS_SIGNAL;
375 
376 	if (sync & 0x02) /* VCXO locked, this criteria should be ok */
377 		*status |= FE_HAS_CARRIER;
378 
379 	if (sync & 0x20)
380 		*status |= FE_HAS_VITERBI;
381 
382 	if (sync & 0x40)
383 		*status |= FE_HAS_SYNC;
384 
385 	if (sync == 0x7f)
386 		*status |= FE_HAS_LOCK;
387 
388 	return 0;
389 }
390 
391 static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
392 {
393 	struct l64781_state* state = fe->demodulator_priv;
394 
395 	/*   XXX FIXME: set up counting period (reg 0x26...0x28)
396 	 */
397 	*ber = l64781_readreg (state, 0x39)
398 	    | (l64781_readreg (state, 0x3a) << 8);
399 
400 	return 0;
401 }
402 
403 static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
404 {
405 	struct l64781_state* state = fe->demodulator_priv;
406 
407 	u8 gain = l64781_readreg (state, 0x0e);
408 	*signal_strength = (gain << 8) | gain;
409 
410 	return 0;
411 }
412 
413 static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
414 {
415 	struct l64781_state* state = fe->demodulator_priv;
416 
417 	u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
418 	*snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
419 
420 	return 0;
421 }
422 
423 static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
424 {
425 	struct l64781_state* state = fe->demodulator_priv;
426 
427 	*ucblocks = l64781_readreg (state, 0x37)
428 	   | (l64781_readreg (state, 0x38) << 8);
429 
430 	return 0;
431 }
432 
433 static int l64781_sleep(struct dvb_frontend* fe)
434 {
435 	struct l64781_state* state = fe->demodulator_priv;
436 
437 	/* Power down */
438 	return l64781_writereg (state, 0x3e, 0x5a);
439 }
440 
441 static int l64781_init(struct dvb_frontend* fe)
442 {
443 	struct l64781_state* state = fe->demodulator_priv;
444 
445 	reset_and_configure (state);
446 
447 	/* Power up */
448 	l64781_writereg (state, 0x3e, 0xa5);
449 
450 	/* Reset hard */
451 	l64781_writereg (state, 0x2a, 0x04);
452 	l64781_writereg (state, 0x2a, 0x00);
453 
454 	/* Set tuner specific things */
455 	/* AFC_POL, set also in reset_afc */
456 	l64781_writereg (state, 0x07, 0x8e);
457 
458 	/* Use internal ADC */
459 	l64781_writereg (state, 0x0b, 0x81);
460 
461 	/* AGC loop gain, and polarity is positive */
462 	l64781_writereg (state, 0x0c, 0x84);
463 
464 	/* Internal ADC outputs two's complement */
465 	l64781_writereg (state, 0x0d, 0x8c);
466 
467 	/* With ppm=8000, it seems the DTR_SENSITIVITY will result in
468 	   value of 2 with all possible bandwidths and guard
469 	   intervals, which is the initial value anyway. */
470 	/*l64781_writereg (state, 0x19, 0x92);*/
471 
472 	/* Everything is two's complement, soft bit and CSI_OUT too */
473 	l64781_writereg (state, 0x1e, 0x09);
474 
475 	/* delay a bit after first init attempt */
476 	if (state->first) {
477 		state->first = 0;
478 		msleep(200);
479 	}
480 
481 	return 0;
482 }
483 
484 static int l64781_get_tune_settings(struct dvb_frontend* fe,
485 				    struct dvb_frontend_tune_settings* fesettings)
486 {
487 	fesettings->min_delay_ms = 4000;
488 	fesettings->step_size = 0;
489 	fesettings->max_drift = 0;
490 	return 0;
491 }
492 
493 static void l64781_release(struct dvb_frontend* fe)
494 {
495 	struct l64781_state* state = fe->demodulator_priv;
496 	kfree(state);
497 }
498 
499 static const struct dvb_frontend_ops l64781_ops;
500 
501 struct dvb_frontend* l64781_attach(const struct l64781_config* config,
502 				   struct i2c_adapter* i2c)
503 {
504 	struct l64781_state* state = NULL;
505 	int reg0x3e = -1;
506 	u8 b0 [] = { 0x1a };
507 	u8 b1 [] = { 0x00 };
508 	struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
509 			   { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
510 
511 	/* allocate memory for the internal state */
512 	state = kzalloc(sizeof(struct l64781_state), GFP_KERNEL);
513 	if (state == NULL) goto error;
514 
515 	/* setup the state */
516 	state->config = config;
517 	state->i2c = i2c;
518 	state->first = 1;
519 
520 	/*
521 	 *  the L64781 won't show up before we send the reset_and_configure()
522 	 *  broadcast. If nothing responds there is no L64781 on the bus...
523 	 */
524 	if (reset_and_configure(state) < 0) {
525 		dprintk("No response to reset and configure broadcast...\n");
526 		goto error;
527 	}
528 
529 	/* The chip always responds to reads */
530 	if (i2c_transfer(state->i2c, msg, 2) != 2) {
531 		dprintk("No response to read on I2C bus\n");
532 		goto error;
533 	}
534 
535 	/* Save current register contents for bailout */
536 	reg0x3e = l64781_readreg(state, 0x3e);
537 
538 	/* Reading the POWER_DOWN register always returns 0 */
539 	if (reg0x3e != 0) {
540 		dprintk("Device doesn't look like L64781\n");
541 		goto error;
542 	}
543 
544 	/* Turn the chip off */
545 	l64781_writereg (state, 0x3e, 0x5a);
546 
547 	/* Responds to all reads with 0 */
548 	if (l64781_readreg(state, 0x1a) != 0) {
549 		dprintk("Read 1 returned unexpected value\n");
550 		goto error;
551 	}
552 
553 	/* Turn the chip on */
554 	l64781_writereg (state, 0x3e, 0xa5);
555 
556 	/* Responds with register default value */
557 	if (l64781_readreg(state, 0x1a) != 0xa1) {
558 		dprintk("Read 2 returned unexpected value\n");
559 		goto error;
560 	}
561 
562 	/* create dvb_frontend */
563 	memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
564 	state->frontend.demodulator_priv = state;
565 	return &state->frontend;
566 
567 error:
568 	if (reg0x3e >= 0)
569 		l64781_writereg (state, 0x3e, reg0x3e);  /* restore reg 0x3e */
570 	kfree(state);
571 	return NULL;
572 }
573 
574 static const struct dvb_frontend_ops l64781_ops = {
575 	.delsys = { SYS_DVBT },
576 	.info = {
577 		.name = "LSI L64781 DVB-T",
578 	/*	.frequency_min_hz = ???,*/
579 	/*	.frequency_max_hz = ???,*/
580 		.frequency_stepsize_hz = 166666,
581 	/*      .symbol_rate_tolerance = ???,*/
582 		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
583 		      FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
584 		      FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
585 		      FE_CAN_MUTE_TS
586 	},
587 
588 	.release = l64781_release,
589 
590 	.init = l64781_init,
591 	.sleep = l64781_sleep,
592 
593 	.set_frontend = apply_frontend_param,
594 	.get_frontend = get_frontend,
595 	.get_tune_settings = l64781_get_tune_settings,
596 
597 	.read_status = l64781_read_status,
598 	.read_ber = l64781_read_ber,
599 	.read_signal_strength = l64781_read_signal_strength,
600 	.read_snr = l64781_read_snr,
601 	.read_ucblocks = l64781_read_ucblocks,
602 };
603 
604 MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
605 MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
606 MODULE_LICENSE("GPL");
607 
608 EXPORT_SYMBOL(l64781_attach);
609