1 /* 2 * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite" 3 * 4 * Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/delay.h> 21 #include <linux/dvb/frontend.h> 22 #include <linux/i2c.h> 23 #include <linux/slab.h> 24 25 #include <media/dvb_frontend.h> 26 27 #include "itd1000.h" 28 #include "itd1000_priv.h" 29 30 /* Max transfer size done by I2C transfer functions */ 31 #define MAX_XFER_SIZE 64 32 33 static int debug; 34 module_param(debug, int, 0644); 35 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); 36 37 #define itd_dbg(args...) do { \ 38 if (debug) { \ 39 printk(KERN_DEBUG "ITD1000: " args);\ 40 } \ 41 } while (0) 42 43 #define itd_warn(args...) do { \ 44 printk(KERN_WARNING "ITD1000: " args); \ 45 } while (0) 46 47 #define itd_info(args...) do { \ 48 printk(KERN_INFO "ITD1000: " args); \ 49 } while (0) 50 51 /* don't write more than one byte with flexcop behind */ 52 static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len) 53 { 54 u8 buf[MAX_XFER_SIZE]; 55 struct i2c_msg msg = { 56 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1 57 }; 58 59 if (1 + len > sizeof(buf)) { 60 printk(KERN_WARNING 61 "itd1000: i2c wr reg=%04x: len=%d is too big!\n", 62 reg, len); 63 return -EINVAL; 64 } 65 66 buf[0] = reg; 67 memcpy(&buf[1], v, len); 68 69 /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */ 70 71 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 72 printk(KERN_WARNING "itd1000 I2C write failed\n"); 73 return -EREMOTEIO; 74 } 75 return 0; 76 } 77 78 static int itd1000_read_reg(struct itd1000_state *state, u8 reg) 79 { 80 u8 val; 81 struct i2c_msg msg[2] = { 82 { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, 83 { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 }, 84 }; 85 86 /* ugly flexcop workaround */ 87 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); 88 89 if (i2c_transfer(state->i2c, msg, 2) != 2) { 90 itd_warn("itd1000 I2C read failed\n"); 91 return -EREMOTEIO; 92 } 93 return val; 94 } 95 96 static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v) 97 { 98 u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 99 int ret = itd1000_write_regs(state, r, &tmp, 1); 100 state->shadow[r] = tmp; 101 return ret; 102 } 103 104 105 static struct { 106 u32 symbol_rate; 107 u8 pgaext : 4; /* PLLFH */ 108 u8 bbgvmin : 4; /* BBGVMIN */ 109 } itd1000_lpf_pga[] = { 110 { 0, 0x8, 0x3 }, 111 { 5200000, 0x8, 0x3 }, 112 { 12200000, 0x4, 0x3 }, 113 { 15400000, 0x2, 0x3 }, 114 { 19800000, 0x2, 0x3 }, 115 { 21500000, 0x2, 0x3 }, 116 { 24500000, 0x2, 0x3 }, 117 { 28400000, 0x2, 0x3 }, 118 { 33400000, 0x2, 0x3 }, 119 { 34400000, 0x1, 0x4 }, 120 { 34400000, 0x1, 0x4 }, 121 { 38400000, 0x1, 0x4 }, 122 { 38400000, 0x1, 0x4 }, 123 { 40400000, 0x1, 0x4 }, 124 { 45400000, 0x1, 0x4 }, 125 }; 126 127 static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate) 128 { 129 u8 i; 130 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd; 131 u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f; 132 u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0; 133 u8 bw = itd1000_read_reg(state, BW) & 0xf0; 134 135 itd_dbg("symbol_rate = %d\n", symbol_rate); 136 137 /* not sure what is that ? - starting to download the table */ 138 itd1000_write_reg(state, CON1, con1 | (1 << 1)); 139 140 for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++) 141 if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) { 142 itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin); 143 itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4)); 144 itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin)); 145 itd1000_write_reg(state, BW, bw | (i & 0x0f)); 146 break; 147 } 148 149 itd1000_write_reg(state, CON1, con1 | (0 << 1)); 150 } 151 152 static struct { 153 u8 vcorg; 154 u32 fmax_rg; 155 } itd1000_vcorg[] = { 156 { 1, 920000 }, 157 { 2, 971000 }, 158 { 3, 1031000 }, 159 { 4, 1091000 }, 160 { 5, 1171000 }, 161 { 6, 1281000 }, 162 { 7, 1381000 }, 163 { 8, 500000 }, /* this is intentional. */ 164 { 9, 1451000 }, 165 { 10, 1531000 }, 166 { 11, 1631000 }, 167 { 12, 1741000 }, 168 { 13, 1891000 }, 169 { 14, 2071000 }, 170 { 15, 2250000 }, 171 }; 172 173 static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz) 174 { 175 u8 i; 176 u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf; 177 u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f; 178 u8 adcout; 179 180 /* reserved bit again (reset ?) */ 181 itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6)); 182 183 for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) { 184 if (freq_khz < itd1000_vcorg[i].fmax_rg) { 185 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4)); 186 msleep(1); 187 188 adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f; 189 190 itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c); 191 192 if (adcout > 13) { 193 if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15)) 194 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4)); 195 } else if (adcout < 2) { 196 if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9)) 197 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4)); 198 } 199 break; 200 } 201 } 202 } 203 204 static const struct { 205 u32 freq; 206 u8 values[10]; /* RFTR, RFST1 - RFST9 */ 207 } itd1000_fre_values[] = { 208 { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 209 { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 210 { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 211 { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 212 { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 213 { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } }, 214 { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } }, 215 { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } }, 216 { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } }, 217 { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } } 218 }; 219 220 221 #define FREF 16 222 223 static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz) 224 { 225 int i, j; 226 u32 plln, pllf; 227 u64 tmp; 228 229 plln = (freq_khz * 1000) / 2 / FREF; 230 231 /* Compute the factional part times 1000 */ 232 tmp = plln % 1000000; 233 plln /= 1000000; 234 235 tmp *= 1048576; 236 do_div(tmp, 1000000); 237 pllf = (u32) tmp; 238 239 state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF; 240 itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln); 241 242 itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */ 243 itd1000_write_reg(state, PLLNL, plln & 0xff); 244 itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f)); 245 itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff); 246 itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff); 247 248 for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) { 249 if (freq_khz <= itd1000_fre_values[i].freq) { 250 itd_dbg("fre_values: %d\n", i); 251 itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]); 252 for (j = 0; j < 9; j++) 253 itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]); 254 break; 255 } 256 } 257 258 itd1000_set_vco(state, freq_khz); 259 } 260 261 static int itd1000_set_parameters(struct dvb_frontend *fe) 262 { 263 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 264 struct itd1000_state *state = fe->tuner_priv; 265 u8 pllcon1; 266 267 itd1000_set_lo(state, c->frequency); 268 itd1000_set_lpf_bw(state, c->symbol_rate); 269 270 pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f; 271 itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7)); 272 itd1000_write_reg(state, PLLCON1, pllcon1); 273 274 return 0; 275 } 276 277 static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency) 278 { 279 struct itd1000_state *state = fe->tuner_priv; 280 *frequency = state->frequency; 281 return 0; 282 } 283 284 static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 285 { 286 return 0; 287 } 288 289 static u8 itd1000_init_tab[][2] = { 290 { PLLCON1, 0x65 }, /* Register does not change */ 291 { PLLNH, 0x80 }, /* Bits [7:6] do not change */ 292 { RESERVED_0X6D, 0x3b }, 293 { VCO_CHP2_I2C, 0x12 }, 294 { 0x72, 0xf9 }, /* No such regsister defined */ 295 { RESERVED_0X73, 0xff }, 296 { RESERVED_0X74, 0xb2 }, 297 { RESERVED_0X75, 0xc7 }, 298 { EXTGVBBRF, 0xf0 }, 299 { DIVAGCCK, 0x80 }, 300 { BBTR, 0xa0 }, 301 { RESERVED_0X7E, 0x4f }, 302 { 0x82, 0x88 }, /* No such regsister defined */ 303 { 0x83, 0x80 }, /* No such regsister defined */ 304 { 0x84, 0x80 }, /* No such regsister defined */ 305 { RESERVED_0X85, 0x74 }, 306 { RESERVED_0X86, 0xff }, 307 { RESERVED_0X88, 0x02 }, 308 { RESERVED_0X89, 0x16 }, 309 { RFST0, 0x1f }, 310 { RESERVED_0X94, 0x66 }, 311 { RESERVED_0X95, 0x66 }, 312 { RESERVED_0X96, 0x77 }, 313 { RESERVED_0X97, 0x99 }, 314 { RESERVED_0X98, 0xff }, 315 { RESERVED_0X99, 0xfc }, 316 { RESERVED_0X9A, 0xba }, 317 { RESERVED_0X9B, 0xaa }, 318 }; 319 320 static u8 itd1000_reinit_tab[][2] = { 321 { VCO_CHP1_I2C, 0x8a }, 322 { BW, 0x87 }, 323 { GVBB_I2C, 0x03 }, 324 { BBGVMIN, 0x03 }, 325 { CON1, 0x2e }, 326 }; 327 328 329 static int itd1000_init(struct dvb_frontend *fe) 330 { 331 struct itd1000_state *state = fe->tuner_priv; 332 int i; 333 334 for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++) 335 itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]); 336 337 for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++) 338 itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]); 339 340 return 0; 341 } 342 343 static int itd1000_sleep(struct dvb_frontend *fe) 344 { 345 return 0; 346 } 347 348 static void itd1000_release(struct dvb_frontend *fe) 349 { 350 kfree(fe->tuner_priv); 351 fe->tuner_priv = NULL; 352 } 353 354 static const struct dvb_tuner_ops itd1000_tuner_ops = { 355 .info = { 356 .name = "Integrant ITD1000", 357 .frequency_min = 950000, 358 .frequency_max = 2150000, 359 .frequency_step = 125, /* kHz for QPSK frontends */ 360 }, 361 362 .release = itd1000_release, 363 364 .init = itd1000_init, 365 .sleep = itd1000_sleep, 366 367 .set_params = itd1000_set_parameters, 368 .get_frequency = itd1000_get_frequency, 369 .get_bandwidth = itd1000_get_bandwidth 370 }; 371 372 373 struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg) 374 { 375 struct itd1000_state *state = NULL; 376 u8 i = 0; 377 378 state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL); 379 if (state == NULL) 380 return NULL; 381 382 state->cfg = cfg; 383 state->i2c = i2c; 384 385 i = itd1000_read_reg(state, 0); 386 if (i != 0) { 387 kfree(state); 388 return NULL; 389 } 390 itd_info("successfully identified (ID: %d)\n", i); 391 392 memset(state->shadow, 0xff, sizeof(state->shadow)); 393 for (i = 0x65; i < 0x9c; i++) 394 state->shadow[i] = itd1000_read_reg(state, i); 395 396 memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops)); 397 398 fe->tuner_priv = state; 399 400 return fe; 401 } 402 EXPORT_SYMBOL(itd1000_attach); 403 404 MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>"); 405 MODULE_DESCRIPTION("Integrant ITD1000 driver"); 406 MODULE_LICENSE("GPL"); 407