1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
29a0bf528SMauro Carvalho Chehab /*
39a0bf528SMauro Carvalho Chehab * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
49a0bf528SMauro Carvalho Chehab *
59a0bf528SMauro Carvalho Chehab * Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org>
69a0bf528SMauro Carvalho Chehab */
79a0bf528SMauro Carvalho Chehab
89a0bf528SMauro Carvalho Chehab #include <linux/module.h>
99a0bf528SMauro Carvalho Chehab #include <linux/moduleparam.h>
109a0bf528SMauro Carvalho Chehab #include <linux/delay.h>
119a0bf528SMauro Carvalho Chehab #include <linux/dvb/frontend.h>
129a0bf528SMauro Carvalho Chehab #include <linux/i2c.h>
139a0bf528SMauro Carvalho Chehab #include <linux/slab.h>
149a0bf528SMauro Carvalho Chehab
15fada1935SMauro Carvalho Chehab #include <media/dvb_frontend.h>
169a0bf528SMauro Carvalho Chehab
179a0bf528SMauro Carvalho Chehab #include "itd1000.h"
189a0bf528SMauro Carvalho Chehab #include "itd1000_priv.h"
199a0bf528SMauro Carvalho Chehab
208393796dSMauro Carvalho Chehab /* Max transfer size done by I2C transfer functions */
218393796dSMauro Carvalho Chehab #define MAX_XFER_SIZE 64
228393796dSMauro Carvalho Chehab
239a0bf528SMauro Carvalho Chehab static int debug;
249a0bf528SMauro Carvalho Chehab module_param(debug, int, 0644);
259a0bf528SMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
269a0bf528SMauro Carvalho Chehab
279a0bf528SMauro Carvalho Chehab #define itd_dbg(args...) do { \
289a0bf528SMauro Carvalho Chehab if (debug) { \
299a0bf528SMauro Carvalho Chehab printk(KERN_DEBUG "ITD1000: " args);\
309a0bf528SMauro Carvalho Chehab } \
319a0bf528SMauro Carvalho Chehab } while (0)
329a0bf528SMauro Carvalho Chehab
339a0bf528SMauro Carvalho Chehab #define itd_warn(args...) do { \
349a0bf528SMauro Carvalho Chehab printk(KERN_WARNING "ITD1000: " args); \
359a0bf528SMauro Carvalho Chehab } while (0)
369a0bf528SMauro Carvalho Chehab
379a0bf528SMauro Carvalho Chehab #define itd_info(args...) do { \
389a0bf528SMauro Carvalho Chehab printk(KERN_INFO "ITD1000: " args); \
399a0bf528SMauro Carvalho Chehab } while (0)
409a0bf528SMauro Carvalho Chehab
419a0bf528SMauro Carvalho Chehab /* don't write more than one byte with flexcop behind */
itd1000_write_regs(struct itd1000_state * state,u8 reg,u8 v[],u8 len)429a0bf528SMauro Carvalho Chehab static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
439a0bf528SMauro Carvalho Chehab {
448393796dSMauro Carvalho Chehab u8 buf[MAX_XFER_SIZE];
459a0bf528SMauro Carvalho Chehab struct i2c_msg msg = {
469a0bf528SMauro Carvalho Chehab .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
479a0bf528SMauro Carvalho Chehab };
488393796dSMauro Carvalho Chehab
498393796dSMauro Carvalho Chehab if (1 + len > sizeof(buf)) {
508393796dSMauro Carvalho Chehab printk(KERN_WARNING
518393796dSMauro Carvalho Chehab "itd1000: i2c wr reg=%04x: len=%d is too big!\n",
528393796dSMauro Carvalho Chehab reg, len);
538393796dSMauro Carvalho Chehab return -EINVAL;
548393796dSMauro Carvalho Chehab }
558393796dSMauro Carvalho Chehab
569a0bf528SMauro Carvalho Chehab buf[0] = reg;
579a0bf528SMauro Carvalho Chehab memcpy(&buf[1], v, len);
589a0bf528SMauro Carvalho Chehab
599a0bf528SMauro Carvalho Chehab /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */
609a0bf528SMauro Carvalho Chehab
619a0bf528SMauro Carvalho Chehab if (i2c_transfer(state->i2c, &msg, 1) != 1) {
629a0bf528SMauro Carvalho Chehab printk(KERN_WARNING "itd1000 I2C write failed\n");
639a0bf528SMauro Carvalho Chehab return -EREMOTEIO;
649a0bf528SMauro Carvalho Chehab }
659a0bf528SMauro Carvalho Chehab return 0;
669a0bf528SMauro Carvalho Chehab }
679a0bf528SMauro Carvalho Chehab
itd1000_read_reg(struct itd1000_state * state,u8 reg)689a0bf528SMauro Carvalho Chehab static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
699a0bf528SMauro Carvalho Chehab {
709a0bf528SMauro Carvalho Chehab u8 val;
719a0bf528SMauro Carvalho Chehab struct i2c_msg msg[2] = {
729a0bf528SMauro Carvalho Chehab { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
739a0bf528SMauro Carvalho Chehab { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
749a0bf528SMauro Carvalho Chehab };
759a0bf528SMauro Carvalho Chehab
769a0bf528SMauro Carvalho Chehab /* ugly flexcop workaround */
779a0bf528SMauro Carvalho Chehab itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
789a0bf528SMauro Carvalho Chehab
799a0bf528SMauro Carvalho Chehab if (i2c_transfer(state->i2c, msg, 2) != 2) {
809a0bf528SMauro Carvalho Chehab itd_warn("itd1000 I2C read failed\n");
819a0bf528SMauro Carvalho Chehab return -EREMOTEIO;
829a0bf528SMauro Carvalho Chehab }
839a0bf528SMauro Carvalho Chehab return val;
849a0bf528SMauro Carvalho Chehab }
859a0bf528SMauro Carvalho Chehab
itd1000_write_reg(struct itd1000_state * state,u8 r,u8 v)869a0bf528SMauro Carvalho Chehab static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
879a0bf528SMauro Carvalho Chehab {
883cd890dbSArnd Bergmann u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
893cd890dbSArnd Bergmann int ret = itd1000_write_regs(state, r, &tmp, 1);
903cd890dbSArnd Bergmann state->shadow[r] = tmp;
919a0bf528SMauro Carvalho Chehab return ret;
929a0bf528SMauro Carvalho Chehab }
939a0bf528SMauro Carvalho Chehab
949a0bf528SMauro Carvalho Chehab
959a0bf528SMauro Carvalho Chehab static struct {
969a0bf528SMauro Carvalho Chehab u32 symbol_rate;
979a0bf528SMauro Carvalho Chehab u8 pgaext : 4; /* PLLFH */
989a0bf528SMauro Carvalho Chehab u8 bbgvmin : 4; /* BBGVMIN */
999a0bf528SMauro Carvalho Chehab } itd1000_lpf_pga[] = {
1009a0bf528SMauro Carvalho Chehab { 0, 0x8, 0x3 },
1019a0bf528SMauro Carvalho Chehab { 5200000, 0x8, 0x3 },
1029a0bf528SMauro Carvalho Chehab { 12200000, 0x4, 0x3 },
1039a0bf528SMauro Carvalho Chehab { 15400000, 0x2, 0x3 },
1049a0bf528SMauro Carvalho Chehab { 19800000, 0x2, 0x3 },
1059a0bf528SMauro Carvalho Chehab { 21500000, 0x2, 0x3 },
1069a0bf528SMauro Carvalho Chehab { 24500000, 0x2, 0x3 },
1079a0bf528SMauro Carvalho Chehab { 28400000, 0x2, 0x3 },
1089a0bf528SMauro Carvalho Chehab { 33400000, 0x2, 0x3 },
1099a0bf528SMauro Carvalho Chehab { 34400000, 0x1, 0x4 },
1109a0bf528SMauro Carvalho Chehab { 34400000, 0x1, 0x4 },
1119a0bf528SMauro Carvalho Chehab { 38400000, 0x1, 0x4 },
1129a0bf528SMauro Carvalho Chehab { 38400000, 0x1, 0x4 },
1139a0bf528SMauro Carvalho Chehab { 40400000, 0x1, 0x4 },
1149a0bf528SMauro Carvalho Chehab { 45400000, 0x1, 0x4 },
1159a0bf528SMauro Carvalho Chehab };
1169a0bf528SMauro Carvalho Chehab
itd1000_set_lpf_bw(struct itd1000_state * state,u32 symbol_rate)1179a0bf528SMauro Carvalho Chehab static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
1189a0bf528SMauro Carvalho Chehab {
1199a0bf528SMauro Carvalho Chehab u8 i;
1209a0bf528SMauro Carvalho Chehab u8 con1 = itd1000_read_reg(state, CON1) & 0xfd;
1219a0bf528SMauro Carvalho Chehab u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f;
1229a0bf528SMauro Carvalho Chehab u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
1239a0bf528SMauro Carvalho Chehab u8 bw = itd1000_read_reg(state, BW) & 0xf0;
1249a0bf528SMauro Carvalho Chehab
1259a0bf528SMauro Carvalho Chehab itd_dbg("symbol_rate = %d\n", symbol_rate);
1269a0bf528SMauro Carvalho Chehab
1279a0bf528SMauro Carvalho Chehab /* not sure what is that ? - starting to download the table */
1289a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, CON1, con1 | (1 << 1));
1299a0bf528SMauro Carvalho Chehab
1309a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
1319a0bf528SMauro Carvalho Chehab if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
1329a0bf528SMauro Carvalho Chehab itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
1339a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4));
1349a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
1359a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, BW, bw | (i & 0x0f));
1369a0bf528SMauro Carvalho Chehab break;
1379a0bf528SMauro Carvalho Chehab }
1389a0bf528SMauro Carvalho Chehab
1399a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, CON1, con1 | (0 << 1));
1409a0bf528SMauro Carvalho Chehab }
1419a0bf528SMauro Carvalho Chehab
1429a0bf528SMauro Carvalho Chehab static struct {
1439a0bf528SMauro Carvalho Chehab u8 vcorg;
1449a0bf528SMauro Carvalho Chehab u32 fmax_rg;
1459a0bf528SMauro Carvalho Chehab } itd1000_vcorg[] = {
1469a0bf528SMauro Carvalho Chehab { 1, 920000 },
1479a0bf528SMauro Carvalho Chehab { 2, 971000 },
1489a0bf528SMauro Carvalho Chehab { 3, 1031000 },
1499a0bf528SMauro Carvalho Chehab { 4, 1091000 },
1509a0bf528SMauro Carvalho Chehab { 5, 1171000 },
1519a0bf528SMauro Carvalho Chehab { 6, 1281000 },
1529a0bf528SMauro Carvalho Chehab { 7, 1381000 },
1539a0bf528SMauro Carvalho Chehab { 8, 500000 }, /* this is intentional. */
1549a0bf528SMauro Carvalho Chehab { 9, 1451000 },
1559a0bf528SMauro Carvalho Chehab { 10, 1531000 },
1569a0bf528SMauro Carvalho Chehab { 11, 1631000 },
1579a0bf528SMauro Carvalho Chehab { 12, 1741000 },
1589a0bf528SMauro Carvalho Chehab { 13, 1891000 },
1599a0bf528SMauro Carvalho Chehab { 14, 2071000 },
1609a0bf528SMauro Carvalho Chehab { 15, 2250000 },
1619a0bf528SMauro Carvalho Chehab };
1629a0bf528SMauro Carvalho Chehab
itd1000_set_vco(struct itd1000_state * state,u32 freq_khz)1639a0bf528SMauro Carvalho Chehab static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
1649a0bf528SMauro Carvalho Chehab {
1659a0bf528SMauro Carvalho Chehab u8 i;
1669a0bf528SMauro Carvalho Chehab u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
1679a0bf528SMauro Carvalho Chehab u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
1689a0bf528SMauro Carvalho Chehab u8 adcout;
1699a0bf528SMauro Carvalho Chehab
1709a0bf528SMauro Carvalho Chehab /* reserved bit again (reset ?) */
1719a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
1729a0bf528SMauro Carvalho Chehab
1739a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
1749a0bf528SMauro Carvalho Chehab if (freq_khz < itd1000_vcorg[i].fmax_rg) {
1759a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
1769a0bf528SMauro Carvalho Chehab msleep(1);
1779a0bf528SMauro Carvalho Chehab
1789a0bf528SMauro Carvalho Chehab adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
1799a0bf528SMauro Carvalho Chehab
1809a0bf528SMauro Carvalho Chehab itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
1819a0bf528SMauro Carvalho Chehab
1829a0bf528SMauro Carvalho Chehab if (adcout > 13) {
1839a0bf528SMauro Carvalho Chehab if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
1849a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
1859a0bf528SMauro Carvalho Chehab } else if (adcout < 2) {
1869a0bf528SMauro Carvalho Chehab if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
1879a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
1889a0bf528SMauro Carvalho Chehab }
1899a0bf528SMauro Carvalho Chehab break;
1909a0bf528SMauro Carvalho Chehab }
1919a0bf528SMauro Carvalho Chehab }
1929a0bf528SMauro Carvalho Chehab }
1939a0bf528SMauro Carvalho Chehab
1949a0bf528SMauro Carvalho Chehab static const struct {
1959a0bf528SMauro Carvalho Chehab u32 freq;
1969a0bf528SMauro Carvalho Chehab u8 values[10]; /* RFTR, RFST1 - RFST9 */
1979a0bf528SMauro Carvalho Chehab } itd1000_fre_values[] = {
1989a0bf528SMauro Carvalho Chehab { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
1999a0bf528SMauro Carvalho Chehab { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
2009a0bf528SMauro Carvalho Chehab { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
2019a0bf528SMauro Carvalho Chehab { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
2029a0bf528SMauro Carvalho Chehab { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
2039a0bf528SMauro Carvalho Chehab { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
2049a0bf528SMauro Carvalho Chehab { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
2059a0bf528SMauro Carvalho Chehab { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
2069a0bf528SMauro Carvalho Chehab { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
2079a0bf528SMauro Carvalho Chehab { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
2089a0bf528SMauro Carvalho Chehab };
2099a0bf528SMauro Carvalho Chehab
2109a0bf528SMauro Carvalho Chehab
2119a0bf528SMauro Carvalho Chehab #define FREF 16
2129a0bf528SMauro Carvalho Chehab
itd1000_set_lo(struct itd1000_state * state,u32 freq_khz)2139a0bf528SMauro Carvalho Chehab static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
2149a0bf528SMauro Carvalho Chehab {
2159a0bf528SMauro Carvalho Chehab int i, j;
2169a0bf528SMauro Carvalho Chehab u32 plln, pllf;
2179a0bf528SMauro Carvalho Chehab u64 tmp;
2189a0bf528SMauro Carvalho Chehab
2199a0bf528SMauro Carvalho Chehab plln = (freq_khz * 1000) / 2 / FREF;
2209a0bf528SMauro Carvalho Chehab
2219a0bf528SMauro Carvalho Chehab /* Compute the factional part times 1000 */
2229a0bf528SMauro Carvalho Chehab tmp = plln % 1000000;
2239a0bf528SMauro Carvalho Chehab plln /= 1000000;
2249a0bf528SMauro Carvalho Chehab
2259a0bf528SMauro Carvalho Chehab tmp *= 1048576;
2269a0bf528SMauro Carvalho Chehab do_div(tmp, 1000000);
2279a0bf528SMauro Carvalho Chehab pllf = (u32) tmp;
2289a0bf528SMauro Carvalho Chehab
2299a0bf528SMauro Carvalho Chehab state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
2309a0bf528SMauro Carvalho Chehab itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
2319a0bf528SMauro Carvalho Chehab
2321c4bbfd1SPeter Senna Tschudin itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
2339a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, PLLNL, plln & 0xff);
2349a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
2359a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
2369a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
2379a0bf528SMauro Carvalho Chehab
2389a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
2399a0bf528SMauro Carvalho Chehab if (freq_khz <= itd1000_fre_values[i].freq) {
2409a0bf528SMauro Carvalho Chehab itd_dbg("fre_values: %d\n", i);
2419a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
2429a0bf528SMauro Carvalho Chehab for (j = 0; j < 9; j++)
2439a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
2449a0bf528SMauro Carvalho Chehab break;
2459a0bf528SMauro Carvalho Chehab }
2469a0bf528SMauro Carvalho Chehab }
2479a0bf528SMauro Carvalho Chehab
2489a0bf528SMauro Carvalho Chehab itd1000_set_vco(state, freq_khz);
2499a0bf528SMauro Carvalho Chehab }
2509a0bf528SMauro Carvalho Chehab
itd1000_set_parameters(struct dvb_frontend * fe)2519a0bf528SMauro Carvalho Chehab static int itd1000_set_parameters(struct dvb_frontend *fe)
2529a0bf528SMauro Carvalho Chehab {
2539a0bf528SMauro Carvalho Chehab struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2549a0bf528SMauro Carvalho Chehab struct itd1000_state *state = fe->tuner_priv;
2559a0bf528SMauro Carvalho Chehab u8 pllcon1;
2569a0bf528SMauro Carvalho Chehab
2579a0bf528SMauro Carvalho Chehab itd1000_set_lo(state, c->frequency);
2589a0bf528SMauro Carvalho Chehab itd1000_set_lpf_bw(state, c->symbol_rate);
2599a0bf528SMauro Carvalho Chehab
2609a0bf528SMauro Carvalho Chehab pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
2619a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
2629a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, PLLCON1, pllcon1);
2639a0bf528SMauro Carvalho Chehab
2649a0bf528SMauro Carvalho Chehab return 0;
2659a0bf528SMauro Carvalho Chehab }
2669a0bf528SMauro Carvalho Chehab
itd1000_get_frequency(struct dvb_frontend * fe,u32 * frequency)2679a0bf528SMauro Carvalho Chehab static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
2689a0bf528SMauro Carvalho Chehab {
2699a0bf528SMauro Carvalho Chehab struct itd1000_state *state = fe->tuner_priv;
2709a0bf528SMauro Carvalho Chehab *frequency = state->frequency;
2719a0bf528SMauro Carvalho Chehab return 0;
2729a0bf528SMauro Carvalho Chehab }
2739a0bf528SMauro Carvalho Chehab
itd1000_get_bandwidth(struct dvb_frontend * fe,u32 * bandwidth)2749a0bf528SMauro Carvalho Chehab static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
2759a0bf528SMauro Carvalho Chehab {
2769a0bf528SMauro Carvalho Chehab return 0;
2779a0bf528SMauro Carvalho Chehab }
2789a0bf528SMauro Carvalho Chehab
2799a0bf528SMauro Carvalho Chehab static u8 itd1000_init_tab[][2] = {
2809a0bf528SMauro Carvalho Chehab { PLLCON1, 0x65 }, /* Register does not change */
2819a0bf528SMauro Carvalho Chehab { PLLNH, 0x80 }, /* Bits [7:6] do not change */
2829a0bf528SMauro Carvalho Chehab { RESERVED_0X6D, 0x3b },
2839a0bf528SMauro Carvalho Chehab { VCO_CHP2_I2C, 0x12 },
2849a0bf528SMauro Carvalho Chehab { 0x72, 0xf9 }, /* No such regsister defined */
2859a0bf528SMauro Carvalho Chehab { RESERVED_0X73, 0xff },
2869a0bf528SMauro Carvalho Chehab { RESERVED_0X74, 0xb2 },
2879a0bf528SMauro Carvalho Chehab { RESERVED_0X75, 0xc7 },
2889a0bf528SMauro Carvalho Chehab { EXTGVBBRF, 0xf0 },
2899a0bf528SMauro Carvalho Chehab { DIVAGCCK, 0x80 },
2909a0bf528SMauro Carvalho Chehab { BBTR, 0xa0 },
2919a0bf528SMauro Carvalho Chehab { RESERVED_0X7E, 0x4f },
2929a0bf528SMauro Carvalho Chehab { 0x82, 0x88 }, /* No such regsister defined */
2939a0bf528SMauro Carvalho Chehab { 0x83, 0x80 }, /* No such regsister defined */
2949a0bf528SMauro Carvalho Chehab { 0x84, 0x80 }, /* No such regsister defined */
2959a0bf528SMauro Carvalho Chehab { RESERVED_0X85, 0x74 },
2969a0bf528SMauro Carvalho Chehab { RESERVED_0X86, 0xff },
2979a0bf528SMauro Carvalho Chehab { RESERVED_0X88, 0x02 },
2989a0bf528SMauro Carvalho Chehab { RESERVED_0X89, 0x16 },
2999a0bf528SMauro Carvalho Chehab { RFST0, 0x1f },
3009a0bf528SMauro Carvalho Chehab { RESERVED_0X94, 0x66 },
3019a0bf528SMauro Carvalho Chehab { RESERVED_0X95, 0x66 },
3029a0bf528SMauro Carvalho Chehab { RESERVED_0X96, 0x77 },
3039a0bf528SMauro Carvalho Chehab { RESERVED_0X97, 0x99 },
3049a0bf528SMauro Carvalho Chehab { RESERVED_0X98, 0xff },
3059a0bf528SMauro Carvalho Chehab { RESERVED_0X99, 0xfc },
3069a0bf528SMauro Carvalho Chehab { RESERVED_0X9A, 0xba },
3079a0bf528SMauro Carvalho Chehab { RESERVED_0X9B, 0xaa },
3089a0bf528SMauro Carvalho Chehab };
3099a0bf528SMauro Carvalho Chehab
3109a0bf528SMauro Carvalho Chehab static u8 itd1000_reinit_tab[][2] = {
3119a0bf528SMauro Carvalho Chehab { VCO_CHP1_I2C, 0x8a },
3129a0bf528SMauro Carvalho Chehab { BW, 0x87 },
3139a0bf528SMauro Carvalho Chehab { GVBB_I2C, 0x03 },
3149a0bf528SMauro Carvalho Chehab { BBGVMIN, 0x03 },
3159a0bf528SMauro Carvalho Chehab { CON1, 0x2e },
3169a0bf528SMauro Carvalho Chehab };
3179a0bf528SMauro Carvalho Chehab
3189a0bf528SMauro Carvalho Chehab
itd1000_init(struct dvb_frontend * fe)3199a0bf528SMauro Carvalho Chehab static int itd1000_init(struct dvb_frontend *fe)
3209a0bf528SMauro Carvalho Chehab {
3219a0bf528SMauro Carvalho Chehab struct itd1000_state *state = fe->tuner_priv;
3229a0bf528SMauro Carvalho Chehab int i;
3239a0bf528SMauro Carvalho Chehab
3249a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
3259a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
3269a0bf528SMauro Carvalho Chehab
3279a0bf528SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
3289a0bf528SMauro Carvalho Chehab itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
3299a0bf528SMauro Carvalho Chehab
3309a0bf528SMauro Carvalho Chehab return 0;
3319a0bf528SMauro Carvalho Chehab }
3329a0bf528SMauro Carvalho Chehab
itd1000_sleep(struct dvb_frontend * fe)3339a0bf528SMauro Carvalho Chehab static int itd1000_sleep(struct dvb_frontend *fe)
3349a0bf528SMauro Carvalho Chehab {
3359a0bf528SMauro Carvalho Chehab return 0;
3369a0bf528SMauro Carvalho Chehab }
3379a0bf528SMauro Carvalho Chehab
itd1000_release(struct dvb_frontend * fe)338f2709c20SMauro Carvalho Chehab static void itd1000_release(struct dvb_frontend *fe)
339f2709c20SMauro Carvalho Chehab {
340f2709c20SMauro Carvalho Chehab kfree(fe->tuner_priv);
341f2709c20SMauro Carvalho Chehab fe->tuner_priv = NULL;
342f2709c20SMauro Carvalho Chehab }
343f2709c20SMauro Carvalho Chehab
3449a0bf528SMauro Carvalho Chehab static const struct dvb_tuner_ops itd1000_tuner_ops = {
3459a0bf528SMauro Carvalho Chehab .info = {
3469a0bf528SMauro Carvalho Chehab .name = "Integrant ITD1000",
347a3f90c75SMauro Carvalho Chehab .frequency_min_hz = 950 * MHz,
348a3f90c75SMauro Carvalho Chehab .frequency_max_hz = 2150 * MHz,
349a3f90c75SMauro Carvalho Chehab .frequency_step_hz = 125 * kHz,
3509a0bf528SMauro Carvalho Chehab },
3519a0bf528SMauro Carvalho Chehab
352f2709c20SMauro Carvalho Chehab .release = itd1000_release,
3539a0bf528SMauro Carvalho Chehab
3549a0bf528SMauro Carvalho Chehab .init = itd1000_init,
3559a0bf528SMauro Carvalho Chehab .sleep = itd1000_sleep,
3569a0bf528SMauro Carvalho Chehab
3579a0bf528SMauro Carvalho Chehab .set_params = itd1000_set_parameters,
3589a0bf528SMauro Carvalho Chehab .get_frequency = itd1000_get_frequency,
3599a0bf528SMauro Carvalho Chehab .get_bandwidth = itd1000_get_bandwidth
3609a0bf528SMauro Carvalho Chehab };
3619a0bf528SMauro Carvalho Chehab
3629a0bf528SMauro Carvalho Chehab
itd1000_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,struct itd1000_config * cfg)3639a0bf528SMauro Carvalho Chehab struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
3649a0bf528SMauro Carvalho Chehab {
3659a0bf528SMauro Carvalho Chehab struct itd1000_state *state = NULL;
3669a0bf528SMauro Carvalho Chehab u8 i = 0;
3679a0bf528SMauro Carvalho Chehab
3689a0bf528SMauro Carvalho Chehab state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
3699a0bf528SMauro Carvalho Chehab if (state == NULL)
3709a0bf528SMauro Carvalho Chehab return NULL;
3719a0bf528SMauro Carvalho Chehab
3729a0bf528SMauro Carvalho Chehab state->cfg = cfg;
3739a0bf528SMauro Carvalho Chehab state->i2c = i2c;
3749a0bf528SMauro Carvalho Chehab
3759a0bf528SMauro Carvalho Chehab i = itd1000_read_reg(state, 0);
3769a0bf528SMauro Carvalho Chehab if (i != 0) {
3779a0bf528SMauro Carvalho Chehab kfree(state);
3789a0bf528SMauro Carvalho Chehab return NULL;
3799a0bf528SMauro Carvalho Chehab }
3809a0bf528SMauro Carvalho Chehab itd_info("successfully identified (ID: %d)\n", i);
3819a0bf528SMauro Carvalho Chehab
3829a0bf528SMauro Carvalho Chehab memset(state->shadow, 0xff, sizeof(state->shadow));
3839a0bf528SMauro Carvalho Chehab for (i = 0x65; i < 0x9c; i++)
3849a0bf528SMauro Carvalho Chehab state->shadow[i] = itd1000_read_reg(state, i);
3859a0bf528SMauro Carvalho Chehab
3869a0bf528SMauro Carvalho Chehab memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
3879a0bf528SMauro Carvalho Chehab
3889a0bf528SMauro Carvalho Chehab fe->tuner_priv = state;
3899a0bf528SMauro Carvalho Chehab
3909a0bf528SMauro Carvalho Chehab return fe;
3919a0bf528SMauro Carvalho Chehab }
392*86495af1SGreg Kroah-Hartman EXPORT_SYMBOL_GPL(itd1000_attach);
3939a0bf528SMauro Carvalho Chehab
3949a0bf528SMauro Carvalho Chehab MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
3959a0bf528SMauro Carvalho Chehab MODULE_DESCRIPTION("Integrant ITD1000 driver");
3969a0bf528SMauro Carvalho Chehab MODULE_LICENSE("GPL");
397