1 #include "drxk_map.h" 2 3 #define DRXK_VERSION_MAJOR 0 4 #define DRXK_VERSION_MINOR 9 5 #define DRXK_VERSION_PATCH 4300 6 7 #define HI_I2C_DELAY 42 8 #define HI_I2C_BRIDGE_DELAY 350 9 #define DRXK_MAX_RETRIES 100 10 11 #define DRIVER_4400 1 12 13 #define DRXX_JTAGID 0x039210D9 14 #define DRXX_J_JTAGID 0x239310D9 15 #define DRXX_K_JTAGID 0x039210D9 16 17 #define DRX_UNKNOWN 254 18 #define DRX_AUTO 255 19 20 #define DRX_SCU_READY 0 21 #define DRXK_MAX_WAITTIME (200) 22 #define SCU_RESULT_OK 0 23 #define SCU_RESULT_SIZE -4 24 #define SCU_RESULT_INVPAR -3 25 #define SCU_RESULT_UNKSTD -2 26 #define SCU_RESULT_UNKCMD -1 27 28 #ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT 29 #define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) 30 #endif 31 32 #define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ 33 #define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ 34 #define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ 35 #define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ 36 #define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ 37 #define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ 38 #define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ 39 #define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ 40 41 #define IQM_CF_OUT_ENA_OFDM__M 0x4 42 #define IQM_FS_ADJ_SEL_B_QAM 0x1 43 #define IQM_FS_ADJ_SEL_B_OFF 0x0 44 #define IQM_FS_ADJ_SEL_B_VSB 0x2 45 #define IQM_RC_ADJ_SEL_B_OFF 0x0 46 #define IQM_RC_ADJ_SEL_B_QAM 0x1 47 #define IQM_RC_ADJ_SEL_B_VSB 0x2 48 49 enum operation_mode { 50 OM_NONE, 51 OM_QAM_ITU_A, 52 OM_QAM_ITU_B, 53 OM_QAM_ITU_C, 54 OM_DVBT 55 }; 56 57 enum drx_power_mode { 58 DRX_POWER_UP = 0, 59 DRX_POWER_MODE_1, 60 DRX_POWER_MODE_2, 61 DRX_POWER_MODE_3, 62 DRX_POWER_MODE_4, 63 DRX_POWER_MODE_5, 64 DRX_POWER_MODE_6, 65 DRX_POWER_MODE_7, 66 DRX_POWER_MODE_8, 67 68 DRX_POWER_MODE_9, 69 DRX_POWER_MODE_10, 70 DRX_POWER_MODE_11, 71 DRX_POWER_MODE_12, 72 DRX_POWER_MODE_13, 73 DRX_POWER_MODE_14, 74 DRX_POWER_MODE_15, 75 DRX_POWER_MODE_16, 76 DRX_POWER_DOWN = 255 77 }; 78 79 80 /* Intermediate power mode for DRXK, power down OFDM clock domain */ 81 #ifndef DRXK_POWER_DOWN_OFDM 82 #define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 83 #endif 84 85 /* Intermediate power mode for DRXK, power down core (sysclk) */ 86 #ifndef DRXK_POWER_DOWN_CORE 87 #define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 88 #endif 89 90 /* Intermediate power mode for DRXK, power down pll (only osc runs) */ 91 #ifndef DRXK_POWER_DOWN_PLL 92 #define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 93 #endif 94 95 96 enum agc_ctrl_mode { 97 DRXK_AGC_CTRL_AUTO = 0, 98 DRXK_AGC_CTRL_USER, 99 DRXK_AGC_CTRL_OFF 100 }; 101 102 enum e_drxk_state { 103 DRXK_UNINITIALIZED = 0, 104 DRXK_STOPPED, 105 DRXK_DTV_STARTED, 106 DRXK_ATV_STARTED, 107 DRXK_POWERED_DOWN, 108 DRXK_NO_DEV /* If drxk init failed */ 109 }; 110 111 enum e_drxk_coef_array_index { 112 DRXK_COEF_IDX_MN = 0, 113 DRXK_COEF_IDX_FM , 114 DRXK_COEF_IDX_L , 115 DRXK_COEF_IDX_LP , 116 DRXK_COEF_IDX_BG , 117 DRXK_COEF_IDX_DK , 118 DRXK_COEF_IDX_I , 119 DRXK_COEF_IDX_MAX 120 }; 121 enum e_drxk_sif_attenuation { 122 DRXK_SIF_ATTENUATION_0DB, 123 DRXK_SIF_ATTENUATION_3DB, 124 DRXK_SIF_ATTENUATION_6DB, 125 DRXK_SIF_ATTENUATION_9DB 126 }; 127 enum e_drxk_constellation { 128 DRX_CONSTELLATION_BPSK = 0, 129 DRX_CONSTELLATION_QPSK, 130 DRX_CONSTELLATION_PSK8, 131 DRX_CONSTELLATION_QAM16, 132 DRX_CONSTELLATION_QAM32, 133 DRX_CONSTELLATION_QAM64, 134 DRX_CONSTELLATION_QAM128, 135 DRX_CONSTELLATION_QAM256, 136 DRX_CONSTELLATION_QAM512, 137 DRX_CONSTELLATION_QAM1024, 138 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, 139 DRX_CONSTELLATION_AUTO = DRX_AUTO 140 }; 141 enum e_drxk_interleave_mode { 142 DRXK_QAM_I12_J17 = 16, 143 DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN 144 }; 145 enum { 146 DRXK_SPIN_A1 = 0, 147 DRXK_SPIN_A2, 148 DRXK_SPIN_A3, 149 DRXK_SPIN_UNKNOWN 150 }; 151 152 enum drxk_cfg_dvbt_sqi_speed { 153 DRXK_DVBT_SQI_SPEED_FAST = 0, 154 DRXK_DVBT_SQI_SPEED_MEDIUM, 155 DRXK_DVBT_SQI_SPEED_SLOW, 156 DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN 157 } ; 158 159 enum drx_fftmode_t { 160 DRX_FFTMODE_2K = 0, 161 DRX_FFTMODE_4K, 162 DRX_FFTMODE_8K, 163 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, 164 DRX_FFTMODE_AUTO = DRX_AUTO 165 }; 166 167 enum drxmpeg_str_width_t { 168 DRX_MPEG_STR_WIDTH_1, 169 DRX_MPEG_STR_WIDTH_8 170 }; 171 172 enum drx_qam_lock_range_t { 173 DRX_QAM_LOCKRANGE_NORMAL, 174 DRX_QAM_LOCKRANGE_EXTENDED 175 }; 176 177 struct drxk_cfg_dvbt_echo_thres_t { 178 u16 threshold; 179 enum drx_fftmode_t fft_mode; 180 } ; 181 182 struct s_cfg_agc { 183 enum agc_ctrl_mode ctrl_mode; /* off, user, auto */ 184 u16 output_level; /* range dependent on AGC */ 185 u16 min_output_level; /* range dependent on AGC */ 186 u16 max_output_level; /* range dependent on AGC */ 187 u16 speed; /* range dependent on AGC */ 188 u16 top; /* rf-agc take over point */ 189 u16 cut_off_current; /* rf-agc is accelerated if output current 190 is below cut-off current */ 191 u16 ingain_tgt_max; 192 u16 fast_clip_ctrl_delay; 193 }; 194 195 struct s_cfg_pre_saw { 196 u16 reference; /* pre SAW reference value, range 0 .. 31 */ 197 bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */ 198 }; 199 200 struct drxk_ofdm_sc_cmd_t { 201 u16 cmd; /* Command number */ 202 u16 subcmd; /* Sub-command parameter*/ 203 u16 param0; /* General purpous param */ 204 u16 param1; /* General purpous param */ 205 u16 param2; /* General purpous param */ 206 u16 param3; /* General purpous param */ 207 u16 param4; /* General purpous param */ 208 }; 209 210 struct drxk_state { 211 struct dvb_frontend frontend; 212 struct dtv_frontend_properties props; 213 struct device *dev; 214 215 struct i2c_adapter *i2c; 216 u8 demod_address; 217 void *priv; 218 219 struct mutex mutex; 220 221 u32 m_instance; /* Channel 1,2,3 or 4 */ 222 223 int m_chunk_size; 224 u8 chunk[256]; 225 226 bool m_has_lna; 227 bool m_has_dvbt; 228 bool m_has_dvbc; 229 bool m_has_audio; 230 bool m_has_atv; 231 bool m_has_oob; 232 bool m_has_sawsw; /* TRUE if mat_tx is available */ 233 bool m_has_gpio1; /* TRUE if mat_rx is available */ 234 bool m_has_gpio2; /* TRUE if GPIO is available */ 235 bool m_has_irqn; /* TRUE if IRQN is available */ 236 u16 m_osc_clock_freq; 237 u16 m_hi_cfg_timing_div; 238 u16 m_hi_cfg_bridge_delay; 239 u16 m_hi_cfg_wake_up_key; 240 u16 m_hi_cfg_timeout; 241 u16 m_hi_cfg_ctrl; 242 s32 m_sys_clock_freq; /* system clock frequency in kHz */ 243 244 enum e_drxk_state m_drxk_state; /* State of Drxk (init,stopped,started) */ 245 enum operation_mode m_operation_mode; /* digital standards */ 246 struct s_cfg_agc m_vsb_rf_agc_cfg; /* settings for VSB RF-AGC */ 247 struct s_cfg_agc m_vsb_if_agc_cfg; /* settings for VSB IF-AGC */ 248 u16 m_vsb_pga_cfg; /* settings for VSB PGA */ 249 struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /* settings for pre SAW sense */ 250 s32 m_Quality83percent; /* MER level (*0.1 dB) for 83% quality indication */ 251 s32 m_Quality93percent; /* MER level (*0.1 dB) for 93% quality indication */ 252 bool m_smart_ant_inverted; 253 bool m_b_debug_enable_bridge; 254 bool m_b_p_down_open_bridge; /* only open DRXK bridge before power-down once it has been accessed */ 255 bool m_b_power_down; /* Power down when not used */ 256 257 u32 m_iqm_fs_rate_ofs; /* frequency shift as written to DRXK register (28bit fixpoint) */ 258 259 bool m_enable_mpeg_output; /* If TRUE, enable MPEG output */ 260 bool m_insert_rs_byte; /* If TRUE, insert RS byte */ 261 bool m_enable_parallel; /* If TRUE, parallel out otherwise serial */ 262 bool m_invert_data; /* If TRUE, invert DATA signals */ 263 bool m_invert_err; /* If TRUE, invert ERR signal */ 264 bool m_invert_str; /* If TRUE, invert STR signals */ 265 bool m_invert_val; /* If TRUE, invert VAL signals */ 266 bool m_invert_clk; /* If TRUE, invert CLK signals */ 267 bool m_dvbc_static_clk; 268 bool m_dvbt_static_clk; /* If TRUE, static MPEG clockrate will 269 be used, otherwise clockrate will 270 adapt to the bitrate of the TS */ 271 u32 m_dvbt_bitrate; 272 u32 m_dvbc_bitrate; 273 274 u8 m_ts_data_strength; 275 u8 m_ts_clockk_strength; 276 277 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */ 278 279 enum drxmpeg_str_width_t m_width_str; /* MPEG start width */ 280 u32 m_mpeg_ts_static_bitrate; /* Maximum bitrate in b/s in case 281 static clockrate is selected */ 282 283 /* LARGE_INTEGER m_startTime; */ /* Contains the time of the last demod start */ 284 s32 m_mpeg_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */ 285 s32 m_demod_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */ 286 287 bool m_disable_te_ihandling; 288 289 bool m_rf_agc_pol; 290 bool m_if_agc_pol; 291 292 struct s_cfg_agc m_atv_rf_agc_cfg; /* settings for ATV RF-AGC */ 293 struct s_cfg_agc m_atv_if_agc_cfg; /* settings for ATV IF-AGC */ 294 struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */ 295 bool m_phase_correction_bypass; 296 s16 m_atv_top_vid_peak; 297 u16 m_atv_top_noise_th; 298 enum e_drxk_sif_attenuation m_sif_attenuation; 299 bool m_enable_cvbs_output; 300 bool m_enable_sif_output; 301 bool m_b_mirror_freq_spect; 302 enum e_drxk_constellation m_constellation; /* constellation type of the channel */ 303 u32 m_curr_symbol_rate; /* Current QAM symbol rate */ 304 struct s_cfg_agc m_qam_rf_agc_cfg; /* settings for QAM RF-AGC */ 305 struct s_cfg_agc m_qam_if_agc_cfg; /* settings for QAM IF-AGC */ 306 u16 m_qam_pga_cfg; /* settings for QAM PGA */ 307 struct s_cfg_pre_saw m_qam_pre_saw_cfg; /* settings for QAM pre SAW sense */ 308 enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */ 309 u16 m_fec_rs_plen; 310 u16 m_fec_rs_prescale; 311 312 enum drxk_cfg_dvbt_sqi_speed m_sqi_speed; 313 314 u16 m_gpio; 315 u16 m_gpio_cfg; 316 317 struct s_cfg_agc m_dvbt_rf_agc_cfg; /* settings for QAM RF-AGC */ 318 struct s_cfg_agc m_dvbt_if_agc_cfg; /* settings for QAM IF-AGC */ 319 struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /* settings for QAM pre SAW sense */ 320 321 u16 m_agcfast_clip_ctrl_delay; 322 bool m_adc_comp_passed; 323 u16 m_adcCompCoef[64]; 324 u16 m_adc_state; 325 326 u8 *m_microcode; 327 int m_microcode_length; 328 bool m_drxk_a3_rom_code; 329 bool m_drxk_a3_patch_code; 330 331 bool m_rfmirror; 332 u8 m_device_spin; 333 u32 m_iqm_rc_rate; 334 335 enum drx_power_mode m_current_power_mode; 336 337 /* when true, avoids other devices to use the I2C bus */ 338 bool drxk_i2c_exclusive_lock; 339 340 /* 341 * Configurable parameters at the driver. They stores the values found 342 * at struct drxk_config. 343 */ 344 345 u16 uio_mask; /* Bits used by UIO */ 346 347 bool enable_merr_cfg; 348 bool single_master; 349 bool no_i2c_bridge; 350 bool antenna_dvbt; 351 u16 antenna_gpio; 352 353 enum fe_status fe_status; 354 355 /* Firmware */ 356 const char *microcode_name; 357 struct completion fw_wait_load; 358 const struct firmware *fw; 359 int qam_demod_parameter_count; 360 }; 361 362 #define NEVER_LOCK 0 363 #define NOT_LOCKED 1 364 #define DEMOD_LOCK 2 365 #define FEC_LOCK 3 366 #define MPEG_LOCK 4 367 368