1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drxk_hard: DRX-K DVB-C/T demodulator driver 4 * 5 * Copyright (C) 2010-2011 Digital Devices GmbH 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/firmware.h> 16 #include <linux/i2c.h> 17 #include <linux/hardirq.h> 18 #include <asm/div64.h> 19 20 #include <media/dvb_frontend.h> 21 #include "drxk.h" 22 #include "drxk_hard.h" 23 #include <media/dvb_math.h> 24 25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode); 26 static int power_down_qam(struct drxk_state *state); 27 static int set_dvbt_standard(struct drxk_state *state, 28 enum operation_mode o_mode); 29 static int set_qam_standard(struct drxk_state *state, 30 enum operation_mode o_mode); 31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, 32 s32 tuner_freq_offset); 33 static int set_dvbt_standard(struct drxk_state *state, 34 enum operation_mode o_mode); 35 static int dvbt_start(struct drxk_state *state); 36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, 37 s32 tuner_freq_offset); 38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status); 39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status); 40 static int switch_antenna_to_qam(struct drxk_state *state); 41 static int switch_antenna_to_dvbt(struct drxk_state *state); 42 43 static bool is_dvbt(struct drxk_state *state) 44 { 45 return state->m_operation_mode == OM_DVBT; 46 } 47 48 static bool is_qam(struct drxk_state *state) 49 { 50 return state->m_operation_mode == OM_QAM_ITU_A || 51 state->m_operation_mode == OM_QAM_ITU_B || 52 state->m_operation_mode == OM_QAM_ITU_C; 53 } 54 55 #define NOA1ROM 0 56 57 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) 58 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) 59 60 #define DEFAULT_MER_83 165 61 #define DEFAULT_MER_93 250 62 63 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 64 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) 65 #endif 66 67 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 68 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) 69 #endif 70 71 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 72 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 73 74 #ifndef DRXK_KI_RAGC_ATV 75 #define DRXK_KI_RAGC_ATV 4 76 #endif 77 #ifndef DRXK_KI_IAGC_ATV 78 #define DRXK_KI_IAGC_ATV 6 79 #endif 80 #ifndef DRXK_KI_DAGC_ATV 81 #define DRXK_KI_DAGC_ATV 7 82 #endif 83 84 #ifndef DRXK_KI_RAGC_QAM 85 #define DRXK_KI_RAGC_QAM 3 86 #endif 87 #ifndef DRXK_KI_IAGC_QAM 88 #define DRXK_KI_IAGC_QAM 4 89 #endif 90 #ifndef DRXK_KI_DAGC_QAM 91 #define DRXK_KI_DAGC_QAM 7 92 #endif 93 #ifndef DRXK_KI_RAGC_DVBT 94 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) 95 #endif 96 #ifndef DRXK_KI_IAGC_DVBT 97 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) 98 #endif 99 #ifndef DRXK_KI_DAGC_DVBT 100 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) 101 #endif 102 103 #ifndef DRXK_AGC_DAC_OFFSET 104 #define DRXK_AGC_DAC_OFFSET (0x800) 105 #endif 106 107 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ 108 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) 109 #endif 110 111 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ 112 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) 113 #endif 114 115 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ 116 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) 117 #endif 118 119 #ifndef DRXK_QAM_SYMBOLRATE_MAX 120 #define DRXK_QAM_SYMBOLRATE_MAX (7233000) 121 #endif 122 123 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 124 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 125 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 126 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24 127 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 128 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 129 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48 130 #define DRXK_BL_ROM_OFFSET_UCODE 0 131 132 #define DRXK_BLC_TIMEOUT 100 133 134 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2 135 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6 136 137 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28 138 139 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH 140 #define DRXK_OFDM_NE_NOTCH_WIDTH (4) 141 #endif 142 143 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) 144 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) 145 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) 146 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) 147 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) 148 149 static unsigned int debug; 150 module_param(debug, int, 0644); 151 MODULE_PARM_DESC(debug, "enable debug messages"); 152 153 #define dprintk(level, fmt, arg...) do { \ 154 if (debug >= level) \ 155 printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \ 156 } while (0) 157 158 static inline u32 Frac28a(u32 a, u32 c) 159 { 160 int i = 0; 161 u32 Q1 = 0; 162 u32 R0 = 0; 163 164 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ 165 Q1 = a / c; /* 166 * integer part, only the 4 least significant 167 * bits will be visible in the result 168 */ 169 170 /* division using radix 16, 7 nibbles in the result */ 171 for (i = 0; i < 7; i++) { 172 Q1 = (Q1 << 4) | (R0 / c); 173 R0 = (R0 % c) << 4; 174 } 175 /* rounding */ 176 if ((R0 >> 3) >= c) 177 Q1++; 178 179 return Q1; 180 } 181 182 static inline u32 log10times100(u32 value) 183 { 184 return (100L * intlog10(value)) >> 24; 185 } 186 187 /***************************************************************************/ 188 /* I2C **********************************************************************/ 189 /***************************************************************************/ 190 191 static int drxk_i2c_lock(struct drxk_state *state) 192 { 193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT); 194 state->drxk_i2c_exclusive_lock = true; 195 196 return 0; 197 } 198 199 static void drxk_i2c_unlock(struct drxk_state *state) 200 { 201 if (!state->drxk_i2c_exclusive_lock) 202 return; 203 204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); 205 state->drxk_i2c_exclusive_lock = false; 206 } 207 208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, 209 unsigned len) 210 { 211 if (state->drxk_i2c_exclusive_lock) 212 return __i2c_transfer(state->i2c, msgs, len); 213 else 214 return i2c_transfer(state->i2c, msgs, len); 215 } 216 217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) 218 { 219 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, 220 .buf = val, .len = 1} 221 }; 222 223 return drxk_i2c_transfer(state, msgs, 1); 224 } 225 226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) 227 { 228 int status; 229 struct i2c_msg msg = { 230 .addr = adr, .flags = 0, .buf = data, .len = len }; 231 232 dprintk(3, ":"); 233 if (debug > 2) { 234 int i; 235 for (i = 0; i < len; i++) 236 pr_cont(" %02x", data[i]); 237 pr_cont("\n"); 238 } 239 status = drxk_i2c_transfer(state, &msg, 1); 240 if (status >= 0 && status != 1) 241 status = -EIO; 242 243 if (status < 0) 244 pr_err("i2c write error at addr 0x%02x\n", adr); 245 246 return status; 247 } 248 249 static int i2c_read(struct drxk_state *state, 250 u8 adr, u8 *msg, int len, u8 *answ, int alen) 251 { 252 int status; 253 struct i2c_msg msgs[2] = { 254 {.addr = adr, .flags = 0, 255 .buf = msg, .len = len}, 256 {.addr = adr, .flags = I2C_M_RD, 257 .buf = answ, .len = alen} 258 }; 259 260 status = drxk_i2c_transfer(state, msgs, 2); 261 if (status != 2) { 262 if (debug > 2) 263 pr_cont(": ERROR!\n"); 264 if (status >= 0) 265 status = -EIO; 266 267 pr_err("i2c read error at addr 0x%02x\n", adr); 268 return status; 269 } 270 if (debug > 2) { 271 int i; 272 dprintk(2, ": read from"); 273 for (i = 0; i < len; i++) 274 pr_cont(" %02x", msg[i]); 275 pr_cont(", value = "); 276 for (i = 0; i < alen; i++) 277 pr_cont(" %02x", answ[i]); 278 pr_cont("\n"); 279 } 280 return 0; 281 } 282 283 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) 284 { 285 int status; 286 u8 adr = state->demod_address, mm1[4], mm2[2], len; 287 288 if (state->single_master) 289 flags |= 0xC0; 290 291 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 292 mm1[0] = (((reg << 1) & 0xFF) | 0x01); 293 mm1[1] = ((reg >> 16) & 0xFF); 294 mm1[2] = ((reg >> 24) & 0xFF) | flags; 295 mm1[3] = ((reg >> 7) & 0xFF); 296 len = 4; 297 } else { 298 mm1[0] = ((reg << 1) & 0xFF); 299 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 300 len = 2; 301 } 302 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 303 status = i2c_read(state, adr, mm1, len, mm2, 2); 304 if (status < 0) 305 return status; 306 if (data) 307 *data = mm2[0] | (mm2[1] << 8); 308 309 return 0; 310 } 311 312 static int read16(struct drxk_state *state, u32 reg, u16 *data) 313 { 314 return read16_flags(state, reg, data, 0); 315 } 316 317 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) 318 { 319 int status; 320 u8 adr = state->demod_address, mm1[4], mm2[4], len; 321 322 if (state->single_master) 323 flags |= 0xC0; 324 325 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 326 mm1[0] = (((reg << 1) & 0xFF) | 0x01); 327 mm1[1] = ((reg >> 16) & 0xFF); 328 mm1[2] = ((reg >> 24) & 0xFF) | flags; 329 mm1[3] = ((reg >> 7) & 0xFF); 330 len = 4; 331 } else { 332 mm1[0] = ((reg << 1) & 0xFF); 333 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 334 len = 2; 335 } 336 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 337 status = i2c_read(state, adr, mm1, len, mm2, 4); 338 if (status < 0) 339 return status; 340 if (data) 341 *data = mm2[0] | (mm2[1] << 8) | 342 (mm2[2] << 16) | (mm2[3] << 24); 343 344 return 0; 345 } 346 347 static int read32(struct drxk_state *state, u32 reg, u32 *data) 348 { 349 return read32_flags(state, reg, data, 0); 350 } 351 352 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) 353 { 354 u8 adr = state->demod_address, mm[6], len; 355 356 if (state->single_master) 357 flags |= 0xC0; 358 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 359 mm[0] = (((reg << 1) & 0xFF) | 0x01); 360 mm[1] = ((reg >> 16) & 0xFF); 361 mm[2] = ((reg >> 24) & 0xFF) | flags; 362 mm[3] = ((reg >> 7) & 0xFF); 363 len = 4; 364 } else { 365 mm[0] = ((reg << 1) & 0xFF); 366 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 367 len = 2; 368 } 369 mm[len] = data & 0xff; 370 mm[len + 1] = (data >> 8) & 0xff; 371 372 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); 373 return i2c_write(state, adr, mm, len + 2); 374 } 375 376 static int write16(struct drxk_state *state, u32 reg, u16 data) 377 { 378 return write16_flags(state, reg, data, 0); 379 } 380 381 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) 382 { 383 u8 adr = state->demod_address, mm[8], len; 384 385 if (state->single_master) 386 flags |= 0xC0; 387 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 388 mm[0] = (((reg << 1) & 0xFF) | 0x01); 389 mm[1] = ((reg >> 16) & 0xFF); 390 mm[2] = ((reg >> 24) & 0xFF) | flags; 391 mm[3] = ((reg >> 7) & 0xFF); 392 len = 4; 393 } else { 394 mm[0] = ((reg << 1) & 0xFF); 395 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 396 len = 2; 397 } 398 mm[len] = data & 0xff; 399 mm[len + 1] = (data >> 8) & 0xff; 400 mm[len + 2] = (data >> 16) & 0xff; 401 mm[len + 3] = (data >> 24) & 0xff; 402 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); 403 404 return i2c_write(state, adr, mm, len + 4); 405 } 406 407 static int write32(struct drxk_state *state, u32 reg, u32 data) 408 { 409 return write32_flags(state, reg, data, 0); 410 } 411 412 static int write_block(struct drxk_state *state, u32 address, 413 const int block_size, const u8 p_block[]) 414 { 415 int status = 0, blk_size = block_size; 416 u8 flags = 0; 417 418 if (state->single_master) 419 flags |= 0xC0; 420 421 while (blk_size > 0) { 422 int chunk = blk_size > state->m_chunk_size ? 423 state->m_chunk_size : blk_size; 424 u8 *adr_buf = &state->chunk[0]; 425 u32 adr_length = 0; 426 427 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) { 428 adr_buf[0] = (((address << 1) & 0xFF) | 0x01); 429 adr_buf[1] = ((address >> 16) & 0xFF); 430 adr_buf[2] = ((address >> 24) & 0xFF); 431 adr_buf[3] = ((address >> 7) & 0xFF); 432 adr_buf[2] |= flags; 433 adr_length = 4; 434 if (chunk == state->m_chunk_size) 435 chunk -= 2; 436 } else { 437 adr_buf[0] = ((address << 1) & 0xFF); 438 adr_buf[1] = (((address >> 16) & 0x0F) | 439 ((address >> 18) & 0xF0)); 440 adr_length = 2; 441 } 442 memcpy(&state->chunk[adr_length], p_block, chunk); 443 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags); 444 if (debug > 1) { 445 int i; 446 if (p_block) 447 for (i = 0; i < chunk; i++) 448 pr_cont(" %02x", p_block[i]); 449 pr_cont("\n"); 450 } 451 status = i2c_write(state, state->demod_address, 452 &state->chunk[0], chunk + adr_length); 453 if (status < 0) { 454 pr_err("%s: i2c write error at addr 0x%02x\n", 455 __func__, address); 456 break; 457 } 458 p_block += chunk; 459 address += (chunk >> 1); 460 blk_size -= chunk; 461 } 462 return status; 463 } 464 465 #ifndef DRXK_MAX_RETRIES_POWERUP 466 #define DRXK_MAX_RETRIES_POWERUP 20 467 #endif 468 469 static int power_up_device(struct drxk_state *state) 470 { 471 int status; 472 u8 data = 0; 473 u16 retry_count = 0; 474 475 dprintk(1, "\n"); 476 477 status = i2c_read1(state, state->demod_address, &data); 478 if (status < 0) { 479 do { 480 data = 0; 481 status = i2c_write(state, state->demod_address, 482 &data, 1); 483 usleep_range(10000, 11000); 484 retry_count++; 485 if (status < 0) 486 continue; 487 status = i2c_read1(state, state->demod_address, 488 &data); 489 } while (status < 0 && 490 (retry_count < DRXK_MAX_RETRIES_POWERUP)); 491 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP) 492 goto error; 493 } 494 495 /* Make sure all clk domains are active */ 496 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); 497 if (status < 0) 498 goto error; 499 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 500 if (status < 0) 501 goto error; 502 /* Enable pll lock tests */ 503 status = write16(state, SIO_CC_PLL_LOCK__A, 1); 504 if (status < 0) 505 goto error; 506 507 state->m_current_power_mode = DRX_POWER_UP; 508 509 error: 510 if (status < 0) 511 pr_err("Error %d on %s\n", status, __func__); 512 513 return status; 514 } 515 516 517 static int init_state(struct drxk_state *state) 518 { 519 /* 520 * FIXME: most (all?) of the values below should be moved into 521 * struct drxk_config, as they are probably board-specific 522 */ 523 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO; 524 u32 ul_vsb_if_agc_output_level = 0; 525 u32 ul_vsb_if_agc_min_level = 0; 526 u32 ul_vsb_if_agc_max_level = 0x7FFF; 527 u32 ul_vsb_if_agc_speed = 3; 528 529 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO; 530 u32 ul_vsb_rf_agc_output_level = 0; 531 u32 ul_vsb_rf_agc_min_level = 0; 532 u32 ul_vsb_rf_agc_max_level = 0x7FFF; 533 u32 ul_vsb_rf_agc_speed = 3; 534 u32 ul_vsb_rf_agc_top = 9500; 535 u32 ul_vsb_rf_agc_cut_off_current = 4000; 536 537 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO; 538 u32 ul_atv_if_agc_output_level = 0; 539 u32 ul_atv_if_agc_min_level = 0; 540 u32 ul_atv_if_agc_max_level = 0; 541 u32 ul_atv_if_agc_speed = 3; 542 543 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF; 544 u32 ul_atv_rf_agc_output_level = 0; 545 u32 ul_atv_rf_agc_min_level = 0; 546 u32 ul_atv_rf_agc_max_level = 0; 547 u32 ul_atv_rf_agc_top = 9500; 548 u32 ul_atv_rf_agc_cut_off_current = 4000; 549 u32 ul_atv_rf_agc_speed = 3; 550 551 u32 ulQual83 = DEFAULT_MER_83; 552 u32 ulQual93 = DEFAULT_MER_93; 553 554 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 555 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 556 557 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 558 /* io_pad_cfg_mode output mode is drive always */ 559 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 560 u32 ul_gpio_cfg = 0x0113; 561 u32 ul_invert_ts_clock = 0; 562 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; 563 u32 ul_dvbt_bitrate = 50000000; 564 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; 565 566 u32 ul_insert_rs_byte = 0; 567 568 u32 ul_rf_mirror = 1; 569 u32 ul_power_down = 0; 570 571 dprintk(1, "\n"); 572 573 state->m_has_lna = false; 574 state->m_has_dvbt = false; 575 state->m_has_dvbc = false; 576 state->m_has_atv = false; 577 state->m_has_oob = false; 578 state->m_has_audio = false; 579 580 if (!state->m_chunk_size) 581 state->m_chunk_size = 124; 582 583 state->m_osc_clock_freq = 0; 584 state->m_smart_ant_inverted = false; 585 state->m_b_p_down_open_bridge = false; 586 587 /* real system clock frequency in kHz */ 588 state->m_sys_clock_freq = 151875; 589 /* Timing div, 250ns/Psys */ 590 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ 591 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * 592 HI_I2C_DELAY) / 1000; 593 /* Clipping */ 594 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) 595 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; 596 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); 597 /* port/bridge/power down ctrl */ 598 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 599 600 state->m_b_power_down = (ul_power_down != 0); 601 602 state->m_drxk_a3_patch_code = false; 603 604 /* Init AGC and PGA parameters */ 605 /* VSB IF */ 606 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; 607 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; 608 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; 609 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; 610 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; 611 state->m_vsb_pga_cfg = 140; 612 613 /* VSB RF */ 614 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; 615 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; 616 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; 617 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; 618 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; 619 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; 620 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; 621 state->m_vsb_pre_saw_cfg.reference = 0x07; 622 state->m_vsb_pre_saw_cfg.use_pre_saw = true; 623 624 state->m_Quality83percent = DEFAULT_MER_83; 625 state->m_Quality93percent = DEFAULT_MER_93; 626 if (ulQual93 <= 500 && ulQual83 < ulQual93) { 627 state->m_Quality83percent = ulQual83; 628 state->m_Quality93percent = ulQual93; 629 } 630 631 /* ATV IF */ 632 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; 633 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; 634 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; 635 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; 636 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; 637 638 /* ATV RF */ 639 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; 640 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; 641 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; 642 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; 643 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; 644 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; 645 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; 646 state->m_atv_pre_saw_cfg.reference = 0x04; 647 state->m_atv_pre_saw_cfg.use_pre_saw = true; 648 649 650 /* DVBT RF */ 651 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; 652 state->m_dvbt_rf_agc_cfg.output_level = 0; 653 state->m_dvbt_rf_agc_cfg.min_output_level = 0; 654 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; 655 state->m_dvbt_rf_agc_cfg.top = 0x2100; 656 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; 657 state->m_dvbt_rf_agc_cfg.speed = 1; 658 659 660 /* DVBT IF */ 661 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; 662 state->m_dvbt_if_agc_cfg.output_level = 0; 663 state->m_dvbt_if_agc_cfg.min_output_level = 0; 664 state->m_dvbt_if_agc_cfg.max_output_level = 9000; 665 state->m_dvbt_if_agc_cfg.top = 13424; 666 state->m_dvbt_if_agc_cfg.cut_off_current = 0; 667 state->m_dvbt_if_agc_cfg.speed = 3; 668 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; 669 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; 670 /* state->m_dvbtPgaCfg = 140; */ 671 672 state->m_dvbt_pre_saw_cfg.reference = 4; 673 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; 674 675 /* QAM RF */ 676 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; 677 state->m_qam_rf_agc_cfg.output_level = 0; 678 state->m_qam_rf_agc_cfg.min_output_level = 6023; 679 state->m_qam_rf_agc_cfg.max_output_level = 27000; 680 state->m_qam_rf_agc_cfg.top = 0x2380; 681 state->m_qam_rf_agc_cfg.cut_off_current = 4000; 682 state->m_qam_rf_agc_cfg.speed = 3; 683 684 /* QAM IF */ 685 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; 686 state->m_qam_if_agc_cfg.output_level = 0; 687 state->m_qam_if_agc_cfg.min_output_level = 0; 688 state->m_qam_if_agc_cfg.max_output_level = 9000; 689 state->m_qam_if_agc_cfg.top = 0x0511; 690 state->m_qam_if_agc_cfg.cut_off_current = 0; 691 state->m_qam_if_agc_cfg.speed = 3; 692 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; 693 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; 694 695 state->m_qam_pga_cfg = 140; 696 state->m_qam_pre_saw_cfg.reference = 4; 697 state->m_qam_pre_saw_cfg.use_pre_saw = false; 698 699 state->m_operation_mode = OM_NONE; 700 state->m_drxk_state = DRXK_UNINITIALIZED; 701 702 /* MPEG output configuration */ 703 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */ 704 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ 705 state->m_invert_data = false; /* If TRUE; invert DATA signals */ 706 state->m_invert_err = false; /* If TRUE; invert ERR signal */ 707 state->m_invert_str = false; /* If TRUE; invert STR signals */ 708 state->m_invert_val = false; /* If TRUE; invert VAL signals */ 709 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ 710 711 /* If TRUE; static MPEG clockrate will be used; 712 otherwise clockrate will adapt to the bitrate of the TS */ 713 714 state->m_dvbt_bitrate = ul_dvbt_bitrate; 715 state->m_dvbc_bitrate = ul_dvbc_bitrate; 716 717 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); 718 719 /* Maximum bitrate in b/s in case static clockrate is selected */ 720 state->m_mpeg_ts_static_bitrate = 19392658; 721 state->m_disable_te_ihandling = false; 722 723 if (ul_insert_rs_byte) 724 state->m_insert_rs_byte = true; 725 726 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 727 if (ul_mpeg_lock_time_out < 10000) 728 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; 729 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 730 if (ul_demod_lock_time_out < 10000) 731 state->m_demod_lock_time_out = ul_demod_lock_time_out; 732 733 /* QAM defaults */ 734 state->m_constellation = DRX_CONSTELLATION_AUTO; 735 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; 736 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ 737 state->m_fec_rs_prescale = 1; 738 739 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; 740 state->m_agcfast_clip_ctrl_delay = 0; 741 742 state->m_gpio_cfg = ul_gpio_cfg; 743 744 state->m_b_power_down = false; 745 state->m_current_power_mode = DRX_POWER_DOWN; 746 747 state->m_rfmirror = (ul_rf_mirror == 0); 748 state->m_if_agc_pol = false; 749 return 0; 750 } 751 752 static int drxx_open(struct drxk_state *state) 753 { 754 int status = 0; 755 u32 jtag = 0; 756 u16 bid = 0; 757 u16 key = 0; 758 759 dprintk(1, "\n"); 760 /* stop lock indicator process */ 761 status = write16(state, SCU_RAM_GPIO__A, 762 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 763 if (status < 0) 764 goto error; 765 /* Check device id */ 766 status = read16(state, SIO_TOP_COMM_KEY__A, &key); 767 if (status < 0) 768 goto error; 769 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 770 if (status < 0) 771 goto error; 772 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); 773 if (status < 0) 774 goto error; 775 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); 776 if (status < 0) 777 goto error; 778 status = write16(state, SIO_TOP_COMM_KEY__A, key); 779 error: 780 if (status < 0) 781 pr_err("Error %d on %s\n", status, __func__); 782 return status; 783 } 784 785 static int get_device_capabilities(struct drxk_state *state) 786 { 787 u16 sio_pdr_ohw_cfg = 0; 788 u32 sio_top_jtagid_lo = 0; 789 int status; 790 const char *spin = ""; 791 792 dprintk(1, "\n"); 793 794 /* driver 0.9.0 */ 795 /* stop lock indicator process */ 796 status = write16(state, SCU_RAM_GPIO__A, 797 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 798 if (status < 0) 799 goto error; 800 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 801 if (status < 0) 802 goto error; 803 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); 804 if (status < 0) 805 goto error; 806 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 807 if (status < 0) 808 goto error; 809 810 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { 811 case 0: 812 /* ignore (bypass ?) */ 813 break; 814 case 1: 815 /* 27 MHz */ 816 state->m_osc_clock_freq = 27000; 817 break; 818 case 2: 819 /* 20.25 MHz */ 820 state->m_osc_clock_freq = 20250; 821 break; 822 case 3: 823 /* 4 MHz */ 824 state->m_osc_clock_freq = 20250; 825 break; 826 default: 827 pr_err("Clock Frequency is unknown\n"); 828 return -EINVAL; 829 } 830 /* 831 Determine device capabilities 832 Based on pinning v14 833 */ 834 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); 835 if (status < 0) 836 goto error; 837 838 pr_info("status = 0x%08x\n", sio_top_jtagid_lo); 839 840 /* driver 0.9.0 */ 841 switch ((sio_top_jtagid_lo >> 29) & 0xF) { 842 case 0: 843 state->m_device_spin = DRXK_SPIN_A1; 844 spin = "A1"; 845 break; 846 case 2: 847 state->m_device_spin = DRXK_SPIN_A2; 848 spin = "A2"; 849 break; 850 case 3: 851 state->m_device_spin = DRXK_SPIN_A3; 852 spin = "A3"; 853 break; 854 default: 855 state->m_device_spin = DRXK_SPIN_UNKNOWN; 856 status = -EINVAL; 857 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF); 858 goto error2; 859 } 860 switch ((sio_top_jtagid_lo >> 12) & 0xFF) { 861 case 0x13: 862 /* typeId = DRX3913K_TYPE_ID */ 863 state->m_has_lna = false; 864 state->m_has_oob = false; 865 state->m_has_atv = false; 866 state->m_has_audio = false; 867 state->m_has_dvbt = true; 868 state->m_has_dvbc = true; 869 state->m_has_sawsw = true; 870 state->m_has_gpio2 = false; 871 state->m_has_gpio1 = false; 872 state->m_has_irqn = false; 873 break; 874 case 0x15: 875 /* typeId = DRX3915K_TYPE_ID */ 876 state->m_has_lna = false; 877 state->m_has_oob = false; 878 state->m_has_atv = true; 879 state->m_has_audio = false; 880 state->m_has_dvbt = true; 881 state->m_has_dvbc = false; 882 state->m_has_sawsw = true; 883 state->m_has_gpio2 = true; 884 state->m_has_gpio1 = true; 885 state->m_has_irqn = false; 886 break; 887 case 0x16: 888 /* typeId = DRX3916K_TYPE_ID */ 889 state->m_has_lna = false; 890 state->m_has_oob = false; 891 state->m_has_atv = true; 892 state->m_has_audio = false; 893 state->m_has_dvbt = true; 894 state->m_has_dvbc = false; 895 state->m_has_sawsw = true; 896 state->m_has_gpio2 = true; 897 state->m_has_gpio1 = true; 898 state->m_has_irqn = false; 899 break; 900 case 0x18: 901 /* typeId = DRX3918K_TYPE_ID */ 902 state->m_has_lna = false; 903 state->m_has_oob = false; 904 state->m_has_atv = true; 905 state->m_has_audio = true; 906 state->m_has_dvbt = true; 907 state->m_has_dvbc = false; 908 state->m_has_sawsw = true; 909 state->m_has_gpio2 = true; 910 state->m_has_gpio1 = true; 911 state->m_has_irqn = false; 912 break; 913 case 0x21: 914 /* typeId = DRX3921K_TYPE_ID */ 915 state->m_has_lna = false; 916 state->m_has_oob = false; 917 state->m_has_atv = true; 918 state->m_has_audio = true; 919 state->m_has_dvbt = true; 920 state->m_has_dvbc = true; 921 state->m_has_sawsw = true; 922 state->m_has_gpio2 = true; 923 state->m_has_gpio1 = true; 924 state->m_has_irqn = false; 925 break; 926 case 0x23: 927 /* typeId = DRX3923K_TYPE_ID */ 928 state->m_has_lna = false; 929 state->m_has_oob = false; 930 state->m_has_atv = true; 931 state->m_has_audio = true; 932 state->m_has_dvbt = true; 933 state->m_has_dvbc = true; 934 state->m_has_sawsw = true; 935 state->m_has_gpio2 = true; 936 state->m_has_gpio1 = true; 937 state->m_has_irqn = false; 938 break; 939 case 0x25: 940 /* typeId = DRX3925K_TYPE_ID */ 941 state->m_has_lna = false; 942 state->m_has_oob = false; 943 state->m_has_atv = true; 944 state->m_has_audio = true; 945 state->m_has_dvbt = true; 946 state->m_has_dvbc = true; 947 state->m_has_sawsw = true; 948 state->m_has_gpio2 = true; 949 state->m_has_gpio1 = true; 950 state->m_has_irqn = false; 951 break; 952 case 0x26: 953 /* typeId = DRX3926K_TYPE_ID */ 954 state->m_has_lna = false; 955 state->m_has_oob = false; 956 state->m_has_atv = true; 957 state->m_has_audio = false; 958 state->m_has_dvbt = true; 959 state->m_has_dvbc = true; 960 state->m_has_sawsw = true; 961 state->m_has_gpio2 = true; 962 state->m_has_gpio1 = true; 963 state->m_has_irqn = false; 964 break; 965 default: 966 pr_err("DeviceID 0x%02x not supported\n", 967 ((sio_top_jtagid_lo >> 12) & 0xFF)); 968 status = -EINVAL; 969 goto error2; 970 } 971 972 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", 973 ((sio_top_jtagid_lo >> 12) & 0xFF), spin, 974 state->m_osc_clock_freq / 1000, 975 state->m_osc_clock_freq % 1000); 976 977 error: 978 if (status < 0) 979 pr_err("Error %d on %s\n", status, __func__); 980 981 error2: 982 return status; 983 } 984 985 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) 986 { 987 int status; 988 bool powerdown_cmd; 989 990 dprintk(1, "\n"); 991 992 /* Write command */ 993 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); 994 if (status < 0) 995 goto error; 996 if (cmd == SIO_HI_RA_RAM_CMD_RESET) 997 usleep_range(1000, 2000); 998 999 powerdown_cmd = 1000 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && 1001 ((state->m_hi_cfg_ctrl) & 1002 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == 1003 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); 1004 if (!powerdown_cmd) { 1005 /* Wait until command rdy */ 1006 u32 retry_count = 0; 1007 u16 wait_cmd; 1008 1009 do { 1010 usleep_range(1000, 2000); 1011 retry_count += 1; 1012 status = read16(state, SIO_HI_RA_RAM_CMD__A, 1013 &wait_cmd); 1014 } while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES)); 1015 if (status < 0) 1016 goto error; 1017 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); 1018 } 1019 error: 1020 if (status < 0) 1021 pr_err("Error %d on %s\n", status, __func__); 1022 1023 return status; 1024 } 1025 1026 static int hi_cfg_command(struct drxk_state *state) 1027 { 1028 int status; 1029 1030 dprintk(1, "\n"); 1031 1032 mutex_lock(&state->mutex); 1033 1034 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, 1035 state->m_hi_cfg_timeout); 1036 if (status < 0) 1037 goto error; 1038 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, 1039 state->m_hi_cfg_ctrl); 1040 if (status < 0) 1041 goto error; 1042 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, 1043 state->m_hi_cfg_wake_up_key); 1044 if (status < 0) 1045 goto error; 1046 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, 1047 state->m_hi_cfg_bridge_delay); 1048 if (status < 0) 1049 goto error; 1050 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 1051 state->m_hi_cfg_timing_div); 1052 if (status < 0) 1053 goto error; 1054 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, 1055 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 1056 if (status < 0) 1057 goto error; 1058 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); 1059 if (status < 0) 1060 goto error; 1061 1062 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1063 error: 1064 mutex_unlock(&state->mutex); 1065 if (status < 0) 1066 pr_err("Error %d on %s\n", status, __func__); 1067 return status; 1068 } 1069 1070 static int init_hi(struct drxk_state *state) 1071 { 1072 dprintk(1, "\n"); 1073 1074 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); 1075 state->m_hi_cfg_timeout = 0x96FF; 1076 /* port/bridge/power down ctrl */ 1077 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 1078 1079 return hi_cfg_command(state); 1080 } 1081 1082 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) 1083 { 1084 int status; 1085 u16 sio_pdr_mclk_cfg = 0; 1086 u16 sio_pdr_mdx_cfg = 0; 1087 u16 err_cfg = 0; 1088 1089 dprintk(1, ": mpeg %s, %s mode\n", 1090 mpeg_enable ? "enable" : "disable", 1091 state->m_enable_parallel ? "parallel" : "serial"); 1092 1093 /* stop lock indicator process */ 1094 status = write16(state, SCU_RAM_GPIO__A, 1095 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1096 if (status < 0) 1097 goto error; 1098 1099 /* MPEG TS pad configuration */ 1100 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 1101 if (status < 0) 1102 goto error; 1103 1104 if (!mpeg_enable) { 1105 /* Set MPEG TS pads to inputmode */ 1106 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); 1107 if (status < 0) 1108 goto error; 1109 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); 1110 if (status < 0) 1111 goto error; 1112 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); 1113 if (status < 0) 1114 goto error; 1115 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); 1116 if (status < 0) 1117 goto error; 1118 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); 1119 if (status < 0) 1120 goto error; 1121 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); 1122 if (status < 0) 1123 goto error; 1124 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); 1125 if (status < 0) 1126 goto error; 1127 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); 1128 if (status < 0) 1129 goto error; 1130 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); 1131 if (status < 0) 1132 goto error; 1133 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); 1134 if (status < 0) 1135 goto error; 1136 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); 1137 if (status < 0) 1138 goto error; 1139 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); 1140 if (status < 0) 1141 goto error; 1142 } else { 1143 /* Enable MPEG output */ 1144 sio_pdr_mdx_cfg = 1145 ((state->m_ts_data_strength << 1146 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); 1147 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << 1148 SIO_PDR_MCLK_CFG_DRIVE__B) | 1149 0x0003); 1150 1151 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); 1152 if (status < 0) 1153 goto error; 1154 1155 if (state->enable_merr_cfg) 1156 err_cfg = sio_pdr_mdx_cfg; 1157 1158 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); 1159 if (status < 0) 1160 goto error; 1161 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); 1162 if (status < 0) 1163 goto error; 1164 1165 if (state->m_enable_parallel) { 1166 /* parallel -> enable MD1 to MD7 */ 1167 status = write16(state, SIO_PDR_MD1_CFG__A, 1168 sio_pdr_mdx_cfg); 1169 if (status < 0) 1170 goto error; 1171 status = write16(state, SIO_PDR_MD2_CFG__A, 1172 sio_pdr_mdx_cfg); 1173 if (status < 0) 1174 goto error; 1175 status = write16(state, SIO_PDR_MD3_CFG__A, 1176 sio_pdr_mdx_cfg); 1177 if (status < 0) 1178 goto error; 1179 status = write16(state, SIO_PDR_MD4_CFG__A, 1180 sio_pdr_mdx_cfg); 1181 if (status < 0) 1182 goto error; 1183 status = write16(state, SIO_PDR_MD5_CFG__A, 1184 sio_pdr_mdx_cfg); 1185 if (status < 0) 1186 goto error; 1187 status = write16(state, SIO_PDR_MD6_CFG__A, 1188 sio_pdr_mdx_cfg); 1189 if (status < 0) 1190 goto error; 1191 status = write16(state, SIO_PDR_MD7_CFG__A, 1192 sio_pdr_mdx_cfg); 1193 if (status < 0) 1194 goto error; 1195 } else { 1196 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << 1197 SIO_PDR_MD0_CFG_DRIVE__B) 1198 | 0x0003); 1199 /* serial -> disable MD1 to MD7 */ 1200 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); 1201 if (status < 0) 1202 goto error; 1203 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); 1204 if (status < 0) 1205 goto error; 1206 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); 1207 if (status < 0) 1208 goto error; 1209 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); 1210 if (status < 0) 1211 goto error; 1212 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); 1213 if (status < 0) 1214 goto error; 1215 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); 1216 if (status < 0) 1217 goto error; 1218 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); 1219 if (status < 0) 1220 goto error; 1221 } 1222 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); 1223 if (status < 0) 1224 goto error; 1225 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); 1226 if (status < 0) 1227 goto error; 1228 } 1229 /* Enable MB output over MPEG pads and ctl input */ 1230 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); 1231 if (status < 0) 1232 goto error; 1233 /* Write nomagic word to enable pdr reg write */ 1234 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 1235 error: 1236 if (status < 0) 1237 pr_err("Error %d on %s\n", status, __func__); 1238 return status; 1239 } 1240 1241 static int mpegts_disable(struct drxk_state *state) 1242 { 1243 dprintk(1, "\n"); 1244 1245 return mpegts_configure_pins(state, false); 1246 } 1247 1248 static int bl_chain_cmd(struct drxk_state *state, 1249 u16 rom_offset, u16 nr_of_elements, u32 time_out) 1250 { 1251 u16 bl_status = 0; 1252 int status; 1253 unsigned long end; 1254 1255 dprintk(1, "\n"); 1256 mutex_lock(&state->mutex); 1257 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); 1258 if (status < 0) 1259 goto error; 1260 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); 1261 if (status < 0) 1262 goto error; 1263 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); 1264 if (status < 0) 1265 goto error; 1266 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 1267 if (status < 0) 1268 goto error; 1269 1270 end = jiffies + msecs_to_jiffies(time_out); 1271 do { 1272 usleep_range(1000, 2000); 1273 status = read16(state, SIO_BL_STATUS__A, &bl_status); 1274 if (status < 0) 1275 goto error; 1276 } while ((bl_status == 0x1) && 1277 ((time_is_after_jiffies(end)))); 1278 1279 if (bl_status == 0x1) { 1280 pr_err("SIO not ready\n"); 1281 status = -EINVAL; 1282 goto error2; 1283 } 1284 error: 1285 if (status < 0) 1286 pr_err("Error %d on %s\n", status, __func__); 1287 error2: 1288 mutex_unlock(&state->mutex); 1289 return status; 1290 } 1291 1292 1293 static int download_microcode(struct drxk_state *state, 1294 const u8 p_mc_image[], u32 length) 1295 { 1296 const u8 *p_src = p_mc_image; 1297 u32 address; 1298 u16 n_blocks; 1299 u16 block_size; 1300 u32 offset = 0; 1301 u32 i; 1302 int status = 0; 1303 1304 dprintk(1, "\n"); 1305 1306 /* down the drain (we don't care about MAGIC_WORD) */ 1307 #if 0 1308 /* For future reference */ 1309 drain = (p_src[0] << 8) | p_src[1]; 1310 #endif 1311 p_src += sizeof(u16); 1312 offset += sizeof(u16); 1313 n_blocks = (p_src[0] << 8) | p_src[1]; 1314 p_src += sizeof(u16); 1315 offset += sizeof(u16); 1316 1317 for (i = 0; i < n_blocks; i += 1) { 1318 address = (p_src[0] << 24) | (p_src[1] << 16) | 1319 (p_src[2] << 8) | p_src[3]; 1320 p_src += sizeof(u32); 1321 offset += sizeof(u32); 1322 1323 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16); 1324 p_src += sizeof(u16); 1325 offset += sizeof(u16); 1326 1327 #if 0 1328 /* For future reference */ 1329 flags = (p_src[0] << 8) | p_src[1]; 1330 #endif 1331 p_src += sizeof(u16); 1332 offset += sizeof(u16); 1333 1334 #if 0 1335 /* For future reference */ 1336 block_crc = (p_src[0] << 8) | p_src[1]; 1337 #endif 1338 p_src += sizeof(u16); 1339 offset += sizeof(u16); 1340 1341 if (offset + block_size > length) { 1342 pr_err("Firmware is corrupted.\n"); 1343 return -EINVAL; 1344 } 1345 1346 status = write_block(state, address, block_size, p_src); 1347 if (status < 0) { 1348 pr_err("Error %d while loading firmware\n", status); 1349 break; 1350 } 1351 p_src += block_size; 1352 offset += block_size; 1353 } 1354 return status; 1355 } 1356 1357 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) 1358 { 1359 int status; 1360 u16 data = 0; 1361 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; 1362 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; 1363 unsigned long end; 1364 1365 dprintk(1, "\n"); 1366 1367 if (!enable) { 1368 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; 1369 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; 1370 } 1371 1372 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1373 if (status >= 0 && data == desired_status) { 1374 /* tokenring already has correct status */ 1375 return status; 1376 } 1377 /* Disable/enable dvbt tokenring bridge */ 1378 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); 1379 1380 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1381 do { 1382 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1383 if ((status >= 0 && data == desired_status) 1384 || time_is_after_jiffies(end)) 1385 break; 1386 usleep_range(1000, 2000); 1387 } while (1); 1388 if (data != desired_status) { 1389 pr_err("SIO not ready\n"); 1390 return -EINVAL; 1391 } 1392 return status; 1393 } 1394 1395 static int mpegts_stop(struct drxk_state *state) 1396 { 1397 int status = 0; 1398 u16 fec_oc_snc_mode = 0; 1399 u16 fec_oc_ipr_mode = 0; 1400 1401 dprintk(1, "\n"); 1402 1403 /* Graceful shutdown (byte boundaries) */ 1404 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); 1405 if (status < 0) 1406 goto error; 1407 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M; 1408 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); 1409 if (status < 0) 1410 goto error; 1411 1412 /* Suppress MCLK during absence of data */ 1413 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); 1414 if (status < 0) 1415 goto error; 1416 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; 1417 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); 1418 1419 error: 1420 if (status < 0) 1421 pr_err("Error %d on %s\n", status, __func__); 1422 1423 return status; 1424 } 1425 1426 static int scu_command(struct drxk_state *state, 1427 u16 cmd, u8 parameter_len, 1428 u16 *parameter, u8 result_len, u16 *result) 1429 { 1430 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 1431 #error DRXK register mapping no longer compatible with this routine! 1432 #endif 1433 u16 cur_cmd = 0; 1434 int status = -EINVAL; 1435 unsigned long end; 1436 u8 buffer[34]; 1437 int cnt = 0, ii; 1438 const char *p; 1439 char errname[30]; 1440 1441 dprintk(1, "\n"); 1442 1443 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) || 1444 ((result_len > 0) && (result == NULL))) { 1445 pr_err("Error %d on %s\n", status, __func__); 1446 return status; 1447 } 1448 1449 mutex_lock(&state->mutex); 1450 1451 /* assume that the command register is ready 1452 since it is checked afterwards */ 1453 if (parameter) { 1454 for (ii = parameter_len - 1; ii >= 0; ii -= 1) { 1455 buffer[cnt++] = (parameter[ii] & 0xFF); 1456 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); 1457 } 1458 } 1459 buffer[cnt++] = (cmd & 0xFF); 1460 buffer[cnt++] = ((cmd >> 8) & 0xFF); 1461 1462 write_block(state, SCU_RAM_PARAM_0__A - 1463 (parameter_len - 1), cnt, buffer); 1464 /* Wait until SCU has processed command */ 1465 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); 1466 do { 1467 usleep_range(1000, 2000); 1468 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); 1469 if (status < 0) 1470 goto error; 1471 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); 1472 if (cur_cmd != DRX_SCU_READY) { 1473 pr_err("SCU not ready\n"); 1474 status = -EIO; 1475 goto error2; 1476 } 1477 /* read results */ 1478 if ((result_len > 0) && (result != NULL)) { 1479 s16 err; 1480 int ii; 1481 1482 for (ii = result_len - 1; ii >= 0; ii -= 1) { 1483 status = read16(state, SCU_RAM_PARAM_0__A - ii, 1484 &result[ii]); 1485 if (status < 0) 1486 goto error; 1487 } 1488 1489 /* Check if an error was reported by SCU */ 1490 err = (s16)result[0]; 1491 if (err >= 0) 1492 goto error; 1493 1494 /* check for the known error codes */ 1495 switch (err) { 1496 case SCU_RESULT_UNKCMD: 1497 p = "SCU_RESULT_UNKCMD"; 1498 break; 1499 case SCU_RESULT_UNKSTD: 1500 p = "SCU_RESULT_UNKSTD"; 1501 break; 1502 case SCU_RESULT_SIZE: 1503 p = "SCU_RESULT_SIZE"; 1504 break; 1505 case SCU_RESULT_INVPAR: 1506 p = "SCU_RESULT_INVPAR"; 1507 break; 1508 default: /* Other negative values are errors */ 1509 sprintf(errname, "ERROR: %d\n", err); 1510 p = errname; 1511 } 1512 pr_err("%s while sending cmd 0x%04x with params:", p, cmd); 1513 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt); 1514 status = -EINVAL; 1515 goto error2; 1516 } 1517 1518 error: 1519 if (status < 0) 1520 pr_err("Error %d on %s\n", status, __func__); 1521 error2: 1522 mutex_unlock(&state->mutex); 1523 return status; 1524 } 1525 1526 static int set_iqm_af(struct drxk_state *state, bool active) 1527 { 1528 u16 data = 0; 1529 int status; 1530 1531 dprintk(1, "\n"); 1532 1533 /* Configure IQM */ 1534 status = read16(state, IQM_AF_STDBY__A, &data); 1535 if (status < 0) 1536 goto error; 1537 1538 if (!active) { 1539 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY 1540 | IQM_AF_STDBY_STDBY_AMP_STANDBY 1541 | IQM_AF_STDBY_STDBY_PD_STANDBY 1542 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 1543 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY); 1544 } else { 1545 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) 1546 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) 1547 & (~IQM_AF_STDBY_STDBY_PD_STANDBY) 1548 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) 1549 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) 1550 ); 1551 } 1552 status = write16(state, IQM_AF_STDBY__A, data); 1553 1554 error: 1555 if (status < 0) 1556 pr_err("Error %d on %s\n", status, __func__); 1557 return status; 1558 } 1559 1560 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) 1561 { 1562 int status = 0; 1563 u16 sio_cc_pwd_mode = 0; 1564 1565 dprintk(1, "\n"); 1566 1567 /* Check arguments */ 1568 if (mode == NULL) 1569 return -EINVAL; 1570 1571 switch (*mode) { 1572 case DRX_POWER_UP: 1573 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; 1574 break; 1575 case DRXK_POWER_DOWN_OFDM: 1576 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM; 1577 break; 1578 case DRXK_POWER_DOWN_CORE: 1579 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; 1580 break; 1581 case DRXK_POWER_DOWN_PLL: 1582 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; 1583 break; 1584 case DRX_POWER_DOWN: 1585 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; 1586 break; 1587 default: 1588 /* Unknow sleep mode */ 1589 return -EINVAL; 1590 } 1591 1592 /* If already in requested power mode, do nothing */ 1593 if (state->m_current_power_mode == *mode) 1594 return 0; 1595 1596 /* For next steps make sure to start from DRX_POWER_UP mode */ 1597 if (state->m_current_power_mode != DRX_POWER_UP) { 1598 status = power_up_device(state); 1599 if (status < 0) 1600 goto error; 1601 status = dvbt_enable_ofdm_token_ring(state, true); 1602 if (status < 0) 1603 goto error; 1604 } 1605 1606 if (*mode == DRX_POWER_UP) { 1607 /* Restore analog & pin configuration */ 1608 } else { 1609 /* Power down to requested mode */ 1610 /* Backup some register settings */ 1611 /* Set pins with possible pull-ups connected 1612 to them in input mode */ 1613 /* Analog power down */ 1614 /* ADC power down */ 1615 /* Power down device */ 1616 /* stop all comm_exec */ 1617 /* Stop and power down previous standard */ 1618 switch (state->m_operation_mode) { 1619 case OM_DVBT: 1620 status = mpegts_stop(state); 1621 if (status < 0) 1622 goto error; 1623 status = power_down_dvbt(state, false); 1624 if (status < 0) 1625 goto error; 1626 break; 1627 case OM_QAM_ITU_A: 1628 case OM_QAM_ITU_C: 1629 status = mpegts_stop(state); 1630 if (status < 0) 1631 goto error; 1632 status = power_down_qam(state); 1633 if (status < 0) 1634 goto error; 1635 break; 1636 default: 1637 break; 1638 } 1639 status = dvbt_enable_ofdm_token_ring(state, false); 1640 if (status < 0) 1641 goto error; 1642 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); 1643 if (status < 0) 1644 goto error; 1645 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 1646 if (status < 0) 1647 goto error; 1648 1649 if (*mode != DRXK_POWER_DOWN_OFDM) { 1650 state->m_hi_cfg_ctrl |= 1651 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1652 status = hi_cfg_command(state); 1653 if (status < 0) 1654 goto error; 1655 } 1656 } 1657 state->m_current_power_mode = *mode; 1658 1659 error: 1660 if (status < 0) 1661 pr_err("Error %d on %s\n", status, __func__); 1662 1663 return status; 1664 } 1665 1666 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) 1667 { 1668 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 1669 u16 cmd_result = 0; 1670 u16 data = 0; 1671 int status; 1672 1673 dprintk(1, "\n"); 1674 1675 status = read16(state, SCU_COMM_EXEC__A, &data); 1676 if (status < 0) 1677 goto error; 1678 if (data == SCU_COMM_EXEC_ACTIVE) { 1679 /* Send OFDM stop command */ 1680 status = scu_command(state, 1681 SCU_RAM_COMMAND_STANDARD_OFDM 1682 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 1683 0, NULL, 1, &cmd_result); 1684 if (status < 0) 1685 goto error; 1686 /* Send OFDM reset command */ 1687 status = scu_command(state, 1688 SCU_RAM_COMMAND_STANDARD_OFDM 1689 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 1690 0, NULL, 1, &cmd_result); 1691 if (status < 0) 1692 goto error; 1693 } 1694 1695 /* Reset datapath for OFDM, processors first */ 1696 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 1697 if (status < 0) 1698 goto error; 1699 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 1700 if (status < 0) 1701 goto error; 1702 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 1703 if (status < 0) 1704 goto error; 1705 1706 /* powerdown AFE */ 1707 status = set_iqm_af(state, false); 1708 if (status < 0) 1709 goto error; 1710 1711 /* powerdown to OFDM mode */ 1712 if (set_power_mode) { 1713 status = ctrl_power_mode(state, &power_mode); 1714 if (status < 0) 1715 goto error; 1716 } 1717 error: 1718 if (status < 0) 1719 pr_err("Error %d on %s\n", status, __func__); 1720 return status; 1721 } 1722 1723 static int setoperation_mode(struct drxk_state *state, 1724 enum operation_mode o_mode) 1725 { 1726 int status = 0; 1727 1728 dprintk(1, "\n"); 1729 /* 1730 Stop and power down previous standard 1731 TODO investigate total power down instead of partial 1732 power down depending on "previous" standard. 1733 */ 1734 1735 /* disable HW lock indicator */ 1736 status = write16(state, SCU_RAM_GPIO__A, 1737 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1738 if (status < 0) 1739 goto error; 1740 1741 /* Device is already at the required mode */ 1742 if (state->m_operation_mode == o_mode) 1743 return 0; 1744 1745 switch (state->m_operation_mode) { 1746 /* OM_NONE was added for start up */ 1747 case OM_NONE: 1748 break; 1749 case OM_DVBT: 1750 status = mpegts_stop(state); 1751 if (status < 0) 1752 goto error; 1753 status = power_down_dvbt(state, true); 1754 if (status < 0) 1755 goto error; 1756 state->m_operation_mode = OM_NONE; 1757 break; 1758 case OM_QAM_ITU_A: 1759 case OM_QAM_ITU_C: 1760 status = mpegts_stop(state); 1761 if (status < 0) 1762 goto error; 1763 status = power_down_qam(state); 1764 if (status < 0) 1765 goto error; 1766 state->m_operation_mode = OM_NONE; 1767 break; 1768 case OM_QAM_ITU_B: 1769 default: 1770 status = -EINVAL; 1771 goto error; 1772 } 1773 1774 /* 1775 Power up new standard 1776 */ 1777 switch (o_mode) { 1778 case OM_DVBT: 1779 dprintk(1, ": DVB-T\n"); 1780 state->m_operation_mode = o_mode; 1781 status = set_dvbt_standard(state, o_mode); 1782 if (status < 0) 1783 goto error; 1784 break; 1785 case OM_QAM_ITU_A: 1786 case OM_QAM_ITU_C: 1787 dprintk(1, ": DVB-C Annex %c\n", 1788 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); 1789 state->m_operation_mode = o_mode; 1790 status = set_qam_standard(state, o_mode); 1791 if (status < 0) 1792 goto error; 1793 break; 1794 case OM_QAM_ITU_B: 1795 default: 1796 status = -EINVAL; 1797 } 1798 error: 1799 if (status < 0) 1800 pr_err("Error %d on %s\n", status, __func__); 1801 return status; 1802 } 1803 1804 static int start(struct drxk_state *state, s32 offset_freq, 1805 s32 intermediate_frequency) 1806 { 1807 int status = -EINVAL; 1808 1809 u16 i_freqk_hz; 1810 s32 offsetk_hz = offset_freq / 1000; 1811 1812 dprintk(1, "\n"); 1813 if (state->m_drxk_state != DRXK_STOPPED && 1814 state->m_drxk_state != DRXK_DTV_STARTED) 1815 goto error; 1816 1817 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); 1818 1819 if (intermediate_frequency < 0) { 1820 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; 1821 intermediate_frequency = -intermediate_frequency; 1822 } 1823 1824 switch (state->m_operation_mode) { 1825 case OM_QAM_ITU_A: 1826 case OM_QAM_ITU_C: 1827 i_freqk_hz = (intermediate_frequency / 1000); 1828 status = set_qam(state, i_freqk_hz, offsetk_hz); 1829 if (status < 0) 1830 goto error; 1831 state->m_drxk_state = DRXK_DTV_STARTED; 1832 break; 1833 case OM_DVBT: 1834 i_freqk_hz = (intermediate_frequency / 1000); 1835 status = mpegts_stop(state); 1836 if (status < 0) 1837 goto error; 1838 status = set_dvbt(state, i_freqk_hz, offsetk_hz); 1839 if (status < 0) 1840 goto error; 1841 status = dvbt_start(state); 1842 if (status < 0) 1843 goto error; 1844 state->m_drxk_state = DRXK_DTV_STARTED; 1845 break; 1846 default: 1847 break; 1848 } 1849 error: 1850 if (status < 0) 1851 pr_err("Error %d on %s\n", status, __func__); 1852 return status; 1853 } 1854 1855 static int shut_down(struct drxk_state *state) 1856 { 1857 dprintk(1, "\n"); 1858 1859 mpegts_stop(state); 1860 return 0; 1861 } 1862 1863 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) 1864 { 1865 int status = -EINVAL; 1866 1867 dprintk(1, "\n"); 1868 1869 if (p_lock_status == NULL) 1870 goto error; 1871 1872 *p_lock_status = NOT_LOCKED; 1873 1874 /* define the SCU command code */ 1875 switch (state->m_operation_mode) { 1876 case OM_QAM_ITU_A: 1877 case OM_QAM_ITU_B: 1878 case OM_QAM_ITU_C: 1879 status = get_qam_lock_status(state, p_lock_status); 1880 break; 1881 case OM_DVBT: 1882 status = get_dvbt_lock_status(state, p_lock_status); 1883 break; 1884 default: 1885 pr_debug("Unsupported operation mode %d in %s\n", 1886 state->m_operation_mode, __func__); 1887 return 0; 1888 } 1889 error: 1890 if (status < 0) 1891 pr_err("Error %d on %s\n", status, __func__); 1892 return status; 1893 } 1894 1895 static int mpegts_start(struct drxk_state *state) 1896 { 1897 int status; 1898 1899 u16 fec_oc_snc_mode = 0; 1900 1901 /* Allow OC to sync again */ 1902 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); 1903 if (status < 0) 1904 goto error; 1905 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; 1906 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); 1907 if (status < 0) 1908 goto error; 1909 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); 1910 error: 1911 if (status < 0) 1912 pr_err("Error %d on %s\n", status, __func__); 1913 return status; 1914 } 1915 1916 static int mpegts_dto_init(struct drxk_state *state) 1917 { 1918 int status; 1919 1920 dprintk(1, "\n"); 1921 1922 /* Rate integration settings */ 1923 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); 1924 if (status < 0) 1925 goto error; 1926 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); 1927 if (status < 0) 1928 goto error; 1929 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); 1930 if (status < 0) 1931 goto error; 1932 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); 1933 if (status < 0) 1934 goto error; 1935 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); 1936 if (status < 0) 1937 goto error; 1938 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); 1939 if (status < 0) 1940 goto error; 1941 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); 1942 if (status < 0) 1943 goto error; 1944 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); 1945 if (status < 0) 1946 goto error; 1947 1948 /* Additional configuration */ 1949 status = write16(state, FEC_OC_OCR_INVERT__A, 0); 1950 if (status < 0) 1951 goto error; 1952 status = write16(state, FEC_OC_SNC_LWM__A, 2); 1953 if (status < 0) 1954 goto error; 1955 status = write16(state, FEC_OC_SNC_HWM__A, 12); 1956 error: 1957 if (status < 0) 1958 pr_err("Error %d on %s\n", status, __func__); 1959 1960 return status; 1961 } 1962 1963 static int mpegts_dto_setup(struct drxk_state *state, 1964 enum operation_mode o_mode) 1965 { 1966 int status; 1967 1968 u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */ 1969 u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */ 1970 u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */ 1971 u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */ 1972 u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */ 1973 u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */ 1974 u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */ 1975 u16 fec_oc_tmd_mode = 0; 1976 u16 fec_oc_tmd_int_upd_rate = 0; 1977 u32 max_bit_rate = 0; 1978 bool static_clk = false; 1979 1980 dprintk(1, "\n"); 1981 1982 /* Check insertion of the Reed-Solomon parity bytes */ 1983 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); 1984 if (status < 0) 1985 goto error; 1986 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); 1987 if (status < 0) 1988 goto error; 1989 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); 1990 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); 1991 if (state->m_insert_rs_byte) { 1992 /* enable parity symbol forward */ 1993 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; 1994 /* MVAL disable during parity bytes */ 1995 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; 1996 /* TS burst length to 204 */ 1997 fec_oc_dto_burst_len = 204; 1998 } 1999 2000 /* Check serial or parallel output */ 2001 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); 2002 if (!state->m_enable_parallel) { 2003 /* MPEG data output is serial -> set ipr_mode[0] */ 2004 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; 2005 } 2006 2007 switch (o_mode) { 2008 case OM_DVBT: 2009 max_bit_rate = state->m_dvbt_bitrate; 2010 fec_oc_tmd_mode = 3; 2011 fec_oc_rcn_ctl_rate = 0xC00000; 2012 static_clk = state->m_dvbt_static_clk; 2013 break; 2014 case OM_QAM_ITU_A: 2015 case OM_QAM_ITU_C: 2016 fec_oc_tmd_mode = 0x0004; 2017 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */ 2018 max_bit_rate = state->m_dvbc_bitrate; 2019 static_clk = state->m_dvbc_static_clk; 2020 break; 2021 default: 2022 status = -EINVAL; 2023 } /* switch (standard) */ 2024 if (status < 0) 2025 goto error; 2026 2027 /* Configure DTO's */ 2028 if (static_clk) { 2029 u32 bit_rate = 0; 2030 2031 /* Rational DTO for MCLK source (static MCLK rate), 2032 Dynamic DTO for optimal grouping 2033 (avoid intra-packet gaps), 2034 DTO offset enable to sync TS burst with MSTRT */ 2035 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M | 2036 FEC_OC_DTO_MODE_OFFSET_ENABLE__M); 2037 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M | 2038 FEC_OC_FCT_MODE_VIRT_ENA__M); 2039 2040 /* Check user defined bitrate */ 2041 bit_rate = max_bit_rate; 2042 if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */ 2043 bit_rate = 75900000UL; 2044 } 2045 /* Rational DTO period: 2046 dto_period = (Fsys / bitrate) - 2 2047 2048 result should be floored, 2049 to make sure >= requested bitrate 2050 */ 2051 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) 2052 * 1000) / bit_rate); 2053 if (fec_oc_dto_period <= 2) 2054 fec_oc_dto_period = 0; 2055 else 2056 fec_oc_dto_period -= 2; 2057 fec_oc_tmd_int_upd_rate = 8; 2058 } else { 2059 /* (commonAttr->static_clk == false) => dynamic mode */ 2060 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M; 2061 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE; 2062 fec_oc_tmd_int_upd_rate = 5; 2063 } 2064 2065 /* Write appropriate registers with requested configuration */ 2066 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); 2067 if (status < 0) 2068 goto error; 2069 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); 2070 if (status < 0) 2071 goto error; 2072 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); 2073 if (status < 0) 2074 goto error; 2075 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); 2076 if (status < 0) 2077 goto error; 2078 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); 2079 if (status < 0) 2080 goto error; 2081 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); 2082 if (status < 0) 2083 goto error; 2084 2085 /* Rate integration settings */ 2086 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); 2087 if (status < 0) 2088 goto error; 2089 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, 2090 fec_oc_tmd_int_upd_rate); 2091 if (status < 0) 2092 goto error; 2093 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); 2094 error: 2095 if (status < 0) 2096 pr_err("Error %d on %s\n", status, __func__); 2097 return status; 2098 } 2099 2100 static int mpegts_configure_polarity(struct drxk_state *state) 2101 { 2102 u16 fec_oc_reg_ipr_invert = 0; 2103 2104 /* Data mask for the output data byte */ 2105 u16 invert_data_mask = 2106 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | 2107 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | 2108 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | 2109 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; 2110 2111 dprintk(1, "\n"); 2112 2113 /* Control selective inversion of output bits */ 2114 fec_oc_reg_ipr_invert &= (~(invert_data_mask)); 2115 if (state->m_invert_data) 2116 fec_oc_reg_ipr_invert |= invert_data_mask; 2117 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); 2118 if (state->m_invert_err) 2119 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; 2120 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); 2121 if (state->m_invert_str) 2122 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; 2123 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); 2124 if (state->m_invert_val) 2125 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; 2126 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); 2127 if (state->m_invert_clk) 2128 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; 2129 2130 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); 2131 } 2132 2133 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 2134 2135 static int set_agc_rf(struct drxk_state *state, 2136 struct s_cfg_agc *p_agc_cfg, bool is_dtv) 2137 { 2138 int status = -EINVAL; 2139 u16 data = 0; 2140 struct s_cfg_agc *p_if_agc_settings; 2141 2142 dprintk(1, "\n"); 2143 2144 if (p_agc_cfg == NULL) 2145 goto error; 2146 2147 switch (p_agc_cfg->ctrl_mode) { 2148 case DRXK_AGC_CTRL_AUTO: 2149 /* Enable RF AGC DAC */ 2150 status = read16(state, IQM_AF_STDBY__A, &data); 2151 if (status < 0) 2152 goto error; 2153 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2154 status = write16(state, IQM_AF_STDBY__A, data); 2155 if (status < 0) 2156 goto error; 2157 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2158 if (status < 0) 2159 goto error; 2160 2161 /* Enable SCU RF AGC loop */ 2162 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2163 2164 /* Polarity */ 2165 if (state->m_rf_agc_pol) 2166 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2167 else 2168 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2169 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2170 if (status < 0) 2171 goto error; 2172 2173 /* Set speed (using complementary reduction value) */ 2174 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2175 if (status < 0) 2176 goto error; 2177 2178 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; 2179 data |= (~(p_agc_cfg->speed << 2180 SCU_RAM_AGC_KI_RED_RAGC_RED__B) 2181 & SCU_RAM_AGC_KI_RED_RAGC_RED__M); 2182 2183 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2184 if (status < 0) 2185 goto error; 2186 2187 if (is_dvbt(state)) 2188 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; 2189 else if (is_qam(state)) 2190 p_if_agc_settings = &state->m_qam_if_agc_cfg; 2191 else 2192 p_if_agc_settings = &state->m_atv_if_agc_cfg; 2193 if (p_if_agc_settings == NULL) { 2194 status = -EINVAL; 2195 goto error; 2196 } 2197 2198 /* Set TOP, only if IF-AGC is in AUTO mode */ 2199 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) { 2200 status = write16(state, 2201 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2202 p_agc_cfg->top); 2203 if (status < 0) 2204 goto error; 2205 } 2206 2207 /* Cut-Off current */ 2208 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 2209 p_agc_cfg->cut_off_current); 2210 if (status < 0) 2211 goto error; 2212 2213 /* Max. output level */ 2214 status = write16(state, SCU_RAM_AGC_RF_MAX__A, 2215 p_agc_cfg->max_output_level); 2216 if (status < 0) 2217 goto error; 2218 2219 break; 2220 2221 case DRXK_AGC_CTRL_USER: 2222 /* Enable RF AGC DAC */ 2223 status = read16(state, IQM_AF_STDBY__A, &data); 2224 if (status < 0) 2225 goto error; 2226 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2227 status = write16(state, IQM_AF_STDBY__A, data); 2228 if (status < 0) 2229 goto error; 2230 2231 /* Disable SCU RF AGC loop */ 2232 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2233 if (status < 0) 2234 goto error; 2235 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2236 if (state->m_rf_agc_pol) 2237 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2238 else 2239 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2240 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2241 if (status < 0) 2242 goto error; 2243 2244 /* SCU c.o.c. to 0, enabling full control range */ 2245 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); 2246 if (status < 0) 2247 goto error; 2248 2249 /* Write value to output pin */ 2250 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 2251 p_agc_cfg->output_level); 2252 if (status < 0) 2253 goto error; 2254 break; 2255 2256 case DRXK_AGC_CTRL_OFF: 2257 /* Disable RF AGC DAC */ 2258 status = read16(state, IQM_AF_STDBY__A, &data); 2259 if (status < 0) 2260 goto error; 2261 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2262 status = write16(state, IQM_AF_STDBY__A, data); 2263 if (status < 0) 2264 goto error; 2265 2266 /* Disable SCU RF AGC loop */ 2267 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2268 if (status < 0) 2269 goto error; 2270 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2271 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2272 if (status < 0) 2273 goto error; 2274 break; 2275 2276 default: 2277 status = -EINVAL; 2278 2279 } 2280 error: 2281 if (status < 0) 2282 pr_err("Error %d on %s\n", status, __func__); 2283 return status; 2284 } 2285 2286 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 2287 2288 static int set_agc_if(struct drxk_state *state, 2289 struct s_cfg_agc *p_agc_cfg, bool is_dtv) 2290 { 2291 u16 data = 0; 2292 int status = 0; 2293 struct s_cfg_agc *p_rf_agc_settings; 2294 2295 dprintk(1, "\n"); 2296 2297 switch (p_agc_cfg->ctrl_mode) { 2298 case DRXK_AGC_CTRL_AUTO: 2299 2300 /* Enable IF AGC DAC */ 2301 status = read16(state, IQM_AF_STDBY__A, &data); 2302 if (status < 0) 2303 goto error; 2304 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2305 status = write16(state, IQM_AF_STDBY__A, data); 2306 if (status < 0) 2307 goto error; 2308 2309 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2310 if (status < 0) 2311 goto error; 2312 2313 /* Enable SCU IF AGC loop */ 2314 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2315 2316 /* Polarity */ 2317 if (state->m_if_agc_pol) 2318 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2319 else 2320 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2321 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2322 if (status < 0) 2323 goto error; 2324 2325 /* Set speed (using complementary reduction value) */ 2326 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2327 if (status < 0) 2328 goto error; 2329 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; 2330 data |= (~(p_agc_cfg->speed << 2331 SCU_RAM_AGC_KI_RED_IAGC_RED__B) 2332 & SCU_RAM_AGC_KI_RED_IAGC_RED__M); 2333 2334 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2335 if (status < 0) 2336 goto error; 2337 2338 if (is_qam(state)) 2339 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; 2340 else 2341 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; 2342 if (p_rf_agc_settings == NULL) 2343 return -1; 2344 /* Restore TOP */ 2345 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2346 p_rf_agc_settings->top); 2347 if (status < 0) 2348 goto error; 2349 break; 2350 2351 case DRXK_AGC_CTRL_USER: 2352 2353 /* Enable IF AGC DAC */ 2354 status = read16(state, IQM_AF_STDBY__A, &data); 2355 if (status < 0) 2356 goto error; 2357 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2358 status = write16(state, IQM_AF_STDBY__A, data); 2359 if (status < 0) 2360 goto error; 2361 2362 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2363 if (status < 0) 2364 goto error; 2365 2366 /* Disable SCU IF AGC loop */ 2367 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2368 2369 /* Polarity */ 2370 if (state->m_if_agc_pol) 2371 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2372 else 2373 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2374 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2375 if (status < 0) 2376 goto error; 2377 2378 /* Write value to output pin */ 2379 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2380 p_agc_cfg->output_level); 2381 if (status < 0) 2382 goto error; 2383 break; 2384 2385 case DRXK_AGC_CTRL_OFF: 2386 2387 /* Disable If AGC DAC */ 2388 status = read16(state, IQM_AF_STDBY__A, &data); 2389 if (status < 0) 2390 goto error; 2391 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2392 status = write16(state, IQM_AF_STDBY__A, data); 2393 if (status < 0) 2394 goto error; 2395 2396 /* Disable SCU IF AGC loop */ 2397 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2398 if (status < 0) 2399 goto error; 2400 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2401 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2402 if (status < 0) 2403 goto error; 2404 break; 2405 } /* switch (agcSettingsIf->ctrl_mode) */ 2406 2407 /* always set the top to support 2408 configurations without if-loop */ 2409 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); 2410 error: 2411 if (status < 0) 2412 pr_err("Error %d on %s\n", status, __func__); 2413 return status; 2414 } 2415 2416 static int get_qam_signal_to_noise(struct drxk_state *state, 2417 s32 *p_signal_to_noise) 2418 { 2419 int status = 0; 2420 u16 qam_sl_err_power = 0; /* accum. error between 2421 raw and sliced symbols */ 2422 u32 qam_sl_sig_power = 0; /* used for MER, depends of 2423 QAM modulation */ 2424 u32 qam_sl_mer = 0; /* QAM MER */ 2425 2426 dprintk(1, "\n"); 2427 2428 /* MER calculation */ 2429 2430 /* get the register value needed for MER */ 2431 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); 2432 if (status < 0) { 2433 pr_err("Error %d on %s\n", status, __func__); 2434 return -EINVAL; 2435 } 2436 2437 switch (state->props.modulation) { 2438 case QAM_16: 2439 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; 2440 break; 2441 case QAM_32: 2442 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; 2443 break; 2444 case QAM_64: 2445 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; 2446 break; 2447 case QAM_128: 2448 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; 2449 break; 2450 default: 2451 case QAM_256: 2452 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; 2453 break; 2454 } 2455 2456 if (qam_sl_err_power > 0) { 2457 qam_sl_mer = log10times100(qam_sl_sig_power) - 2458 log10times100((u32) qam_sl_err_power); 2459 } 2460 *p_signal_to_noise = qam_sl_mer; 2461 2462 return status; 2463 } 2464 2465 static int get_dvbt_signal_to_noise(struct drxk_state *state, 2466 s32 *p_signal_to_noise) 2467 { 2468 int status; 2469 u16 reg_data = 0; 2470 u32 eq_reg_td_sqr_err_i = 0; 2471 u32 eq_reg_td_sqr_err_q = 0; 2472 u16 eq_reg_td_sqr_err_exp = 0; 2473 u16 eq_reg_td_tps_pwr_ofs = 0; 2474 u16 eq_reg_td_req_smb_cnt = 0; 2475 u32 tps_cnt = 0; 2476 u32 sqr_err_iq = 0; 2477 u32 a = 0; 2478 u32 b = 0; 2479 u32 c = 0; 2480 u32 i_mer = 0; 2481 u16 transmission_params = 0; 2482 2483 dprintk(1, "\n"); 2484 2485 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, 2486 &eq_reg_td_tps_pwr_ofs); 2487 if (status < 0) 2488 goto error; 2489 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, 2490 &eq_reg_td_req_smb_cnt); 2491 if (status < 0) 2492 goto error; 2493 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, 2494 &eq_reg_td_sqr_err_exp); 2495 if (status < 0) 2496 goto error; 2497 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, 2498 ®_data); 2499 if (status < 0) 2500 goto error; 2501 /* Extend SQR_ERR_I operational range */ 2502 eq_reg_td_sqr_err_i = (u32) reg_data; 2503 if ((eq_reg_td_sqr_err_exp > 11) && 2504 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) { 2505 eq_reg_td_sqr_err_i += 0x00010000UL; 2506 } 2507 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); 2508 if (status < 0) 2509 goto error; 2510 /* Extend SQR_ERR_Q operational range */ 2511 eq_reg_td_sqr_err_q = (u32) reg_data; 2512 if ((eq_reg_td_sqr_err_exp > 11) && 2513 (eq_reg_td_sqr_err_q < 0x00000FFFUL)) 2514 eq_reg_td_sqr_err_q += 0x00010000UL; 2515 2516 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, 2517 &transmission_params); 2518 if (status < 0) 2519 goto error; 2520 2521 /* Check input data for MER */ 2522 2523 /* MER calculation (in 0.1 dB) without math.h */ 2524 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0)) 2525 i_mer = 0; 2526 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) { 2527 /* No error at all, this must be the HW reset value 2528 * Apparently no first measurement yet 2529 * Set MER to 0.0 */ 2530 i_mer = 0; 2531 } else { 2532 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) << 2533 eq_reg_td_sqr_err_exp; 2534 if ((transmission_params & 2535 OFDM_SC_RA_RAM_OP_PARAM_MODE__M) 2536 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) 2537 tps_cnt = 17; 2538 else 2539 tps_cnt = 68; 2540 2541 /* IMER = 100 * log10 (x) 2542 where x = (eq_reg_td_tps_pwr_ofs^2 * 2543 eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq 2544 2545 => IMER = a + b -c 2546 where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2) 2547 b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt) 2548 c = 100 * log10 (sqr_err_iq) 2549 */ 2550 2551 /* log(x) x = 9bits * 9bits->18 bits */ 2552 a = log10times100(eq_reg_td_tps_pwr_ofs * 2553 eq_reg_td_tps_pwr_ofs); 2554 /* log(x) x = 16bits * 7bits->23 bits */ 2555 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt); 2556 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ 2557 c = log10times100(sqr_err_iq); 2558 2559 i_mer = a + b - c; 2560 } 2561 *p_signal_to_noise = i_mer; 2562 2563 error: 2564 if (status < 0) 2565 pr_err("Error %d on %s\n", status, __func__); 2566 return status; 2567 } 2568 2569 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) 2570 { 2571 dprintk(1, "\n"); 2572 2573 *p_signal_to_noise = 0; 2574 switch (state->m_operation_mode) { 2575 case OM_DVBT: 2576 return get_dvbt_signal_to_noise(state, p_signal_to_noise); 2577 case OM_QAM_ITU_A: 2578 case OM_QAM_ITU_C: 2579 return get_qam_signal_to_noise(state, p_signal_to_noise); 2580 default: 2581 break; 2582 } 2583 return 0; 2584 } 2585 2586 #if 0 2587 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) 2588 { 2589 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ 2590 int status = 0; 2591 2592 dprintk(1, "\n"); 2593 2594 static s32 QE_SN[] = { 2595 51, /* QPSK 1/2 */ 2596 69, /* QPSK 2/3 */ 2597 79, /* QPSK 3/4 */ 2598 89, /* QPSK 5/6 */ 2599 97, /* QPSK 7/8 */ 2600 108, /* 16-QAM 1/2 */ 2601 131, /* 16-QAM 2/3 */ 2602 146, /* 16-QAM 3/4 */ 2603 156, /* 16-QAM 5/6 */ 2604 160, /* 16-QAM 7/8 */ 2605 165, /* 64-QAM 1/2 */ 2606 187, /* 64-QAM 2/3 */ 2607 202, /* 64-QAM 3/4 */ 2608 216, /* 64-QAM 5/6 */ 2609 225, /* 64-QAM 7/8 */ 2610 }; 2611 2612 *p_quality = 0; 2613 2614 do { 2615 s32 signal_to_noise = 0; 2616 u16 constellation = 0; 2617 u16 code_rate = 0; 2618 u32 signal_to_noise_rel; 2619 u32 ber_quality; 2620 2621 status = get_dvbt_signal_to_noise(state, &signal_to_noise); 2622 if (status < 0) 2623 break; 2624 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, 2625 &constellation); 2626 if (status < 0) 2627 break; 2628 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; 2629 2630 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, 2631 &code_rate); 2632 if (status < 0) 2633 break; 2634 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; 2635 2636 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || 2637 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) 2638 break; 2639 signal_to_noise_rel = signal_to_noise - 2640 QE_SN[constellation * 5 + code_rate]; 2641 ber_quality = 100; 2642 2643 if (signal_to_noise_rel < -70) 2644 *p_quality = 0; 2645 else if (signal_to_noise_rel < 30) 2646 *p_quality = ((signal_to_noise_rel + 70) * 2647 ber_quality) / 100; 2648 else 2649 *p_quality = ber_quality; 2650 } while (0); 2651 return 0; 2652 }; 2653 2654 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality) 2655 { 2656 int status = 0; 2657 *p_quality = 0; 2658 2659 dprintk(1, "\n"); 2660 2661 do { 2662 u32 signal_to_noise = 0; 2663 u32 ber_quality = 100; 2664 u32 signal_to_noise_rel = 0; 2665 2666 status = get_qam_signal_to_noise(state, &signal_to_noise); 2667 if (status < 0) 2668 break; 2669 2670 switch (state->props.modulation) { 2671 case QAM_16: 2672 signal_to_noise_rel = signal_to_noise - 200; 2673 break; 2674 case QAM_32: 2675 signal_to_noise_rel = signal_to_noise - 230; 2676 break; /* Not in NorDig */ 2677 case QAM_64: 2678 signal_to_noise_rel = signal_to_noise - 260; 2679 break; 2680 case QAM_128: 2681 signal_to_noise_rel = signal_to_noise - 290; 2682 break; 2683 default: 2684 case QAM_256: 2685 signal_to_noise_rel = signal_to_noise - 320; 2686 break; 2687 } 2688 2689 if (signal_to_noise_rel < -70) 2690 *p_quality = 0; 2691 else if (signal_to_noise_rel < 30) 2692 *p_quality = ((signal_to_noise_rel + 70) * 2693 ber_quality) / 100; 2694 else 2695 *p_quality = ber_quality; 2696 } while (0); 2697 2698 return status; 2699 } 2700 2701 static int get_quality(struct drxk_state *state, s32 *p_quality) 2702 { 2703 dprintk(1, "\n"); 2704 2705 switch (state->m_operation_mode) { 2706 case OM_DVBT: 2707 return get_dvbt_quality(state, p_quality); 2708 case OM_QAM_ITU_A: 2709 return get_dvbc_quality(state, p_quality); 2710 default: 2711 break; 2712 } 2713 2714 return 0; 2715 } 2716 #endif 2717 2718 /* Free data ram in SIO HI */ 2719 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 2720 #define SIO_HI_RA_RAM_USR_END__A 0x420060 2721 2722 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) 2723 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) 2724 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 2725 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 2726 2727 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) 2728 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) 2729 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) 2730 2731 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) 2732 { 2733 int status = -EINVAL; 2734 2735 dprintk(1, "\n"); 2736 2737 if (state->m_drxk_state == DRXK_UNINITIALIZED) 2738 return 0; 2739 if (state->m_drxk_state == DRXK_POWERED_DOWN) 2740 goto error; 2741 2742 if (state->no_i2c_bridge) 2743 return 0; 2744 2745 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, 2746 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 2747 if (status < 0) 2748 goto error; 2749 if (b_enable_bridge) { 2750 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 2751 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); 2752 if (status < 0) 2753 goto error; 2754 } else { 2755 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 2756 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); 2757 if (status < 0) 2758 goto error; 2759 } 2760 2761 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); 2762 2763 error: 2764 if (status < 0) 2765 pr_err("Error %d on %s\n", status, __func__); 2766 return status; 2767 } 2768 2769 static int set_pre_saw(struct drxk_state *state, 2770 struct s_cfg_pre_saw *p_pre_saw_cfg) 2771 { 2772 int status = -EINVAL; 2773 2774 dprintk(1, "\n"); 2775 2776 if ((p_pre_saw_cfg == NULL) 2777 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M)) 2778 goto error; 2779 2780 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); 2781 error: 2782 if (status < 0) 2783 pr_err("Error %d on %s\n", status, __func__); 2784 return status; 2785 } 2786 2787 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, 2788 u16 rom_offset, u16 nr_of_elements, u32 time_out) 2789 { 2790 u16 bl_status = 0; 2791 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF); 2792 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF); 2793 int status; 2794 unsigned long end; 2795 2796 dprintk(1, "\n"); 2797 2798 mutex_lock(&state->mutex); 2799 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); 2800 if (status < 0) 2801 goto error; 2802 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); 2803 if (status < 0) 2804 goto error; 2805 status = write16(state, SIO_BL_TGT_ADDR__A, offset); 2806 if (status < 0) 2807 goto error; 2808 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); 2809 if (status < 0) 2810 goto error; 2811 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); 2812 if (status < 0) 2813 goto error; 2814 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 2815 if (status < 0) 2816 goto error; 2817 2818 end = jiffies + msecs_to_jiffies(time_out); 2819 do { 2820 status = read16(state, SIO_BL_STATUS__A, &bl_status); 2821 if (status < 0) 2822 goto error; 2823 } while ((bl_status == 0x1) && time_is_after_jiffies(end)); 2824 if (bl_status == 0x1) { 2825 pr_err("SIO not ready\n"); 2826 status = -EINVAL; 2827 goto error2; 2828 } 2829 error: 2830 if (status < 0) 2831 pr_err("Error %d on %s\n", status, __func__); 2832 error2: 2833 mutex_unlock(&state->mutex); 2834 return status; 2835 2836 } 2837 2838 static int adc_sync_measurement(struct drxk_state *state, u16 *count) 2839 { 2840 u16 data = 0; 2841 int status; 2842 2843 dprintk(1, "\n"); 2844 2845 /* start measurement */ 2846 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); 2847 if (status < 0) 2848 goto error; 2849 status = write16(state, IQM_AF_START_LOCK__A, 1); 2850 if (status < 0) 2851 goto error; 2852 2853 *count = 0; 2854 status = read16(state, IQM_AF_PHASE0__A, &data); 2855 if (status < 0) 2856 goto error; 2857 if (data == 127) 2858 *count = *count + 1; 2859 status = read16(state, IQM_AF_PHASE1__A, &data); 2860 if (status < 0) 2861 goto error; 2862 if (data == 127) 2863 *count = *count + 1; 2864 status = read16(state, IQM_AF_PHASE2__A, &data); 2865 if (status < 0) 2866 goto error; 2867 if (data == 127) 2868 *count = *count + 1; 2869 2870 error: 2871 if (status < 0) 2872 pr_err("Error %d on %s\n", status, __func__); 2873 return status; 2874 } 2875 2876 static int adc_synchronization(struct drxk_state *state) 2877 { 2878 u16 count = 0; 2879 int status; 2880 2881 dprintk(1, "\n"); 2882 2883 status = adc_sync_measurement(state, &count); 2884 if (status < 0) 2885 goto error; 2886 2887 if (count == 1) { 2888 /* Try sampling on a different edge */ 2889 u16 clk_neg = 0; 2890 2891 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); 2892 if (status < 0) 2893 goto error; 2894 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) == 2895 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { 2896 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2897 clk_neg |= 2898 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; 2899 } else { 2900 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2901 clk_neg |= 2902 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; 2903 } 2904 status = write16(state, IQM_AF_CLKNEG__A, clk_neg); 2905 if (status < 0) 2906 goto error; 2907 status = adc_sync_measurement(state, &count); 2908 if (status < 0) 2909 goto error; 2910 } 2911 2912 if (count < 2) 2913 status = -EINVAL; 2914 error: 2915 if (status < 0) 2916 pr_err("Error %d on %s\n", status, __func__); 2917 return status; 2918 } 2919 2920 static int set_frequency_shifter(struct drxk_state *state, 2921 u16 intermediate_freqk_hz, 2922 s32 tuner_freq_offset, bool is_dtv) 2923 { 2924 bool select_pos_image = false; 2925 u32 rf_freq_residual = tuner_freq_offset; 2926 u32 fm_frequency_shift = 0; 2927 bool tuner_mirror = !state->m_b_mirror_freq_spect; 2928 u32 adc_freq; 2929 bool adc_flip; 2930 int status; 2931 u32 if_freq_actual; 2932 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); 2933 u32 frequency_shift; 2934 bool image_to_select; 2935 2936 dprintk(1, "\n"); 2937 2938 /* 2939 Program frequency shifter 2940 No need to account for mirroring on RF 2941 */ 2942 if (is_dtv) { 2943 if ((state->m_operation_mode == OM_QAM_ITU_A) || 2944 (state->m_operation_mode == OM_QAM_ITU_C) || 2945 (state->m_operation_mode == OM_DVBT)) 2946 select_pos_image = true; 2947 else 2948 select_pos_image = false; 2949 } 2950 if (tuner_mirror) 2951 /* tuner doesn't mirror */ 2952 if_freq_actual = intermediate_freqk_hz + 2953 rf_freq_residual + fm_frequency_shift; 2954 else 2955 /* tuner mirrors */ 2956 if_freq_actual = intermediate_freqk_hz - 2957 rf_freq_residual - fm_frequency_shift; 2958 if (if_freq_actual > sampling_frequency / 2) { 2959 /* adc mirrors */ 2960 adc_freq = sampling_frequency - if_freq_actual; 2961 adc_flip = true; 2962 } else { 2963 /* adc doesn't mirror */ 2964 adc_freq = if_freq_actual; 2965 adc_flip = false; 2966 } 2967 2968 frequency_shift = adc_freq; 2969 image_to_select = state->m_rfmirror ^ tuner_mirror ^ 2970 adc_flip ^ select_pos_image; 2971 state->m_iqm_fs_rate_ofs = 2972 Frac28a((frequency_shift), sampling_frequency); 2973 2974 if (image_to_select) 2975 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; 2976 2977 /* Program frequency shifter with tuner offset compensation */ 2978 /* frequency_shift += tuner_freq_offset; TODO */ 2979 status = write32(state, IQM_FS_RATE_OFS_LO__A, 2980 state->m_iqm_fs_rate_ofs); 2981 if (status < 0) 2982 pr_err("Error %d on %s\n", status, __func__); 2983 return status; 2984 } 2985 2986 static int init_agc(struct drxk_state *state, bool is_dtv) 2987 { 2988 u16 ingain_tgt = 0; 2989 u16 ingain_tgt_min = 0; 2990 u16 ingain_tgt_max = 0; 2991 u16 clp_cyclen = 0; 2992 u16 clp_sum_min = 0; 2993 u16 clp_dir_to = 0; 2994 u16 sns_sum_min = 0; 2995 u16 sns_sum_max = 0; 2996 u16 clp_sum_max = 0; 2997 u16 sns_dir_to = 0; 2998 u16 ki_innergain_min = 0; 2999 u16 if_iaccu_hi_tgt = 0; 3000 u16 if_iaccu_hi_tgt_min = 0; 3001 u16 if_iaccu_hi_tgt_max = 0; 3002 u16 data = 0; 3003 u16 fast_clp_ctrl_delay = 0; 3004 u16 clp_ctrl_mode = 0; 3005 int status = 0; 3006 3007 dprintk(1, "\n"); 3008 3009 /* Common settings */ 3010 sns_sum_max = 1023; 3011 if_iaccu_hi_tgt_min = 2047; 3012 clp_cyclen = 500; 3013 clp_sum_max = 1023; 3014 3015 /* AGCInit() not available for DVBT; init done in microcode */ 3016 if (!is_qam(state)) { 3017 pr_err("%s: mode %d is not DVB-C\n", 3018 __func__, state->m_operation_mode); 3019 return -EINVAL; 3020 } 3021 3022 /* FIXME: Analog TV AGC require different settings */ 3023 3024 /* Standard specific settings */ 3025 clp_sum_min = 8; 3026 clp_dir_to = (u16) -9; 3027 clp_ctrl_mode = 0; 3028 sns_sum_min = 8; 3029 sns_dir_to = (u16) -9; 3030 ki_innergain_min = (u16) -1030; 3031 if_iaccu_hi_tgt_max = 0x2380; 3032 if_iaccu_hi_tgt = 0x2380; 3033 ingain_tgt_min = 0x0511; 3034 ingain_tgt = 0x0511; 3035 ingain_tgt_max = 5119; 3036 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; 3037 3038 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 3039 fast_clp_ctrl_delay); 3040 if (status < 0) 3041 goto error; 3042 3043 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); 3044 if (status < 0) 3045 goto error; 3046 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); 3047 if (status < 0) 3048 goto error; 3049 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); 3050 if (status < 0) 3051 goto error; 3052 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); 3053 if (status < 0) 3054 goto error; 3055 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, 3056 if_iaccu_hi_tgt_min); 3057 if (status < 0) 3058 goto error; 3059 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 3060 if_iaccu_hi_tgt_max); 3061 if (status < 0) 3062 goto error; 3063 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); 3064 if (status < 0) 3065 goto error; 3066 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); 3067 if (status < 0) 3068 goto error; 3069 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); 3070 if (status < 0) 3071 goto error; 3072 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); 3073 if (status < 0) 3074 goto error; 3075 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); 3076 if (status < 0) 3077 goto error; 3078 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); 3079 if (status < 0) 3080 goto error; 3081 3082 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, 3083 ki_innergain_min); 3084 if (status < 0) 3085 goto error; 3086 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 3087 if_iaccu_hi_tgt); 3088 if (status < 0) 3089 goto error; 3090 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); 3091 if (status < 0) 3092 goto error; 3093 3094 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); 3095 if (status < 0) 3096 goto error; 3097 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); 3098 if (status < 0) 3099 goto error; 3100 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); 3101 if (status < 0) 3102 goto error; 3103 3104 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); 3105 if (status < 0) 3106 goto error; 3107 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); 3108 if (status < 0) 3109 goto error; 3110 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); 3111 if (status < 0) 3112 goto error; 3113 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); 3114 if (status < 0) 3115 goto error; 3116 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); 3117 if (status < 0) 3118 goto error; 3119 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); 3120 if (status < 0) 3121 goto error; 3122 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); 3123 if (status < 0) 3124 goto error; 3125 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); 3126 if (status < 0) 3127 goto error; 3128 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); 3129 if (status < 0) 3130 goto error; 3131 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); 3132 if (status < 0) 3133 goto error; 3134 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); 3135 if (status < 0) 3136 goto error; 3137 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); 3138 if (status < 0) 3139 goto error; 3140 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); 3141 if (status < 0) 3142 goto error; 3143 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); 3144 if (status < 0) 3145 goto error; 3146 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); 3147 if (status < 0) 3148 goto error; 3149 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); 3150 if (status < 0) 3151 goto error; 3152 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); 3153 if (status < 0) 3154 goto error; 3155 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); 3156 if (status < 0) 3157 goto error; 3158 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); 3159 if (status < 0) 3160 goto error; 3161 3162 /* Initialize inner-loop KI gain factors */ 3163 status = read16(state, SCU_RAM_AGC_KI__A, &data); 3164 if (status < 0) 3165 goto error; 3166 3167 data = 0x0657; 3168 data &= ~SCU_RAM_AGC_KI_RF__M; 3169 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); 3170 data &= ~SCU_RAM_AGC_KI_IF__M; 3171 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); 3172 3173 status = write16(state, SCU_RAM_AGC_KI__A, data); 3174 error: 3175 if (status < 0) 3176 pr_err("Error %d on %s\n", status, __func__); 3177 return status; 3178 } 3179 3180 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) 3181 { 3182 int status; 3183 3184 dprintk(1, "\n"); 3185 if (packet_err == NULL) 3186 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 3187 else 3188 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 3189 packet_err); 3190 if (status < 0) 3191 pr_err("Error %d on %s\n", status, __func__); 3192 return status; 3193 } 3194 3195 static int dvbt_sc_command(struct drxk_state *state, 3196 u16 cmd, u16 subcmd, 3197 u16 param0, u16 param1, u16 param2, 3198 u16 param3, u16 param4) 3199 { 3200 u16 cur_cmd = 0; 3201 u16 err_code = 0; 3202 u16 retry_cnt = 0; 3203 u16 sc_exec = 0; 3204 int status; 3205 3206 dprintk(1, "\n"); 3207 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); 3208 if (sc_exec != 1) { 3209 /* SC is not running */ 3210 status = -EINVAL; 3211 } 3212 if (status < 0) 3213 goto error; 3214 3215 /* Wait until sc is ready to receive command */ 3216 retry_cnt = 0; 3217 do { 3218 usleep_range(1000, 2000); 3219 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); 3220 retry_cnt++; 3221 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); 3222 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) 3223 goto error; 3224 3225 /* Write sub-command */ 3226 switch (cmd) { 3227 /* All commands using sub-cmd */ 3228 case OFDM_SC_RA_RAM_CMD_PROC_START: 3229 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3230 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3231 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); 3232 if (status < 0) 3233 goto error; 3234 break; 3235 default: 3236 /* Do nothing */ 3237 break; 3238 } 3239 3240 /* Write needed parameters and the command */ 3241 status = 0; 3242 switch (cmd) { 3243 /* All commands using 5 parameters */ 3244 /* All commands using 4 parameters */ 3245 /* All commands using 3 parameters */ 3246 /* All commands using 2 parameters */ 3247 case OFDM_SC_RA_RAM_CMD_PROC_START: 3248 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3249 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3250 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); 3251 fallthrough; /* All commands using 1 parameters */ 3252 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3253 case OFDM_SC_RA_RAM_CMD_USER_IO: 3254 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); 3255 fallthrough; /* All commands using 0 parameters */ 3256 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3257 case OFDM_SC_RA_RAM_CMD_NULL: 3258 /* Write command */ 3259 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); 3260 break; 3261 default: 3262 /* Unknown command */ 3263 status = -EINVAL; 3264 } 3265 if (status < 0) 3266 goto error; 3267 3268 /* Wait until sc is ready processing command */ 3269 retry_cnt = 0; 3270 do { 3271 usleep_range(1000, 2000); 3272 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); 3273 retry_cnt++; 3274 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); 3275 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) 3276 goto error; 3277 3278 /* Check for illegal cmd */ 3279 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); 3280 if (err_code == 0xFFFF) { 3281 /* illegal command */ 3282 status = -EINVAL; 3283 } 3284 if (status < 0) 3285 goto error; 3286 3287 /* Retrieve results parameters from SC */ 3288 switch (cmd) { 3289 /* All commands yielding 5 results */ 3290 /* All commands yielding 4 results */ 3291 /* All commands yielding 3 results */ 3292 /* All commands yielding 2 results */ 3293 /* All commands yielding 1 result */ 3294 case OFDM_SC_RA_RAM_CMD_USER_IO: 3295 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3296 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); 3297 /* All commands yielding 0 results */ 3298 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3299 case OFDM_SC_RA_RAM_CMD_SET_TIMER: 3300 case OFDM_SC_RA_RAM_CMD_PROC_START: 3301 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3302 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3303 case OFDM_SC_RA_RAM_CMD_NULL: 3304 break; 3305 default: 3306 /* Unknown command */ 3307 status = -EINVAL; 3308 break; 3309 } /* switch (cmd->cmd) */ 3310 error: 3311 if (status < 0) 3312 pr_err("Error %d on %s\n", status, __func__); 3313 return status; 3314 } 3315 3316 static int power_up_dvbt(struct drxk_state *state) 3317 { 3318 enum drx_power_mode power_mode = DRX_POWER_UP; 3319 int status; 3320 3321 dprintk(1, "\n"); 3322 status = ctrl_power_mode(state, &power_mode); 3323 if (status < 0) 3324 pr_err("Error %d on %s\n", status, __func__); 3325 return status; 3326 } 3327 3328 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) 3329 { 3330 int status; 3331 3332 dprintk(1, "\n"); 3333 if (*enabled) 3334 status = write16(state, IQM_CF_BYPASSDET__A, 0); 3335 else 3336 status = write16(state, IQM_CF_BYPASSDET__A, 1); 3337 if (status < 0) 3338 pr_err("Error %d on %s\n", status, __func__); 3339 return status; 3340 } 3341 3342 #define DEFAULT_FR_THRES_8K 4000 3343 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) 3344 { 3345 3346 int status; 3347 3348 dprintk(1, "\n"); 3349 if (*enabled) { 3350 /* write mask to 1 */ 3351 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 3352 DEFAULT_FR_THRES_8K); 3353 } else { 3354 /* write mask to 0 */ 3355 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); 3356 } 3357 if (status < 0) 3358 pr_err("Error %d on %s\n", status, __func__); 3359 3360 return status; 3361 } 3362 3363 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, 3364 struct drxk_cfg_dvbt_echo_thres_t *echo_thres) 3365 { 3366 u16 data = 0; 3367 int status; 3368 3369 dprintk(1, "\n"); 3370 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); 3371 if (status < 0) 3372 goto error; 3373 3374 switch (echo_thres->fft_mode) { 3375 case DRX_FFTMODE_2K: 3376 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; 3377 data |= ((echo_thres->threshold << 3378 OFDM_SC_RA_RAM_ECHO_THRES_2K__B) 3379 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); 3380 break; 3381 case DRX_FFTMODE_8K: 3382 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; 3383 data |= ((echo_thres->threshold << 3384 OFDM_SC_RA_RAM_ECHO_THRES_8K__B) 3385 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); 3386 break; 3387 default: 3388 return -EINVAL; 3389 } 3390 3391 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); 3392 error: 3393 if (status < 0) 3394 pr_err("Error %d on %s\n", status, __func__); 3395 return status; 3396 } 3397 3398 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, 3399 enum drxk_cfg_dvbt_sqi_speed *speed) 3400 { 3401 int status = -EINVAL; 3402 3403 dprintk(1, "\n"); 3404 3405 switch (*speed) { 3406 case DRXK_DVBT_SQI_SPEED_FAST: 3407 case DRXK_DVBT_SQI_SPEED_MEDIUM: 3408 case DRXK_DVBT_SQI_SPEED_SLOW: 3409 break; 3410 default: 3411 goto error; 3412 } 3413 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, 3414 (u16) *speed); 3415 error: 3416 if (status < 0) 3417 pr_err("Error %d on %s\n", status, __func__); 3418 return status; 3419 } 3420 3421 /*============================================================================*/ 3422 3423 /* 3424 * \brief Activate DVBT specific presets 3425 * \param demod instance of demodulator. 3426 * \return DRXStatus_t. 3427 * 3428 * Called in DVBTSetStandard 3429 * 3430 */ 3431 static int dvbt_activate_presets(struct drxk_state *state) 3432 { 3433 int status; 3434 bool setincenable = false; 3435 bool setfrenable = true; 3436 3437 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K }; 3438 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K }; 3439 3440 dprintk(1, "\n"); 3441 status = dvbt_ctrl_set_inc_enable(state, &setincenable); 3442 if (status < 0) 3443 goto error; 3444 status = dvbt_ctrl_set_fr_enable(state, &setfrenable); 3445 if (status < 0) 3446 goto error; 3447 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); 3448 if (status < 0) 3449 goto error; 3450 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); 3451 if (status < 0) 3452 goto error; 3453 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, 3454 state->m_dvbt_if_agc_cfg.ingain_tgt_max); 3455 error: 3456 if (status < 0) 3457 pr_err("Error %d on %s\n", status, __func__); 3458 return status; 3459 } 3460 3461 /*============================================================================*/ 3462 3463 /* 3464 * \brief Initialize channelswitch-independent settings for DVBT. 3465 * \param demod instance of demodulator. 3466 * \return DRXStatus_t. 3467 * 3468 * For ROM code channel filter taps are loaded from the bootloader. For microcode 3469 * the DVB-T taps from the drxk_filters.h are used. 3470 */ 3471 static int set_dvbt_standard(struct drxk_state *state, 3472 enum operation_mode o_mode) 3473 { 3474 u16 cmd_result = 0; 3475 u16 data = 0; 3476 int status; 3477 3478 dprintk(1, "\n"); 3479 3480 power_up_dvbt(state); 3481 /* added antenna switch */ 3482 switch_antenna_to_dvbt(state); 3483 /* send OFDM reset command */ 3484 status = scu_command(state, 3485 SCU_RAM_COMMAND_STANDARD_OFDM 3486 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 3487 0, NULL, 1, &cmd_result); 3488 if (status < 0) 3489 goto error; 3490 3491 /* send OFDM setenv command */ 3492 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 3493 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 3494 0, NULL, 1, &cmd_result); 3495 if (status < 0) 3496 goto error; 3497 3498 /* reset datapath for OFDM, processors first */ 3499 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3500 if (status < 0) 3501 goto error; 3502 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3503 if (status < 0) 3504 goto error; 3505 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 3506 if (status < 0) 3507 goto error; 3508 3509 /* IQM setup */ 3510 /* synchronize on ofdstate->m_festart */ 3511 status = write16(state, IQM_AF_UPD_SEL__A, 1); 3512 if (status < 0) 3513 goto error; 3514 /* window size for clipping ADC detection */ 3515 status = write16(state, IQM_AF_CLP_LEN__A, 0); 3516 if (status < 0) 3517 goto error; 3518 /* window size for for sense pre-SAW detection */ 3519 status = write16(state, IQM_AF_SNS_LEN__A, 0); 3520 if (status < 0) 3521 goto error; 3522 /* sense threshold for sense pre-SAW detection */ 3523 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 3524 if (status < 0) 3525 goto error; 3526 status = set_iqm_af(state, true); 3527 if (status < 0) 3528 goto error; 3529 3530 status = write16(state, IQM_AF_AGC_RF__A, 0); 3531 if (status < 0) 3532 goto error; 3533 3534 /* Impulse noise cruncher setup */ 3535 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ 3536 if (status < 0) 3537 goto error; 3538 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ 3539 if (status < 0) 3540 goto error; 3541 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ 3542 if (status < 0) 3543 goto error; 3544 3545 status = write16(state, IQM_RC_STRETCH__A, 16); 3546 if (status < 0) 3547 goto error; 3548 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ 3549 if (status < 0) 3550 goto error; 3551 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ 3552 if (status < 0) 3553 goto error; 3554 status = write16(state, IQM_CF_SCALE__A, 1600); 3555 if (status < 0) 3556 goto error; 3557 status = write16(state, IQM_CF_SCALE_SH__A, 0); 3558 if (status < 0) 3559 goto error; 3560 3561 /* virtual clipping threshold for clipping ADC detection */ 3562 status = write16(state, IQM_AF_CLP_TH__A, 448); 3563 if (status < 0) 3564 goto error; 3565 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ 3566 if (status < 0) 3567 goto error; 3568 3569 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, 3570 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 3571 if (status < 0) 3572 goto error; 3573 3574 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ 3575 if (status < 0) 3576 goto error; 3577 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); 3578 if (status < 0) 3579 goto error; 3580 /* enable power measurement interrupt */ 3581 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); 3582 if (status < 0) 3583 goto error; 3584 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 3585 if (status < 0) 3586 goto error; 3587 3588 /* IQM will not be reset from here, sync ADC and update/init AGC */ 3589 status = adc_synchronization(state); 3590 if (status < 0) 3591 goto error; 3592 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); 3593 if (status < 0) 3594 goto error; 3595 3596 /* Halt SCU to enable safe non-atomic accesses */ 3597 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3598 if (status < 0) 3599 goto error; 3600 3601 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); 3602 if (status < 0) 3603 goto error; 3604 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); 3605 if (status < 0) 3606 goto error; 3607 3608 /* Set Noise Estimation notch width and enable DC fix */ 3609 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); 3610 if (status < 0) 3611 goto error; 3612 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; 3613 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); 3614 if (status < 0) 3615 goto error; 3616 3617 /* Activate SCU to enable SCU commands */ 3618 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 3619 if (status < 0) 3620 goto error; 3621 3622 if (!state->m_drxk_a3_rom_code) { 3623 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */ 3624 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 3625 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); 3626 if (status < 0) 3627 goto error; 3628 } 3629 3630 /* OFDM_SC setup */ 3631 #ifdef COMPILE_FOR_NONRT 3632 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); 3633 if (status < 0) 3634 goto error; 3635 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); 3636 if (status < 0) 3637 goto error; 3638 #endif 3639 3640 /* FEC setup */ 3641 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ 3642 if (status < 0) 3643 goto error; 3644 3645 3646 #ifdef COMPILE_FOR_NONRT 3647 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); 3648 if (status < 0) 3649 goto error; 3650 #else 3651 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); 3652 if (status < 0) 3653 goto error; 3654 #endif 3655 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); 3656 if (status < 0) 3657 goto error; 3658 3659 /* Setup MPEG bus */ 3660 status = mpegts_dto_setup(state, OM_DVBT); 3661 if (status < 0) 3662 goto error; 3663 /* Set DVBT Presets */ 3664 status = dvbt_activate_presets(state); 3665 if (status < 0) 3666 goto error; 3667 3668 error: 3669 if (status < 0) 3670 pr_err("Error %d on %s\n", status, __func__); 3671 return status; 3672 } 3673 3674 /*============================================================================*/ 3675 /* 3676 * \brief start dvbt demodulating for channel. 3677 * \param demod instance of demodulator. 3678 * \return DRXStatus_t. 3679 */ 3680 static int dvbt_start(struct drxk_state *state) 3681 { 3682 u16 param1; 3683 int status; 3684 /* drxk_ofdm_sc_cmd_t scCmd; */ 3685 3686 dprintk(1, "\n"); 3687 /* start correct processes to get in lock */ 3688 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ 3689 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; 3690 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, 3691 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 3692 0, 0, 0); 3693 if (status < 0) 3694 goto error; 3695 /* start FEC OC */ 3696 status = mpegts_start(state); 3697 if (status < 0) 3698 goto error; 3699 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 3700 if (status < 0) 3701 goto error; 3702 error: 3703 if (status < 0) 3704 pr_err("Error %d on %s\n", status, __func__); 3705 return status; 3706 } 3707 3708 3709 /*============================================================================*/ 3710 3711 /* 3712 * \brief Set up dvbt demodulator for channel. 3713 * \param demod instance of demodulator. 3714 * \return DRXStatus_t. 3715 * // original DVBTSetChannel() 3716 */ 3717 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, 3718 s32 tuner_freq_offset) 3719 { 3720 u16 cmd_result = 0; 3721 u16 transmission_params = 0; 3722 u16 operation_mode = 0; 3723 u32 iqm_rc_rate_ofs = 0; 3724 u32 bandwidth = 0; 3725 u16 param1; 3726 int status; 3727 3728 dprintk(1, "IF =%d, TFO = %d\n", 3729 intermediate_freqk_hz, tuner_freq_offset); 3730 3731 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 3732 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 3733 0, NULL, 1, &cmd_result); 3734 if (status < 0) 3735 goto error; 3736 3737 /* Halt SCU to enable safe non-atomic accesses */ 3738 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3739 if (status < 0) 3740 goto error; 3741 3742 /* Stop processors */ 3743 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3744 if (status < 0) 3745 goto error; 3746 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3747 if (status < 0) 3748 goto error; 3749 3750 /* Mandatory fix, always stop CP, required to set spl offset back to 3751 hardware default (is set to 0 by ucode during pilot detection */ 3752 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); 3753 if (status < 0) 3754 goto error; 3755 3756 /*== Write channel settings to device ================================*/ 3757 3758 /* mode */ 3759 switch (state->props.transmission_mode) { 3760 case TRANSMISSION_MODE_AUTO: 3761 default: 3762 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; 3763 fallthrough; /* try first guess DRX_FFTMODE_8K */ 3764 case TRANSMISSION_MODE_8K: 3765 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; 3766 break; 3767 case TRANSMISSION_MODE_2K: 3768 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; 3769 break; 3770 } 3771 3772 /* guard */ 3773 switch (state->props.guard_interval) { 3774 default: 3775 case GUARD_INTERVAL_AUTO: 3776 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; 3777 fallthrough; /* try first guess DRX_GUARD_1DIV4 */ 3778 case GUARD_INTERVAL_1_4: 3779 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; 3780 break; 3781 case GUARD_INTERVAL_1_32: 3782 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; 3783 break; 3784 case GUARD_INTERVAL_1_16: 3785 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; 3786 break; 3787 case GUARD_INTERVAL_1_8: 3788 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; 3789 break; 3790 } 3791 3792 /* hierarchy */ 3793 switch (state->props.hierarchy) { 3794 case HIERARCHY_AUTO: 3795 case HIERARCHY_NONE: 3796 default: 3797 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; 3798 /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ 3799 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ 3800 fallthrough; 3801 case HIERARCHY_1: 3802 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; 3803 break; 3804 case HIERARCHY_2: 3805 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; 3806 break; 3807 case HIERARCHY_4: 3808 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; 3809 break; 3810 } 3811 3812 3813 /* modulation */ 3814 switch (state->props.modulation) { 3815 case QAM_AUTO: 3816 default: 3817 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; 3818 fallthrough; /* try first guess DRX_CONSTELLATION_QAM64 */ 3819 case QAM_64: 3820 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; 3821 break; 3822 case QPSK: 3823 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; 3824 break; 3825 case QAM_16: 3826 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; 3827 break; 3828 } 3829 #if 0 3830 /* No hierarchical channels support in BDA */ 3831 /* Priority (only for hierarchical channels) */ 3832 switch (channel->priority) { 3833 case DRX_PRIORITY_LOW: 3834 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; 3835 WR16(dev_addr, OFDM_EC_SB_PRIOR__A, 3836 OFDM_EC_SB_PRIOR_LO); 3837 break; 3838 case DRX_PRIORITY_HIGH: 3839 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3840 WR16(dev_addr, OFDM_EC_SB_PRIOR__A, 3841 OFDM_EC_SB_PRIOR_HI)); 3842 break; 3843 case DRX_PRIORITY_UNKNOWN: 3844 default: 3845 status = -EINVAL; 3846 goto error; 3847 } 3848 #else 3849 /* Set Priority high */ 3850 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3851 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); 3852 if (status < 0) 3853 goto error; 3854 #endif 3855 3856 /* coderate */ 3857 switch (state->props.code_rate_HP) { 3858 case FEC_AUTO: 3859 default: 3860 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; 3861 fallthrough; /* try first guess DRX_CODERATE_2DIV3 */ 3862 case FEC_2_3: 3863 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; 3864 break; 3865 case FEC_1_2: 3866 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; 3867 break; 3868 case FEC_3_4: 3869 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; 3870 break; 3871 case FEC_5_6: 3872 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; 3873 break; 3874 case FEC_7_8: 3875 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; 3876 break; 3877 } 3878 3879 /* 3880 * SAW filter selection: normally not necessary, but if wanted 3881 * the application can select a SAW filter via the driver by 3882 * using UIOs 3883 */ 3884 3885 /* First determine real bandwidth (Hz) */ 3886 /* Also set delay for impulse noise cruncher */ 3887 /* 3888 * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is 3889 * changed by SC for fix for some 8K,1/8 guard but is restored by 3890 * InitEC and ResetEC functions 3891 */ 3892 switch (state->props.bandwidth_hz) { 3893 case 0: 3894 state->props.bandwidth_hz = 8000000; 3895 fallthrough; 3896 case 8000000: 3897 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3898 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3899 3052); 3900 if (status < 0) 3901 goto error; 3902 /* cochannel protection for PAL 8 MHz */ 3903 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3904 7); 3905 if (status < 0) 3906 goto error; 3907 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3908 7); 3909 if (status < 0) 3910 goto error; 3911 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3912 7); 3913 if (status < 0) 3914 goto error; 3915 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3916 1); 3917 if (status < 0) 3918 goto error; 3919 break; 3920 case 7000000: 3921 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3922 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3923 3491); 3924 if (status < 0) 3925 goto error; 3926 /* cochannel protection for PAL 7 MHz */ 3927 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3928 8); 3929 if (status < 0) 3930 goto error; 3931 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3932 8); 3933 if (status < 0) 3934 goto error; 3935 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3936 4); 3937 if (status < 0) 3938 goto error; 3939 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3940 1); 3941 if (status < 0) 3942 goto error; 3943 break; 3944 case 6000000: 3945 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3946 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3947 4073); 3948 if (status < 0) 3949 goto error; 3950 /* cochannel protection for NTSC 6 MHz */ 3951 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3952 19); 3953 if (status < 0) 3954 goto error; 3955 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3956 19); 3957 if (status < 0) 3958 goto error; 3959 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3960 14); 3961 if (status < 0) 3962 goto error; 3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3964 1); 3965 if (status < 0) 3966 goto error; 3967 break; 3968 default: 3969 status = -EINVAL; 3970 goto error; 3971 } 3972 3973 if (iqm_rc_rate_ofs == 0) { 3974 /* Now compute IQM_RC_RATE_OFS 3975 (((SysFreq/BandWidth)/2)/2) -1) * 2^23) 3976 => 3977 ((SysFreq / BandWidth) * (2^21)) - (2^23) 3978 */ 3979 /* (SysFreq / BandWidth) * (2^28) */ 3980 /* 3981 * assert (MAX(sysClk)/MIN(bandwidth) < 16) 3982 * => assert(MAX(sysClk) < 16*MIN(bandwidth)) 3983 * => assert(109714272 > 48000000) = true 3984 * so Frac 28 can be used 3985 */ 3986 iqm_rc_rate_ofs = Frac28a((u32) 3987 ((state->m_sys_clock_freq * 3988 1000) / 3), bandwidth); 3989 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ 3990 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40) 3991 iqm_rc_rate_ofs += 0x80L; 3992 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7; 3993 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ 3994 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23); 3995 } 3996 3997 iqm_rc_rate_ofs &= 3998 ((((u32) IQM_RC_RATE_OFS_HI__M) << 3999 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); 4000 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); 4001 if (status < 0) 4002 goto error; 4003 4004 /* Bandwidth setting done */ 4005 4006 #if 0 4007 status = dvbt_set_frequency_shift(demod, channel, tuner_offset); 4008 if (status < 0) 4009 goto error; 4010 #endif 4011 status = set_frequency_shifter(state, intermediate_freqk_hz, 4012 tuner_freq_offset, true); 4013 if (status < 0) 4014 goto error; 4015 4016 /*== start SC, write channel settings to SC ==========================*/ 4017 4018 /* Activate SCU to enable SCU commands */ 4019 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 4020 if (status < 0) 4021 goto error; 4022 4023 /* Enable SC after setting all other parameters */ 4024 status = write16(state, OFDM_SC_COMM_STATE__A, 0); 4025 if (status < 0) 4026 goto error; 4027 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); 4028 if (status < 0) 4029 goto error; 4030 4031 4032 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 4033 | SCU_RAM_COMMAND_CMD_DEMOD_START, 4034 0, NULL, 1, &cmd_result); 4035 if (status < 0) 4036 goto error; 4037 4038 /* Write SC parameter registers, set all AUTO flags in operation mode */ 4039 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | 4040 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M | 4041 OFDM_SC_RA_RAM_OP_AUTO_CONST__M | 4042 OFDM_SC_RA_RAM_OP_AUTO_HIER__M | 4043 OFDM_SC_RA_RAM_OP_AUTO_RATE__M); 4044 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, 4045 0, transmission_params, param1, 0, 0, 0); 4046 if (status < 0) 4047 goto error; 4048 4049 if (!state->m_drxk_a3_rom_code) 4050 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); 4051 error: 4052 if (status < 0) 4053 pr_err("Error %d on %s\n", status, __func__); 4054 4055 return status; 4056 } 4057 4058 4059 /*============================================================================*/ 4060 4061 /* 4062 * \brief Retrieve lock status . 4063 * \param demod Pointer to demodulator instance. 4064 * \param lockStat Pointer to lock status structure. 4065 * \return DRXStatus_t. 4066 * 4067 */ 4068 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) 4069 { 4070 int status; 4071 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | 4072 OFDM_SC_RA_RAM_LOCK_FEC__M); 4073 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); 4074 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; 4075 4076 u16 sc_ra_ram_lock = 0; 4077 u16 sc_comm_exec = 0; 4078 4079 dprintk(1, "\n"); 4080 4081 *p_lock_status = NOT_LOCKED; 4082 /* driver 0.9.0 */ 4083 /* Check if SC is running */ 4084 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); 4085 if (status < 0) 4086 goto end; 4087 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP) 4088 goto end; 4089 4090 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); 4091 if (status < 0) 4092 goto end; 4093 4094 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask) 4095 *p_lock_status = MPEG_LOCK; 4096 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask) 4097 *p_lock_status = FEC_LOCK; 4098 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask) 4099 *p_lock_status = DEMOD_LOCK; 4100 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) 4101 *p_lock_status = NEVER_LOCK; 4102 end: 4103 if (status < 0) 4104 pr_err("Error %d on %s\n", status, __func__); 4105 4106 return status; 4107 } 4108 4109 static int power_up_qam(struct drxk_state *state) 4110 { 4111 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 4112 int status; 4113 4114 dprintk(1, "\n"); 4115 status = ctrl_power_mode(state, &power_mode); 4116 if (status < 0) 4117 pr_err("Error %d on %s\n", status, __func__); 4118 4119 return status; 4120 } 4121 4122 4123 /* Power Down QAM */ 4124 static int power_down_qam(struct drxk_state *state) 4125 { 4126 u16 data = 0; 4127 u16 cmd_result; 4128 int status = 0; 4129 4130 dprintk(1, "\n"); 4131 status = read16(state, SCU_COMM_EXEC__A, &data); 4132 if (status < 0) 4133 goto error; 4134 if (data == SCU_COMM_EXEC_ACTIVE) { 4135 /* 4136 STOP demodulator 4137 QAM and HW blocks 4138 */ 4139 /* stop all comstate->m_exec */ 4140 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 4141 if (status < 0) 4142 goto error; 4143 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 4144 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 4145 0, NULL, 1, &cmd_result); 4146 if (status < 0) 4147 goto error; 4148 } 4149 /* powerdown AFE */ 4150 status = set_iqm_af(state, false); 4151 4152 error: 4153 if (status < 0) 4154 pr_err("Error %d on %s\n", status, __func__); 4155 4156 return status; 4157 } 4158 4159 /*============================================================================*/ 4160 4161 /* 4162 * \brief Setup of the QAM Measurement intervals for signal quality 4163 * \param demod instance of demod. 4164 * \param modulation current modulation. 4165 * \return DRXStatus_t. 4166 * 4167 * NOTE: 4168 * Take into account that for certain settings the errorcounters can overflow. 4169 * The implementation does not check this. 4170 * 4171 */ 4172 static int set_qam_measurement(struct drxk_state *state, 4173 enum e_drxk_constellation modulation, 4174 u32 symbol_rate) 4175 { 4176 u32 fec_bits_desired = 0; /* BER accounting period */ 4177 u32 fec_rs_period_total = 0; /* Total period */ 4178 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ 4179 u16 fec_rs_period = 0; /* Value for corresponding I2C register */ 4180 int status = 0; 4181 4182 dprintk(1, "\n"); 4183 4184 fec_rs_prescale = 1; 4185 /* fec_bits_desired = symbol_rate [kHz] * 4186 FrameLenght [ms] * 4187 (modulation + 1) * 4188 SyncLoss (== 1) * 4189 ViterbiLoss (==1) 4190 */ 4191 switch (modulation) { 4192 case DRX_CONSTELLATION_QAM16: 4193 fec_bits_desired = 4 * symbol_rate; 4194 break; 4195 case DRX_CONSTELLATION_QAM32: 4196 fec_bits_desired = 5 * symbol_rate; 4197 break; 4198 case DRX_CONSTELLATION_QAM64: 4199 fec_bits_desired = 6 * symbol_rate; 4200 break; 4201 case DRX_CONSTELLATION_QAM128: 4202 fec_bits_desired = 7 * symbol_rate; 4203 break; 4204 case DRX_CONSTELLATION_QAM256: 4205 fec_bits_desired = 8 * symbol_rate; 4206 break; 4207 default: 4208 status = -EINVAL; 4209 } 4210 if (status < 0) 4211 goto error; 4212 4213 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ 4214 fec_bits_desired *= 500; /* meas. period [ms] */ 4215 4216 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ 4217 /* fec_rs_period_total = fec_bits_desired / 1632 */ 4218 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */ 4219 4220 /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */ 4221 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16); 4222 if (fec_rs_prescale == 0) { 4223 /* Divide by zero (though impossible) */ 4224 status = -EINVAL; 4225 if (status < 0) 4226 goto error; 4227 } 4228 fec_rs_period = 4229 ((u16) fec_rs_period_total + 4230 (fec_rs_prescale >> 1)) / fec_rs_prescale; 4231 4232 /* write corresponding registers */ 4233 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); 4234 if (status < 0) 4235 goto error; 4236 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 4237 fec_rs_prescale); 4238 if (status < 0) 4239 goto error; 4240 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); 4241 error: 4242 if (status < 0) 4243 pr_err("Error %d on %s\n", status, __func__); 4244 return status; 4245 } 4246 4247 static int set_qam16(struct drxk_state *state) 4248 { 4249 int status = 0; 4250 4251 dprintk(1, "\n"); 4252 /* QAM Equalizer Setup */ 4253 /* Equalizer */ 4254 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); 4255 if (status < 0) 4256 goto error; 4257 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); 4258 if (status < 0) 4259 goto error; 4260 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); 4261 if (status < 0) 4262 goto error; 4263 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); 4264 if (status < 0) 4265 goto error; 4266 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); 4267 if (status < 0) 4268 goto error; 4269 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); 4270 if (status < 0) 4271 goto error; 4272 /* Decision Feedback Equalizer */ 4273 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); 4274 if (status < 0) 4275 goto error; 4276 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); 4277 if (status < 0) 4278 goto error; 4279 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); 4280 if (status < 0) 4281 goto error; 4282 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); 4283 if (status < 0) 4284 goto error; 4285 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); 4286 if (status < 0) 4287 goto error; 4288 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4289 if (status < 0) 4290 goto error; 4291 4292 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4293 if (status < 0) 4294 goto error; 4295 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4296 if (status < 0) 4297 goto error; 4298 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4299 if (status < 0) 4300 goto error; 4301 4302 /* QAM Slicer Settings */ 4303 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4304 DRXK_QAM_SL_SIG_POWER_QAM16); 4305 if (status < 0) 4306 goto error; 4307 4308 /* QAM Loop Controller Coeficients */ 4309 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4310 if (status < 0) 4311 goto error; 4312 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4313 if (status < 0) 4314 goto error; 4315 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4316 if (status < 0) 4317 goto error; 4318 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4319 if (status < 0) 4320 goto error; 4321 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4322 if (status < 0) 4323 goto error; 4324 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4325 if (status < 0) 4326 goto error; 4327 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4328 if (status < 0) 4329 goto error; 4330 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4331 if (status < 0) 4332 goto error; 4333 4334 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4335 if (status < 0) 4336 goto error; 4337 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4338 if (status < 0) 4339 goto error; 4340 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4341 if (status < 0) 4342 goto error; 4343 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4344 if (status < 0) 4345 goto error; 4346 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4347 if (status < 0) 4348 goto error; 4349 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4350 if (status < 0) 4351 goto error; 4352 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4353 if (status < 0) 4354 goto error; 4355 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4356 if (status < 0) 4357 goto error; 4358 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); 4359 if (status < 0) 4360 goto error; 4361 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4362 if (status < 0) 4363 goto error; 4364 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4365 if (status < 0) 4366 goto error; 4367 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4368 if (status < 0) 4369 goto error; 4370 4371 4372 /* QAM State Machine (FSM) Thresholds */ 4373 4374 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); 4375 if (status < 0) 4376 goto error; 4377 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4378 if (status < 0) 4379 goto error; 4380 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); 4381 if (status < 0) 4382 goto error; 4383 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); 4384 if (status < 0) 4385 goto error; 4386 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); 4387 if (status < 0) 4388 goto error; 4389 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); 4390 if (status < 0) 4391 goto error; 4392 4393 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4394 if (status < 0) 4395 goto error; 4396 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4397 if (status < 0) 4398 goto error; 4399 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); 4400 if (status < 0) 4401 goto error; 4402 4403 4404 /* QAM FSM Tracking Parameters */ 4405 4406 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); 4407 if (status < 0) 4408 goto error; 4409 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); 4410 if (status < 0) 4411 goto error; 4412 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); 4413 if (status < 0) 4414 goto error; 4415 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); 4416 if (status < 0) 4417 goto error; 4418 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); 4419 if (status < 0) 4420 goto error; 4421 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); 4422 if (status < 0) 4423 goto error; 4424 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); 4425 if (status < 0) 4426 goto error; 4427 4428 error: 4429 if (status < 0) 4430 pr_err("Error %d on %s\n", status, __func__); 4431 return status; 4432 } 4433 4434 /*============================================================================*/ 4435 4436 /* 4437 * \brief QAM32 specific setup 4438 * \param demod instance of demod. 4439 * \return DRXStatus_t. 4440 */ 4441 static int set_qam32(struct drxk_state *state) 4442 { 4443 int status = 0; 4444 4445 dprintk(1, "\n"); 4446 4447 /* QAM Equalizer Setup */ 4448 /* Equalizer */ 4449 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); 4450 if (status < 0) 4451 goto error; 4452 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); 4453 if (status < 0) 4454 goto error; 4455 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); 4456 if (status < 0) 4457 goto error; 4458 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); 4459 if (status < 0) 4460 goto error; 4461 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); 4462 if (status < 0) 4463 goto error; 4464 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); 4465 if (status < 0) 4466 goto error; 4467 4468 /* Decision Feedback Equalizer */ 4469 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); 4470 if (status < 0) 4471 goto error; 4472 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); 4473 if (status < 0) 4474 goto error; 4475 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); 4476 if (status < 0) 4477 goto error; 4478 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); 4479 if (status < 0) 4480 goto error; 4481 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4482 if (status < 0) 4483 goto error; 4484 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4485 if (status < 0) 4486 goto error; 4487 4488 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4489 if (status < 0) 4490 goto error; 4491 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4492 if (status < 0) 4493 goto error; 4494 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4495 if (status < 0) 4496 goto error; 4497 4498 /* QAM Slicer Settings */ 4499 4500 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4501 DRXK_QAM_SL_SIG_POWER_QAM32); 4502 if (status < 0) 4503 goto error; 4504 4505 4506 /* QAM Loop Controller Coeficients */ 4507 4508 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4509 if (status < 0) 4510 goto error; 4511 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4512 if (status < 0) 4513 goto error; 4514 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4515 if (status < 0) 4516 goto error; 4517 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4518 if (status < 0) 4519 goto error; 4520 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4521 if (status < 0) 4522 goto error; 4523 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4524 if (status < 0) 4525 goto error; 4526 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4527 if (status < 0) 4528 goto error; 4529 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4530 if (status < 0) 4531 goto error; 4532 4533 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4534 if (status < 0) 4535 goto error; 4536 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4537 if (status < 0) 4538 goto error; 4539 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4540 if (status < 0) 4541 goto error; 4542 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4543 if (status < 0) 4544 goto error; 4545 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4546 if (status < 0) 4547 goto error; 4548 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4549 if (status < 0) 4550 goto error; 4551 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4552 if (status < 0) 4553 goto error; 4554 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4555 if (status < 0) 4556 goto error; 4557 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); 4558 if (status < 0) 4559 goto error; 4560 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4561 if (status < 0) 4562 goto error; 4563 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4564 if (status < 0) 4565 goto error; 4566 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4567 if (status < 0) 4568 goto error; 4569 4570 4571 /* QAM State Machine (FSM) Thresholds */ 4572 4573 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); 4574 if (status < 0) 4575 goto error; 4576 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4577 if (status < 0) 4578 goto error; 4579 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4580 if (status < 0) 4581 goto error; 4582 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4583 if (status < 0) 4584 goto error; 4585 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); 4586 if (status < 0) 4587 goto error; 4588 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); 4589 if (status < 0) 4590 goto error; 4591 4592 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4593 if (status < 0) 4594 goto error; 4595 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4596 if (status < 0) 4597 goto error; 4598 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); 4599 if (status < 0) 4600 goto error; 4601 4602 4603 /* QAM FSM Tracking Parameters */ 4604 4605 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4606 if (status < 0) 4607 goto error; 4608 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); 4609 if (status < 0) 4610 goto error; 4611 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); 4612 if (status < 0) 4613 goto error; 4614 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); 4615 if (status < 0) 4616 goto error; 4617 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); 4618 if (status < 0) 4619 goto error; 4620 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); 4621 if (status < 0) 4622 goto error; 4623 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); 4624 error: 4625 if (status < 0) 4626 pr_err("Error %d on %s\n", status, __func__); 4627 return status; 4628 } 4629 4630 /*============================================================================*/ 4631 4632 /* 4633 * \brief QAM64 specific setup 4634 * \param demod instance of demod. 4635 * \return DRXStatus_t. 4636 */ 4637 static int set_qam64(struct drxk_state *state) 4638 { 4639 int status = 0; 4640 4641 dprintk(1, "\n"); 4642 /* QAM Equalizer Setup */ 4643 /* Equalizer */ 4644 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); 4645 if (status < 0) 4646 goto error; 4647 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); 4648 if (status < 0) 4649 goto error; 4650 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); 4651 if (status < 0) 4652 goto error; 4653 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); 4654 if (status < 0) 4655 goto error; 4656 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); 4657 if (status < 0) 4658 goto error; 4659 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); 4660 if (status < 0) 4661 goto error; 4662 4663 /* Decision Feedback Equalizer */ 4664 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); 4665 if (status < 0) 4666 goto error; 4667 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); 4668 if (status < 0) 4669 goto error; 4670 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); 4671 if (status < 0) 4672 goto error; 4673 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); 4674 if (status < 0) 4675 goto error; 4676 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4677 if (status < 0) 4678 goto error; 4679 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4680 if (status < 0) 4681 goto error; 4682 4683 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4684 if (status < 0) 4685 goto error; 4686 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4687 if (status < 0) 4688 goto error; 4689 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4690 if (status < 0) 4691 goto error; 4692 4693 /* QAM Slicer Settings */ 4694 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4695 DRXK_QAM_SL_SIG_POWER_QAM64); 4696 if (status < 0) 4697 goto error; 4698 4699 4700 /* QAM Loop Controller Coeficients */ 4701 4702 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4703 if (status < 0) 4704 goto error; 4705 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4706 if (status < 0) 4707 goto error; 4708 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4709 if (status < 0) 4710 goto error; 4711 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4712 if (status < 0) 4713 goto error; 4714 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4715 if (status < 0) 4716 goto error; 4717 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4718 if (status < 0) 4719 goto error; 4720 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4721 if (status < 0) 4722 goto error; 4723 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4724 if (status < 0) 4725 goto error; 4726 4727 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4728 if (status < 0) 4729 goto error; 4730 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); 4731 if (status < 0) 4732 goto error; 4733 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); 4734 if (status < 0) 4735 goto error; 4736 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4737 if (status < 0) 4738 goto error; 4739 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); 4740 if (status < 0) 4741 goto error; 4742 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4743 if (status < 0) 4744 goto error; 4745 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4746 if (status < 0) 4747 goto error; 4748 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4749 if (status < 0) 4750 goto error; 4751 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 4752 if (status < 0) 4753 goto error; 4754 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4755 if (status < 0) 4756 goto error; 4757 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4758 if (status < 0) 4759 goto error; 4760 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4761 if (status < 0) 4762 goto error; 4763 4764 4765 /* QAM State Machine (FSM) Thresholds */ 4766 4767 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); 4768 if (status < 0) 4769 goto error; 4770 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4771 if (status < 0) 4772 goto error; 4773 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4774 if (status < 0) 4775 goto error; 4776 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); 4777 if (status < 0) 4778 goto error; 4779 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); 4780 if (status < 0) 4781 goto error; 4782 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); 4783 if (status < 0) 4784 goto error; 4785 4786 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4787 if (status < 0) 4788 goto error; 4789 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4790 if (status < 0) 4791 goto error; 4792 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); 4793 if (status < 0) 4794 goto error; 4795 4796 4797 /* QAM FSM Tracking Parameters */ 4798 4799 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4800 if (status < 0) 4801 goto error; 4802 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); 4803 if (status < 0) 4804 goto error; 4805 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); 4806 if (status < 0) 4807 goto error; 4808 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); 4809 if (status < 0) 4810 goto error; 4811 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); 4812 if (status < 0) 4813 goto error; 4814 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); 4815 if (status < 0) 4816 goto error; 4817 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); 4818 error: 4819 if (status < 0) 4820 pr_err("Error %d on %s\n", status, __func__); 4821 4822 return status; 4823 } 4824 4825 /*============================================================================*/ 4826 4827 /* 4828 * \brief QAM128 specific setup 4829 * \param demod: instance of demod. 4830 * \return DRXStatus_t. 4831 */ 4832 static int set_qam128(struct drxk_state *state) 4833 { 4834 int status = 0; 4835 4836 dprintk(1, "\n"); 4837 /* QAM Equalizer Setup */ 4838 /* Equalizer */ 4839 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); 4840 if (status < 0) 4841 goto error; 4842 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); 4843 if (status < 0) 4844 goto error; 4845 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); 4846 if (status < 0) 4847 goto error; 4848 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); 4849 if (status < 0) 4850 goto error; 4851 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); 4852 if (status < 0) 4853 goto error; 4854 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); 4855 if (status < 0) 4856 goto error; 4857 4858 /* Decision Feedback Equalizer */ 4859 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); 4860 if (status < 0) 4861 goto error; 4862 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); 4863 if (status < 0) 4864 goto error; 4865 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); 4866 if (status < 0) 4867 goto error; 4868 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); 4869 if (status < 0) 4870 goto error; 4871 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); 4872 if (status < 0) 4873 goto error; 4874 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4875 if (status < 0) 4876 goto error; 4877 4878 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4879 if (status < 0) 4880 goto error; 4881 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4882 if (status < 0) 4883 goto error; 4884 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4885 if (status < 0) 4886 goto error; 4887 4888 4889 /* QAM Slicer Settings */ 4890 4891 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4892 DRXK_QAM_SL_SIG_POWER_QAM128); 4893 if (status < 0) 4894 goto error; 4895 4896 4897 /* QAM Loop Controller Coeficients */ 4898 4899 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4900 if (status < 0) 4901 goto error; 4902 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4903 if (status < 0) 4904 goto error; 4905 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4906 if (status < 0) 4907 goto error; 4908 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4909 if (status < 0) 4910 goto error; 4911 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4912 if (status < 0) 4913 goto error; 4914 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4915 if (status < 0) 4916 goto error; 4917 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4918 if (status < 0) 4919 goto error; 4920 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4921 if (status < 0) 4922 goto error; 4923 4924 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4925 if (status < 0) 4926 goto error; 4927 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); 4928 if (status < 0) 4929 goto error; 4930 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); 4931 if (status < 0) 4932 goto error; 4933 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4934 if (status < 0) 4935 goto error; 4936 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); 4937 if (status < 0) 4938 goto error; 4939 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); 4940 if (status < 0) 4941 goto error; 4942 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4943 if (status < 0) 4944 goto error; 4945 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4946 if (status < 0) 4947 goto error; 4948 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); 4949 if (status < 0) 4950 goto error; 4951 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4952 if (status < 0) 4953 goto error; 4954 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4955 if (status < 0) 4956 goto error; 4957 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4958 if (status < 0) 4959 goto error; 4960 4961 4962 /* QAM State Machine (FSM) Thresholds */ 4963 4964 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 4965 if (status < 0) 4966 goto error; 4967 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4968 if (status < 0) 4969 goto error; 4970 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4971 if (status < 0) 4972 goto error; 4973 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4974 if (status < 0) 4975 goto error; 4976 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); 4977 if (status < 0) 4978 goto error; 4979 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); 4980 if (status < 0) 4981 goto error; 4982 4983 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4984 if (status < 0) 4985 goto error; 4986 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); 4987 if (status < 0) 4988 goto error; 4989 4990 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 4991 if (status < 0) 4992 goto error; 4993 4994 /* QAM FSM Tracking Parameters */ 4995 4996 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 4997 if (status < 0) 4998 goto error; 4999 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); 5000 if (status < 0) 5001 goto error; 5002 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); 5003 if (status < 0) 5004 goto error; 5005 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); 5006 if (status < 0) 5007 goto error; 5008 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); 5009 if (status < 0) 5010 goto error; 5011 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); 5012 if (status < 0) 5013 goto error; 5014 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); 5015 error: 5016 if (status < 0) 5017 pr_err("Error %d on %s\n", status, __func__); 5018 5019 return status; 5020 } 5021 5022 /*============================================================================*/ 5023 5024 /* 5025 * \brief QAM256 specific setup 5026 * \param demod: instance of demod. 5027 * \return DRXStatus_t. 5028 */ 5029 static int set_qam256(struct drxk_state *state) 5030 { 5031 int status = 0; 5032 5033 dprintk(1, "\n"); 5034 /* QAM Equalizer Setup */ 5035 /* Equalizer */ 5036 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); 5037 if (status < 0) 5038 goto error; 5039 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); 5040 if (status < 0) 5041 goto error; 5042 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); 5043 if (status < 0) 5044 goto error; 5045 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); 5046 if (status < 0) 5047 goto error; 5048 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); 5049 if (status < 0) 5050 goto error; 5051 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); 5052 if (status < 0) 5053 goto error; 5054 5055 /* Decision Feedback Equalizer */ 5056 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); 5057 if (status < 0) 5058 goto error; 5059 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); 5060 if (status < 0) 5061 goto error; 5062 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); 5063 if (status < 0) 5064 goto error; 5065 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); 5066 if (status < 0) 5067 goto error; 5068 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); 5069 if (status < 0) 5070 goto error; 5071 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 5072 if (status < 0) 5073 goto error; 5074 5075 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 5076 if (status < 0) 5077 goto error; 5078 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 5079 if (status < 0) 5080 goto error; 5081 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 5082 if (status < 0) 5083 goto error; 5084 5085 /* QAM Slicer Settings */ 5086 5087 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 5088 DRXK_QAM_SL_SIG_POWER_QAM256); 5089 if (status < 0) 5090 goto error; 5091 5092 5093 /* QAM Loop Controller Coeficients */ 5094 5095 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 5096 if (status < 0) 5097 goto error; 5098 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 5099 if (status < 0) 5100 goto error; 5101 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 5102 if (status < 0) 5103 goto error; 5104 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 5105 if (status < 0) 5106 goto error; 5107 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 5108 if (status < 0) 5109 goto error; 5110 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 5111 if (status < 0) 5112 goto error; 5113 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 5114 if (status < 0) 5115 goto error; 5116 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 5117 if (status < 0) 5118 goto error; 5119 5120 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 5121 if (status < 0) 5122 goto error; 5123 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); 5124 if (status < 0) 5125 goto error; 5126 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); 5127 if (status < 0) 5128 goto error; 5129 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 5130 if (status < 0) 5131 goto error; 5132 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); 5133 if (status < 0) 5134 goto error; 5135 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); 5136 if (status < 0) 5137 goto error; 5138 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 5139 if (status < 0) 5140 goto error; 5141 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 5142 if (status < 0) 5143 goto error; 5144 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 5145 if (status < 0) 5146 goto error; 5147 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 5148 if (status < 0) 5149 goto error; 5150 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 5151 if (status < 0) 5152 goto error; 5153 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 5154 if (status < 0) 5155 goto error; 5156 5157 5158 /* QAM State Machine (FSM) Thresholds */ 5159 5160 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 5161 if (status < 0) 5162 goto error; 5163 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 5164 if (status < 0) 5165 goto error; 5166 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 5167 if (status < 0) 5168 goto error; 5169 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 5170 if (status < 0) 5171 goto error; 5172 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); 5173 if (status < 0) 5174 goto error; 5175 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); 5176 if (status < 0) 5177 goto error; 5178 5179 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5180 if (status < 0) 5181 goto error; 5182 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 5183 if (status < 0) 5184 goto error; 5185 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5186 if (status < 0) 5187 goto error; 5188 5189 5190 /* QAM FSM Tracking Parameters */ 5191 5192 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5193 if (status < 0) 5194 goto error; 5195 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); 5196 if (status < 0) 5197 goto error; 5198 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); 5199 if (status < 0) 5200 goto error; 5201 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); 5202 if (status < 0) 5203 goto error; 5204 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); 5205 if (status < 0) 5206 goto error; 5207 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); 5208 if (status < 0) 5209 goto error; 5210 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); 5211 error: 5212 if (status < 0) 5213 pr_err("Error %d on %s\n", status, __func__); 5214 return status; 5215 } 5216 5217 5218 /*============================================================================*/ 5219 /* 5220 * \brief Reset QAM block. 5221 * \param demod: instance of demod. 5222 * \param channel: pointer to channel data. 5223 * \return DRXStatus_t. 5224 */ 5225 static int qam_reset_qam(struct drxk_state *state) 5226 { 5227 int status; 5228 u16 cmd_result; 5229 5230 dprintk(1, "\n"); 5231 /* Stop QAM comstate->m_exec */ 5232 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 5233 if (status < 0) 5234 goto error; 5235 5236 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 5237 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 5238 0, NULL, 1, &cmd_result); 5239 error: 5240 if (status < 0) 5241 pr_err("Error %d on %s\n", status, __func__); 5242 return status; 5243 } 5244 5245 /*============================================================================*/ 5246 5247 /* 5248 * \brief Set QAM symbolrate. 5249 * \param demod: instance of demod. 5250 * \param channel: pointer to channel data. 5251 * \return DRXStatus_t. 5252 */ 5253 static int qam_set_symbolrate(struct drxk_state *state) 5254 { 5255 u32 adc_frequency = 0; 5256 u32 symb_freq = 0; 5257 u32 iqm_rc_rate = 0; 5258 u16 ratesel = 0; 5259 u32 lc_symb_rate = 0; 5260 int status; 5261 5262 dprintk(1, "\n"); 5263 /* Select & calculate correct IQM rate */ 5264 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; 5265 ratesel = 0; 5266 if (state->props.symbol_rate <= 1188750) 5267 ratesel = 3; 5268 else if (state->props.symbol_rate <= 2377500) 5269 ratesel = 2; 5270 else if (state->props.symbol_rate <= 4755000) 5271 ratesel = 1; 5272 status = write16(state, IQM_FD_RATESEL__A, ratesel); 5273 if (status < 0) 5274 goto error; 5275 5276 /* 5277 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) 5278 */ 5279 symb_freq = state->props.symbol_rate * (1 << ratesel); 5280 if (symb_freq == 0) { 5281 /* Divide by zero */ 5282 status = -EINVAL; 5283 goto error; 5284 } 5285 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) + 5286 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) - 5287 (1 << 23); 5288 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); 5289 if (status < 0) 5290 goto error; 5291 state->m_iqm_rc_rate = iqm_rc_rate; 5292 /* 5293 LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15)) 5294 */ 5295 symb_freq = state->props.symbol_rate; 5296 if (adc_frequency == 0) { 5297 /* Divide by zero */ 5298 status = -EINVAL; 5299 goto error; 5300 } 5301 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) + 5302 (Frac28a((symb_freq % adc_frequency), adc_frequency) >> 5303 16); 5304 if (lc_symb_rate > 511) 5305 lc_symb_rate = 511; 5306 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); 5307 5308 error: 5309 if (status < 0) 5310 pr_err("Error %d on %s\n", status, __func__); 5311 return status; 5312 } 5313 5314 /*============================================================================*/ 5315 5316 /* 5317 * \brief Get QAM lock status. 5318 * \param demod: instance of demod. 5319 * \param channel: pointer to channel data. 5320 * \return DRXStatus_t. 5321 */ 5322 5323 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) 5324 { 5325 int status; 5326 u16 result[2] = { 0, 0 }; 5327 5328 dprintk(1, "\n"); 5329 *p_lock_status = NOT_LOCKED; 5330 status = scu_command(state, 5331 SCU_RAM_COMMAND_STANDARD_QAM | 5332 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, 5333 result); 5334 if (status < 0) 5335 pr_err("Error %d on %s\n", status, __func__); 5336 5337 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { 5338 /* 0x0000 NOT LOCKED */ 5339 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { 5340 /* 0x4000 DEMOD LOCKED */ 5341 *p_lock_status = DEMOD_LOCK; 5342 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { 5343 /* 0x8000 DEMOD + FEC LOCKED (system lock) */ 5344 *p_lock_status = MPEG_LOCK; 5345 } else { 5346 /* 0xC000 NEVER LOCKED */ 5347 /* (system will never be able to lock to the signal) */ 5348 /* 5349 * TODO: check this, intermediate & standard specific lock 5350 * states are not taken into account here 5351 */ 5352 *p_lock_status = NEVER_LOCK; 5353 } 5354 return status; 5355 } 5356 5357 #define QAM_MIRROR__M 0x03 5358 #define QAM_MIRROR_NORMAL 0x00 5359 #define QAM_MIRRORED 0x01 5360 #define QAM_MIRROR_AUTO_ON 0x02 5361 #define QAM_LOCKRANGE__M 0x10 5362 #define QAM_LOCKRANGE_NORMAL 0x10 5363 5364 static int qam_demodulator_command(struct drxk_state *state, 5365 int number_of_parameters) 5366 { 5367 int status; 5368 u16 cmd_result; 5369 u16 set_param_parameters[4] = { 0, 0, 0, 0 }; 5370 5371 set_param_parameters[0] = state->m_constellation; /* modulation */ 5372 set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5373 5374 if (number_of_parameters == 2) { 5375 u16 set_env_parameters[1] = { 0 }; 5376 5377 if (state->m_operation_mode == OM_QAM_ITU_C) 5378 set_env_parameters[0] = QAM_TOP_ANNEX_C; 5379 else 5380 set_env_parameters[0] = QAM_TOP_ANNEX_A; 5381 5382 status = scu_command(state, 5383 SCU_RAM_COMMAND_STANDARD_QAM 5384 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 5385 1, set_env_parameters, 1, &cmd_result); 5386 if (status < 0) 5387 goto error; 5388 5389 status = scu_command(state, 5390 SCU_RAM_COMMAND_STANDARD_QAM 5391 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5392 number_of_parameters, set_param_parameters, 5393 1, &cmd_result); 5394 } else if (number_of_parameters == 4) { 5395 if (state->m_operation_mode == OM_QAM_ITU_C) 5396 set_param_parameters[2] = QAM_TOP_ANNEX_C; 5397 else 5398 set_param_parameters[2] = QAM_TOP_ANNEX_A; 5399 5400 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON); 5401 /* Env parameters */ 5402 /* check for LOCKRANGE Extended */ 5403 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */ 5404 5405 status = scu_command(state, 5406 SCU_RAM_COMMAND_STANDARD_QAM 5407 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5408 number_of_parameters, set_param_parameters, 5409 1, &cmd_result); 5410 } else { 5411 pr_warn("Unknown QAM demodulator parameter count %d\n", 5412 number_of_parameters); 5413 status = -EINVAL; 5414 } 5415 5416 error: 5417 if (status < 0) 5418 pr_warn("Warning %d on %s\n", status, __func__); 5419 return status; 5420 } 5421 5422 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, 5423 s32 tuner_freq_offset) 5424 { 5425 int status; 5426 u16 cmd_result; 5427 int qam_demod_param_count = state->qam_demod_parameter_count; 5428 5429 dprintk(1, "\n"); 5430 /* 5431 * STEP 1: reset demodulator 5432 * resets FEC DI and FEC RS 5433 * resets QAM block 5434 * resets SCU variables 5435 */ 5436 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); 5437 if (status < 0) 5438 goto error; 5439 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); 5440 if (status < 0) 5441 goto error; 5442 status = qam_reset_qam(state); 5443 if (status < 0) 5444 goto error; 5445 5446 /* 5447 * STEP 2: configure demodulator 5448 * -set params; resets IQM,QAM,FEC HW; initializes some 5449 * SCU variables 5450 */ 5451 status = qam_set_symbolrate(state); 5452 if (status < 0) 5453 goto error; 5454 5455 /* Set params */ 5456 switch (state->props.modulation) { 5457 case QAM_256: 5458 state->m_constellation = DRX_CONSTELLATION_QAM256; 5459 break; 5460 case QAM_AUTO: 5461 case QAM_64: 5462 state->m_constellation = DRX_CONSTELLATION_QAM64; 5463 break; 5464 case QAM_16: 5465 state->m_constellation = DRX_CONSTELLATION_QAM16; 5466 break; 5467 case QAM_32: 5468 state->m_constellation = DRX_CONSTELLATION_QAM32; 5469 break; 5470 case QAM_128: 5471 state->m_constellation = DRX_CONSTELLATION_QAM128; 5472 break; 5473 default: 5474 status = -EINVAL; 5475 break; 5476 } 5477 if (status < 0) 5478 goto error; 5479 5480 /* Use the 4-parameter if it's requested or we're probing for 5481 * the correct command. */ 5482 if (state->qam_demod_parameter_count == 4 5483 || !state->qam_demod_parameter_count) { 5484 qam_demod_param_count = 4; 5485 status = qam_demodulator_command(state, qam_demod_param_count); 5486 } 5487 5488 /* Use the 2-parameter command if it was requested or if we're 5489 * probing for the correct command and the 4-parameter command 5490 * failed. */ 5491 if (state->qam_demod_parameter_count == 2 5492 || (!state->qam_demod_parameter_count && status < 0)) { 5493 qam_demod_param_count = 2; 5494 status = qam_demodulator_command(state, qam_demod_param_count); 5495 } 5496 5497 if (status < 0) { 5498 dprintk(1, "Could not set demodulator parameters.\n"); 5499 dprintk(1, 5500 "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n", 5501 state->qam_demod_parameter_count, 5502 state->microcode_name); 5503 goto error; 5504 } else if (!state->qam_demod_parameter_count) { 5505 dprintk(1, 5506 "Auto-probing the QAM command parameters was successful - using %d parameters.\n", 5507 qam_demod_param_count); 5508 5509 /* 5510 * One of our commands was successful. We don't need to 5511 * auto-probe anymore, now that we got the correct command. 5512 */ 5513 state->qam_demod_parameter_count = qam_demod_param_count; 5514 } 5515 5516 /* 5517 * STEP 3: enable the system in a mode where the ADC provides valid 5518 * signal setup modulation independent registers 5519 */ 5520 #if 0 5521 status = set_frequency(channel, tuner_freq_offset)); 5522 if (status < 0) 5523 goto error; 5524 #endif 5525 status = set_frequency_shifter(state, intermediate_freqk_hz, 5526 tuner_freq_offset, true); 5527 if (status < 0) 5528 goto error; 5529 5530 /* Setup BER measurement */ 5531 status = set_qam_measurement(state, state->m_constellation, 5532 state->props.symbol_rate); 5533 if (status < 0) 5534 goto error; 5535 5536 /* Reset default values */ 5537 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); 5538 if (status < 0) 5539 goto error; 5540 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); 5541 if (status < 0) 5542 goto error; 5543 5544 /* Reset default LC values */ 5545 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); 5546 if (status < 0) 5547 goto error; 5548 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); 5549 if (status < 0) 5550 goto error; 5551 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); 5552 if (status < 0) 5553 goto error; 5554 status = write16(state, QAM_LC_MODE__A, 7); 5555 if (status < 0) 5556 goto error; 5557 5558 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); 5559 if (status < 0) 5560 goto error; 5561 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); 5562 if (status < 0) 5563 goto error; 5564 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); 5565 if (status < 0) 5566 goto error; 5567 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); 5568 if (status < 0) 5569 goto error; 5570 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); 5571 if (status < 0) 5572 goto error; 5573 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); 5574 if (status < 0) 5575 goto error; 5576 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); 5577 if (status < 0) 5578 goto error; 5579 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); 5580 if (status < 0) 5581 goto error; 5582 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); 5583 if (status < 0) 5584 goto error; 5585 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); 5586 if (status < 0) 5587 goto error; 5588 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); 5589 if (status < 0) 5590 goto error; 5591 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); 5592 if (status < 0) 5593 goto error; 5594 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); 5595 if (status < 0) 5596 goto error; 5597 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); 5598 if (status < 0) 5599 goto error; 5600 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); 5601 if (status < 0) 5602 goto error; 5603 5604 /* Mirroring, QAM-block starting point not inverted */ 5605 status = write16(state, QAM_SY_SP_INV__A, 5606 QAM_SY_SP_INV_SPECTRUM_INV_DIS); 5607 if (status < 0) 5608 goto error; 5609 5610 /* Halt SCU to enable safe non-atomic accesses */ 5611 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5612 if (status < 0) 5613 goto error; 5614 5615 /* STEP 4: modulation specific setup */ 5616 switch (state->props.modulation) { 5617 case QAM_16: 5618 status = set_qam16(state); 5619 break; 5620 case QAM_32: 5621 status = set_qam32(state); 5622 break; 5623 case QAM_AUTO: 5624 case QAM_64: 5625 status = set_qam64(state); 5626 break; 5627 case QAM_128: 5628 status = set_qam128(state); 5629 break; 5630 case QAM_256: 5631 status = set_qam256(state); 5632 break; 5633 default: 5634 status = -EINVAL; 5635 break; 5636 } 5637 if (status < 0) 5638 goto error; 5639 5640 /* Activate SCU to enable SCU commands */ 5641 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5642 if (status < 0) 5643 goto error; 5644 5645 /* Re-configure MPEG output, requires knowledge of channel bitrate */ 5646 /* extAttr->currentChannel.modulation = channel->modulation; */ 5647 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ 5648 status = mpegts_dto_setup(state, state->m_operation_mode); 5649 if (status < 0) 5650 goto error; 5651 5652 /* start processes */ 5653 status = mpegts_start(state); 5654 if (status < 0) 5655 goto error; 5656 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 5657 if (status < 0) 5658 goto error; 5659 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); 5660 if (status < 0) 5661 goto error; 5662 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 5663 if (status < 0) 5664 goto error; 5665 5666 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 5667 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 5668 | SCU_RAM_COMMAND_CMD_DEMOD_START, 5669 0, NULL, 1, &cmd_result); 5670 if (status < 0) 5671 goto error; 5672 5673 /* update global DRXK data container */ 5674 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ 5675 5676 error: 5677 if (status < 0) 5678 pr_err("Error %d on %s\n", status, __func__); 5679 return status; 5680 } 5681 5682 static int set_qam_standard(struct drxk_state *state, 5683 enum operation_mode o_mode) 5684 { 5685 int status; 5686 #ifdef DRXK_QAM_TAPS 5687 #define DRXK_QAMA_TAPS_SELECT 5688 #include "drxk_filters.h" 5689 #undef DRXK_QAMA_TAPS_SELECT 5690 #endif 5691 5692 dprintk(1, "\n"); 5693 5694 /* added antenna switch */ 5695 switch_antenna_to_qam(state); 5696 5697 /* Ensure correct power-up mode */ 5698 status = power_up_qam(state); 5699 if (status < 0) 5700 goto error; 5701 /* Reset QAM block */ 5702 status = qam_reset_qam(state); 5703 if (status < 0) 5704 goto error; 5705 5706 /* Setup IQM */ 5707 5708 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 5709 if (status < 0) 5710 goto error; 5711 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 5712 if (status < 0) 5713 goto error; 5714 5715 /* Upload IQM Channel Filter settings by 5716 boot loader from ROM table */ 5717 switch (o_mode) { 5718 case OM_QAM_ITU_A: 5719 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, 5720 DRXK_BLCC_NR_ELEMENTS_TAPS, 5721 DRXK_BLC_TIMEOUT); 5722 break; 5723 case OM_QAM_ITU_C: 5724 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, 5725 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5726 DRXK_BLDC_NR_ELEMENTS_TAPS, 5727 DRXK_BLC_TIMEOUT); 5728 if (status < 0) 5729 goto error; 5730 status = bl_direct_cmd(state, 5731 IQM_CF_TAP_IM0__A, 5732 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5733 DRXK_BLDC_NR_ELEMENTS_TAPS, 5734 DRXK_BLC_TIMEOUT); 5735 break; 5736 default: 5737 status = -EINVAL; 5738 } 5739 if (status < 0) 5740 goto error; 5741 5742 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); 5743 if (status < 0) 5744 goto error; 5745 status = write16(state, IQM_CF_SYMMETRIC__A, 0); 5746 if (status < 0) 5747 goto error; 5748 status = write16(state, IQM_CF_MIDTAP__A, 5749 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); 5750 if (status < 0) 5751 goto error; 5752 5753 status = write16(state, IQM_RC_STRETCH__A, 21); 5754 if (status < 0) 5755 goto error; 5756 status = write16(state, IQM_AF_CLP_LEN__A, 0); 5757 if (status < 0) 5758 goto error; 5759 status = write16(state, IQM_AF_CLP_TH__A, 448); 5760 if (status < 0) 5761 goto error; 5762 status = write16(state, IQM_AF_SNS_LEN__A, 0); 5763 if (status < 0) 5764 goto error; 5765 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); 5766 if (status < 0) 5767 goto error; 5768 5769 status = write16(state, IQM_FS_ADJ_SEL__A, 1); 5770 if (status < 0) 5771 goto error; 5772 status = write16(state, IQM_RC_ADJ_SEL__A, 1); 5773 if (status < 0) 5774 goto error; 5775 status = write16(state, IQM_CF_ADJ_SEL__A, 1); 5776 if (status < 0) 5777 goto error; 5778 status = write16(state, IQM_AF_UPD_SEL__A, 0); 5779 if (status < 0) 5780 goto error; 5781 5782 /* IQM Impulse Noise Processing Unit */ 5783 status = write16(state, IQM_CF_CLP_VAL__A, 500); 5784 if (status < 0) 5785 goto error; 5786 status = write16(state, IQM_CF_DATATH__A, 1000); 5787 if (status < 0) 5788 goto error; 5789 status = write16(state, IQM_CF_BYPASSDET__A, 1); 5790 if (status < 0) 5791 goto error; 5792 status = write16(state, IQM_CF_DET_LCT__A, 0); 5793 if (status < 0) 5794 goto error; 5795 status = write16(state, IQM_CF_WND_LEN__A, 1); 5796 if (status < 0) 5797 goto error; 5798 status = write16(state, IQM_CF_PKDTH__A, 1); 5799 if (status < 0) 5800 goto error; 5801 status = write16(state, IQM_AF_INC_BYPASS__A, 1); 5802 if (status < 0) 5803 goto error; 5804 5805 /* turn on IQMAF. Must be done before setAgc**() */ 5806 status = set_iqm_af(state, true); 5807 if (status < 0) 5808 goto error; 5809 status = write16(state, IQM_AF_START_LOCK__A, 0x01); 5810 if (status < 0) 5811 goto error; 5812 5813 /* IQM will not be reset from here, sync ADC and update/init AGC */ 5814 status = adc_synchronization(state); 5815 if (status < 0) 5816 goto error; 5817 5818 /* Set the FSM step period */ 5819 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); 5820 if (status < 0) 5821 goto error; 5822 5823 /* Halt SCU to enable safe non-atomic accesses */ 5824 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5825 if (status < 0) 5826 goto error; 5827 5828 /* No more resets of the IQM, current standard correctly set => 5829 now AGCs can be configured. */ 5830 5831 status = init_agc(state, true); 5832 if (status < 0) 5833 goto error; 5834 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); 5835 if (status < 0) 5836 goto error; 5837 5838 /* Configure AGC's */ 5839 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); 5840 if (status < 0) 5841 goto error; 5842 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); 5843 if (status < 0) 5844 goto error; 5845 5846 /* Activate SCU to enable SCU commands */ 5847 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5848 error: 5849 if (status < 0) 5850 pr_err("Error %d on %s\n", status, __func__); 5851 return status; 5852 } 5853 5854 static int write_gpio(struct drxk_state *state) 5855 { 5856 int status; 5857 u16 value = 0; 5858 5859 dprintk(1, "\n"); 5860 /* stop lock indicator process */ 5861 status = write16(state, SCU_RAM_GPIO__A, 5862 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5863 if (status < 0) 5864 goto error; 5865 5866 /* Write magic word to enable pdr reg write */ 5867 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 5868 if (status < 0) 5869 goto error; 5870 5871 if (state->m_has_sawsw) { 5872 if (state->uio_mask & 0x0001) { /* UIO-1 */ 5873 /* write to io pad configuration register - output mode */ 5874 status = write16(state, SIO_PDR_SMA_TX_CFG__A, 5875 state->m_gpio_cfg); 5876 if (status < 0) 5877 goto error; 5878 5879 /* use corresponding bit in io data output registar */ 5880 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5881 if (status < 0) 5882 goto error; 5883 if ((state->m_gpio & 0x0001) == 0) 5884 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ 5885 else 5886 value |= 0x8000; /* write one to 15th bit - 1st UIO */ 5887 /* write back to io data output register */ 5888 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5889 if (status < 0) 5890 goto error; 5891 } 5892 if (state->uio_mask & 0x0002) { /* UIO-2 */ 5893 /* write to io pad configuration register - output mode */ 5894 status = write16(state, SIO_PDR_SMA_RX_CFG__A, 5895 state->m_gpio_cfg); 5896 if (status < 0) 5897 goto error; 5898 5899 /* use corresponding bit in io data output registar */ 5900 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5901 if (status < 0) 5902 goto error; 5903 if ((state->m_gpio & 0x0002) == 0) 5904 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ 5905 else 5906 value |= 0x4000; /* write one to 14th bit - 2st UIO */ 5907 /* write back to io data output register */ 5908 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5909 if (status < 0) 5910 goto error; 5911 } 5912 if (state->uio_mask & 0x0004) { /* UIO-3 */ 5913 /* write to io pad configuration register - output mode */ 5914 status = write16(state, SIO_PDR_GPIO_CFG__A, 5915 state->m_gpio_cfg); 5916 if (status < 0) 5917 goto error; 5918 5919 /* use corresponding bit in io data output registar */ 5920 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5921 if (status < 0) 5922 goto error; 5923 if ((state->m_gpio & 0x0004) == 0) 5924 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ 5925 else 5926 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ 5927 /* write back to io data output register */ 5928 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5929 if (status < 0) 5930 goto error; 5931 } 5932 } 5933 /* Write magic word to disable pdr reg write */ 5934 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 5935 error: 5936 if (status < 0) 5937 pr_err("Error %d on %s\n", status, __func__); 5938 return status; 5939 } 5940 5941 static int switch_antenna_to_qam(struct drxk_state *state) 5942 { 5943 int status = 0; 5944 bool gpio_state; 5945 5946 dprintk(1, "\n"); 5947 5948 if (!state->antenna_gpio) 5949 return 0; 5950 5951 gpio_state = state->m_gpio & state->antenna_gpio; 5952 5953 if (state->antenna_dvbt ^ gpio_state) { 5954 /* Antenna is on DVB-T mode. Switch */ 5955 if (state->antenna_dvbt) 5956 state->m_gpio &= ~state->antenna_gpio; 5957 else 5958 state->m_gpio |= state->antenna_gpio; 5959 status = write_gpio(state); 5960 } 5961 if (status < 0) 5962 pr_err("Error %d on %s\n", status, __func__); 5963 return status; 5964 } 5965 5966 static int switch_antenna_to_dvbt(struct drxk_state *state) 5967 { 5968 int status = 0; 5969 bool gpio_state; 5970 5971 dprintk(1, "\n"); 5972 5973 if (!state->antenna_gpio) 5974 return 0; 5975 5976 gpio_state = state->m_gpio & state->antenna_gpio; 5977 5978 if (!(state->antenna_dvbt ^ gpio_state)) { 5979 /* Antenna is on DVB-C mode. Switch */ 5980 if (state->antenna_dvbt) 5981 state->m_gpio |= state->antenna_gpio; 5982 else 5983 state->m_gpio &= ~state->antenna_gpio; 5984 status = write_gpio(state); 5985 } 5986 if (status < 0) 5987 pr_err("Error %d on %s\n", status, __func__); 5988 return status; 5989 } 5990 5991 5992 static int power_down_device(struct drxk_state *state) 5993 { 5994 /* Power down to requested mode */ 5995 /* Backup some register settings */ 5996 /* Set pins with possible pull-ups connected to them in input mode */ 5997 /* Analog power down */ 5998 /* ADC power down */ 5999 /* Power down device */ 6000 int status; 6001 6002 dprintk(1, "\n"); 6003 if (state->m_b_p_down_open_bridge) { 6004 /* Open I2C bridge before power down of DRXK */ 6005 status = ConfigureI2CBridge(state, true); 6006 if (status < 0) 6007 goto error; 6008 } 6009 /* driver 0.9.0 */ 6010 status = dvbt_enable_ofdm_token_ring(state, false); 6011 if (status < 0) 6012 goto error; 6013 6014 status = write16(state, SIO_CC_PWD_MODE__A, 6015 SIO_CC_PWD_MODE_LEVEL_CLOCK); 6016 if (status < 0) 6017 goto error; 6018 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6019 if (status < 0) 6020 goto error; 6021 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 6022 status = hi_cfg_command(state); 6023 error: 6024 if (status < 0) 6025 pr_err("Error %d on %s\n", status, __func__); 6026 6027 return status; 6028 } 6029 6030 static int init_drxk(struct drxk_state *state) 6031 { 6032 int status = 0, n = 0; 6033 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 6034 u16 driver_version; 6035 6036 dprintk(1, "\n"); 6037 if (state->m_drxk_state == DRXK_UNINITIALIZED) { 6038 drxk_i2c_lock(state); 6039 status = power_up_device(state); 6040 if (status < 0) 6041 goto error; 6042 status = drxx_open(state); 6043 if (status < 0) 6044 goto error; 6045 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 6046 status = write16(state, SIO_CC_SOFT_RST__A, 6047 SIO_CC_SOFT_RST_OFDM__M 6048 | SIO_CC_SOFT_RST_SYS__M 6049 | SIO_CC_SOFT_RST_OSC__M); 6050 if (status < 0) 6051 goto error; 6052 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6053 if (status < 0) 6054 goto error; 6055 /* 6056 * TODO is this needed? If yes, how much delay in 6057 * worst case scenario 6058 */ 6059 usleep_range(1000, 2000); 6060 state->m_drxk_a3_patch_code = true; 6061 status = get_device_capabilities(state); 6062 if (status < 0) 6063 goto error; 6064 6065 /* Bridge delay, uses oscilator clock */ 6066 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ 6067 /* SDA brdige delay */ 6068 state->m_hi_cfg_bridge_delay = 6069 (u16) ((state->m_osc_clock_freq / 1000) * 6070 HI_I2C_BRIDGE_DELAY) / 1000; 6071 /* Clipping */ 6072 if (state->m_hi_cfg_bridge_delay > 6073 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { 6074 state->m_hi_cfg_bridge_delay = 6075 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; 6076 } 6077 /* SCL bridge delay, same as SDA for now */ 6078 state->m_hi_cfg_bridge_delay += 6079 state->m_hi_cfg_bridge_delay << 6080 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; 6081 6082 status = init_hi(state); 6083 if (status < 0) 6084 goto error; 6085 /* disable various processes */ 6086 #if NOA1ROM 6087 if (!(state->m_DRXK_A1_ROM_CODE) 6088 && !(state->m_DRXK_A2_ROM_CODE)) 6089 #endif 6090 { 6091 status = write16(state, SCU_RAM_GPIO__A, 6092 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 6093 if (status < 0) 6094 goto error; 6095 } 6096 6097 /* disable MPEG port */ 6098 status = mpegts_disable(state); 6099 if (status < 0) 6100 goto error; 6101 6102 /* Stop AUD and SCU */ 6103 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); 6104 if (status < 0) 6105 goto error; 6106 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); 6107 if (status < 0) 6108 goto error; 6109 6110 /* enable token-ring bus through OFDM block for possible ucode upload */ 6111 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 6112 SIO_OFDM_SH_OFDM_RING_ENABLE_ON); 6113 if (status < 0) 6114 goto error; 6115 6116 /* include boot loader section */ 6117 status = write16(state, SIO_BL_COMM_EXEC__A, 6118 SIO_BL_COMM_EXEC_ACTIVE); 6119 if (status < 0) 6120 goto error; 6121 status = bl_chain_cmd(state, 0, 6, 100); 6122 if (status < 0) 6123 goto error; 6124 6125 if (state->fw) { 6126 status = download_microcode(state, state->fw->data, 6127 state->fw->size); 6128 if (status < 0) 6129 goto error; 6130 } 6131 6132 /* disable token-ring bus through OFDM block for possible ucode upload */ 6133 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 6134 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); 6135 if (status < 0) 6136 goto error; 6137 6138 /* Run SCU for a little while to initialize microcode version numbers */ 6139 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 6140 if (status < 0) 6141 goto error; 6142 status = drxx_open(state); 6143 if (status < 0) 6144 goto error; 6145 /* added for test */ 6146 msleep(30); 6147 6148 power_mode = DRXK_POWER_DOWN_OFDM; 6149 status = ctrl_power_mode(state, &power_mode); 6150 if (status < 0) 6151 goto error; 6152 6153 /* Stamp driver version number in SCU data RAM in BCD code 6154 Done to enable field application engineers to retrieve drxdriver version 6155 via I2C from SCU RAM. 6156 Not using SCU command interface for SCU register access since no 6157 microcode may be present. 6158 */ 6159 driver_version = 6160 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + 6161 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + 6162 ((DRXK_VERSION_MAJOR % 10) << 4) + 6163 (DRXK_VERSION_MINOR % 10); 6164 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, 6165 driver_version); 6166 if (status < 0) 6167 goto error; 6168 driver_version = 6169 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + 6170 (((DRXK_VERSION_PATCH / 100) % 10) << 8) + 6171 (((DRXK_VERSION_PATCH / 10) % 10) << 4) + 6172 (DRXK_VERSION_PATCH % 10); 6173 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, 6174 driver_version); 6175 if (status < 0) 6176 goto error; 6177 6178 pr_info("DRXK driver version %d.%d.%d\n", 6179 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, 6180 DRXK_VERSION_PATCH); 6181 6182 /* 6183 * Dirty fix of default values for ROM/PATCH microcode 6184 * Dirty because this fix makes it impossible to setup 6185 * suitable values before calling DRX_Open. This solution 6186 * requires changes to RF AGC speed to be done via the CTRL 6187 * function after calling DRX_Open 6188 */ 6189 6190 /* m_dvbt_rf_agc_cfg.speed = 3; */ 6191 6192 /* Reset driver debug flags to 0 */ 6193 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); 6194 if (status < 0) 6195 goto error; 6196 /* driver 0.9.0 */ 6197 /* Setup FEC OC: 6198 NOTE: No more full FEC resets allowed afterwards!! */ 6199 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); 6200 if (status < 0) 6201 goto error; 6202 /* MPEGTS functions are still the same */ 6203 status = mpegts_dto_init(state); 6204 if (status < 0) 6205 goto error; 6206 status = mpegts_stop(state); 6207 if (status < 0) 6208 goto error; 6209 status = mpegts_configure_polarity(state); 6210 if (status < 0) 6211 goto error; 6212 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); 6213 if (status < 0) 6214 goto error; 6215 /* added: configure GPIO */ 6216 status = write_gpio(state); 6217 if (status < 0) 6218 goto error; 6219 6220 state->m_drxk_state = DRXK_STOPPED; 6221 6222 if (state->m_b_power_down) { 6223 status = power_down_device(state); 6224 if (status < 0) 6225 goto error; 6226 state->m_drxk_state = DRXK_POWERED_DOWN; 6227 } else 6228 state->m_drxk_state = DRXK_STOPPED; 6229 6230 /* Initialize the supported delivery systems */ 6231 n = 0; 6232 if (state->m_has_dvbc) { 6233 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; 6234 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; 6235 strlcat(state->frontend.ops.info.name, " DVB-C", 6236 sizeof(state->frontend.ops.info.name)); 6237 } 6238 if (state->m_has_dvbt) { 6239 state->frontend.ops.delsys[n++] = SYS_DVBT; 6240 strlcat(state->frontend.ops.info.name, " DVB-T", 6241 sizeof(state->frontend.ops.info.name)); 6242 } 6243 drxk_i2c_unlock(state); 6244 } 6245 error: 6246 if (status < 0) { 6247 state->m_drxk_state = DRXK_NO_DEV; 6248 drxk_i2c_unlock(state); 6249 pr_err("Error %d on %s\n", status, __func__); 6250 } 6251 6252 return status; 6253 } 6254 6255 static void load_firmware_cb(const struct firmware *fw, 6256 void *context) 6257 { 6258 struct drxk_state *state = context; 6259 6260 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded"); 6261 if (!fw) { 6262 pr_err("Could not load firmware file %s.\n", 6263 state->microcode_name); 6264 pr_info("Copy %s to your hotplug directory!\n", 6265 state->microcode_name); 6266 state->microcode_name = NULL; 6267 6268 /* 6269 * As firmware is now load asynchronous, it is not possible 6270 * anymore to fail at frontend attach. We might silently 6271 * return here, and hope that the driver won't crash. 6272 * We might also change all DVB callbacks to return -ENODEV 6273 * if the device is not initialized. 6274 * As the DRX-K devices have their own internal firmware, 6275 * let's just hope that it will match a firmware revision 6276 * compatible with this driver and proceed. 6277 */ 6278 } 6279 state->fw = fw; 6280 6281 init_drxk(state); 6282 } 6283 6284 static void drxk_release(struct dvb_frontend *fe) 6285 { 6286 struct drxk_state *state = fe->demodulator_priv; 6287 6288 dprintk(1, "\n"); 6289 release_firmware(state->fw); 6290 6291 kfree(state); 6292 } 6293 6294 static int drxk_sleep(struct dvb_frontend *fe) 6295 { 6296 struct drxk_state *state = fe->demodulator_priv; 6297 6298 dprintk(1, "\n"); 6299 6300 if (state->m_drxk_state == DRXK_NO_DEV) 6301 return -ENODEV; 6302 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6303 return 0; 6304 6305 shut_down(state); 6306 return 0; 6307 } 6308 6309 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) 6310 { 6311 struct drxk_state *state = fe->demodulator_priv; 6312 6313 dprintk(1, ": %s\n", enable ? "enable" : "disable"); 6314 6315 if (state->m_drxk_state == DRXK_NO_DEV) 6316 return -ENODEV; 6317 6318 return ConfigureI2CBridge(state, enable ? true : false); 6319 } 6320 6321 static int drxk_set_parameters(struct dvb_frontend *fe) 6322 { 6323 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 6324 u32 delsys = p->delivery_system, old_delsys; 6325 struct drxk_state *state = fe->demodulator_priv; 6326 u32 IF; 6327 6328 dprintk(1, "\n"); 6329 6330 if (state->m_drxk_state == DRXK_NO_DEV) 6331 return -ENODEV; 6332 6333 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6334 return -EAGAIN; 6335 6336 if (!fe->ops.tuner_ops.get_if_frequency) { 6337 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); 6338 return -EINVAL; 6339 } 6340 6341 if (fe->ops.i2c_gate_ctrl) 6342 fe->ops.i2c_gate_ctrl(fe, 1); 6343 if (fe->ops.tuner_ops.set_params) 6344 fe->ops.tuner_ops.set_params(fe); 6345 if (fe->ops.i2c_gate_ctrl) 6346 fe->ops.i2c_gate_ctrl(fe, 0); 6347 6348 old_delsys = state->props.delivery_system; 6349 state->props = *p; 6350 6351 if (old_delsys != delsys) { 6352 shut_down(state); 6353 switch (delsys) { 6354 case SYS_DVBC_ANNEX_A: 6355 case SYS_DVBC_ANNEX_C: 6356 if (!state->m_has_dvbc) 6357 return -EINVAL; 6358 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? 6359 true : false; 6360 if (state->m_itut_annex_c) 6361 setoperation_mode(state, OM_QAM_ITU_C); 6362 else 6363 setoperation_mode(state, OM_QAM_ITU_A); 6364 break; 6365 case SYS_DVBT: 6366 if (!state->m_has_dvbt) 6367 return -EINVAL; 6368 setoperation_mode(state, OM_DVBT); 6369 break; 6370 default: 6371 return -EINVAL; 6372 } 6373 } 6374 6375 fe->ops.tuner_ops.get_if_frequency(fe, &IF); 6376 start(state, 0, IF); 6377 6378 /* After set_frontend, stats aren't available */ 6379 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 6380 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6381 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6382 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6383 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6384 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6385 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6386 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6387 6388 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ 6389 6390 return 0; 6391 } 6392 6393 static int get_strength(struct drxk_state *state, u64 *strength) 6394 { 6395 int status; 6396 struct s_cfg_agc rf_agc, if_agc; 6397 u32 total_gain = 0; 6398 u32 atten = 0; 6399 u32 agc_range = 0; 6400 u16 scu_lvl = 0; 6401 u16 scu_coc = 0; 6402 /* FIXME: those are part of the tuner presets */ 6403 u16 tuner_rf_gain = 50; /* Default value on az6007 driver */ 6404 u16 tuner_if_gain = 40; /* Default value on az6007 driver */ 6405 6406 *strength = 0; 6407 6408 if (is_dvbt(state)) { 6409 rf_agc = state->m_dvbt_rf_agc_cfg; 6410 if_agc = state->m_dvbt_if_agc_cfg; 6411 } else if (is_qam(state)) { 6412 rf_agc = state->m_qam_rf_agc_cfg; 6413 if_agc = state->m_qam_if_agc_cfg; 6414 } else { 6415 rf_agc = state->m_atv_rf_agc_cfg; 6416 if_agc = state->m_atv_if_agc_cfg; 6417 } 6418 6419 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { 6420 /* SCU output_level */ 6421 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); 6422 if (status < 0) 6423 return status; 6424 6425 /* SCU c.o.c. */ 6426 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); 6427 if (status < 0) 6428 return status; 6429 6430 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff) 6431 rf_agc.output_level = scu_lvl + scu_coc; 6432 else 6433 rf_agc.output_level = 0xffff; 6434 6435 /* Take RF gain into account */ 6436 total_gain += tuner_rf_gain; 6437 6438 /* clip output value */ 6439 if (rf_agc.output_level < rf_agc.min_output_level) 6440 rf_agc.output_level = rf_agc.min_output_level; 6441 if (rf_agc.output_level > rf_agc.max_output_level) 6442 rf_agc.output_level = rf_agc.max_output_level; 6443 6444 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level); 6445 if (agc_range > 0) { 6446 atten += 100UL * 6447 ((u32)(tuner_rf_gain)) * 6448 ((u32)(rf_agc.output_level - rf_agc.min_output_level)) 6449 / agc_range; 6450 } 6451 } 6452 6453 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { 6454 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 6455 &if_agc.output_level); 6456 if (status < 0) 6457 return status; 6458 6459 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, 6460 &if_agc.top); 6461 if (status < 0) 6462 return status; 6463 6464 /* Take IF gain into account */ 6465 total_gain += (u32) tuner_if_gain; 6466 6467 /* clip output value */ 6468 if (if_agc.output_level < if_agc.min_output_level) 6469 if_agc.output_level = if_agc.min_output_level; 6470 if (if_agc.output_level > if_agc.max_output_level) 6471 if_agc.output_level = if_agc.max_output_level; 6472 6473 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level); 6474 if (agc_range > 0) { 6475 atten += 100UL * 6476 ((u32)(tuner_if_gain)) * 6477 ((u32)(if_agc.output_level - if_agc.min_output_level)) 6478 / agc_range; 6479 } 6480 } 6481 6482 /* 6483 * Convert to 0..65535 scale. 6484 * If it can't be measured (AGC is disabled), just show 100%. 6485 */ 6486 if (total_gain > 0) 6487 *strength = (65535UL * atten / total_gain / 100); 6488 else 6489 *strength = 65535; 6490 6491 return 0; 6492 } 6493 6494 static int drxk_get_stats(struct dvb_frontend *fe) 6495 { 6496 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6497 struct drxk_state *state = fe->demodulator_priv; 6498 int status; 6499 u32 stat; 6500 u16 reg16; 6501 u32 post_bit_count; 6502 u32 post_bit_err_count; 6503 u32 post_bit_error_scale; 6504 u32 pre_bit_err_count; 6505 u32 pre_bit_count; 6506 u32 pkt_count; 6507 u32 pkt_error_count; 6508 s32 cnr; 6509 6510 if (state->m_drxk_state == DRXK_NO_DEV) 6511 return -ENODEV; 6512 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6513 return -EAGAIN; 6514 6515 /* get status */ 6516 state->fe_status = 0; 6517 get_lock_status(state, &stat); 6518 if (stat == MPEG_LOCK) 6519 state->fe_status |= 0x1f; 6520 if (stat == FEC_LOCK) 6521 state->fe_status |= 0x0f; 6522 if (stat == DEMOD_LOCK) 6523 state->fe_status |= 0x07; 6524 6525 /* 6526 * Estimate signal strength from AGC 6527 */ 6528 get_strength(state, &c->strength.stat[0].uvalue); 6529 c->strength.stat[0].scale = FE_SCALE_RELATIVE; 6530 6531 6532 if (stat >= DEMOD_LOCK) { 6533 get_signal_to_noise(state, &cnr); 6534 c->cnr.stat[0].svalue = cnr * 100; 6535 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 6536 } else { 6537 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6538 } 6539 6540 if (stat < FEC_LOCK) { 6541 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6542 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6543 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6544 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6545 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6546 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6547 return 0; 6548 } 6549 6550 /* Get post BER */ 6551 6552 /* BER measurement is valid if at least FEC lock is achieved */ 6553 6554 /* 6555 * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be 6556 * written to set nr of symbols or bits over which to measure 6557 * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). 6558 */ 6559 6560 /* Read registers for post/preViterbi BER calculation */ 6561 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); 6562 if (status < 0) 6563 goto error; 6564 pre_bit_err_count = reg16; 6565 6566 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); 6567 if (status < 0) 6568 goto error; 6569 pre_bit_count = reg16; 6570 6571 /* Number of bit-errors */ 6572 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); 6573 if (status < 0) 6574 goto error; 6575 post_bit_err_count = reg16; 6576 6577 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); 6578 if (status < 0) 6579 goto error; 6580 post_bit_error_scale = reg16; 6581 6582 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); 6583 if (status < 0) 6584 goto error; 6585 pkt_count = reg16; 6586 6587 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); 6588 if (status < 0) 6589 goto error; 6590 pkt_error_count = reg16; 6591 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 6592 6593 post_bit_err_count *= post_bit_error_scale; 6594 6595 post_bit_count = pkt_count * 204 * 8; 6596 6597 /* Store the results */ 6598 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 6599 c->block_error.stat[0].uvalue += pkt_error_count; 6600 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 6601 c->block_count.stat[0].uvalue += pkt_count; 6602 6603 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 6604 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count; 6605 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 6606 c->pre_bit_count.stat[0].uvalue += pre_bit_count; 6607 6608 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 6609 c->post_bit_error.stat[0].uvalue += post_bit_err_count; 6610 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 6611 c->post_bit_count.stat[0].uvalue += post_bit_count; 6612 6613 error: 6614 return status; 6615 } 6616 6617 6618 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status) 6619 { 6620 struct drxk_state *state = fe->demodulator_priv; 6621 int rc; 6622 6623 dprintk(1, "\n"); 6624 6625 rc = drxk_get_stats(fe); 6626 if (rc < 0) 6627 return rc; 6628 6629 *status = state->fe_status; 6630 6631 return 0; 6632 } 6633 6634 static int drxk_read_signal_strength(struct dvb_frontend *fe, 6635 u16 *strength) 6636 { 6637 struct drxk_state *state = fe->demodulator_priv; 6638 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6639 6640 dprintk(1, "\n"); 6641 6642 if (state->m_drxk_state == DRXK_NO_DEV) 6643 return -ENODEV; 6644 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6645 return -EAGAIN; 6646 6647 *strength = c->strength.stat[0].uvalue; 6648 return 0; 6649 } 6650 6651 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) 6652 { 6653 struct drxk_state *state = fe->demodulator_priv; 6654 s32 snr2; 6655 6656 dprintk(1, "\n"); 6657 6658 if (state->m_drxk_state == DRXK_NO_DEV) 6659 return -ENODEV; 6660 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6661 return -EAGAIN; 6662 6663 get_signal_to_noise(state, &snr2); 6664 6665 /* No negative SNR, clip to zero */ 6666 if (snr2 < 0) 6667 snr2 = 0; 6668 *snr = snr2 & 0xffff; 6669 return 0; 6670 } 6671 6672 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 6673 { 6674 struct drxk_state *state = fe->demodulator_priv; 6675 u16 err; 6676 6677 dprintk(1, "\n"); 6678 6679 if (state->m_drxk_state == DRXK_NO_DEV) 6680 return -ENODEV; 6681 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6682 return -EAGAIN; 6683 6684 dvbtqam_get_acc_pkt_err(state, &err); 6685 *ucblocks = (u32) err; 6686 return 0; 6687 } 6688 6689 static int drxk_get_tune_settings(struct dvb_frontend *fe, 6690 struct dvb_frontend_tune_settings *sets) 6691 { 6692 struct drxk_state *state = fe->demodulator_priv; 6693 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 6694 6695 dprintk(1, "\n"); 6696 6697 if (state->m_drxk_state == DRXK_NO_DEV) 6698 return -ENODEV; 6699 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6700 return -EAGAIN; 6701 6702 switch (p->delivery_system) { 6703 case SYS_DVBC_ANNEX_A: 6704 case SYS_DVBC_ANNEX_C: 6705 case SYS_DVBT: 6706 sets->min_delay_ms = 3000; 6707 sets->max_drift = 0; 6708 sets->step_size = 0; 6709 return 0; 6710 default: 6711 return -EINVAL; 6712 } 6713 } 6714 6715 static const struct dvb_frontend_ops drxk_ops = { 6716 /* .delsys will be filled dynamically */ 6717 .info = { 6718 .name = "DRXK", 6719 .frequency_min_hz = 47 * MHz, 6720 .frequency_max_hz = 865 * MHz, 6721 /* For DVB-C */ 6722 .symbol_rate_min = 870000, 6723 .symbol_rate_max = 11700000, 6724 /* For DVB-T */ 6725 .frequency_stepsize_hz = 166667, 6726 6727 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | 6728 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | 6729 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 6730 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS | 6731 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | 6732 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO 6733 }, 6734 6735 .release = drxk_release, 6736 .sleep = drxk_sleep, 6737 .i2c_gate_ctrl = drxk_gate_ctrl, 6738 6739 .set_frontend = drxk_set_parameters, 6740 .get_tune_settings = drxk_get_tune_settings, 6741 6742 .read_status = drxk_read_status, 6743 .read_signal_strength = drxk_read_signal_strength, 6744 .read_snr = drxk_read_snr, 6745 .read_ucblocks = drxk_read_ucblocks, 6746 }; 6747 6748 struct dvb_frontend *drxk_attach(const struct drxk_config *config, 6749 struct i2c_adapter *i2c) 6750 { 6751 struct dtv_frontend_properties *p; 6752 struct drxk_state *state = NULL; 6753 u8 adr = config->adr; 6754 int status; 6755 6756 dprintk(1, "\n"); 6757 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); 6758 if (!state) 6759 return NULL; 6760 6761 state->i2c = i2c; 6762 state->demod_address = adr; 6763 state->single_master = config->single_master; 6764 state->microcode_name = config->microcode_name; 6765 state->qam_demod_parameter_count = config->qam_demod_parameter_count; 6766 state->no_i2c_bridge = config->no_i2c_bridge; 6767 state->antenna_gpio = config->antenna_gpio; 6768 state->antenna_dvbt = config->antenna_dvbt; 6769 state->m_chunk_size = config->chunk_size; 6770 state->enable_merr_cfg = config->enable_merr_cfg; 6771 6772 if (config->dynamic_clk) { 6773 state->m_dvbt_static_clk = false; 6774 state->m_dvbc_static_clk = false; 6775 } else { 6776 state->m_dvbt_static_clk = true; 6777 state->m_dvbc_static_clk = true; 6778 } 6779 6780 6781 if (config->mpeg_out_clk_strength) 6782 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; 6783 else 6784 state->m_ts_clockk_strength = 0x06; 6785 6786 if (config->parallel_ts) 6787 state->m_enable_parallel = true; 6788 else 6789 state->m_enable_parallel = false; 6790 6791 /* NOTE: as more UIO bits will be used, add them to the mask */ 6792 state->uio_mask = config->antenna_gpio; 6793 6794 /* Default gpio to DVB-C */ 6795 if (!state->antenna_dvbt && state->antenna_gpio) 6796 state->m_gpio |= state->antenna_gpio; 6797 else 6798 state->m_gpio &= ~state->antenna_gpio; 6799 6800 mutex_init(&state->mutex); 6801 6802 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); 6803 state->frontend.demodulator_priv = state; 6804 6805 init_state(state); 6806 6807 /* Load firmware and initialize DRX-K */ 6808 if (state->microcode_name) { 6809 const struct firmware *fw = NULL; 6810 6811 status = request_firmware(&fw, state->microcode_name, 6812 state->i2c->dev.parent); 6813 if (status < 0) 6814 fw = NULL; 6815 load_firmware_cb(fw, state); 6816 } else if (init_drxk(state) < 0) 6817 goto error; 6818 6819 6820 /* Initialize stats */ 6821 p = &state->frontend.dtv_property_cache; 6822 p->strength.len = 1; 6823 p->cnr.len = 1; 6824 p->block_error.len = 1; 6825 p->block_count.len = 1; 6826 p->pre_bit_error.len = 1; 6827 p->pre_bit_count.len = 1; 6828 p->post_bit_error.len = 1; 6829 p->post_bit_count.len = 1; 6830 6831 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 6832 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6833 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6834 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6835 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6836 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6837 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6838 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6839 6840 pr_info("frontend initialized.\n"); 6841 return &state->frontend; 6842 6843 error: 6844 pr_err("not found\n"); 6845 kfree(state); 6846 return NULL; 6847 } 6848 EXPORT_SYMBOL(drxk_attach); 6849 6850 MODULE_DESCRIPTION("DRX-K driver"); 6851 MODULE_AUTHOR("Ralph Metzler"); 6852 MODULE_LICENSE("GPL"); 6853