1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * drxk_hard: DRX-K DVB-C/T demodulator driver
4  *
5  * Copyright (C) 2010-2011 Digital Devices GmbH
6  */
7 
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/i2c.h>
17 #include <linux/hardirq.h>
18 #include <asm/div64.h>
19 
20 #include <media/dvb_frontend.h>
21 #include "drxk.h"
22 #include "drxk_hard.h"
23 #include <media/dvb_math.h>
24 
25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26 static int power_down_qam(struct drxk_state *state);
27 static int set_dvbt_standard(struct drxk_state *state,
28 			   enum operation_mode o_mode);
29 static int set_qam_standard(struct drxk_state *state,
30 			  enum operation_mode o_mode);
31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
32 		  s32 tuner_freq_offset);
33 static int set_dvbt_standard(struct drxk_state *state,
34 			   enum operation_mode o_mode);
35 static int dvbt_start(struct drxk_state *state);
36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
37 		   s32 tuner_freq_offset);
38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40 static int switch_antenna_to_qam(struct drxk_state *state);
41 static int switch_antenna_to_dvbt(struct drxk_state *state);
42 
43 static bool is_dvbt(struct drxk_state *state)
44 {
45 	return state->m_operation_mode == OM_DVBT;
46 }
47 
48 static bool is_qam(struct drxk_state *state)
49 {
50 	return state->m_operation_mode == OM_QAM_ITU_A ||
51 	    state->m_operation_mode == OM_QAM_ITU_B ||
52 	    state->m_operation_mode == OM_QAM_ITU_C;
53 }
54 
55 #define NOA1ROM 0
56 
57 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
58 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
59 
60 #define DEFAULT_MER_83  165
61 #define DEFAULT_MER_93  250
62 
63 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
64 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
65 #endif
66 
67 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
68 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
69 #endif
70 
71 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
72 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
73 
74 #ifndef DRXK_KI_RAGC_ATV
75 #define DRXK_KI_RAGC_ATV   4
76 #endif
77 #ifndef DRXK_KI_IAGC_ATV
78 #define DRXK_KI_IAGC_ATV   6
79 #endif
80 #ifndef DRXK_KI_DAGC_ATV
81 #define DRXK_KI_DAGC_ATV   7
82 #endif
83 
84 #ifndef DRXK_KI_RAGC_QAM
85 #define DRXK_KI_RAGC_QAM   3
86 #endif
87 #ifndef DRXK_KI_IAGC_QAM
88 #define DRXK_KI_IAGC_QAM   4
89 #endif
90 #ifndef DRXK_KI_DAGC_QAM
91 #define DRXK_KI_DAGC_QAM   7
92 #endif
93 #ifndef DRXK_KI_RAGC_DVBT
94 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
95 #endif
96 #ifndef DRXK_KI_IAGC_DVBT
97 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
98 #endif
99 #ifndef DRXK_KI_DAGC_DVBT
100 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
101 #endif
102 
103 #ifndef DRXK_AGC_DAC_OFFSET
104 #define DRXK_AGC_DAC_OFFSET (0x800)
105 #endif
106 
107 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
108 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
109 #endif
110 
111 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
112 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
113 #endif
114 
115 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
116 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
117 #endif
118 
119 #ifndef DRXK_QAM_SYMBOLRATE_MAX
120 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
121 #endif
122 
123 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
124 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
125 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
126 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
127 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
128 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
129 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
130 #define DRXK_BL_ROM_OFFSET_UCODE        0
131 
132 #define DRXK_BLC_TIMEOUT                100
133 
134 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
135 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
136 
137 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
138 
139 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
140 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
141 #endif
142 
143 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
144 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
145 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
146 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
147 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
148 
149 static unsigned int debug;
150 module_param(debug, int, 0644);
151 MODULE_PARM_DESC(debug, "enable debug messages");
152 
153 #define dprintk(level, fmt, arg...) do {				\
154 if (debug >= level)							\
155 	printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg);	\
156 } while (0)
157 
158 static inline u32 Frac28a(u32 a, u32 c)
159 {
160 	int i = 0;
161 	u32 Q1 = 0;
162 	u32 R0 = 0;
163 
164 	R0 = (a % c) << 4;	/* 32-28 == 4 shifts possible at max */
165 	Q1 = a / c;		/*
166 				 * integer part, only the 4 least significant
167 				 * bits will be visible in the result
168 				 */
169 
170 	/* division using radix 16, 7 nibbles in the result */
171 	for (i = 0; i < 7; i++) {
172 		Q1 = (Q1 << 4) | (R0 / c);
173 		R0 = (R0 % c) << 4;
174 	}
175 	/* rounding */
176 	if ((R0 >> 3) >= c)
177 		Q1++;
178 
179 	return Q1;
180 }
181 
182 static inline u32 log10times100(u32 value)
183 {
184 	return (100L * intlog10(value)) >> 24;
185 }
186 
187 /***************************************************************************/
188 /* I2C **********************************************************************/
189 /***************************************************************************/
190 
191 static int drxk_i2c_lock(struct drxk_state *state)
192 {
193 	i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
194 	state->drxk_i2c_exclusive_lock = true;
195 
196 	return 0;
197 }
198 
199 static void drxk_i2c_unlock(struct drxk_state *state)
200 {
201 	if (!state->drxk_i2c_exclusive_lock)
202 		return;
203 
204 	i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
205 	state->drxk_i2c_exclusive_lock = false;
206 }
207 
208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
209 			     unsigned len)
210 {
211 	if (state->drxk_i2c_exclusive_lock)
212 		return __i2c_transfer(state->i2c, msgs, len);
213 	else
214 		return i2c_transfer(state->i2c, msgs, len);
215 }
216 
217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
218 {
219 	struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
220 				    .buf = val, .len = 1}
221 	};
222 
223 	return drxk_i2c_transfer(state, msgs, 1);
224 }
225 
226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
227 {
228 	int status;
229 	struct i2c_msg msg = {
230 	    .addr = adr, .flags = 0, .buf = data, .len = len };
231 
232 	dprintk(3, ":");
233 	if (debug > 2) {
234 		int i;
235 		for (i = 0; i < len; i++)
236 			pr_cont(" %02x", data[i]);
237 		pr_cont("\n");
238 	}
239 	status = drxk_i2c_transfer(state, &msg, 1);
240 	if (status >= 0 && status != 1)
241 		status = -EIO;
242 
243 	if (status < 0)
244 		pr_err("i2c write error at addr 0x%02x\n", adr);
245 
246 	return status;
247 }
248 
249 static int i2c_read(struct drxk_state *state,
250 		    u8 adr, u8 *msg, int len, u8 *answ, int alen)
251 {
252 	int status;
253 	struct i2c_msg msgs[2] = {
254 		{.addr = adr, .flags = 0,
255 				    .buf = msg, .len = len},
256 		{.addr = adr, .flags = I2C_M_RD,
257 		 .buf = answ, .len = alen}
258 	};
259 
260 	status = drxk_i2c_transfer(state, msgs, 2);
261 	if (status != 2) {
262 		if (debug > 2)
263 			pr_cont(": ERROR!\n");
264 		if (status >= 0)
265 			status = -EIO;
266 
267 		pr_err("i2c read error at addr 0x%02x\n", adr);
268 		return status;
269 	}
270 	if (debug > 2) {
271 		int i;
272 		dprintk(2, ": read from");
273 		for (i = 0; i < len; i++)
274 			pr_cont(" %02x", msg[i]);
275 		pr_cont(", value = ");
276 		for (i = 0; i < alen; i++)
277 			pr_cont(" %02x", answ[i]);
278 		pr_cont("\n");
279 	}
280 	return 0;
281 }
282 
283 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
284 {
285 	int status;
286 	u8 adr = state->demod_address, mm1[4], mm2[2], len;
287 
288 	if (state->single_master)
289 		flags |= 0xC0;
290 
291 	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
292 		mm1[0] = (((reg << 1) & 0xFF) | 0x01);
293 		mm1[1] = ((reg >> 16) & 0xFF);
294 		mm1[2] = ((reg >> 24) & 0xFF) | flags;
295 		mm1[3] = ((reg >> 7) & 0xFF);
296 		len = 4;
297 	} else {
298 		mm1[0] = ((reg << 1) & 0xFF);
299 		mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
300 		len = 2;
301 	}
302 	dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
303 	status = i2c_read(state, adr, mm1, len, mm2, 2);
304 	if (status < 0)
305 		return status;
306 	if (data)
307 		*data = mm2[0] | (mm2[1] << 8);
308 
309 	return 0;
310 }
311 
312 static int read16(struct drxk_state *state, u32 reg, u16 *data)
313 {
314 	return read16_flags(state, reg, data, 0);
315 }
316 
317 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
318 {
319 	int status;
320 	u8 adr = state->demod_address, mm1[4], mm2[4], len;
321 
322 	if (state->single_master)
323 		flags |= 0xC0;
324 
325 	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
326 		mm1[0] = (((reg << 1) & 0xFF) | 0x01);
327 		mm1[1] = ((reg >> 16) & 0xFF);
328 		mm1[2] = ((reg >> 24) & 0xFF) | flags;
329 		mm1[3] = ((reg >> 7) & 0xFF);
330 		len = 4;
331 	} else {
332 		mm1[0] = ((reg << 1) & 0xFF);
333 		mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
334 		len = 2;
335 	}
336 	dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
337 	status = i2c_read(state, adr, mm1, len, mm2, 4);
338 	if (status < 0)
339 		return status;
340 	if (data)
341 		*data = mm2[0] | (mm2[1] << 8) |
342 		    (mm2[2] << 16) | (mm2[3] << 24);
343 
344 	return 0;
345 }
346 
347 static int read32(struct drxk_state *state, u32 reg, u32 *data)
348 {
349 	return read32_flags(state, reg, data, 0);
350 }
351 
352 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
353 {
354 	u8 adr = state->demod_address, mm[6], len;
355 
356 	if (state->single_master)
357 		flags |= 0xC0;
358 	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
359 		mm[0] = (((reg << 1) & 0xFF) | 0x01);
360 		mm[1] = ((reg >> 16) & 0xFF);
361 		mm[2] = ((reg >> 24) & 0xFF) | flags;
362 		mm[3] = ((reg >> 7) & 0xFF);
363 		len = 4;
364 	} else {
365 		mm[0] = ((reg << 1) & 0xFF);
366 		mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
367 		len = 2;
368 	}
369 	mm[len] = data & 0xff;
370 	mm[len + 1] = (data >> 8) & 0xff;
371 
372 	dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
373 	return i2c_write(state, adr, mm, len + 2);
374 }
375 
376 static int write16(struct drxk_state *state, u32 reg, u16 data)
377 {
378 	return write16_flags(state, reg, data, 0);
379 }
380 
381 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
382 {
383 	u8 adr = state->demod_address, mm[8], len;
384 
385 	if (state->single_master)
386 		flags |= 0xC0;
387 	if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
388 		mm[0] = (((reg << 1) & 0xFF) | 0x01);
389 		mm[1] = ((reg >> 16) & 0xFF);
390 		mm[2] = ((reg >> 24) & 0xFF) | flags;
391 		mm[3] = ((reg >> 7) & 0xFF);
392 		len = 4;
393 	} else {
394 		mm[0] = ((reg << 1) & 0xFF);
395 		mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
396 		len = 2;
397 	}
398 	mm[len] = data & 0xff;
399 	mm[len + 1] = (data >> 8) & 0xff;
400 	mm[len + 2] = (data >> 16) & 0xff;
401 	mm[len + 3] = (data >> 24) & 0xff;
402 	dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
403 
404 	return i2c_write(state, adr, mm, len + 4);
405 }
406 
407 static int write32(struct drxk_state *state, u32 reg, u32 data)
408 {
409 	return write32_flags(state, reg, data, 0);
410 }
411 
412 static int write_block(struct drxk_state *state, u32 address,
413 		      const int block_size, const u8 p_block[])
414 {
415 	int status = 0, blk_size = block_size;
416 	u8 flags = 0;
417 
418 	if (state->single_master)
419 		flags |= 0xC0;
420 
421 	while (blk_size > 0) {
422 		int chunk = blk_size > state->m_chunk_size ?
423 		    state->m_chunk_size : blk_size;
424 		u8 *adr_buf = &state->chunk[0];
425 		u32 adr_length = 0;
426 
427 		if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
428 			adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
429 			adr_buf[1] = ((address >> 16) & 0xFF);
430 			adr_buf[2] = ((address >> 24) & 0xFF);
431 			adr_buf[3] = ((address >> 7) & 0xFF);
432 			adr_buf[2] |= flags;
433 			adr_length = 4;
434 			if (chunk == state->m_chunk_size)
435 				chunk -= 2;
436 		} else {
437 			adr_buf[0] = ((address << 1) & 0xFF);
438 			adr_buf[1] = (((address >> 16) & 0x0F) |
439 				     ((address >> 18) & 0xF0));
440 			adr_length = 2;
441 		}
442 		memcpy(&state->chunk[adr_length], p_block, chunk);
443 		dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
444 		if (debug > 1) {
445 			int i;
446 			if (p_block)
447 				for (i = 0; i < chunk; i++)
448 					pr_cont(" %02x", p_block[i]);
449 			pr_cont("\n");
450 		}
451 		status = i2c_write(state, state->demod_address,
452 				   &state->chunk[0], chunk + adr_length);
453 		if (status < 0) {
454 			pr_err("%s: i2c write error at addr 0x%02x\n",
455 			       __func__, address);
456 			break;
457 		}
458 		p_block += chunk;
459 		address += (chunk >> 1);
460 		blk_size -= chunk;
461 	}
462 	return status;
463 }
464 
465 #ifndef DRXK_MAX_RETRIES_POWERUP
466 #define DRXK_MAX_RETRIES_POWERUP 20
467 #endif
468 
469 static int power_up_device(struct drxk_state *state)
470 {
471 	int status;
472 	u8 data = 0;
473 	u16 retry_count = 0;
474 
475 	dprintk(1, "\n");
476 
477 	status = i2c_read1(state, state->demod_address, &data);
478 	if (status < 0) {
479 		do {
480 			data = 0;
481 			status = i2c_write(state, state->demod_address,
482 					   &data, 1);
483 			usleep_range(10000, 11000);
484 			retry_count++;
485 			if (status < 0)
486 				continue;
487 			status = i2c_read1(state, state->demod_address,
488 					   &data);
489 		} while (status < 0 &&
490 			 (retry_count < DRXK_MAX_RETRIES_POWERUP));
491 		if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
492 			goto error;
493 	}
494 
495 	/* Make sure all clk domains are active */
496 	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
497 	if (status < 0)
498 		goto error;
499 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
500 	if (status < 0)
501 		goto error;
502 	/* Enable pll lock tests */
503 	status = write16(state, SIO_CC_PLL_LOCK__A, 1);
504 	if (status < 0)
505 		goto error;
506 
507 	state->m_current_power_mode = DRX_POWER_UP;
508 
509 error:
510 	if (status < 0)
511 		pr_err("Error %d on %s\n", status, __func__);
512 
513 	return status;
514 }
515 
516 
517 static int init_state(struct drxk_state *state)
518 {
519 	/*
520 	 * FIXME: most (all?) of the values below should be moved into
521 	 * struct drxk_config, as they are probably board-specific
522 	 */
523 	u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
524 	u32 ul_vsb_if_agc_output_level = 0;
525 	u32 ul_vsb_if_agc_min_level = 0;
526 	u32 ul_vsb_if_agc_max_level = 0x7FFF;
527 	u32 ul_vsb_if_agc_speed = 3;
528 
529 	u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
530 	u32 ul_vsb_rf_agc_output_level = 0;
531 	u32 ul_vsb_rf_agc_min_level = 0;
532 	u32 ul_vsb_rf_agc_max_level = 0x7FFF;
533 	u32 ul_vsb_rf_agc_speed = 3;
534 	u32 ul_vsb_rf_agc_top = 9500;
535 	u32 ul_vsb_rf_agc_cut_off_current = 4000;
536 
537 	u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
538 	u32 ul_atv_if_agc_output_level = 0;
539 	u32 ul_atv_if_agc_min_level = 0;
540 	u32 ul_atv_if_agc_max_level = 0;
541 	u32 ul_atv_if_agc_speed = 3;
542 
543 	u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
544 	u32 ul_atv_rf_agc_output_level = 0;
545 	u32 ul_atv_rf_agc_min_level = 0;
546 	u32 ul_atv_rf_agc_max_level = 0;
547 	u32 ul_atv_rf_agc_top = 9500;
548 	u32 ul_atv_rf_agc_cut_off_current = 4000;
549 	u32 ul_atv_rf_agc_speed = 3;
550 
551 	u32 ulQual83 = DEFAULT_MER_83;
552 	u32 ulQual93 = DEFAULT_MER_93;
553 
554 	u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
555 	u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
556 
557 	/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
558 	/* io_pad_cfg_mode output mode is drive always */
559 	/* io_pad_cfg_drive is set to power 2 (23 mA) */
560 	u32 ul_gpio_cfg = 0x0113;
561 	u32 ul_invert_ts_clock = 0;
562 	u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
563 	u32 ul_dvbt_bitrate = 50000000;
564 	u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
565 
566 	u32 ul_insert_rs_byte = 0;
567 
568 	u32 ul_rf_mirror = 1;
569 	u32 ul_power_down = 0;
570 
571 	dprintk(1, "\n");
572 
573 	state->m_has_lna = false;
574 	state->m_has_dvbt = false;
575 	state->m_has_dvbc = false;
576 	state->m_has_atv = false;
577 	state->m_has_oob = false;
578 	state->m_has_audio = false;
579 
580 	if (!state->m_chunk_size)
581 		state->m_chunk_size = 124;
582 
583 	state->m_osc_clock_freq = 0;
584 	state->m_smart_ant_inverted = false;
585 	state->m_b_p_down_open_bridge = false;
586 
587 	/* real system clock frequency in kHz */
588 	state->m_sys_clock_freq = 151875;
589 	/* Timing div, 250ns/Psys */
590 	/* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
591 	state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
592 				   HI_I2C_DELAY) / 1000;
593 	/* Clipping */
594 	if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
595 		state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
596 	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
597 	/* port/bridge/power down ctrl */
598 	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
599 
600 	state->m_b_power_down = (ul_power_down != 0);
601 
602 	state->m_drxk_a3_patch_code = false;
603 
604 	/* Init AGC and PGA parameters */
605 	/* VSB IF */
606 	state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
607 	state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
608 	state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
609 	state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
610 	state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
611 	state->m_vsb_pga_cfg = 140;
612 
613 	/* VSB RF */
614 	state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
615 	state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
616 	state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
617 	state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
618 	state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
619 	state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
620 	state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
621 	state->m_vsb_pre_saw_cfg.reference = 0x07;
622 	state->m_vsb_pre_saw_cfg.use_pre_saw = true;
623 
624 	state->m_Quality83percent = DEFAULT_MER_83;
625 	state->m_Quality93percent = DEFAULT_MER_93;
626 	if (ulQual93 <= 500 && ulQual83 < ulQual93) {
627 		state->m_Quality83percent = ulQual83;
628 		state->m_Quality93percent = ulQual93;
629 	}
630 
631 	/* ATV IF */
632 	state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
633 	state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
634 	state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
635 	state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
636 	state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
637 
638 	/* ATV RF */
639 	state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
640 	state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
641 	state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
642 	state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
643 	state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
644 	state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
645 	state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
646 	state->m_atv_pre_saw_cfg.reference = 0x04;
647 	state->m_atv_pre_saw_cfg.use_pre_saw = true;
648 
649 
650 	/* DVBT RF */
651 	state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
652 	state->m_dvbt_rf_agc_cfg.output_level = 0;
653 	state->m_dvbt_rf_agc_cfg.min_output_level = 0;
654 	state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
655 	state->m_dvbt_rf_agc_cfg.top = 0x2100;
656 	state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
657 	state->m_dvbt_rf_agc_cfg.speed = 1;
658 
659 
660 	/* DVBT IF */
661 	state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
662 	state->m_dvbt_if_agc_cfg.output_level = 0;
663 	state->m_dvbt_if_agc_cfg.min_output_level = 0;
664 	state->m_dvbt_if_agc_cfg.max_output_level = 9000;
665 	state->m_dvbt_if_agc_cfg.top = 13424;
666 	state->m_dvbt_if_agc_cfg.cut_off_current = 0;
667 	state->m_dvbt_if_agc_cfg.speed = 3;
668 	state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
669 	state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
670 	/* state->m_dvbtPgaCfg = 140; */
671 
672 	state->m_dvbt_pre_saw_cfg.reference = 4;
673 	state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
674 
675 	/* QAM RF */
676 	state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
677 	state->m_qam_rf_agc_cfg.output_level = 0;
678 	state->m_qam_rf_agc_cfg.min_output_level = 6023;
679 	state->m_qam_rf_agc_cfg.max_output_level = 27000;
680 	state->m_qam_rf_agc_cfg.top = 0x2380;
681 	state->m_qam_rf_agc_cfg.cut_off_current = 4000;
682 	state->m_qam_rf_agc_cfg.speed = 3;
683 
684 	/* QAM IF */
685 	state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
686 	state->m_qam_if_agc_cfg.output_level = 0;
687 	state->m_qam_if_agc_cfg.min_output_level = 0;
688 	state->m_qam_if_agc_cfg.max_output_level = 9000;
689 	state->m_qam_if_agc_cfg.top = 0x0511;
690 	state->m_qam_if_agc_cfg.cut_off_current = 0;
691 	state->m_qam_if_agc_cfg.speed = 3;
692 	state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
693 	state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
694 
695 	state->m_qam_pga_cfg = 140;
696 	state->m_qam_pre_saw_cfg.reference = 4;
697 	state->m_qam_pre_saw_cfg.use_pre_saw = false;
698 
699 	state->m_operation_mode = OM_NONE;
700 	state->m_drxk_state = DRXK_UNINITIALIZED;
701 
702 	/* MPEG output configuration */
703 	state->m_enable_mpeg_output = true;	/* If TRUE; enable MPEG output */
704 	state->m_insert_rs_byte = false;	/* If TRUE; insert RS byte */
705 	state->m_invert_data = false;	/* If TRUE; invert DATA signals */
706 	state->m_invert_err = false;	/* If TRUE; invert ERR signal */
707 	state->m_invert_str = false;	/* If TRUE; invert STR signals */
708 	state->m_invert_val = false;	/* If TRUE; invert VAL signals */
709 	state->m_invert_clk = (ul_invert_ts_clock != 0);	/* If TRUE; invert CLK signals */
710 
711 	/* If TRUE; static MPEG clockrate will be used;
712 	   otherwise clockrate will adapt to the bitrate of the TS */
713 
714 	state->m_dvbt_bitrate = ul_dvbt_bitrate;
715 	state->m_dvbc_bitrate = ul_dvbc_bitrate;
716 
717 	state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
718 
719 	/* Maximum bitrate in b/s in case static clockrate is selected */
720 	state->m_mpeg_ts_static_bitrate = 19392658;
721 	state->m_disable_te_ihandling = false;
722 
723 	if (ul_insert_rs_byte)
724 		state->m_insert_rs_byte = true;
725 
726 	state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
727 	if (ul_mpeg_lock_time_out < 10000)
728 		state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
729 	state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
730 	if (ul_demod_lock_time_out < 10000)
731 		state->m_demod_lock_time_out = ul_demod_lock_time_out;
732 
733 	/* QAM defaults */
734 	state->m_constellation = DRX_CONSTELLATION_AUTO;
735 	state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
736 	state->m_fec_rs_plen = 204 * 8;	/* fecRsPlen  annex A */
737 	state->m_fec_rs_prescale = 1;
738 
739 	state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
740 	state->m_agcfast_clip_ctrl_delay = 0;
741 
742 	state->m_gpio_cfg = ul_gpio_cfg;
743 
744 	state->m_b_power_down = false;
745 	state->m_current_power_mode = DRX_POWER_DOWN;
746 
747 	state->m_rfmirror = (ul_rf_mirror == 0);
748 	state->m_if_agc_pol = false;
749 	return 0;
750 }
751 
752 static int drxx_open(struct drxk_state *state)
753 {
754 	int status = 0;
755 	u32 jtag = 0;
756 	u16 bid = 0;
757 	u16 key = 0;
758 
759 	dprintk(1, "\n");
760 	/* stop lock indicator process */
761 	status = write16(state, SCU_RAM_GPIO__A,
762 			 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
763 	if (status < 0)
764 		goto error;
765 	/* Check device id */
766 	status = read16(state, SIO_TOP_COMM_KEY__A, &key);
767 	if (status < 0)
768 		goto error;
769 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
770 	if (status < 0)
771 		goto error;
772 	status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
773 	if (status < 0)
774 		goto error;
775 	status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
776 	if (status < 0)
777 		goto error;
778 	status = write16(state, SIO_TOP_COMM_KEY__A, key);
779 error:
780 	if (status < 0)
781 		pr_err("Error %d on %s\n", status, __func__);
782 	return status;
783 }
784 
785 static int get_device_capabilities(struct drxk_state *state)
786 {
787 	u16 sio_pdr_ohw_cfg = 0;
788 	u32 sio_top_jtagid_lo = 0;
789 	int status;
790 	const char *spin = "";
791 
792 	dprintk(1, "\n");
793 
794 	/* driver 0.9.0 */
795 	/* stop lock indicator process */
796 	status = write16(state, SCU_RAM_GPIO__A,
797 			 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
798 	if (status < 0)
799 		goto error;
800 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
801 	if (status < 0)
802 		goto error;
803 	status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
804 	if (status < 0)
805 		goto error;
806 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
807 	if (status < 0)
808 		goto error;
809 
810 	switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
811 	case 0:
812 		/* ignore (bypass ?) */
813 		break;
814 	case 1:
815 		/* 27 MHz */
816 		state->m_osc_clock_freq = 27000;
817 		break;
818 	case 2:
819 		/* 20.25 MHz */
820 		state->m_osc_clock_freq = 20250;
821 		break;
822 	case 3:
823 		/* 4 MHz */
824 		state->m_osc_clock_freq = 20250;
825 		break;
826 	default:
827 		pr_err("Clock Frequency is unknown\n");
828 		return -EINVAL;
829 	}
830 	/*
831 		Determine device capabilities
832 		Based on pinning v14
833 		*/
834 	status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
835 	if (status < 0)
836 		goto error;
837 
838 	pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
839 
840 	/* driver 0.9.0 */
841 	switch ((sio_top_jtagid_lo >> 29) & 0xF) {
842 	case 0:
843 		state->m_device_spin = DRXK_SPIN_A1;
844 		spin = "A1";
845 		break;
846 	case 2:
847 		state->m_device_spin = DRXK_SPIN_A2;
848 		spin = "A2";
849 		break;
850 	case 3:
851 		state->m_device_spin = DRXK_SPIN_A3;
852 		spin = "A3";
853 		break;
854 	default:
855 		state->m_device_spin = DRXK_SPIN_UNKNOWN;
856 		status = -EINVAL;
857 		pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
858 		goto error2;
859 	}
860 	switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
861 	case 0x13:
862 		/* typeId = DRX3913K_TYPE_ID */
863 		state->m_has_lna = false;
864 		state->m_has_oob = false;
865 		state->m_has_atv = false;
866 		state->m_has_audio = false;
867 		state->m_has_dvbt = true;
868 		state->m_has_dvbc = true;
869 		state->m_has_sawsw = true;
870 		state->m_has_gpio2 = false;
871 		state->m_has_gpio1 = false;
872 		state->m_has_irqn = false;
873 		break;
874 	case 0x15:
875 		/* typeId = DRX3915K_TYPE_ID */
876 		state->m_has_lna = false;
877 		state->m_has_oob = false;
878 		state->m_has_atv = true;
879 		state->m_has_audio = false;
880 		state->m_has_dvbt = true;
881 		state->m_has_dvbc = false;
882 		state->m_has_sawsw = true;
883 		state->m_has_gpio2 = true;
884 		state->m_has_gpio1 = true;
885 		state->m_has_irqn = false;
886 		break;
887 	case 0x16:
888 		/* typeId = DRX3916K_TYPE_ID */
889 		state->m_has_lna = false;
890 		state->m_has_oob = false;
891 		state->m_has_atv = true;
892 		state->m_has_audio = false;
893 		state->m_has_dvbt = true;
894 		state->m_has_dvbc = false;
895 		state->m_has_sawsw = true;
896 		state->m_has_gpio2 = true;
897 		state->m_has_gpio1 = true;
898 		state->m_has_irqn = false;
899 		break;
900 	case 0x18:
901 		/* typeId = DRX3918K_TYPE_ID */
902 		state->m_has_lna = false;
903 		state->m_has_oob = false;
904 		state->m_has_atv = true;
905 		state->m_has_audio = true;
906 		state->m_has_dvbt = true;
907 		state->m_has_dvbc = false;
908 		state->m_has_sawsw = true;
909 		state->m_has_gpio2 = true;
910 		state->m_has_gpio1 = true;
911 		state->m_has_irqn = false;
912 		break;
913 	case 0x21:
914 		/* typeId = DRX3921K_TYPE_ID */
915 		state->m_has_lna = false;
916 		state->m_has_oob = false;
917 		state->m_has_atv = true;
918 		state->m_has_audio = true;
919 		state->m_has_dvbt = true;
920 		state->m_has_dvbc = true;
921 		state->m_has_sawsw = true;
922 		state->m_has_gpio2 = true;
923 		state->m_has_gpio1 = true;
924 		state->m_has_irqn = false;
925 		break;
926 	case 0x23:
927 		/* typeId = DRX3923K_TYPE_ID */
928 		state->m_has_lna = false;
929 		state->m_has_oob = false;
930 		state->m_has_atv = true;
931 		state->m_has_audio = true;
932 		state->m_has_dvbt = true;
933 		state->m_has_dvbc = true;
934 		state->m_has_sawsw = true;
935 		state->m_has_gpio2 = true;
936 		state->m_has_gpio1 = true;
937 		state->m_has_irqn = false;
938 		break;
939 	case 0x25:
940 		/* typeId = DRX3925K_TYPE_ID */
941 		state->m_has_lna = false;
942 		state->m_has_oob = false;
943 		state->m_has_atv = true;
944 		state->m_has_audio = true;
945 		state->m_has_dvbt = true;
946 		state->m_has_dvbc = true;
947 		state->m_has_sawsw = true;
948 		state->m_has_gpio2 = true;
949 		state->m_has_gpio1 = true;
950 		state->m_has_irqn = false;
951 		break;
952 	case 0x26:
953 		/* typeId = DRX3926K_TYPE_ID */
954 		state->m_has_lna = false;
955 		state->m_has_oob = false;
956 		state->m_has_atv = true;
957 		state->m_has_audio = false;
958 		state->m_has_dvbt = true;
959 		state->m_has_dvbc = true;
960 		state->m_has_sawsw = true;
961 		state->m_has_gpio2 = true;
962 		state->m_has_gpio1 = true;
963 		state->m_has_irqn = false;
964 		break;
965 	default:
966 		pr_err("DeviceID 0x%02x not supported\n",
967 			((sio_top_jtagid_lo >> 12) & 0xFF));
968 		status = -EINVAL;
969 		goto error2;
970 	}
971 
972 	pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
973 	       ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
974 	       state->m_osc_clock_freq / 1000,
975 	       state->m_osc_clock_freq % 1000);
976 
977 error:
978 	if (status < 0)
979 		pr_err("Error %d on %s\n", status, __func__);
980 
981 error2:
982 	return status;
983 }
984 
985 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
986 {
987 	int status;
988 	bool powerdown_cmd;
989 
990 	dprintk(1, "\n");
991 
992 	/* Write command */
993 	status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
994 	if (status < 0)
995 		goto error;
996 	if (cmd == SIO_HI_RA_RAM_CMD_RESET)
997 		usleep_range(1000, 2000);
998 
999 	powerdown_cmd =
1000 	    (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1001 		    ((state->m_hi_cfg_ctrl) &
1002 		     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1003 		    SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1004 	if (!powerdown_cmd) {
1005 		/* Wait until command rdy */
1006 		u32 retry_count = 0;
1007 		u16 wait_cmd;
1008 
1009 		do {
1010 			usleep_range(1000, 2000);
1011 			retry_count += 1;
1012 			status = read16(state, SIO_HI_RA_RAM_CMD__A,
1013 					  &wait_cmd);
1014 		} while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));
1015 		if (status < 0)
1016 			goto error;
1017 		status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1018 	}
1019 error:
1020 	if (status < 0)
1021 		pr_err("Error %d on %s\n", status, __func__);
1022 
1023 	return status;
1024 }
1025 
1026 static int hi_cfg_command(struct drxk_state *state)
1027 {
1028 	int status;
1029 
1030 	dprintk(1, "\n");
1031 
1032 	mutex_lock(&state->mutex);
1033 
1034 	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1035 			 state->m_hi_cfg_timeout);
1036 	if (status < 0)
1037 		goto error;
1038 	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1039 			 state->m_hi_cfg_ctrl);
1040 	if (status < 0)
1041 		goto error;
1042 	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1043 			 state->m_hi_cfg_wake_up_key);
1044 	if (status < 0)
1045 		goto error;
1046 	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1047 			 state->m_hi_cfg_bridge_delay);
1048 	if (status < 0)
1049 		goto error;
1050 	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1051 			 state->m_hi_cfg_timing_div);
1052 	if (status < 0)
1053 		goto error;
1054 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1055 			 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1056 	if (status < 0)
1057 		goto error;
1058 	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1059 	if (status < 0)
1060 		goto error;
1061 
1062 	state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1063 error:
1064 	mutex_unlock(&state->mutex);
1065 	if (status < 0)
1066 		pr_err("Error %d on %s\n", status, __func__);
1067 	return status;
1068 }
1069 
1070 static int init_hi(struct drxk_state *state)
1071 {
1072 	dprintk(1, "\n");
1073 
1074 	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1075 	state->m_hi_cfg_timeout = 0x96FF;
1076 	/* port/bridge/power down ctrl */
1077 	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1078 
1079 	return hi_cfg_command(state);
1080 }
1081 
1082 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1083 {
1084 	int status;
1085 	u16 sio_pdr_mclk_cfg = 0;
1086 	u16 sio_pdr_mdx_cfg = 0;
1087 	u16 err_cfg = 0;
1088 
1089 	dprintk(1, ": mpeg %s, %s mode\n",
1090 		mpeg_enable ? "enable" : "disable",
1091 		state->m_enable_parallel ? "parallel" : "serial");
1092 
1093 	/* stop lock indicator process */
1094 	status = write16(state, SCU_RAM_GPIO__A,
1095 			 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1096 	if (status < 0)
1097 		goto error;
1098 
1099 	/*  MPEG TS pad configuration */
1100 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1101 	if (status < 0)
1102 		goto error;
1103 
1104 	if (!mpeg_enable) {
1105 		/*  Set MPEG TS pads to inputmode */
1106 		status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1107 		if (status < 0)
1108 			goto error;
1109 		status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1110 		if (status < 0)
1111 			goto error;
1112 		status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1113 		if (status < 0)
1114 			goto error;
1115 		status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1116 		if (status < 0)
1117 			goto error;
1118 		status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1119 		if (status < 0)
1120 			goto error;
1121 		status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1122 		if (status < 0)
1123 			goto error;
1124 		status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1125 		if (status < 0)
1126 			goto error;
1127 		status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1128 		if (status < 0)
1129 			goto error;
1130 		status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1131 		if (status < 0)
1132 			goto error;
1133 		status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1134 		if (status < 0)
1135 			goto error;
1136 		status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1137 		if (status < 0)
1138 			goto error;
1139 		status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1140 		if (status < 0)
1141 			goto error;
1142 	} else {
1143 		/* Enable MPEG output */
1144 		sio_pdr_mdx_cfg =
1145 			((state->m_ts_data_strength <<
1146 			SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1147 		sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1148 					SIO_PDR_MCLK_CFG_DRIVE__B) |
1149 					0x0003);
1150 
1151 		status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1152 		if (status < 0)
1153 			goto error;
1154 
1155 		if (state->enable_merr_cfg)
1156 			err_cfg = sio_pdr_mdx_cfg;
1157 
1158 		status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1159 		if (status < 0)
1160 			goto error;
1161 		status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1162 		if (status < 0)
1163 			goto error;
1164 
1165 		if (state->m_enable_parallel) {
1166 			/* parallel -> enable MD1 to MD7 */
1167 			status = write16(state, SIO_PDR_MD1_CFG__A,
1168 					 sio_pdr_mdx_cfg);
1169 			if (status < 0)
1170 				goto error;
1171 			status = write16(state, SIO_PDR_MD2_CFG__A,
1172 					 sio_pdr_mdx_cfg);
1173 			if (status < 0)
1174 				goto error;
1175 			status = write16(state, SIO_PDR_MD3_CFG__A,
1176 					 sio_pdr_mdx_cfg);
1177 			if (status < 0)
1178 				goto error;
1179 			status = write16(state, SIO_PDR_MD4_CFG__A,
1180 					 sio_pdr_mdx_cfg);
1181 			if (status < 0)
1182 				goto error;
1183 			status = write16(state, SIO_PDR_MD5_CFG__A,
1184 					 sio_pdr_mdx_cfg);
1185 			if (status < 0)
1186 				goto error;
1187 			status = write16(state, SIO_PDR_MD6_CFG__A,
1188 					 sio_pdr_mdx_cfg);
1189 			if (status < 0)
1190 				goto error;
1191 			status = write16(state, SIO_PDR_MD7_CFG__A,
1192 					 sio_pdr_mdx_cfg);
1193 			if (status < 0)
1194 				goto error;
1195 		} else {
1196 			sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1197 						SIO_PDR_MD0_CFG_DRIVE__B)
1198 					| 0x0003);
1199 			/* serial -> disable MD1 to MD7 */
1200 			status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1201 			if (status < 0)
1202 				goto error;
1203 			status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1204 			if (status < 0)
1205 				goto error;
1206 			status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1207 			if (status < 0)
1208 				goto error;
1209 			status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1210 			if (status < 0)
1211 				goto error;
1212 			status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1213 			if (status < 0)
1214 				goto error;
1215 			status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1216 			if (status < 0)
1217 				goto error;
1218 			status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1219 			if (status < 0)
1220 				goto error;
1221 		}
1222 		status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1223 		if (status < 0)
1224 			goto error;
1225 		status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1226 		if (status < 0)
1227 			goto error;
1228 	}
1229 	/*  Enable MB output over MPEG pads and ctl input */
1230 	status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1231 	if (status < 0)
1232 		goto error;
1233 	/*  Write nomagic word to enable pdr reg write */
1234 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1235 error:
1236 	if (status < 0)
1237 		pr_err("Error %d on %s\n", status, __func__);
1238 	return status;
1239 }
1240 
1241 static int mpegts_disable(struct drxk_state *state)
1242 {
1243 	dprintk(1, "\n");
1244 
1245 	return mpegts_configure_pins(state, false);
1246 }
1247 
1248 static int bl_chain_cmd(struct drxk_state *state,
1249 		      u16 rom_offset, u16 nr_of_elements, u32 time_out)
1250 {
1251 	u16 bl_status = 0;
1252 	int status;
1253 	unsigned long end;
1254 
1255 	dprintk(1, "\n");
1256 	mutex_lock(&state->mutex);
1257 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1258 	if (status < 0)
1259 		goto error;
1260 	status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1261 	if (status < 0)
1262 		goto error;
1263 	status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1264 	if (status < 0)
1265 		goto error;
1266 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1267 	if (status < 0)
1268 		goto error;
1269 
1270 	end = jiffies + msecs_to_jiffies(time_out);
1271 	do {
1272 		usleep_range(1000, 2000);
1273 		status = read16(state, SIO_BL_STATUS__A, &bl_status);
1274 		if (status < 0)
1275 			goto error;
1276 	} while ((bl_status == 0x1) &&
1277 			((time_is_after_jiffies(end))));
1278 
1279 	if (bl_status == 0x1) {
1280 		pr_err("SIO not ready\n");
1281 		status = -EINVAL;
1282 		goto error2;
1283 	}
1284 error:
1285 	if (status < 0)
1286 		pr_err("Error %d on %s\n", status, __func__);
1287 error2:
1288 	mutex_unlock(&state->mutex);
1289 	return status;
1290 }
1291 
1292 
1293 static int download_microcode(struct drxk_state *state,
1294 			     const u8 p_mc_image[], u32 length)
1295 {
1296 	const u8 *p_src = p_mc_image;
1297 	u32 address;
1298 	u16 n_blocks;
1299 	u16 block_size;
1300 	u32 offset = 0;
1301 	u32 i;
1302 	int status = 0;
1303 
1304 	dprintk(1, "\n");
1305 
1306 	/* down the drain (we don't care about MAGIC_WORD) */
1307 #if 0
1308 	/* For future reference */
1309 	drain = (p_src[0] << 8) | p_src[1];
1310 #endif
1311 	p_src += sizeof(u16);
1312 	offset += sizeof(u16);
1313 	n_blocks = (p_src[0] << 8) | p_src[1];
1314 	p_src += sizeof(u16);
1315 	offset += sizeof(u16);
1316 
1317 	for (i = 0; i < n_blocks; i += 1) {
1318 		address = (p_src[0] << 24) | (p_src[1] << 16) |
1319 		    (p_src[2] << 8) | p_src[3];
1320 		p_src += sizeof(u32);
1321 		offset += sizeof(u32);
1322 
1323 		block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1324 		p_src += sizeof(u16);
1325 		offset += sizeof(u16);
1326 
1327 #if 0
1328 		/* For future reference */
1329 		flags = (p_src[0] << 8) | p_src[1];
1330 #endif
1331 		p_src += sizeof(u16);
1332 		offset += sizeof(u16);
1333 
1334 #if 0
1335 		/* For future reference */
1336 		block_crc = (p_src[0] << 8) | p_src[1];
1337 #endif
1338 		p_src += sizeof(u16);
1339 		offset += sizeof(u16);
1340 
1341 		if (offset + block_size > length) {
1342 			pr_err("Firmware is corrupted.\n");
1343 			return -EINVAL;
1344 		}
1345 
1346 		status = write_block(state, address, block_size, p_src);
1347 		if (status < 0) {
1348 			pr_err("Error %d while loading firmware\n", status);
1349 			break;
1350 		}
1351 		p_src += block_size;
1352 		offset += block_size;
1353 	}
1354 	return status;
1355 }
1356 
1357 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1358 {
1359 	int status;
1360 	u16 data = 0;
1361 	u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1362 	u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1363 	unsigned long end;
1364 
1365 	dprintk(1, "\n");
1366 
1367 	if (!enable) {
1368 		desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1369 		desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1370 	}
1371 
1372 	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1373 	if (status >= 0 && data == desired_status) {
1374 		/* tokenring already has correct status */
1375 		return status;
1376 	}
1377 	/* Disable/enable dvbt tokenring bridge   */
1378 	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1379 
1380 	end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1381 	do {
1382 		status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1383 		if ((status >= 0 && data == desired_status)
1384 		    || time_is_after_jiffies(end))
1385 			break;
1386 		usleep_range(1000, 2000);
1387 	} while (1);
1388 	if (data != desired_status) {
1389 		pr_err("SIO not ready\n");
1390 		return -EINVAL;
1391 	}
1392 	return status;
1393 }
1394 
1395 static int mpegts_stop(struct drxk_state *state)
1396 {
1397 	int status = 0;
1398 	u16 fec_oc_snc_mode = 0;
1399 	u16 fec_oc_ipr_mode = 0;
1400 
1401 	dprintk(1, "\n");
1402 
1403 	/* Graceful shutdown (byte boundaries) */
1404 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1405 	if (status < 0)
1406 		goto error;
1407 	fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1408 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1409 	if (status < 0)
1410 		goto error;
1411 
1412 	/* Suppress MCLK during absence of data */
1413 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1414 	if (status < 0)
1415 		goto error;
1416 	fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1417 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1418 
1419 error:
1420 	if (status < 0)
1421 		pr_err("Error %d on %s\n", status, __func__);
1422 
1423 	return status;
1424 }
1425 
1426 static int scu_command(struct drxk_state *state,
1427 		       u16 cmd, u8 parameter_len,
1428 		       u16 *parameter, u8 result_len, u16 *result)
1429 {
1430 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1431 #error DRXK register mapping no longer compatible with this routine!
1432 #endif
1433 	u16 cur_cmd = 0;
1434 	int status = -EINVAL;
1435 	unsigned long end;
1436 	u8 buffer[34];
1437 	int cnt = 0, ii;
1438 	const char *p;
1439 	char errname[30];
1440 
1441 	dprintk(1, "\n");
1442 
1443 	if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1444 	    ((result_len > 0) && (result == NULL))) {
1445 		pr_err("Error %d on %s\n", status, __func__);
1446 		return status;
1447 	}
1448 
1449 	mutex_lock(&state->mutex);
1450 
1451 	/* assume that the command register is ready
1452 		since it is checked afterwards */
1453 	if (parameter) {
1454 		for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1455 			buffer[cnt++] = (parameter[ii] & 0xFF);
1456 			buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1457 		}
1458 	}
1459 	buffer[cnt++] = (cmd & 0xFF);
1460 	buffer[cnt++] = ((cmd >> 8) & 0xFF);
1461 
1462 	write_block(state, SCU_RAM_PARAM_0__A -
1463 			(parameter_len - 1), cnt, buffer);
1464 	/* Wait until SCU has processed command */
1465 	end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1466 	do {
1467 		usleep_range(1000, 2000);
1468 		status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1469 		if (status < 0)
1470 			goto error;
1471 	} while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1472 	if (cur_cmd != DRX_SCU_READY) {
1473 		pr_err("SCU not ready\n");
1474 		status = -EIO;
1475 		goto error2;
1476 	}
1477 	/* read results */
1478 	if ((result_len > 0) && (result != NULL)) {
1479 		s16 err;
1480 		int ii;
1481 
1482 		for (ii = result_len - 1; ii >= 0; ii -= 1) {
1483 			status = read16(state, SCU_RAM_PARAM_0__A - ii,
1484 					&result[ii]);
1485 			if (status < 0)
1486 				goto error;
1487 		}
1488 
1489 		/* Check if an error was reported by SCU */
1490 		err = (s16)result[0];
1491 		if (err >= 0)
1492 			goto error;
1493 
1494 		/* check for the known error codes */
1495 		switch (err) {
1496 		case SCU_RESULT_UNKCMD:
1497 			p = "SCU_RESULT_UNKCMD";
1498 			break;
1499 		case SCU_RESULT_UNKSTD:
1500 			p = "SCU_RESULT_UNKSTD";
1501 			break;
1502 		case SCU_RESULT_SIZE:
1503 			p = "SCU_RESULT_SIZE";
1504 			break;
1505 		case SCU_RESULT_INVPAR:
1506 			p = "SCU_RESULT_INVPAR";
1507 			break;
1508 		default: /* Other negative values are errors */
1509 			sprintf(errname, "ERROR: %d\n", err);
1510 			p = errname;
1511 		}
1512 		pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1513 		print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1514 		status = -EINVAL;
1515 		goto error2;
1516 	}
1517 
1518 error:
1519 	if (status < 0)
1520 		pr_err("Error %d on %s\n", status, __func__);
1521 error2:
1522 	mutex_unlock(&state->mutex);
1523 	return status;
1524 }
1525 
1526 static int set_iqm_af(struct drxk_state *state, bool active)
1527 {
1528 	u16 data = 0;
1529 	int status;
1530 
1531 	dprintk(1, "\n");
1532 
1533 	/* Configure IQM */
1534 	status = read16(state, IQM_AF_STDBY__A, &data);
1535 	if (status < 0)
1536 		goto error;
1537 
1538 	if (!active) {
1539 		data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1540 				| IQM_AF_STDBY_STDBY_AMP_STANDBY
1541 				| IQM_AF_STDBY_STDBY_PD_STANDBY
1542 				| IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1543 				| IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1544 	} else {
1545 		data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1546 				& (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1547 				& (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1548 				& (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1549 				& (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1550 			);
1551 	}
1552 	status = write16(state, IQM_AF_STDBY__A, data);
1553 
1554 error:
1555 	if (status < 0)
1556 		pr_err("Error %d on %s\n", status, __func__);
1557 	return status;
1558 }
1559 
1560 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1561 {
1562 	int status = 0;
1563 	u16 sio_cc_pwd_mode = 0;
1564 
1565 	dprintk(1, "\n");
1566 
1567 	/* Check arguments */
1568 	if (mode == NULL)
1569 		return -EINVAL;
1570 
1571 	switch (*mode) {
1572 	case DRX_POWER_UP:
1573 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1574 		break;
1575 	case DRXK_POWER_DOWN_OFDM:
1576 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1577 		break;
1578 	case DRXK_POWER_DOWN_CORE:
1579 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1580 		break;
1581 	case DRXK_POWER_DOWN_PLL:
1582 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1583 		break;
1584 	case DRX_POWER_DOWN:
1585 		sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1586 		break;
1587 	default:
1588 		/* Unknow sleep mode */
1589 		return -EINVAL;
1590 	}
1591 
1592 	/* If already in requested power mode, do nothing */
1593 	if (state->m_current_power_mode == *mode)
1594 		return 0;
1595 
1596 	/* For next steps make sure to start from DRX_POWER_UP mode */
1597 	if (state->m_current_power_mode != DRX_POWER_UP) {
1598 		status = power_up_device(state);
1599 		if (status < 0)
1600 			goto error;
1601 		status = dvbt_enable_ofdm_token_ring(state, true);
1602 		if (status < 0)
1603 			goto error;
1604 	}
1605 
1606 	if (*mode == DRX_POWER_UP) {
1607 		/* Restore analog & pin configuration */
1608 	} else {
1609 		/* Power down to requested mode */
1610 		/* Backup some register settings */
1611 		/* Set pins with possible pull-ups connected
1612 		   to them in input mode */
1613 		/* Analog power down */
1614 		/* ADC power down */
1615 		/* Power down device */
1616 		/* stop all comm_exec */
1617 		/* Stop and power down previous standard */
1618 		switch (state->m_operation_mode) {
1619 		case OM_DVBT:
1620 			status = mpegts_stop(state);
1621 			if (status < 0)
1622 				goto error;
1623 			status = power_down_dvbt(state, false);
1624 			if (status < 0)
1625 				goto error;
1626 			break;
1627 		case OM_QAM_ITU_A:
1628 		case OM_QAM_ITU_C:
1629 			status = mpegts_stop(state);
1630 			if (status < 0)
1631 				goto error;
1632 			status = power_down_qam(state);
1633 			if (status < 0)
1634 				goto error;
1635 			break;
1636 		default:
1637 			break;
1638 		}
1639 		status = dvbt_enable_ofdm_token_ring(state, false);
1640 		if (status < 0)
1641 			goto error;
1642 		status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1643 		if (status < 0)
1644 			goto error;
1645 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1646 		if (status < 0)
1647 			goto error;
1648 
1649 		if (*mode != DRXK_POWER_DOWN_OFDM) {
1650 			state->m_hi_cfg_ctrl |=
1651 				SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1652 			status = hi_cfg_command(state);
1653 			if (status < 0)
1654 				goto error;
1655 		}
1656 	}
1657 	state->m_current_power_mode = *mode;
1658 
1659 error:
1660 	if (status < 0)
1661 		pr_err("Error %d on %s\n", status, __func__);
1662 
1663 	return status;
1664 }
1665 
1666 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1667 {
1668 	enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1669 	u16 cmd_result = 0;
1670 	u16 data = 0;
1671 	int status;
1672 
1673 	dprintk(1, "\n");
1674 
1675 	status = read16(state, SCU_COMM_EXEC__A, &data);
1676 	if (status < 0)
1677 		goto error;
1678 	if (data == SCU_COMM_EXEC_ACTIVE) {
1679 		/* Send OFDM stop command */
1680 		status = scu_command(state,
1681 				     SCU_RAM_COMMAND_STANDARD_OFDM
1682 				     | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1683 				     0, NULL, 1, &cmd_result);
1684 		if (status < 0)
1685 			goto error;
1686 		/* Send OFDM reset command */
1687 		status = scu_command(state,
1688 				     SCU_RAM_COMMAND_STANDARD_OFDM
1689 				     | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1690 				     0, NULL, 1, &cmd_result);
1691 		if (status < 0)
1692 			goto error;
1693 	}
1694 
1695 	/* Reset datapath for OFDM, processors first */
1696 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1697 	if (status < 0)
1698 		goto error;
1699 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1700 	if (status < 0)
1701 		goto error;
1702 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1703 	if (status < 0)
1704 		goto error;
1705 
1706 	/* powerdown AFE                   */
1707 	status = set_iqm_af(state, false);
1708 	if (status < 0)
1709 		goto error;
1710 
1711 	/* powerdown to OFDM mode          */
1712 	if (set_power_mode) {
1713 		status = ctrl_power_mode(state, &power_mode);
1714 		if (status < 0)
1715 			goto error;
1716 	}
1717 error:
1718 	if (status < 0)
1719 		pr_err("Error %d on %s\n", status, __func__);
1720 	return status;
1721 }
1722 
1723 static int setoperation_mode(struct drxk_state *state,
1724 			    enum operation_mode o_mode)
1725 {
1726 	int status = 0;
1727 
1728 	dprintk(1, "\n");
1729 	/*
1730 	   Stop and power down previous standard
1731 	   TODO investigate total power down instead of partial
1732 	   power down depending on "previous" standard.
1733 	 */
1734 
1735 	/* disable HW lock indicator */
1736 	status = write16(state, SCU_RAM_GPIO__A,
1737 			 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1738 	if (status < 0)
1739 		goto error;
1740 
1741 	/* Device is already at the required mode */
1742 	if (state->m_operation_mode == o_mode)
1743 		return 0;
1744 
1745 	switch (state->m_operation_mode) {
1746 		/* OM_NONE was added for start up */
1747 	case OM_NONE:
1748 		break;
1749 	case OM_DVBT:
1750 		status = mpegts_stop(state);
1751 		if (status < 0)
1752 			goto error;
1753 		status = power_down_dvbt(state, true);
1754 		if (status < 0)
1755 			goto error;
1756 		state->m_operation_mode = OM_NONE;
1757 		break;
1758 	case OM_QAM_ITU_A:
1759 	case OM_QAM_ITU_C:
1760 		status = mpegts_stop(state);
1761 		if (status < 0)
1762 			goto error;
1763 		status = power_down_qam(state);
1764 		if (status < 0)
1765 			goto error;
1766 		state->m_operation_mode = OM_NONE;
1767 		break;
1768 	case OM_QAM_ITU_B:
1769 	default:
1770 		status = -EINVAL;
1771 		goto error;
1772 	}
1773 
1774 	/*
1775 		Power up new standard
1776 		*/
1777 	switch (o_mode) {
1778 	case OM_DVBT:
1779 		dprintk(1, ": DVB-T\n");
1780 		state->m_operation_mode = o_mode;
1781 		status = set_dvbt_standard(state, o_mode);
1782 		if (status < 0)
1783 			goto error;
1784 		break;
1785 	case OM_QAM_ITU_A:
1786 	case OM_QAM_ITU_C:
1787 		dprintk(1, ": DVB-C Annex %c\n",
1788 			(state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1789 		state->m_operation_mode = o_mode;
1790 		status = set_qam_standard(state, o_mode);
1791 		if (status < 0)
1792 			goto error;
1793 		break;
1794 	case OM_QAM_ITU_B:
1795 	default:
1796 		status = -EINVAL;
1797 	}
1798 error:
1799 	if (status < 0)
1800 		pr_err("Error %d on %s\n", status, __func__);
1801 	return status;
1802 }
1803 
1804 static int start(struct drxk_state *state, s32 offset_freq,
1805 		 s32 intermediate_frequency)
1806 {
1807 	int status = -EINVAL;
1808 
1809 	u16 i_freqk_hz;
1810 	s32 offsetk_hz = offset_freq / 1000;
1811 
1812 	dprintk(1, "\n");
1813 	if (state->m_drxk_state != DRXK_STOPPED &&
1814 		state->m_drxk_state != DRXK_DTV_STARTED)
1815 		goto error;
1816 
1817 	state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1818 
1819 	if (intermediate_frequency < 0) {
1820 		state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1821 		intermediate_frequency = -intermediate_frequency;
1822 	}
1823 
1824 	switch (state->m_operation_mode) {
1825 	case OM_QAM_ITU_A:
1826 	case OM_QAM_ITU_C:
1827 		i_freqk_hz = (intermediate_frequency / 1000);
1828 		status = set_qam(state, i_freqk_hz, offsetk_hz);
1829 		if (status < 0)
1830 			goto error;
1831 		state->m_drxk_state = DRXK_DTV_STARTED;
1832 		break;
1833 	case OM_DVBT:
1834 		i_freqk_hz = (intermediate_frequency / 1000);
1835 		status = mpegts_stop(state);
1836 		if (status < 0)
1837 			goto error;
1838 		status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1839 		if (status < 0)
1840 			goto error;
1841 		status = dvbt_start(state);
1842 		if (status < 0)
1843 			goto error;
1844 		state->m_drxk_state = DRXK_DTV_STARTED;
1845 		break;
1846 	default:
1847 		break;
1848 	}
1849 error:
1850 	if (status < 0)
1851 		pr_err("Error %d on %s\n", status, __func__);
1852 	return status;
1853 }
1854 
1855 static int shut_down(struct drxk_state *state)
1856 {
1857 	dprintk(1, "\n");
1858 
1859 	mpegts_stop(state);
1860 	return 0;
1861 }
1862 
1863 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1864 {
1865 	int status = -EINVAL;
1866 
1867 	dprintk(1, "\n");
1868 
1869 	if (p_lock_status == NULL)
1870 		goto error;
1871 
1872 	*p_lock_status = NOT_LOCKED;
1873 
1874 	/* define the SCU command code */
1875 	switch (state->m_operation_mode) {
1876 	case OM_QAM_ITU_A:
1877 	case OM_QAM_ITU_B:
1878 	case OM_QAM_ITU_C:
1879 		status = get_qam_lock_status(state, p_lock_status);
1880 		break;
1881 	case OM_DVBT:
1882 		status = get_dvbt_lock_status(state, p_lock_status);
1883 		break;
1884 	default:
1885 		pr_debug("Unsupported operation mode %d in %s\n",
1886 			state->m_operation_mode, __func__);
1887 		return 0;
1888 	}
1889 error:
1890 	if (status < 0)
1891 		pr_err("Error %d on %s\n", status, __func__);
1892 	return status;
1893 }
1894 
1895 static int mpegts_start(struct drxk_state *state)
1896 {
1897 	int status;
1898 
1899 	u16 fec_oc_snc_mode = 0;
1900 
1901 	/* Allow OC to sync again */
1902 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1903 	if (status < 0)
1904 		goto error;
1905 	fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1906 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1907 	if (status < 0)
1908 		goto error;
1909 	status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1910 error:
1911 	if (status < 0)
1912 		pr_err("Error %d on %s\n", status, __func__);
1913 	return status;
1914 }
1915 
1916 static int mpegts_dto_init(struct drxk_state *state)
1917 {
1918 	int status;
1919 
1920 	dprintk(1, "\n");
1921 
1922 	/* Rate integration settings */
1923 	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1924 	if (status < 0)
1925 		goto error;
1926 	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1927 	if (status < 0)
1928 		goto error;
1929 	status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1930 	if (status < 0)
1931 		goto error;
1932 	status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1933 	if (status < 0)
1934 		goto error;
1935 	status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1936 	if (status < 0)
1937 		goto error;
1938 	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1939 	if (status < 0)
1940 		goto error;
1941 	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1942 	if (status < 0)
1943 		goto error;
1944 	status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1945 	if (status < 0)
1946 		goto error;
1947 
1948 	/* Additional configuration */
1949 	status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1950 	if (status < 0)
1951 		goto error;
1952 	status = write16(state, FEC_OC_SNC_LWM__A, 2);
1953 	if (status < 0)
1954 		goto error;
1955 	status = write16(state, FEC_OC_SNC_HWM__A, 12);
1956 error:
1957 	if (status < 0)
1958 		pr_err("Error %d on %s\n", status, __func__);
1959 
1960 	return status;
1961 }
1962 
1963 static int mpegts_dto_setup(struct drxk_state *state,
1964 			  enum operation_mode o_mode)
1965 {
1966 	int status;
1967 
1968 	u16 fec_oc_reg_mode = 0;	/* FEC_OC_MODE       register value */
1969 	u16 fec_oc_reg_ipr_mode = 0;	/* FEC_OC_IPR_MODE   register value */
1970 	u16 fec_oc_dto_mode = 0;	/* FEC_OC_IPR_INVERT register value */
1971 	u16 fec_oc_fct_mode = 0;	/* FEC_OC_IPR_INVERT register value */
1972 	u16 fec_oc_dto_period = 2;	/* FEC_OC_IPR_INVERT register value */
1973 	u16 fec_oc_dto_burst_len = 188;	/* FEC_OC_IPR_INVERT register value */
1974 	u32 fec_oc_rcn_ctl_rate = 0;	/* FEC_OC_IPR_INVERT register value */
1975 	u16 fec_oc_tmd_mode = 0;
1976 	u16 fec_oc_tmd_int_upd_rate = 0;
1977 	u32 max_bit_rate = 0;
1978 	bool static_clk = false;
1979 
1980 	dprintk(1, "\n");
1981 
1982 	/* Check insertion of the Reed-Solomon parity bytes */
1983 	status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1984 	if (status < 0)
1985 		goto error;
1986 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1987 	if (status < 0)
1988 		goto error;
1989 	fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
1990 	fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1991 	if (state->m_insert_rs_byte) {
1992 		/* enable parity symbol forward */
1993 		fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
1994 		/* MVAL disable during parity bytes */
1995 		fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
1996 		/* TS burst length to 204 */
1997 		fec_oc_dto_burst_len = 204;
1998 	}
1999 
2000 	/* Check serial or parallel output */
2001 	fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2002 	if (!state->m_enable_parallel) {
2003 		/* MPEG data output is serial -> set ipr_mode[0] */
2004 		fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2005 	}
2006 
2007 	switch (o_mode) {
2008 	case OM_DVBT:
2009 		max_bit_rate = state->m_dvbt_bitrate;
2010 		fec_oc_tmd_mode = 3;
2011 		fec_oc_rcn_ctl_rate = 0xC00000;
2012 		static_clk = state->m_dvbt_static_clk;
2013 		break;
2014 	case OM_QAM_ITU_A:
2015 	case OM_QAM_ITU_C:
2016 		fec_oc_tmd_mode = 0x0004;
2017 		fec_oc_rcn_ctl_rate = 0xD2B4EE;	/* good for >63 Mb/s */
2018 		max_bit_rate = state->m_dvbc_bitrate;
2019 		static_clk = state->m_dvbc_static_clk;
2020 		break;
2021 	default:
2022 		status = -EINVAL;
2023 	}		/* switch (standard) */
2024 	if (status < 0)
2025 		goto error;
2026 
2027 	/* Configure DTO's */
2028 	if (static_clk) {
2029 		u32 bit_rate = 0;
2030 
2031 		/* Rational DTO for MCLK source (static MCLK rate),
2032 			Dynamic DTO for optimal grouping
2033 			(avoid intra-packet gaps),
2034 			DTO offset enable to sync TS burst with MSTRT */
2035 		fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2036 				FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2037 		fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2038 				FEC_OC_FCT_MODE_VIRT_ENA__M);
2039 
2040 		/* Check user defined bitrate */
2041 		bit_rate = max_bit_rate;
2042 		if (bit_rate > 75900000UL) {	/* max is 75.9 Mb/s */
2043 			bit_rate = 75900000UL;
2044 		}
2045 		/* Rational DTO period:
2046 			dto_period = (Fsys / bitrate) - 2
2047 
2048 			result should be floored,
2049 			to make sure >= requested bitrate
2050 			*/
2051 		fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2052 						* 1000) / bit_rate);
2053 		if (fec_oc_dto_period <= 2)
2054 			fec_oc_dto_period = 0;
2055 		else
2056 			fec_oc_dto_period -= 2;
2057 		fec_oc_tmd_int_upd_rate = 8;
2058 	} else {
2059 		/* (commonAttr->static_clk == false) => dynamic mode */
2060 		fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2061 		fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2062 		fec_oc_tmd_int_upd_rate = 5;
2063 	}
2064 
2065 	/* Write appropriate registers with requested configuration */
2066 	status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2067 	if (status < 0)
2068 		goto error;
2069 	status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2070 	if (status < 0)
2071 		goto error;
2072 	status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2073 	if (status < 0)
2074 		goto error;
2075 	status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2076 	if (status < 0)
2077 		goto error;
2078 	status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2079 	if (status < 0)
2080 		goto error;
2081 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2082 	if (status < 0)
2083 		goto error;
2084 
2085 	/* Rate integration settings */
2086 	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2087 	if (status < 0)
2088 		goto error;
2089 	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2090 			 fec_oc_tmd_int_upd_rate);
2091 	if (status < 0)
2092 		goto error;
2093 	status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2094 error:
2095 	if (status < 0)
2096 		pr_err("Error %d on %s\n", status, __func__);
2097 	return status;
2098 }
2099 
2100 static int mpegts_configure_polarity(struct drxk_state *state)
2101 {
2102 	u16 fec_oc_reg_ipr_invert = 0;
2103 
2104 	/* Data mask for the output data byte */
2105 	u16 invert_data_mask =
2106 	    FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2107 	    FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2108 	    FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2109 	    FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2110 
2111 	dprintk(1, "\n");
2112 
2113 	/* Control selective inversion of output bits */
2114 	fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2115 	if (state->m_invert_data)
2116 		fec_oc_reg_ipr_invert |= invert_data_mask;
2117 	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2118 	if (state->m_invert_err)
2119 		fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2120 	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2121 	if (state->m_invert_str)
2122 		fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2123 	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2124 	if (state->m_invert_val)
2125 		fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2126 	fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2127 	if (state->m_invert_clk)
2128 		fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2129 
2130 	return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2131 }
2132 
2133 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2134 
2135 static int set_agc_rf(struct drxk_state *state,
2136 		    struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2137 {
2138 	int status = -EINVAL;
2139 	u16 data = 0;
2140 	struct s_cfg_agc *p_if_agc_settings;
2141 
2142 	dprintk(1, "\n");
2143 
2144 	if (p_agc_cfg == NULL)
2145 		goto error;
2146 
2147 	switch (p_agc_cfg->ctrl_mode) {
2148 	case DRXK_AGC_CTRL_AUTO:
2149 		/* Enable RF AGC DAC */
2150 		status = read16(state, IQM_AF_STDBY__A, &data);
2151 		if (status < 0)
2152 			goto error;
2153 		data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2154 		status = write16(state, IQM_AF_STDBY__A, data);
2155 		if (status < 0)
2156 			goto error;
2157 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2158 		if (status < 0)
2159 			goto error;
2160 
2161 		/* Enable SCU RF AGC loop */
2162 		data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2163 
2164 		/* Polarity */
2165 		if (state->m_rf_agc_pol)
2166 			data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2167 		else
2168 			data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2169 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2170 		if (status < 0)
2171 			goto error;
2172 
2173 		/* Set speed (using complementary reduction value) */
2174 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2175 		if (status < 0)
2176 			goto error;
2177 
2178 		data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2179 		data |= (~(p_agc_cfg->speed <<
2180 				SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2181 				& SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2182 
2183 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2184 		if (status < 0)
2185 			goto error;
2186 
2187 		if (is_dvbt(state))
2188 			p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2189 		else if (is_qam(state))
2190 			p_if_agc_settings = &state->m_qam_if_agc_cfg;
2191 		else
2192 			p_if_agc_settings = &state->m_atv_if_agc_cfg;
2193 		if (p_if_agc_settings == NULL) {
2194 			status = -EINVAL;
2195 			goto error;
2196 		}
2197 
2198 		/* Set TOP, only if IF-AGC is in AUTO mode */
2199 		if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
2200 			status = write16(state,
2201 					 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2202 					 p_agc_cfg->top);
2203 			if (status < 0)
2204 				goto error;
2205 		}
2206 
2207 		/* Cut-Off current */
2208 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2209 				 p_agc_cfg->cut_off_current);
2210 		if (status < 0)
2211 			goto error;
2212 
2213 		/* Max. output level */
2214 		status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2215 				 p_agc_cfg->max_output_level);
2216 		if (status < 0)
2217 			goto error;
2218 
2219 		break;
2220 
2221 	case DRXK_AGC_CTRL_USER:
2222 		/* Enable RF AGC DAC */
2223 		status = read16(state, IQM_AF_STDBY__A, &data);
2224 		if (status < 0)
2225 			goto error;
2226 		data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2227 		status = write16(state, IQM_AF_STDBY__A, data);
2228 		if (status < 0)
2229 			goto error;
2230 
2231 		/* Disable SCU RF AGC loop */
2232 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2233 		if (status < 0)
2234 			goto error;
2235 		data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2236 		if (state->m_rf_agc_pol)
2237 			data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2238 		else
2239 			data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2240 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2241 		if (status < 0)
2242 			goto error;
2243 
2244 		/* SCU c.o.c. to 0, enabling full control range */
2245 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2246 		if (status < 0)
2247 			goto error;
2248 
2249 		/* Write value to output pin */
2250 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2251 				 p_agc_cfg->output_level);
2252 		if (status < 0)
2253 			goto error;
2254 		break;
2255 
2256 	case DRXK_AGC_CTRL_OFF:
2257 		/* Disable RF AGC DAC */
2258 		status = read16(state, IQM_AF_STDBY__A, &data);
2259 		if (status < 0)
2260 			goto error;
2261 		data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2262 		status = write16(state, IQM_AF_STDBY__A, data);
2263 		if (status < 0)
2264 			goto error;
2265 
2266 		/* Disable SCU RF AGC loop */
2267 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2268 		if (status < 0)
2269 			goto error;
2270 		data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2271 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2272 		if (status < 0)
2273 			goto error;
2274 		break;
2275 
2276 	default:
2277 		status = -EINVAL;
2278 
2279 	}
2280 error:
2281 	if (status < 0)
2282 		pr_err("Error %d on %s\n", status, __func__);
2283 	return status;
2284 }
2285 
2286 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2287 
2288 static int set_agc_if(struct drxk_state *state,
2289 		    struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2290 {
2291 	u16 data = 0;
2292 	int status = 0;
2293 	struct s_cfg_agc *p_rf_agc_settings;
2294 
2295 	dprintk(1, "\n");
2296 
2297 	switch (p_agc_cfg->ctrl_mode) {
2298 	case DRXK_AGC_CTRL_AUTO:
2299 
2300 		/* Enable IF AGC DAC */
2301 		status = read16(state, IQM_AF_STDBY__A, &data);
2302 		if (status < 0)
2303 			goto error;
2304 		data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2305 		status = write16(state, IQM_AF_STDBY__A, data);
2306 		if (status < 0)
2307 			goto error;
2308 
2309 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2310 		if (status < 0)
2311 			goto error;
2312 
2313 		/* Enable SCU IF AGC loop */
2314 		data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2315 
2316 		/* Polarity */
2317 		if (state->m_if_agc_pol)
2318 			data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2319 		else
2320 			data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2321 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2322 		if (status < 0)
2323 			goto error;
2324 
2325 		/* Set speed (using complementary reduction value) */
2326 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2327 		if (status < 0)
2328 			goto error;
2329 		data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2330 		data |= (~(p_agc_cfg->speed <<
2331 				SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2332 				& SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2333 
2334 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2335 		if (status < 0)
2336 			goto error;
2337 
2338 		if (is_qam(state))
2339 			p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2340 		else
2341 			p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2342 		if (p_rf_agc_settings == NULL)
2343 			return -1;
2344 		/* Restore TOP */
2345 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2346 				 p_rf_agc_settings->top);
2347 		if (status < 0)
2348 			goto error;
2349 		break;
2350 
2351 	case DRXK_AGC_CTRL_USER:
2352 
2353 		/* Enable IF AGC DAC */
2354 		status = read16(state, IQM_AF_STDBY__A, &data);
2355 		if (status < 0)
2356 			goto error;
2357 		data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2358 		status = write16(state, IQM_AF_STDBY__A, data);
2359 		if (status < 0)
2360 			goto error;
2361 
2362 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2363 		if (status < 0)
2364 			goto error;
2365 
2366 		/* Disable SCU IF AGC loop */
2367 		data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2368 
2369 		/* Polarity */
2370 		if (state->m_if_agc_pol)
2371 			data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2372 		else
2373 			data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2374 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2375 		if (status < 0)
2376 			goto error;
2377 
2378 		/* Write value to output pin */
2379 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2380 				 p_agc_cfg->output_level);
2381 		if (status < 0)
2382 			goto error;
2383 		break;
2384 
2385 	case DRXK_AGC_CTRL_OFF:
2386 
2387 		/* Disable If AGC DAC */
2388 		status = read16(state, IQM_AF_STDBY__A, &data);
2389 		if (status < 0)
2390 			goto error;
2391 		data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2392 		status = write16(state, IQM_AF_STDBY__A, data);
2393 		if (status < 0)
2394 			goto error;
2395 
2396 		/* Disable SCU IF AGC loop */
2397 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2398 		if (status < 0)
2399 			goto error;
2400 		data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2401 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2402 		if (status < 0)
2403 			goto error;
2404 		break;
2405 	}		/* switch (agcSettingsIf->ctrl_mode) */
2406 
2407 	/* always set the top to support
2408 		configurations without if-loop */
2409 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2410 error:
2411 	if (status < 0)
2412 		pr_err("Error %d on %s\n", status, __func__);
2413 	return status;
2414 }
2415 
2416 static int get_qam_signal_to_noise(struct drxk_state *state,
2417 			       s32 *p_signal_to_noise)
2418 {
2419 	int status = 0;
2420 	u16 qam_sl_err_power = 0;	/* accum. error between
2421 					raw and sliced symbols */
2422 	u32 qam_sl_sig_power = 0;	/* used for MER, depends of
2423 					QAM modulation */
2424 	u32 qam_sl_mer = 0;	/* QAM MER */
2425 
2426 	dprintk(1, "\n");
2427 
2428 	/* MER calculation */
2429 
2430 	/* get the register value needed for MER */
2431 	status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2432 	if (status < 0) {
2433 		pr_err("Error %d on %s\n", status, __func__);
2434 		return -EINVAL;
2435 	}
2436 
2437 	switch (state->props.modulation) {
2438 	case QAM_16:
2439 		qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2440 		break;
2441 	case QAM_32:
2442 		qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2443 		break;
2444 	case QAM_64:
2445 		qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2446 		break;
2447 	case QAM_128:
2448 		qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2449 		break;
2450 	default:
2451 	case QAM_256:
2452 		qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2453 		break;
2454 	}
2455 
2456 	if (qam_sl_err_power > 0) {
2457 		qam_sl_mer = log10times100(qam_sl_sig_power) -
2458 			log10times100((u32) qam_sl_err_power);
2459 	}
2460 	*p_signal_to_noise = qam_sl_mer;
2461 
2462 	return status;
2463 }
2464 
2465 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2466 				s32 *p_signal_to_noise)
2467 {
2468 	int status;
2469 	u16 reg_data = 0;
2470 	u32 eq_reg_td_sqr_err_i = 0;
2471 	u32 eq_reg_td_sqr_err_q = 0;
2472 	u16 eq_reg_td_sqr_err_exp = 0;
2473 	u16 eq_reg_td_tps_pwr_ofs = 0;
2474 	u16 eq_reg_td_req_smb_cnt = 0;
2475 	u32 tps_cnt = 0;
2476 	u32 sqr_err_iq = 0;
2477 	u32 a = 0;
2478 	u32 b = 0;
2479 	u32 c = 0;
2480 	u32 i_mer = 0;
2481 	u16 transmission_params = 0;
2482 
2483 	dprintk(1, "\n");
2484 
2485 	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2486 			&eq_reg_td_tps_pwr_ofs);
2487 	if (status < 0)
2488 		goto error;
2489 	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2490 			&eq_reg_td_req_smb_cnt);
2491 	if (status < 0)
2492 		goto error;
2493 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2494 			&eq_reg_td_sqr_err_exp);
2495 	if (status < 0)
2496 		goto error;
2497 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2498 			&reg_data);
2499 	if (status < 0)
2500 		goto error;
2501 	/* Extend SQR_ERR_I operational range */
2502 	eq_reg_td_sqr_err_i = (u32) reg_data;
2503 	if ((eq_reg_td_sqr_err_exp > 11) &&
2504 		(eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2505 		eq_reg_td_sqr_err_i += 0x00010000UL;
2506 	}
2507 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);
2508 	if (status < 0)
2509 		goto error;
2510 	/* Extend SQR_ERR_Q operational range */
2511 	eq_reg_td_sqr_err_q = (u32) reg_data;
2512 	if ((eq_reg_td_sqr_err_exp > 11) &&
2513 		(eq_reg_td_sqr_err_q < 0x00000FFFUL))
2514 		eq_reg_td_sqr_err_q += 0x00010000UL;
2515 
2516 	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2517 			&transmission_params);
2518 	if (status < 0)
2519 		goto error;
2520 
2521 	/* Check input data for MER */
2522 
2523 	/* MER calculation (in 0.1 dB) without math.h */
2524 	if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2525 		i_mer = 0;
2526 	else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2527 		/* No error at all, this must be the HW reset value
2528 			* Apparently no first measurement yet
2529 			* Set MER to 0.0 */
2530 		i_mer = 0;
2531 	} else {
2532 		sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2533 			eq_reg_td_sqr_err_exp;
2534 		if ((transmission_params &
2535 			OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2536 			== OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2537 			tps_cnt = 17;
2538 		else
2539 			tps_cnt = 68;
2540 
2541 		/* IMER = 100 * log10 (x)
2542 			where x = (eq_reg_td_tps_pwr_ofs^2 *
2543 			eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2544 
2545 			=> IMER = a + b -c
2546 			where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2547 			b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2548 			c = 100 * log10 (sqr_err_iq)
2549 			*/
2550 
2551 		/* log(x) x = 9bits * 9bits->18 bits  */
2552 		a = log10times100(eq_reg_td_tps_pwr_ofs *
2553 					eq_reg_td_tps_pwr_ofs);
2554 		/* log(x) x = 16bits * 7bits->23 bits  */
2555 		b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2556 		/* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2557 		c = log10times100(sqr_err_iq);
2558 
2559 		i_mer = a + b - c;
2560 	}
2561 	*p_signal_to_noise = i_mer;
2562 
2563 error:
2564 	if (status < 0)
2565 		pr_err("Error %d on %s\n", status, __func__);
2566 	return status;
2567 }
2568 
2569 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2570 {
2571 	dprintk(1, "\n");
2572 
2573 	*p_signal_to_noise = 0;
2574 	switch (state->m_operation_mode) {
2575 	case OM_DVBT:
2576 		return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2577 	case OM_QAM_ITU_A:
2578 	case OM_QAM_ITU_C:
2579 		return get_qam_signal_to_noise(state, p_signal_to_noise);
2580 	default:
2581 		break;
2582 	}
2583 	return 0;
2584 }
2585 
2586 #if 0
2587 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2588 {
2589 	/* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2590 	int status = 0;
2591 
2592 	dprintk(1, "\n");
2593 
2594 	static s32 QE_SN[] = {
2595 		51,		/* QPSK 1/2 */
2596 		69,		/* QPSK 2/3 */
2597 		79,		/* QPSK 3/4 */
2598 		89,		/* QPSK 5/6 */
2599 		97,		/* QPSK 7/8 */
2600 		108,		/* 16-QAM 1/2 */
2601 		131,		/* 16-QAM 2/3 */
2602 		146,		/* 16-QAM 3/4 */
2603 		156,		/* 16-QAM 5/6 */
2604 		160,		/* 16-QAM 7/8 */
2605 		165,		/* 64-QAM 1/2 */
2606 		187,		/* 64-QAM 2/3 */
2607 		202,		/* 64-QAM 3/4 */
2608 		216,		/* 64-QAM 5/6 */
2609 		225,		/* 64-QAM 7/8 */
2610 	};
2611 
2612 	*p_quality = 0;
2613 
2614 	do {
2615 		s32 signal_to_noise = 0;
2616 		u16 constellation = 0;
2617 		u16 code_rate = 0;
2618 		u32 signal_to_noise_rel;
2619 		u32 ber_quality;
2620 
2621 		status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2622 		if (status < 0)
2623 			break;
2624 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2625 				&constellation);
2626 		if (status < 0)
2627 			break;
2628 		constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2629 
2630 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2631 				&code_rate);
2632 		if (status < 0)
2633 			break;
2634 		code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2635 
2636 		if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2637 		    code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2638 			break;
2639 		signal_to_noise_rel = signal_to_noise -
2640 		    QE_SN[constellation * 5 + code_rate];
2641 		ber_quality = 100;
2642 
2643 		if (signal_to_noise_rel < -70)
2644 			*p_quality = 0;
2645 		else if (signal_to_noise_rel < 30)
2646 			*p_quality = ((signal_to_noise_rel + 70) *
2647 				     ber_quality) / 100;
2648 		else
2649 			*p_quality = ber_quality;
2650 	} while (0);
2651 	return 0;
2652 };
2653 
2654 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2655 {
2656 	int status = 0;
2657 	*p_quality = 0;
2658 
2659 	dprintk(1, "\n");
2660 
2661 	do {
2662 		u32 signal_to_noise = 0;
2663 		u32 ber_quality = 100;
2664 		u32 signal_to_noise_rel = 0;
2665 
2666 		status = get_qam_signal_to_noise(state, &signal_to_noise);
2667 		if (status < 0)
2668 			break;
2669 
2670 		switch (state->props.modulation) {
2671 		case QAM_16:
2672 			signal_to_noise_rel = signal_to_noise - 200;
2673 			break;
2674 		case QAM_32:
2675 			signal_to_noise_rel = signal_to_noise - 230;
2676 			break;	/* Not in NorDig */
2677 		case QAM_64:
2678 			signal_to_noise_rel = signal_to_noise - 260;
2679 			break;
2680 		case QAM_128:
2681 			signal_to_noise_rel = signal_to_noise - 290;
2682 			break;
2683 		default:
2684 		case QAM_256:
2685 			signal_to_noise_rel = signal_to_noise - 320;
2686 			break;
2687 		}
2688 
2689 		if (signal_to_noise_rel < -70)
2690 			*p_quality = 0;
2691 		else if (signal_to_noise_rel < 30)
2692 			*p_quality = ((signal_to_noise_rel + 70) *
2693 				     ber_quality) / 100;
2694 		else
2695 			*p_quality = ber_quality;
2696 	} while (0);
2697 
2698 	return status;
2699 }
2700 
2701 static int get_quality(struct drxk_state *state, s32 *p_quality)
2702 {
2703 	dprintk(1, "\n");
2704 
2705 	switch (state->m_operation_mode) {
2706 	case OM_DVBT:
2707 		return get_dvbt_quality(state, p_quality);
2708 	case OM_QAM_ITU_A:
2709 		return get_dvbc_quality(state, p_quality);
2710 	default:
2711 		break;
2712 	}
2713 
2714 	return 0;
2715 }
2716 #endif
2717 
2718 /* Free data ram in SIO HI */
2719 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2720 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2721 
2722 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2723 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2724 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2725 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2726 
2727 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2728 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2729 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2730 
2731 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2732 {
2733 	int status = -EINVAL;
2734 
2735 	dprintk(1, "\n");
2736 
2737 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
2738 		return 0;
2739 	if (state->m_drxk_state == DRXK_POWERED_DOWN)
2740 		goto error;
2741 
2742 	if (state->no_i2c_bridge)
2743 		return 0;
2744 
2745 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2746 			 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2747 	if (status < 0)
2748 		goto error;
2749 	if (b_enable_bridge) {
2750 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2751 				 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2752 		if (status < 0)
2753 			goto error;
2754 	} else {
2755 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2756 				 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2757 		if (status < 0)
2758 			goto error;
2759 	}
2760 
2761 	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2762 
2763 error:
2764 	if (status < 0)
2765 		pr_err("Error %d on %s\n", status, __func__);
2766 	return status;
2767 }
2768 
2769 static int set_pre_saw(struct drxk_state *state,
2770 		     struct s_cfg_pre_saw *p_pre_saw_cfg)
2771 {
2772 	int status = -EINVAL;
2773 
2774 	dprintk(1, "\n");
2775 
2776 	if ((p_pre_saw_cfg == NULL)
2777 	    || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2778 		goto error;
2779 
2780 	status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2781 error:
2782 	if (status < 0)
2783 		pr_err("Error %d on %s\n", status, __func__);
2784 	return status;
2785 }
2786 
2787 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2788 		       u16 rom_offset, u16 nr_of_elements, u32 time_out)
2789 {
2790 	u16 bl_status = 0;
2791 	u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2792 	u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2793 	int status;
2794 	unsigned long end;
2795 
2796 	dprintk(1, "\n");
2797 
2798 	mutex_lock(&state->mutex);
2799 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2800 	if (status < 0)
2801 		goto error;
2802 	status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2803 	if (status < 0)
2804 		goto error;
2805 	status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2806 	if (status < 0)
2807 		goto error;
2808 	status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2809 	if (status < 0)
2810 		goto error;
2811 	status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2812 	if (status < 0)
2813 		goto error;
2814 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2815 	if (status < 0)
2816 		goto error;
2817 
2818 	end = jiffies + msecs_to_jiffies(time_out);
2819 	do {
2820 		status = read16(state, SIO_BL_STATUS__A, &bl_status);
2821 		if (status < 0)
2822 			goto error;
2823 	} while ((bl_status == 0x1) && time_is_after_jiffies(end));
2824 	if (bl_status == 0x1) {
2825 		pr_err("SIO not ready\n");
2826 		status = -EINVAL;
2827 		goto error2;
2828 	}
2829 error:
2830 	if (status < 0)
2831 		pr_err("Error %d on %s\n", status, __func__);
2832 error2:
2833 	mutex_unlock(&state->mutex);
2834 	return status;
2835 
2836 }
2837 
2838 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2839 {
2840 	u16 data = 0;
2841 	int status;
2842 
2843 	dprintk(1, "\n");
2844 
2845 	/* start measurement */
2846 	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2847 	if (status < 0)
2848 		goto error;
2849 	status = write16(state, IQM_AF_START_LOCK__A, 1);
2850 	if (status < 0)
2851 		goto error;
2852 
2853 	*count = 0;
2854 	status = read16(state, IQM_AF_PHASE0__A, &data);
2855 	if (status < 0)
2856 		goto error;
2857 	if (data == 127)
2858 		*count = *count + 1;
2859 	status = read16(state, IQM_AF_PHASE1__A, &data);
2860 	if (status < 0)
2861 		goto error;
2862 	if (data == 127)
2863 		*count = *count + 1;
2864 	status = read16(state, IQM_AF_PHASE2__A, &data);
2865 	if (status < 0)
2866 		goto error;
2867 	if (data == 127)
2868 		*count = *count + 1;
2869 
2870 error:
2871 	if (status < 0)
2872 		pr_err("Error %d on %s\n", status, __func__);
2873 	return status;
2874 }
2875 
2876 static int adc_synchronization(struct drxk_state *state)
2877 {
2878 	u16 count = 0;
2879 	int status;
2880 
2881 	dprintk(1, "\n");
2882 
2883 	status = adc_sync_measurement(state, &count);
2884 	if (status < 0)
2885 		goto error;
2886 
2887 	if (count == 1) {
2888 		/* Try sampling on a different edge */
2889 		u16 clk_neg = 0;
2890 
2891 		status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2892 		if (status < 0)
2893 			goto error;
2894 		if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2895 			IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2896 			clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2897 			clk_neg |=
2898 				IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2899 		} else {
2900 			clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2901 			clk_neg |=
2902 				IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2903 		}
2904 		status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2905 		if (status < 0)
2906 			goto error;
2907 		status = adc_sync_measurement(state, &count);
2908 		if (status < 0)
2909 			goto error;
2910 	}
2911 
2912 	if (count < 2)
2913 		status = -EINVAL;
2914 error:
2915 	if (status < 0)
2916 		pr_err("Error %d on %s\n", status, __func__);
2917 	return status;
2918 }
2919 
2920 static int set_frequency_shifter(struct drxk_state *state,
2921 			       u16 intermediate_freqk_hz,
2922 			       s32 tuner_freq_offset, bool is_dtv)
2923 {
2924 	bool select_pos_image = false;
2925 	u32 rf_freq_residual = tuner_freq_offset;
2926 	u32 fm_frequency_shift = 0;
2927 	bool tuner_mirror = !state->m_b_mirror_freq_spect;
2928 	u32 adc_freq;
2929 	bool adc_flip;
2930 	int status;
2931 	u32 if_freq_actual;
2932 	u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2933 	u32 frequency_shift;
2934 	bool image_to_select;
2935 
2936 	dprintk(1, "\n");
2937 
2938 	/*
2939 	   Program frequency shifter
2940 	   No need to account for mirroring on RF
2941 	 */
2942 	if (is_dtv) {
2943 		if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2944 		    (state->m_operation_mode == OM_QAM_ITU_C) ||
2945 		    (state->m_operation_mode == OM_DVBT))
2946 			select_pos_image = true;
2947 		else
2948 			select_pos_image = false;
2949 	}
2950 	if (tuner_mirror)
2951 		/* tuner doesn't mirror */
2952 		if_freq_actual = intermediate_freqk_hz +
2953 		    rf_freq_residual + fm_frequency_shift;
2954 	else
2955 		/* tuner mirrors */
2956 		if_freq_actual = intermediate_freqk_hz -
2957 		    rf_freq_residual - fm_frequency_shift;
2958 	if (if_freq_actual > sampling_frequency / 2) {
2959 		/* adc mirrors */
2960 		adc_freq = sampling_frequency - if_freq_actual;
2961 		adc_flip = true;
2962 	} else {
2963 		/* adc doesn't mirror */
2964 		adc_freq = if_freq_actual;
2965 		adc_flip = false;
2966 	}
2967 
2968 	frequency_shift = adc_freq;
2969 	image_to_select = state->m_rfmirror ^ tuner_mirror ^
2970 	    adc_flip ^ select_pos_image;
2971 	state->m_iqm_fs_rate_ofs =
2972 	    Frac28a((frequency_shift), sampling_frequency);
2973 
2974 	if (image_to_select)
2975 		state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2976 
2977 	/* Program frequency shifter with tuner offset compensation */
2978 	/* frequency_shift += tuner_freq_offset; TODO */
2979 	status = write32(state, IQM_FS_RATE_OFS_LO__A,
2980 			 state->m_iqm_fs_rate_ofs);
2981 	if (status < 0)
2982 		pr_err("Error %d on %s\n", status, __func__);
2983 	return status;
2984 }
2985 
2986 static int init_agc(struct drxk_state *state, bool is_dtv)
2987 {
2988 	u16 ingain_tgt = 0;
2989 	u16 ingain_tgt_min = 0;
2990 	u16 ingain_tgt_max = 0;
2991 	u16 clp_cyclen = 0;
2992 	u16 clp_sum_min = 0;
2993 	u16 clp_dir_to = 0;
2994 	u16 sns_sum_min = 0;
2995 	u16 sns_sum_max = 0;
2996 	u16 clp_sum_max = 0;
2997 	u16 sns_dir_to = 0;
2998 	u16 ki_innergain_min = 0;
2999 	u16 if_iaccu_hi_tgt = 0;
3000 	u16 if_iaccu_hi_tgt_min = 0;
3001 	u16 if_iaccu_hi_tgt_max = 0;
3002 	u16 data = 0;
3003 	u16 fast_clp_ctrl_delay = 0;
3004 	u16 clp_ctrl_mode = 0;
3005 	int status = 0;
3006 
3007 	dprintk(1, "\n");
3008 
3009 	/* Common settings */
3010 	sns_sum_max = 1023;
3011 	if_iaccu_hi_tgt_min = 2047;
3012 	clp_cyclen = 500;
3013 	clp_sum_max = 1023;
3014 
3015 	/* AGCInit() not available for DVBT; init done in microcode */
3016 	if (!is_qam(state)) {
3017 		pr_err("%s: mode %d is not DVB-C\n",
3018 		       __func__, state->m_operation_mode);
3019 		return -EINVAL;
3020 	}
3021 
3022 	/* FIXME: Analog TV AGC require different settings */
3023 
3024 	/* Standard specific settings */
3025 	clp_sum_min = 8;
3026 	clp_dir_to = (u16) -9;
3027 	clp_ctrl_mode = 0;
3028 	sns_sum_min = 8;
3029 	sns_dir_to = (u16) -9;
3030 	ki_innergain_min = (u16) -1030;
3031 	if_iaccu_hi_tgt_max = 0x2380;
3032 	if_iaccu_hi_tgt = 0x2380;
3033 	ingain_tgt_min = 0x0511;
3034 	ingain_tgt = 0x0511;
3035 	ingain_tgt_max = 5119;
3036 	fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3037 
3038 	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3039 			 fast_clp_ctrl_delay);
3040 	if (status < 0)
3041 		goto error;
3042 
3043 	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3044 	if (status < 0)
3045 		goto error;
3046 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3047 	if (status < 0)
3048 		goto error;
3049 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3050 	if (status < 0)
3051 		goto error;
3052 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3053 	if (status < 0)
3054 		goto error;
3055 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3056 			 if_iaccu_hi_tgt_min);
3057 	if (status < 0)
3058 		goto error;
3059 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3060 			 if_iaccu_hi_tgt_max);
3061 	if (status < 0)
3062 		goto error;
3063 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3064 	if (status < 0)
3065 		goto error;
3066 	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3067 	if (status < 0)
3068 		goto error;
3069 	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3070 	if (status < 0)
3071 		goto error;
3072 	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3073 	if (status < 0)
3074 		goto error;
3075 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3076 	if (status < 0)
3077 		goto error;
3078 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3079 	if (status < 0)
3080 		goto error;
3081 
3082 	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3083 			 ki_innergain_min);
3084 	if (status < 0)
3085 		goto error;
3086 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3087 			 if_iaccu_hi_tgt);
3088 	if (status < 0)
3089 		goto error;
3090 	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3091 	if (status < 0)
3092 		goto error;
3093 
3094 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3095 	if (status < 0)
3096 		goto error;
3097 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3098 	if (status < 0)
3099 		goto error;
3100 	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3101 	if (status < 0)
3102 		goto error;
3103 
3104 	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3105 	if (status < 0)
3106 		goto error;
3107 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3108 	if (status < 0)
3109 		goto error;
3110 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3111 	if (status < 0)
3112 		goto error;
3113 	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3114 	if (status < 0)
3115 		goto error;
3116 	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3117 	if (status < 0)
3118 		goto error;
3119 	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3120 	if (status < 0)
3121 		goto error;
3122 	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3123 	if (status < 0)
3124 		goto error;
3125 	status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3126 	if (status < 0)
3127 		goto error;
3128 	status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3129 	if (status < 0)
3130 		goto error;
3131 	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3132 	if (status < 0)
3133 		goto error;
3134 	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3135 	if (status < 0)
3136 		goto error;
3137 	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3138 	if (status < 0)
3139 		goto error;
3140 	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3141 	if (status < 0)
3142 		goto error;
3143 	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3144 	if (status < 0)
3145 		goto error;
3146 	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3147 	if (status < 0)
3148 		goto error;
3149 	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3150 	if (status < 0)
3151 		goto error;
3152 	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3153 	if (status < 0)
3154 		goto error;
3155 	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3156 	if (status < 0)
3157 		goto error;
3158 	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3159 	if (status < 0)
3160 		goto error;
3161 
3162 	/* Initialize inner-loop KI gain factors */
3163 	status = read16(state, SCU_RAM_AGC_KI__A, &data);
3164 	if (status < 0)
3165 		goto error;
3166 
3167 	data = 0x0657;
3168 	data &= ~SCU_RAM_AGC_KI_RF__M;
3169 	data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3170 	data &= ~SCU_RAM_AGC_KI_IF__M;
3171 	data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3172 
3173 	status = write16(state, SCU_RAM_AGC_KI__A, data);
3174 error:
3175 	if (status < 0)
3176 		pr_err("Error %d on %s\n", status, __func__);
3177 	return status;
3178 }
3179 
3180 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3181 {
3182 	int status;
3183 
3184 	dprintk(1, "\n");
3185 	if (packet_err == NULL)
3186 		status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3187 	else
3188 		status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3189 				packet_err);
3190 	if (status < 0)
3191 		pr_err("Error %d on %s\n", status, __func__);
3192 	return status;
3193 }
3194 
3195 static int dvbt_sc_command(struct drxk_state *state,
3196 			 u16 cmd, u16 subcmd,
3197 			 u16 param0, u16 param1, u16 param2,
3198 			 u16 param3, u16 param4)
3199 {
3200 	u16 cur_cmd = 0;
3201 	u16 err_code = 0;
3202 	u16 retry_cnt = 0;
3203 	u16 sc_exec = 0;
3204 	int status;
3205 
3206 	dprintk(1, "\n");
3207 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3208 	if (sc_exec != 1) {
3209 		/* SC is not running */
3210 		status = -EINVAL;
3211 	}
3212 	if (status < 0)
3213 		goto error;
3214 
3215 	/* Wait until sc is ready to receive command */
3216 	retry_cnt = 0;
3217 	do {
3218 		usleep_range(1000, 2000);
3219 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3220 		retry_cnt++;
3221 	} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3222 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3223 		goto error;
3224 
3225 	/* Write sub-command */
3226 	switch (cmd) {
3227 		/* All commands using sub-cmd */
3228 	case OFDM_SC_RA_RAM_CMD_PROC_START:
3229 	case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3230 	case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3231 		status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3232 		if (status < 0)
3233 			goto error;
3234 		break;
3235 	default:
3236 		/* Do nothing */
3237 		break;
3238 	}
3239 
3240 	/* Write needed parameters and the command */
3241 	status = 0;
3242 	switch (cmd) {
3243 		/* All commands using 5 parameters */
3244 		/* All commands using 4 parameters */
3245 		/* All commands using 3 parameters */
3246 		/* All commands using 2 parameters */
3247 	case OFDM_SC_RA_RAM_CMD_PROC_START:
3248 	case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3249 	case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3250 		status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3251 		fallthrough;	/* All commands using 1 parameters */
3252 	case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3253 	case OFDM_SC_RA_RAM_CMD_USER_IO:
3254 		status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3255 		fallthrough;	/* All commands using 0 parameters */
3256 	case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3257 	case OFDM_SC_RA_RAM_CMD_NULL:
3258 		/* Write command */
3259 		status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3260 		break;
3261 	default:
3262 		/* Unknown command */
3263 		status = -EINVAL;
3264 	}
3265 	if (status < 0)
3266 		goto error;
3267 
3268 	/* Wait until sc is ready processing command */
3269 	retry_cnt = 0;
3270 	do {
3271 		usleep_range(1000, 2000);
3272 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3273 		retry_cnt++;
3274 	} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3275 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3276 		goto error;
3277 
3278 	/* Check for illegal cmd */
3279 	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3280 	if (err_code == 0xFFFF) {
3281 		/* illegal command */
3282 		status = -EINVAL;
3283 	}
3284 	if (status < 0)
3285 		goto error;
3286 
3287 	/* Retrieve results parameters from SC */
3288 	switch (cmd) {
3289 		/* All commands yielding 5 results */
3290 		/* All commands yielding 4 results */
3291 		/* All commands yielding 3 results */
3292 		/* All commands yielding 2 results */
3293 		/* All commands yielding 1 result */
3294 	case OFDM_SC_RA_RAM_CMD_USER_IO:
3295 	case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3296 		status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3297 		break;
3298 		/* All commands yielding 0 results */
3299 	case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3300 	case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3301 	case OFDM_SC_RA_RAM_CMD_PROC_START:
3302 	case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3303 	case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3304 	case OFDM_SC_RA_RAM_CMD_NULL:
3305 		break;
3306 	default:
3307 		/* Unknown command */
3308 		status = -EINVAL;
3309 		break;
3310 	}			/* switch (cmd->cmd) */
3311 error:
3312 	if (status < 0)
3313 		pr_err("Error %d on %s\n", status, __func__);
3314 	return status;
3315 }
3316 
3317 static int power_up_dvbt(struct drxk_state *state)
3318 {
3319 	enum drx_power_mode power_mode = DRX_POWER_UP;
3320 	int status;
3321 
3322 	dprintk(1, "\n");
3323 	status = ctrl_power_mode(state, &power_mode);
3324 	if (status < 0)
3325 		pr_err("Error %d on %s\n", status, __func__);
3326 	return status;
3327 }
3328 
3329 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3330 {
3331 	int status;
3332 
3333 	dprintk(1, "\n");
3334 	if (*enabled)
3335 		status = write16(state, IQM_CF_BYPASSDET__A, 0);
3336 	else
3337 		status = write16(state, IQM_CF_BYPASSDET__A, 1);
3338 	if (status < 0)
3339 		pr_err("Error %d on %s\n", status, __func__);
3340 	return status;
3341 }
3342 
3343 #define DEFAULT_FR_THRES_8K     4000
3344 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3345 {
3346 
3347 	int status;
3348 
3349 	dprintk(1, "\n");
3350 	if (*enabled) {
3351 		/* write mask to 1 */
3352 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3353 				   DEFAULT_FR_THRES_8K);
3354 	} else {
3355 		/* write mask to 0 */
3356 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3357 	}
3358 	if (status < 0)
3359 		pr_err("Error %d on %s\n", status, __func__);
3360 
3361 	return status;
3362 }
3363 
3364 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3365 				struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3366 {
3367 	u16 data = 0;
3368 	int status;
3369 
3370 	dprintk(1, "\n");
3371 	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3372 	if (status < 0)
3373 		goto error;
3374 
3375 	switch (echo_thres->fft_mode) {
3376 	case DRX_FFTMODE_2K:
3377 		data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3378 		data |= ((echo_thres->threshold <<
3379 			OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3380 			& (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3381 		break;
3382 	case DRX_FFTMODE_8K:
3383 		data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3384 		data |= ((echo_thres->threshold <<
3385 			OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3386 			& (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3387 		break;
3388 	default:
3389 		return -EINVAL;
3390 	}
3391 
3392 	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3393 error:
3394 	if (status < 0)
3395 		pr_err("Error %d on %s\n", status, __func__);
3396 	return status;
3397 }
3398 
3399 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3400 			       enum drxk_cfg_dvbt_sqi_speed *speed)
3401 {
3402 	int status = -EINVAL;
3403 
3404 	dprintk(1, "\n");
3405 
3406 	switch (*speed) {
3407 	case DRXK_DVBT_SQI_SPEED_FAST:
3408 	case DRXK_DVBT_SQI_SPEED_MEDIUM:
3409 	case DRXK_DVBT_SQI_SPEED_SLOW:
3410 		break;
3411 	default:
3412 		goto error;
3413 	}
3414 	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3415 			   (u16) *speed);
3416 error:
3417 	if (status < 0)
3418 		pr_err("Error %d on %s\n", status, __func__);
3419 	return status;
3420 }
3421 
3422 /*============================================================================*/
3423 
3424 /*
3425 * \brief Activate DVBT specific presets
3426 * \param demod instance of demodulator.
3427 * \return DRXStatus_t.
3428 *
3429 * Called in DVBTSetStandard
3430 *
3431 */
3432 static int dvbt_activate_presets(struct drxk_state *state)
3433 {
3434 	int status;
3435 	bool setincenable = false;
3436 	bool setfrenable = true;
3437 
3438 	struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3439 	struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3440 
3441 	dprintk(1, "\n");
3442 	status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3443 	if (status < 0)
3444 		goto error;
3445 	status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3446 	if (status < 0)
3447 		goto error;
3448 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3449 	if (status < 0)
3450 		goto error;
3451 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3452 	if (status < 0)
3453 		goto error;
3454 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3455 			 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3456 error:
3457 	if (status < 0)
3458 		pr_err("Error %d on %s\n", status, __func__);
3459 	return status;
3460 }
3461 
3462 /*============================================================================*/
3463 
3464 /*
3465 * \brief Initialize channelswitch-independent settings for DVBT.
3466 * \param demod instance of demodulator.
3467 * \return DRXStatus_t.
3468 *
3469 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3470 * the DVB-T taps from the drxk_filters.h are used.
3471 */
3472 static int set_dvbt_standard(struct drxk_state *state,
3473 			   enum operation_mode o_mode)
3474 {
3475 	u16 cmd_result = 0;
3476 	u16 data = 0;
3477 	int status;
3478 
3479 	dprintk(1, "\n");
3480 
3481 	power_up_dvbt(state);
3482 	/* added antenna switch */
3483 	switch_antenna_to_dvbt(state);
3484 	/* send OFDM reset command */
3485 	status = scu_command(state,
3486 			     SCU_RAM_COMMAND_STANDARD_OFDM
3487 			     | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3488 			     0, NULL, 1, &cmd_result);
3489 	if (status < 0)
3490 		goto error;
3491 
3492 	/* send OFDM setenv command */
3493 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3494 			     | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3495 			     0, NULL, 1, &cmd_result);
3496 	if (status < 0)
3497 		goto error;
3498 
3499 	/* reset datapath for OFDM, processors first */
3500 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3501 	if (status < 0)
3502 		goto error;
3503 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3504 	if (status < 0)
3505 		goto error;
3506 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3507 	if (status < 0)
3508 		goto error;
3509 
3510 	/* IQM setup */
3511 	/* synchronize on ofdstate->m_festart */
3512 	status = write16(state, IQM_AF_UPD_SEL__A, 1);
3513 	if (status < 0)
3514 		goto error;
3515 	/* window size for clipping ADC detection */
3516 	status = write16(state, IQM_AF_CLP_LEN__A, 0);
3517 	if (status < 0)
3518 		goto error;
3519 	/* window size for for sense pre-SAW detection */
3520 	status = write16(state, IQM_AF_SNS_LEN__A, 0);
3521 	if (status < 0)
3522 		goto error;
3523 	/* sense threshold for sense pre-SAW detection */
3524 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3525 	if (status < 0)
3526 		goto error;
3527 	status = set_iqm_af(state, true);
3528 	if (status < 0)
3529 		goto error;
3530 
3531 	status = write16(state, IQM_AF_AGC_RF__A, 0);
3532 	if (status < 0)
3533 		goto error;
3534 
3535 	/* Impulse noise cruncher setup */
3536 	status = write16(state, IQM_AF_INC_LCT__A, 0);	/* crunch in IQM_CF */
3537 	if (status < 0)
3538 		goto error;
3539 	status = write16(state, IQM_CF_DET_LCT__A, 0);	/* detect in IQM_CF */
3540 	if (status < 0)
3541 		goto error;
3542 	status = write16(state, IQM_CF_WND_LEN__A, 3);	/* peak detector window length */
3543 	if (status < 0)
3544 		goto error;
3545 
3546 	status = write16(state, IQM_RC_STRETCH__A, 16);
3547 	if (status < 0)
3548 		goto error;
3549 	status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3550 	if (status < 0)
3551 		goto error;
3552 	status = write16(state, IQM_CF_DS_ENA__A, 0x4);	/* decimate output 2 */
3553 	if (status < 0)
3554 		goto error;
3555 	status = write16(state, IQM_CF_SCALE__A, 1600);
3556 	if (status < 0)
3557 		goto error;
3558 	status = write16(state, IQM_CF_SCALE_SH__A, 0);
3559 	if (status < 0)
3560 		goto error;
3561 
3562 	/* virtual clipping threshold for clipping ADC detection */
3563 	status = write16(state, IQM_AF_CLP_TH__A, 448);
3564 	if (status < 0)
3565 		goto error;
3566 	status = write16(state, IQM_CF_DATATH__A, 495);	/* crunching threshold */
3567 	if (status < 0)
3568 		goto error;
3569 
3570 	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3571 			      DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3572 	if (status < 0)
3573 		goto error;
3574 
3575 	status = write16(state, IQM_CF_PKDTH__A, 2);	/* peak detector threshold */
3576 	if (status < 0)
3577 		goto error;
3578 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3579 	if (status < 0)
3580 		goto error;
3581 	/* enable power measurement interrupt */
3582 	status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3583 	if (status < 0)
3584 		goto error;
3585 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3586 	if (status < 0)
3587 		goto error;
3588 
3589 	/* IQM will not be reset from here, sync ADC and update/init AGC */
3590 	status = adc_synchronization(state);
3591 	if (status < 0)
3592 		goto error;
3593 	status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3594 	if (status < 0)
3595 		goto error;
3596 
3597 	/* Halt SCU to enable safe non-atomic accesses */
3598 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3599 	if (status < 0)
3600 		goto error;
3601 
3602 	status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3603 	if (status < 0)
3604 		goto error;
3605 	status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3606 	if (status < 0)
3607 		goto error;
3608 
3609 	/* Set Noise Estimation notch width and enable DC fix */
3610 	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3611 	if (status < 0)
3612 		goto error;
3613 	data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3614 	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3615 	if (status < 0)
3616 		goto error;
3617 
3618 	/* Activate SCU to enable SCU commands */
3619 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3620 	if (status < 0)
3621 		goto error;
3622 
3623 	if (!state->m_drxk_a3_rom_code) {
3624 		/* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay  */
3625 		status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3626 				 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3627 		if (status < 0)
3628 			goto error;
3629 	}
3630 
3631 	/* OFDM_SC setup */
3632 #ifdef COMPILE_FOR_NONRT
3633 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3634 	if (status < 0)
3635 		goto error;
3636 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3637 	if (status < 0)
3638 		goto error;
3639 #endif
3640 
3641 	/* FEC setup */
3642 	status = write16(state, FEC_DI_INPUT_CTL__A, 1);	/* OFDM input */
3643 	if (status < 0)
3644 		goto error;
3645 
3646 
3647 #ifdef COMPILE_FOR_NONRT
3648 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3649 	if (status < 0)
3650 		goto error;
3651 #else
3652 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3653 	if (status < 0)
3654 		goto error;
3655 #endif
3656 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3657 	if (status < 0)
3658 		goto error;
3659 
3660 	/* Setup MPEG bus */
3661 	status = mpegts_dto_setup(state, OM_DVBT);
3662 	if (status < 0)
3663 		goto error;
3664 	/* Set DVBT Presets */
3665 	status = dvbt_activate_presets(state);
3666 	if (status < 0)
3667 		goto error;
3668 
3669 error:
3670 	if (status < 0)
3671 		pr_err("Error %d on %s\n", status, __func__);
3672 	return status;
3673 }
3674 
3675 /*============================================================================*/
3676 /*
3677 * \brief start dvbt demodulating for channel.
3678 * \param demod instance of demodulator.
3679 * \return DRXStatus_t.
3680 */
3681 static int dvbt_start(struct drxk_state *state)
3682 {
3683 	u16 param1;
3684 	int status;
3685 	/* drxk_ofdm_sc_cmd_t scCmd; */
3686 
3687 	dprintk(1, "\n");
3688 	/* start correct processes to get in lock */
3689 	/* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3690 	param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3691 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3692 				 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3693 				 0, 0, 0);
3694 	if (status < 0)
3695 		goto error;
3696 	/* start FEC OC */
3697 	status = mpegts_start(state);
3698 	if (status < 0)
3699 		goto error;
3700 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3701 	if (status < 0)
3702 		goto error;
3703 error:
3704 	if (status < 0)
3705 		pr_err("Error %d on %s\n", status, __func__);
3706 	return status;
3707 }
3708 
3709 
3710 /*============================================================================*/
3711 
3712 /*
3713 * \brief Set up dvbt demodulator for channel.
3714 * \param demod instance of demodulator.
3715 * \return DRXStatus_t.
3716 * // original DVBTSetChannel()
3717 */
3718 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3719 		   s32 tuner_freq_offset)
3720 {
3721 	u16 cmd_result = 0;
3722 	u16 transmission_params = 0;
3723 	u16 operation_mode = 0;
3724 	u32 iqm_rc_rate_ofs = 0;
3725 	u32 bandwidth = 0;
3726 	u16 param1;
3727 	int status;
3728 
3729 	dprintk(1, "IF =%d, TFO = %d\n",
3730 		intermediate_freqk_hz, tuner_freq_offset);
3731 
3732 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3733 			    | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3734 			    0, NULL, 1, &cmd_result);
3735 	if (status < 0)
3736 		goto error;
3737 
3738 	/* Halt SCU to enable safe non-atomic accesses */
3739 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3740 	if (status < 0)
3741 		goto error;
3742 
3743 	/* Stop processors */
3744 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3745 	if (status < 0)
3746 		goto error;
3747 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3748 	if (status < 0)
3749 		goto error;
3750 
3751 	/* Mandatory fix, always stop CP, required to set spl offset back to
3752 		hardware default (is set to 0 by ucode during pilot detection */
3753 	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3754 	if (status < 0)
3755 		goto error;
3756 
3757 	/*== Write channel settings to device ================================*/
3758 
3759 	/* mode */
3760 	switch (state->props.transmission_mode) {
3761 	case TRANSMISSION_MODE_AUTO:
3762 	default:
3763 		operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3764 		fallthrough;	/* try first guess DRX_FFTMODE_8K */
3765 	case TRANSMISSION_MODE_8K:
3766 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3767 		break;
3768 	case TRANSMISSION_MODE_2K:
3769 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3770 		break;
3771 	}
3772 
3773 	/* guard */
3774 	switch (state->props.guard_interval) {
3775 	default:
3776 	case GUARD_INTERVAL_AUTO:
3777 		operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3778 		fallthrough;	/* try first guess DRX_GUARD_1DIV4 */
3779 	case GUARD_INTERVAL_1_4:
3780 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3781 		break;
3782 	case GUARD_INTERVAL_1_32:
3783 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3784 		break;
3785 	case GUARD_INTERVAL_1_16:
3786 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3787 		break;
3788 	case GUARD_INTERVAL_1_8:
3789 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3790 		break;
3791 	}
3792 
3793 	/* hierarchy */
3794 	switch (state->props.hierarchy) {
3795 	case HIERARCHY_AUTO:
3796 	case HIERARCHY_NONE:
3797 	default:
3798 		operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3799 		/* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3800 		/* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3801 		fallthrough;
3802 	case HIERARCHY_1:
3803 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3804 		break;
3805 	case HIERARCHY_2:
3806 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3807 		break;
3808 	case HIERARCHY_4:
3809 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3810 		break;
3811 	}
3812 
3813 
3814 	/* modulation */
3815 	switch (state->props.modulation) {
3816 	case QAM_AUTO:
3817 	default:
3818 		operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3819 		fallthrough;	/* try first guess DRX_CONSTELLATION_QAM64 */
3820 	case QAM_64:
3821 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3822 		break;
3823 	case QPSK:
3824 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3825 		break;
3826 	case QAM_16:
3827 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3828 		break;
3829 	}
3830 #if 0
3831 	/* No hierarchical channels support in BDA */
3832 	/* Priority (only for hierarchical channels) */
3833 	switch (channel->priority) {
3834 	case DRX_PRIORITY_LOW:
3835 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3836 		WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3837 			OFDM_EC_SB_PRIOR_LO);
3838 		break;
3839 	case DRX_PRIORITY_HIGH:
3840 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3841 		WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3842 			OFDM_EC_SB_PRIOR_HI));
3843 		break;
3844 	case DRX_PRIORITY_UNKNOWN:
3845 	default:
3846 		status = -EINVAL;
3847 		goto error;
3848 	}
3849 #else
3850 	/* Set Priority high */
3851 	transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3852 	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3853 	if (status < 0)
3854 		goto error;
3855 #endif
3856 
3857 	/* coderate */
3858 	switch (state->props.code_rate_HP) {
3859 	case FEC_AUTO:
3860 	default:
3861 		operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3862 		fallthrough;	/* try first guess DRX_CODERATE_2DIV3 */
3863 	case FEC_2_3:
3864 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3865 		break;
3866 	case FEC_1_2:
3867 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3868 		break;
3869 	case FEC_3_4:
3870 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3871 		break;
3872 	case FEC_5_6:
3873 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3874 		break;
3875 	case FEC_7_8:
3876 		transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3877 		break;
3878 	}
3879 
3880 	/*
3881 	 * SAW filter selection: normally not necessary, but if wanted
3882 	 * the application can select a SAW filter via the driver by
3883 	 * using UIOs
3884 	 */
3885 
3886 	/* First determine real bandwidth (Hz) */
3887 	/* Also set delay for impulse noise cruncher */
3888 	/*
3889 	 * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3890 	 * changed by SC for fix for some 8K,1/8 guard but is restored by
3891 	 * InitEC and ResetEC functions
3892 	 */
3893 	switch (state->props.bandwidth_hz) {
3894 	case 0:
3895 		state->props.bandwidth_hz = 8000000;
3896 		fallthrough;
3897 	case 8000000:
3898 		bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3899 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3900 				 3052);
3901 		if (status < 0)
3902 			goto error;
3903 		/* cochannel protection for PAL 8 MHz */
3904 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3905 				 7);
3906 		if (status < 0)
3907 			goto error;
3908 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3909 				 7);
3910 		if (status < 0)
3911 			goto error;
3912 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3913 				 7);
3914 		if (status < 0)
3915 			goto error;
3916 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3917 				 1);
3918 		if (status < 0)
3919 			goto error;
3920 		break;
3921 	case 7000000:
3922 		bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3923 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3924 				 3491);
3925 		if (status < 0)
3926 			goto error;
3927 		/* cochannel protection for PAL 7 MHz */
3928 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3929 				 8);
3930 		if (status < 0)
3931 			goto error;
3932 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3933 				 8);
3934 		if (status < 0)
3935 			goto error;
3936 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3937 				 4);
3938 		if (status < 0)
3939 			goto error;
3940 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3941 				 1);
3942 		if (status < 0)
3943 			goto error;
3944 		break;
3945 	case 6000000:
3946 		bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3947 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3948 				 4073);
3949 		if (status < 0)
3950 			goto error;
3951 		/* cochannel protection for NTSC 6 MHz */
3952 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3953 				 19);
3954 		if (status < 0)
3955 			goto error;
3956 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3957 				 19);
3958 		if (status < 0)
3959 			goto error;
3960 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3961 				 14);
3962 		if (status < 0)
3963 			goto error;
3964 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3965 				 1);
3966 		if (status < 0)
3967 			goto error;
3968 		break;
3969 	default:
3970 		status = -EINVAL;
3971 		goto error;
3972 	}
3973 
3974 	if (iqm_rc_rate_ofs == 0) {
3975 		/* Now compute IQM_RC_RATE_OFS
3976 			(((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3977 			=>
3978 			((SysFreq / BandWidth) * (2^21)) - (2^23)
3979 			*/
3980 		/* (SysFreq / BandWidth) * (2^28)  */
3981 		/*
3982 		 * assert (MAX(sysClk)/MIN(bandwidth) < 16)
3983 		 *	=> assert(MAX(sysClk) < 16*MIN(bandwidth))
3984 		 *	=> assert(109714272 > 48000000) = true
3985 		 * so Frac 28 can be used
3986 		 */
3987 		iqm_rc_rate_ofs = Frac28a((u32)
3988 					((state->m_sys_clock_freq *
3989 						1000) / 3), bandwidth);
3990 		/* (SysFreq / BandWidth) * (2^21), rounding before truncating */
3991 		if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
3992 			iqm_rc_rate_ofs += 0x80L;
3993 		iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
3994 		/* ((SysFreq / BandWidth) * (2^21)) - (2^23)  */
3995 		iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
3996 	}
3997 
3998 	iqm_rc_rate_ofs &=
3999 		((((u32) IQM_RC_RATE_OFS_HI__M) <<
4000 		IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4001 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4002 	if (status < 0)
4003 		goto error;
4004 
4005 	/* Bandwidth setting done */
4006 
4007 #if 0
4008 	status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4009 	if (status < 0)
4010 		goto error;
4011 #endif
4012 	status = set_frequency_shifter(state, intermediate_freqk_hz,
4013 				       tuner_freq_offset, true);
4014 	if (status < 0)
4015 		goto error;
4016 
4017 	/*== start SC, write channel settings to SC ==========================*/
4018 
4019 	/* Activate SCU to enable SCU commands */
4020 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4021 	if (status < 0)
4022 		goto error;
4023 
4024 	/* Enable SC after setting all other parameters */
4025 	status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4026 	if (status < 0)
4027 		goto error;
4028 	status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4029 	if (status < 0)
4030 		goto error;
4031 
4032 
4033 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4034 			     | SCU_RAM_COMMAND_CMD_DEMOD_START,
4035 			     0, NULL, 1, &cmd_result);
4036 	if (status < 0)
4037 		goto error;
4038 
4039 	/* Write SC parameter registers, set all AUTO flags in operation mode */
4040 	param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4041 			OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4042 			OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4043 			OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4044 			OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4045 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4046 				0, transmission_params, param1, 0, 0, 0);
4047 	if (status < 0)
4048 		goto error;
4049 
4050 	if (!state->m_drxk_a3_rom_code)
4051 		status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4052 error:
4053 	if (status < 0)
4054 		pr_err("Error %d on %s\n", status, __func__);
4055 
4056 	return status;
4057 }
4058 
4059 
4060 /*============================================================================*/
4061 
4062 /*
4063 * \brief Retrieve lock status .
4064 * \param demod    Pointer to demodulator instance.
4065 * \param lockStat Pointer to lock status structure.
4066 * \return DRXStatus_t.
4067 *
4068 */
4069 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4070 {
4071 	int status;
4072 	const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4073 				    OFDM_SC_RA_RAM_LOCK_FEC__M);
4074 	const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4075 	const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4076 
4077 	u16 sc_ra_ram_lock = 0;
4078 	u16 sc_comm_exec = 0;
4079 
4080 	dprintk(1, "\n");
4081 
4082 	*p_lock_status = NOT_LOCKED;
4083 	/* driver 0.9.0 */
4084 	/* Check if SC is running */
4085 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4086 	if (status < 0)
4087 		goto end;
4088 	if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4089 		goto end;
4090 
4091 	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4092 	if (status < 0)
4093 		goto end;
4094 
4095 	if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4096 		*p_lock_status = MPEG_LOCK;
4097 	else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4098 		*p_lock_status = FEC_LOCK;
4099 	else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4100 		*p_lock_status = DEMOD_LOCK;
4101 	else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4102 		*p_lock_status = NEVER_LOCK;
4103 end:
4104 	if (status < 0)
4105 		pr_err("Error %d on %s\n", status, __func__);
4106 
4107 	return status;
4108 }
4109 
4110 static int power_up_qam(struct drxk_state *state)
4111 {
4112 	enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4113 	int status;
4114 
4115 	dprintk(1, "\n");
4116 	status = ctrl_power_mode(state, &power_mode);
4117 	if (status < 0)
4118 		pr_err("Error %d on %s\n", status, __func__);
4119 
4120 	return status;
4121 }
4122 
4123 
4124 /* Power Down QAM */
4125 static int power_down_qam(struct drxk_state *state)
4126 {
4127 	u16 data = 0;
4128 	u16 cmd_result;
4129 	int status = 0;
4130 
4131 	dprintk(1, "\n");
4132 	status = read16(state, SCU_COMM_EXEC__A, &data);
4133 	if (status < 0)
4134 		goto error;
4135 	if (data == SCU_COMM_EXEC_ACTIVE) {
4136 		/*
4137 			STOP demodulator
4138 			QAM and HW blocks
4139 			*/
4140 		/* stop all comstate->m_exec */
4141 		status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4142 		if (status < 0)
4143 			goto error;
4144 		status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4145 				     | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4146 				     0, NULL, 1, &cmd_result);
4147 		if (status < 0)
4148 			goto error;
4149 	}
4150 	/* powerdown AFE                   */
4151 	status = set_iqm_af(state, false);
4152 
4153 error:
4154 	if (status < 0)
4155 		pr_err("Error %d on %s\n", status, __func__);
4156 
4157 	return status;
4158 }
4159 
4160 /*============================================================================*/
4161 
4162 /*
4163 * \brief Setup of the QAM Measurement intervals for signal quality
4164 * \param demod instance of demod.
4165 * \param modulation current modulation.
4166 * \return DRXStatus_t.
4167 *
4168 *  NOTE:
4169 *  Take into account that for certain settings the errorcounters can overflow.
4170 *  The implementation does not check this.
4171 *
4172 */
4173 static int set_qam_measurement(struct drxk_state *state,
4174 			     enum e_drxk_constellation modulation,
4175 			     u32 symbol_rate)
4176 {
4177 	u32 fec_bits_desired = 0;	/* BER accounting period */
4178 	u32 fec_rs_period_total = 0;	/* Total period */
4179 	u16 fec_rs_prescale = 0;	/* ReedSolomon Measurement Prescale */
4180 	u16 fec_rs_period = 0;	/* Value for corresponding I2C register */
4181 	int status = 0;
4182 
4183 	dprintk(1, "\n");
4184 
4185 	fec_rs_prescale = 1;
4186 	/* fec_bits_desired = symbol_rate [kHz] *
4187 		FrameLenght [ms] *
4188 		(modulation + 1) *
4189 		SyncLoss (== 1) *
4190 		ViterbiLoss (==1)
4191 		*/
4192 	switch (modulation) {
4193 	case DRX_CONSTELLATION_QAM16:
4194 		fec_bits_desired = 4 * symbol_rate;
4195 		break;
4196 	case DRX_CONSTELLATION_QAM32:
4197 		fec_bits_desired = 5 * symbol_rate;
4198 		break;
4199 	case DRX_CONSTELLATION_QAM64:
4200 		fec_bits_desired = 6 * symbol_rate;
4201 		break;
4202 	case DRX_CONSTELLATION_QAM128:
4203 		fec_bits_desired = 7 * symbol_rate;
4204 		break;
4205 	case DRX_CONSTELLATION_QAM256:
4206 		fec_bits_desired = 8 * symbol_rate;
4207 		break;
4208 	default:
4209 		status = -EINVAL;
4210 	}
4211 	if (status < 0)
4212 		goto error;
4213 
4214 	fec_bits_desired /= 1000;	/* symbol_rate [Hz] -> symbol_rate [kHz] */
4215 	fec_bits_desired *= 500;	/* meas. period [ms] */
4216 
4217 	/* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4218 	/* fec_rs_period_total = fec_bits_desired / 1632 */
4219 	fec_rs_period_total = (fec_bits_desired / 1632UL) + 1;	/* roughly ceil */
4220 
4221 	/* fec_rs_period_total =  fec_rs_prescale * fec_rs_period  */
4222 	fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4223 	if (fec_rs_prescale == 0) {
4224 		/* Divide by zero (though impossible) */
4225 		status = -EINVAL;
4226 		if (status < 0)
4227 			goto error;
4228 	}
4229 	fec_rs_period =
4230 		((u16) fec_rs_period_total +
4231 		(fec_rs_prescale >> 1)) / fec_rs_prescale;
4232 
4233 	/* write corresponding registers */
4234 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4235 	if (status < 0)
4236 		goto error;
4237 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4238 			 fec_rs_prescale);
4239 	if (status < 0)
4240 		goto error;
4241 	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4242 error:
4243 	if (status < 0)
4244 		pr_err("Error %d on %s\n", status, __func__);
4245 	return status;
4246 }
4247 
4248 static int set_qam16(struct drxk_state *state)
4249 {
4250 	int status = 0;
4251 
4252 	dprintk(1, "\n");
4253 	/* QAM Equalizer Setup */
4254 	/* Equalizer */
4255 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4256 	if (status < 0)
4257 		goto error;
4258 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4259 	if (status < 0)
4260 		goto error;
4261 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4262 	if (status < 0)
4263 		goto error;
4264 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4265 	if (status < 0)
4266 		goto error;
4267 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4268 	if (status < 0)
4269 		goto error;
4270 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4271 	if (status < 0)
4272 		goto error;
4273 	/* Decision Feedback Equalizer */
4274 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4275 	if (status < 0)
4276 		goto error;
4277 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4278 	if (status < 0)
4279 		goto error;
4280 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4281 	if (status < 0)
4282 		goto error;
4283 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4284 	if (status < 0)
4285 		goto error;
4286 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4287 	if (status < 0)
4288 		goto error;
4289 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4290 	if (status < 0)
4291 		goto error;
4292 
4293 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4294 	if (status < 0)
4295 		goto error;
4296 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4297 	if (status < 0)
4298 		goto error;
4299 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4300 	if (status < 0)
4301 		goto error;
4302 
4303 	/* QAM Slicer Settings */
4304 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4305 			 DRXK_QAM_SL_SIG_POWER_QAM16);
4306 	if (status < 0)
4307 		goto error;
4308 
4309 	/* QAM Loop Controller Coeficients */
4310 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4311 	if (status < 0)
4312 		goto error;
4313 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4314 	if (status < 0)
4315 		goto error;
4316 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4317 	if (status < 0)
4318 		goto error;
4319 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4320 	if (status < 0)
4321 		goto error;
4322 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4323 	if (status < 0)
4324 		goto error;
4325 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4326 	if (status < 0)
4327 		goto error;
4328 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4329 	if (status < 0)
4330 		goto error;
4331 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4332 	if (status < 0)
4333 		goto error;
4334 
4335 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4336 	if (status < 0)
4337 		goto error;
4338 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4339 	if (status < 0)
4340 		goto error;
4341 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4342 	if (status < 0)
4343 		goto error;
4344 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4345 	if (status < 0)
4346 		goto error;
4347 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4348 	if (status < 0)
4349 		goto error;
4350 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4351 	if (status < 0)
4352 		goto error;
4353 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4354 	if (status < 0)
4355 		goto error;
4356 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4357 	if (status < 0)
4358 		goto error;
4359 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4360 	if (status < 0)
4361 		goto error;
4362 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4363 	if (status < 0)
4364 		goto error;
4365 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4366 	if (status < 0)
4367 		goto error;
4368 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4369 	if (status < 0)
4370 		goto error;
4371 
4372 
4373 	/* QAM State Machine (FSM) Thresholds */
4374 
4375 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4376 	if (status < 0)
4377 		goto error;
4378 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4379 	if (status < 0)
4380 		goto error;
4381 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4382 	if (status < 0)
4383 		goto error;
4384 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4385 	if (status < 0)
4386 		goto error;
4387 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4388 	if (status < 0)
4389 		goto error;
4390 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4391 	if (status < 0)
4392 		goto error;
4393 
4394 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4395 	if (status < 0)
4396 		goto error;
4397 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4398 	if (status < 0)
4399 		goto error;
4400 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4401 	if (status < 0)
4402 		goto error;
4403 
4404 
4405 	/* QAM FSM Tracking Parameters */
4406 
4407 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4408 	if (status < 0)
4409 		goto error;
4410 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4411 	if (status < 0)
4412 		goto error;
4413 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4414 	if (status < 0)
4415 		goto error;
4416 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4417 	if (status < 0)
4418 		goto error;
4419 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4420 	if (status < 0)
4421 		goto error;
4422 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4423 	if (status < 0)
4424 		goto error;
4425 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4426 	if (status < 0)
4427 		goto error;
4428 
4429 error:
4430 	if (status < 0)
4431 		pr_err("Error %d on %s\n", status, __func__);
4432 	return status;
4433 }
4434 
4435 /*============================================================================*/
4436 
4437 /*
4438 * \brief QAM32 specific setup
4439 * \param demod instance of demod.
4440 * \return DRXStatus_t.
4441 */
4442 static int set_qam32(struct drxk_state *state)
4443 {
4444 	int status = 0;
4445 
4446 	dprintk(1, "\n");
4447 
4448 	/* QAM Equalizer Setup */
4449 	/* Equalizer */
4450 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4451 	if (status < 0)
4452 		goto error;
4453 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4454 	if (status < 0)
4455 		goto error;
4456 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4457 	if (status < 0)
4458 		goto error;
4459 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4460 	if (status < 0)
4461 		goto error;
4462 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4463 	if (status < 0)
4464 		goto error;
4465 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4466 	if (status < 0)
4467 		goto error;
4468 
4469 	/* Decision Feedback Equalizer */
4470 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4471 	if (status < 0)
4472 		goto error;
4473 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4474 	if (status < 0)
4475 		goto error;
4476 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4477 	if (status < 0)
4478 		goto error;
4479 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4480 	if (status < 0)
4481 		goto error;
4482 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4483 	if (status < 0)
4484 		goto error;
4485 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4486 	if (status < 0)
4487 		goto error;
4488 
4489 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4490 	if (status < 0)
4491 		goto error;
4492 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4493 	if (status < 0)
4494 		goto error;
4495 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4496 	if (status < 0)
4497 		goto error;
4498 
4499 	/* QAM Slicer Settings */
4500 
4501 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4502 			 DRXK_QAM_SL_SIG_POWER_QAM32);
4503 	if (status < 0)
4504 		goto error;
4505 
4506 
4507 	/* QAM Loop Controller Coeficients */
4508 
4509 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4510 	if (status < 0)
4511 		goto error;
4512 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4513 	if (status < 0)
4514 		goto error;
4515 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4516 	if (status < 0)
4517 		goto error;
4518 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4519 	if (status < 0)
4520 		goto error;
4521 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4522 	if (status < 0)
4523 		goto error;
4524 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4525 	if (status < 0)
4526 		goto error;
4527 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4528 	if (status < 0)
4529 		goto error;
4530 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4531 	if (status < 0)
4532 		goto error;
4533 
4534 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4535 	if (status < 0)
4536 		goto error;
4537 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4538 	if (status < 0)
4539 		goto error;
4540 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4541 	if (status < 0)
4542 		goto error;
4543 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4544 	if (status < 0)
4545 		goto error;
4546 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4547 	if (status < 0)
4548 		goto error;
4549 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4550 	if (status < 0)
4551 		goto error;
4552 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4553 	if (status < 0)
4554 		goto error;
4555 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4556 	if (status < 0)
4557 		goto error;
4558 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4559 	if (status < 0)
4560 		goto error;
4561 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4562 	if (status < 0)
4563 		goto error;
4564 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4565 	if (status < 0)
4566 		goto error;
4567 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4568 	if (status < 0)
4569 		goto error;
4570 
4571 
4572 	/* QAM State Machine (FSM) Thresholds */
4573 
4574 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4575 	if (status < 0)
4576 		goto error;
4577 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4578 	if (status < 0)
4579 		goto error;
4580 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4581 	if (status < 0)
4582 		goto error;
4583 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4584 	if (status < 0)
4585 		goto error;
4586 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4587 	if (status < 0)
4588 		goto error;
4589 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4590 	if (status < 0)
4591 		goto error;
4592 
4593 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4594 	if (status < 0)
4595 		goto error;
4596 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4597 	if (status < 0)
4598 		goto error;
4599 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4600 	if (status < 0)
4601 		goto error;
4602 
4603 
4604 	/* QAM FSM Tracking Parameters */
4605 
4606 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4607 	if (status < 0)
4608 		goto error;
4609 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4610 	if (status < 0)
4611 		goto error;
4612 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4613 	if (status < 0)
4614 		goto error;
4615 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4616 	if (status < 0)
4617 		goto error;
4618 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4619 	if (status < 0)
4620 		goto error;
4621 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4622 	if (status < 0)
4623 		goto error;
4624 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4625 error:
4626 	if (status < 0)
4627 		pr_err("Error %d on %s\n", status, __func__);
4628 	return status;
4629 }
4630 
4631 /*============================================================================*/
4632 
4633 /*
4634 * \brief QAM64 specific setup
4635 * \param demod instance of demod.
4636 * \return DRXStatus_t.
4637 */
4638 static int set_qam64(struct drxk_state *state)
4639 {
4640 	int status = 0;
4641 
4642 	dprintk(1, "\n");
4643 	/* QAM Equalizer Setup */
4644 	/* Equalizer */
4645 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4646 	if (status < 0)
4647 		goto error;
4648 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4649 	if (status < 0)
4650 		goto error;
4651 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4652 	if (status < 0)
4653 		goto error;
4654 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4655 	if (status < 0)
4656 		goto error;
4657 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4658 	if (status < 0)
4659 		goto error;
4660 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4661 	if (status < 0)
4662 		goto error;
4663 
4664 	/* Decision Feedback Equalizer */
4665 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4666 	if (status < 0)
4667 		goto error;
4668 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4669 	if (status < 0)
4670 		goto error;
4671 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4672 	if (status < 0)
4673 		goto error;
4674 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4675 	if (status < 0)
4676 		goto error;
4677 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4678 	if (status < 0)
4679 		goto error;
4680 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4681 	if (status < 0)
4682 		goto error;
4683 
4684 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4685 	if (status < 0)
4686 		goto error;
4687 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4688 	if (status < 0)
4689 		goto error;
4690 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4691 	if (status < 0)
4692 		goto error;
4693 
4694 	/* QAM Slicer Settings */
4695 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4696 			 DRXK_QAM_SL_SIG_POWER_QAM64);
4697 	if (status < 0)
4698 		goto error;
4699 
4700 
4701 	/* QAM Loop Controller Coeficients */
4702 
4703 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4704 	if (status < 0)
4705 		goto error;
4706 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4707 	if (status < 0)
4708 		goto error;
4709 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4710 	if (status < 0)
4711 		goto error;
4712 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4713 	if (status < 0)
4714 		goto error;
4715 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4716 	if (status < 0)
4717 		goto error;
4718 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4719 	if (status < 0)
4720 		goto error;
4721 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4722 	if (status < 0)
4723 		goto error;
4724 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4725 	if (status < 0)
4726 		goto error;
4727 
4728 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4729 	if (status < 0)
4730 		goto error;
4731 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4732 	if (status < 0)
4733 		goto error;
4734 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4735 	if (status < 0)
4736 		goto error;
4737 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4738 	if (status < 0)
4739 		goto error;
4740 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4741 	if (status < 0)
4742 		goto error;
4743 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4744 	if (status < 0)
4745 		goto error;
4746 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4747 	if (status < 0)
4748 		goto error;
4749 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4750 	if (status < 0)
4751 		goto error;
4752 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4753 	if (status < 0)
4754 		goto error;
4755 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4756 	if (status < 0)
4757 		goto error;
4758 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4759 	if (status < 0)
4760 		goto error;
4761 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4762 	if (status < 0)
4763 		goto error;
4764 
4765 
4766 	/* QAM State Machine (FSM) Thresholds */
4767 
4768 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4769 	if (status < 0)
4770 		goto error;
4771 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4772 	if (status < 0)
4773 		goto error;
4774 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4775 	if (status < 0)
4776 		goto error;
4777 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4778 	if (status < 0)
4779 		goto error;
4780 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4781 	if (status < 0)
4782 		goto error;
4783 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4784 	if (status < 0)
4785 		goto error;
4786 
4787 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4788 	if (status < 0)
4789 		goto error;
4790 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4791 	if (status < 0)
4792 		goto error;
4793 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4794 	if (status < 0)
4795 		goto error;
4796 
4797 
4798 	/* QAM FSM Tracking Parameters */
4799 
4800 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4801 	if (status < 0)
4802 		goto error;
4803 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4804 	if (status < 0)
4805 		goto error;
4806 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4807 	if (status < 0)
4808 		goto error;
4809 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4810 	if (status < 0)
4811 		goto error;
4812 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4813 	if (status < 0)
4814 		goto error;
4815 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4816 	if (status < 0)
4817 		goto error;
4818 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4819 error:
4820 	if (status < 0)
4821 		pr_err("Error %d on %s\n", status, __func__);
4822 
4823 	return status;
4824 }
4825 
4826 /*============================================================================*/
4827 
4828 /*
4829 * \brief QAM128 specific setup
4830 * \param demod: instance of demod.
4831 * \return DRXStatus_t.
4832 */
4833 static int set_qam128(struct drxk_state *state)
4834 {
4835 	int status = 0;
4836 
4837 	dprintk(1, "\n");
4838 	/* QAM Equalizer Setup */
4839 	/* Equalizer */
4840 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4841 	if (status < 0)
4842 		goto error;
4843 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4844 	if (status < 0)
4845 		goto error;
4846 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4847 	if (status < 0)
4848 		goto error;
4849 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4850 	if (status < 0)
4851 		goto error;
4852 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4853 	if (status < 0)
4854 		goto error;
4855 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4856 	if (status < 0)
4857 		goto error;
4858 
4859 	/* Decision Feedback Equalizer */
4860 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4861 	if (status < 0)
4862 		goto error;
4863 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4864 	if (status < 0)
4865 		goto error;
4866 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4867 	if (status < 0)
4868 		goto error;
4869 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4870 	if (status < 0)
4871 		goto error;
4872 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4873 	if (status < 0)
4874 		goto error;
4875 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4876 	if (status < 0)
4877 		goto error;
4878 
4879 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4880 	if (status < 0)
4881 		goto error;
4882 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4883 	if (status < 0)
4884 		goto error;
4885 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4886 	if (status < 0)
4887 		goto error;
4888 
4889 
4890 	/* QAM Slicer Settings */
4891 
4892 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4893 			 DRXK_QAM_SL_SIG_POWER_QAM128);
4894 	if (status < 0)
4895 		goto error;
4896 
4897 
4898 	/* QAM Loop Controller Coeficients */
4899 
4900 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4901 	if (status < 0)
4902 		goto error;
4903 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4904 	if (status < 0)
4905 		goto error;
4906 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4907 	if (status < 0)
4908 		goto error;
4909 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4910 	if (status < 0)
4911 		goto error;
4912 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4913 	if (status < 0)
4914 		goto error;
4915 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4916 	if (status < 0)
4917 		goto error;
4918 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4919 	if (status < 0)
4920 		goto error;
4921 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4922 	if (status < 0)
4923 		goto error;
4924 
4925 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4926 	if (status < 0)
4927 		goto error;
4928 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4929 	if (status < 0)
4930 		goto error;
4931 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4932 	if (status < 0)
4933 		goto error;
4934 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4935 	if (status < 0)
4936 		goto error;
4937 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4938 	if (status < 0)
4939 		goto error;
4940 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4941 	if (status < 0)
4942 		goto error;
4943 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4944 	if (status < 0)
4945 		goto error;
4946 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4947 	if (status < 0)
4948 		goto error;
4949 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4950 	if (status < 0)
4951 		goto error;
4952 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4953 	if (status < 0)
4954 		goto error;
4955 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4956 	if (status < 0)
4957 		goto error;
4958 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4959 	if (status < 0)
4960 		goto error;
4961 
4962 
4963 	/* QAM State Machine (FSM) Thresholds */
4964 
4965 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4966 	if (status < 0)
4967 		goto error;
4968 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4969 	if (status < 0)
4970 		goto error;
4971 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4972 	if (status < 0)
4973 		goto error;
4974 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4975 	if (status < 0)
4976 		goto error;
4977 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4978 	if (status < 0)
4979 		goto error;
4980 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4981 	if (status < 0)
4982 		goto error;
4983 
4984 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4985 	if (status < 0)
4986 		goto error;
4987 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4988 	if (status < 0)
4989 		goto error;
4990 
4991 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4992 	if (status < 0)
4993 		goto error;
4994 
4995 	/* QAM FSM Tracking Parameters */
4996 
4997 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4998 	if (status < 0)
4999 		goto error;
5000 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5001 	if (status < 0)
5002 		goto error;
5003 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5004 	if (status < 0)
5005 		goto error;
5006 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5007 	if (status < 0)
5008 		goto error;
5009 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5010 	if (status < 0)
5011 		goto error;
5012 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5013 	if (status < 0)
5014 		goto error;
5015 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5016 error:
5017 	if (status < 0)
5018 		pr_err("Error %d on %s\n", status, __func__);
5019 
5020 	return status;
5021 }
5022 
5023 /*============================================================================*/
5024 
5025 /*
5026 * \brief QAM256 specific setup
5027 * \param demod: instance of demod.
5028 * \return DRXStatus_t.
5029 */
5030 static int set_qam256(struct drxk_state *state)
5031 {
5032 	int status = 0;
5033 
5034 	dprintk(1, "\n");
5035 	/* QAM Equalizer Setup */
5036 	/* Equalizer */
5037 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5038 	if (status < 0)
5039 		goto error;
5040 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5041 	if (status < 0)
5042 		goto error;
5043 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5044 	if (status < 0)
5045 		goto error;
5046 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5047 	if (status < 0)
5048 		goto error;
5049 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5050 	if (status < 0)
5051 		goto error;
5052 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5053 	if (status < 0)
5054 		goto error;
5055 
5056 	/* Decision Feedback Equalizer */
5057 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5058 	if (status < 0)
5059 		goto error;
5060 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5061 	if (status < 0)
5062 		goto error;
5063 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5064 	if (status < 0)
5065 		goto error;
5066 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5067 	if (status < 0)
5068 		goto error;
5069 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5070 	if (status < 0)
5071 		goto error;
5072 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5073 	if (status < 0)
5074 		goto error;
5075 
5076 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5077 	if (status < 0)
5078 		goto error;
5079 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5080 	if (status < 0)
5081 		goto error;
5082 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5083 	if (status < 0)
5084 		goto error;
5085 
5086 	/* QAM Slicer Settings */
5087 
5088 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5089 			 DRXK_QAM_SL_SIG_POWER_QAM256);
5090 	if (status < 0)
5091 		goto error;
5092 
5093 
5094 	/* QAM Loop Controller Coeficients */
5095 
5096 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5097 	if (status < 0)
5098 		goto error;
5099 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5100 	if (status < 0)
5101 		goto error;
5102 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5103 	if (status < 0)
5104 		goto error;
5105 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5106 	if (status < 0)
5107 		goto error;
5108 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5109 	if (status < 0)
5110 		goto error;
5111 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5112 	if (status < 0)
5113 		goto error;
5114 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5115 	if (status < 0)
5116 		goto error;
5117 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5118 	if (status < 0)
5119 		goto error;
5120 
5121 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5122 	if (status < 0)
5123 		goto error;
5124 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5125 	if (status < 0)
5126 		goto error;
5127 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5128 	if (status < 0)
5129 		goto error;
5130 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5131 	if (status < 0)
5132 		goto error;
5133 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5134 	if (status < 0)
5135 		goto error;
5136 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5137 	if (status < 0)
5138 		goto error;
5139 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5140 	if (status < 0)
5141 		goto error;
5142 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5143 	if (status < 0)
5144 		goto error;
5145 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5146 	if (status < 0)
5147 		goto error;
5148 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5149 	if (status < 0)
5150 		goto error;
5151 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5152 	if (status < 0)
5153 		goto error;
5154 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5155 	if (status < 0)
5156 		goto error;
5157 
5158 
5159 	/* QAM State Machine (FSM) Thresholds */
5160 
5161 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5162 	if (status < 0)
5163 		goto error;
5164 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5165 	if (status < 0)
5166 		goto error;
5167 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5168 	if (status < 0)
5169 		goto error;
5170 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5171 	if (status < 0)
5172 		goto error;
5173 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5174 	if (status < 0)
5175 		goto error;
5176 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5177 	if (status < 0)
5178 		goto error;
5179 
5180 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5181 	if (status < 0)
5182 		goto error;
5183 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5184 	if (status < 0)
5185 		goto error;
5186 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5187 	if (status < 0)
5188 		goto error;
5189 
5190 
5191 	/* QAM FSM Tracking Parameters */
5192 
5193 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5194 	if (status < 0)
5195 		goto error;
5196 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5197 	if (status < 0)
5198 		goto error;
5199 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5200 	if (status < 0)
5201 		goto error;
5202 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5203 	if (status < 0)
5204 		goto error;
5205 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5206 	if (status < 0)
5207 		goto error;
5208 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5209 	if (status < 0)
5210 		goto error;
5211 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5212 error:
5213 	if (status < 0)
5214 		pr_err("Error %d on %s\n", status, __func__);
5215 	return status;
5216 }
5217 
5218 
5219 /*============================================================================*/
5220 /*
5221 * \brief Reset QAM block.
5222 * \param demod:   instance of demod.
5223 * \param channel: pointer to channel data.
5224 * \return DRXStatus_t.
5225 */
5226 static int qam_reset_qam(struct drxk_state *state)
5227 {
5228 	int status;
5229 	u16 cmd_result;
5230 
5231 	dprintk(1, "\n");
5232 	/* Stop QAM comstate->m_exec */
5233 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5234 	if (status < 0)
5235 		goto error;
5236 
5237 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5238 			     | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5239 			     0, NULL, 1, &cmd_result);
5240 error:
5241 	if (status < 0)
5242 		pr_err("Error %d on %s\n", status, __func__);
5243 	return status;
5244 }
5245 
5246 /*============================================================================*/
5247 
5248 /*
5249 * \brief Set QAM symbolrate.
5250 * \param demod:   instance of demod.
5251 * \param channel: pointer to channel data.
5252 * \return DRXStatus_t.
5253 */
5254 static int qam_set_symbolrate(struct drxk_state *state)
5255 {
5256 	u32 adc_frequency = 0;
5257 	u32 symb_freq = 0;
5258 	u32 iqm_rc_rate = 0;
5259 	u16 ratesel = 0;
5260 	u32 lc_symb_rate = 0;
5261 	int status;
5262 
5263 	dprintk(1, "\n");
5264 	/* Select & calculate correct IQM rate */
5265 	adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5266 	ratesel = 0;
5267 	if (state->props.symbol_rate <= 1188750)
5268 		ratesel = 3;
5269 	else if (state->props.symbol_rate <= 2377500)
5270 		ratesel = 2;
5271 	else if (state->props.symbol_rate <= 4755000)
5272 		ratesel = 1;
5273 	status = write16(state, IQM_FD_RATESEL__A, ratesel);
5274 	if (status < 0)
5275 		goto error;
5276 
5277 	/*
5278 		IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5279 		*/
5280 	symb_freq = state->props.symbol_rate * (1 << ratesel);
5281 	if (symb_freq == 0) {
5282 		/* Divide by zero */
5283 		status = -EINVAL;
5284 		goto error;
5285 	}
5286 	iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5287 		(Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5288 		(1 << 23);
5289 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5290 	if (status < 0)
5291 		goto error;
5292 	state->m_iqm_rc_rate = iqm_rc_rate;
5293 	/*
5294 		LcSymbFreq = round (.125 *  symbolrate / adc_freq * (1<<15))
5295 		*/
5296 	symb_freq = state->props.symbol_rate;
5297 	if (adc_frequency == 0) {
5298 		/* Divide by zero */
5299 		status = -EINVAL;
5300 		goto error;
5301 	}
5302 	lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5303 		(Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5304 		16);
5305 	if (lc_symb_rate > 511)
5306 		lc_symb_rate = 511;
5307 	status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5308 
5309 error:
5310 	if (status < 0)
5311 		pr_err("Error %d on %s\n", status, __func__);
5312 	return status;
5313 }
5314 
5315 /*============================================================================*/
5316 
5317 /*
5318 * \brief Get QAM lock status.
5319 * \param demod:   instance of demod.
5320 * \param channel: pointer to channel data.
5321 * \return DRXStatus_t.
5322 */
5323 
5324 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5325 {
5326 	int status;
5327 	u16 result[2] = { 0, 0 };
5328 
5329 	dprintk(1, "\n");
5330 	*p_lock_status = NOT_LOCKED;
5331 	status = scu_command(state,
5332 			SCU_RAM_COMMAND_STANDARD_QAM |
5333 			SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5334 			result);
5335 	if (status < 0)
5336 		pr_err("Error %d on %s\n", status, __func__);
5337 
5338 	if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5339 		/* 0x0000 NOT LOCKED */
5340 	} else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5341 		/* 0x4000 DEMOD LOCKED */
5342 		*p_lock_status = DEMOD_LOCK;
5343 	} else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5344 		/* 0x8000 DEMOD + FEC LOCKED (system lock) */
5345 		*p_lock_status = MPEG_LOCK;
5346 	} else {
5347 		/* 0xC000 NEVER LOCKED */
5348 		/* (system will never be able to lock to the signal) */
5349 		/*
5350 		 * TODO: check this, intermediate & standard specific lock
5351 		 * states are not taken into account here
5352 		 */
5353 		*p_lock_status = NEVER_LOCK;
5354 	}
5355 	return status;
5356 }
5357 
5358 #define QAM_MIRROR__M         0x03
5359 #define QAM_MIRROR_NORMAL     0x00
5360 #define QAM_MIRRORED          0x01
5361 #define QAM_MIRROR_AUTO_ON    0x02
5362 #define QAM_LOCKRANGE__M      0x10
5363 #define QAM_LOCKRANGE_NORMAL  0x10
5364 
5365 static int qam_demodulator_command(struct drxk_state *state,
5366 				 int number_of_parameters)
5367 {
5368 	int status;
5369 	u16 cmd_result;
5370 	u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5371 
5372 	set_param_parameters[0] = state->m_constellation;	/* modulation     */
5373 	set_param_parameters[1] = DRXK_QAM_I12_J17;	/* interleave mode   */
5374 
5375 	if (number_of_parameters == 2) {
5376 		u16 set_env_parameters[1] = { 0 };
5377 
5378 		if (state->m_operation_mode == OM_QAM_ITU_C)
5379 			set_env_parameters[0] = QAM_TOP_ANNEX_C;
5380 		else
5381 			set_env_parameters[0] = QAM_TOP_ANNEX_A;
5382 
5383 		status = scu_command(state,
5384 				     SCU_RAM_COMMAND_STANDARD_QAM
5385 				     | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5386 				     1, set_env_parameters, 1, &cmd_result);
5387 		if (status < 0)
5388 			goto error;
5389 
5390 		status = scu_command(state,
5391 				     SCU_RAM_COMMAND_STANDARD_QAM
5392 				     | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5393 				     number_of_parameters, set_param_parameters,
5394 				     1, &cmd_result);
5395 	} else if (number_of_parameters == 4) {
5396 		if (state->m_operation_mode == OM_QAM_ITU_C)
5397 			set_param_parameters[2] = QAM_TOP_ANNEX_C;
5398 		else
5399 			set_param_parameters[2] = QAM_TOP_ANNEX_A;
5400 
5401 		set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5402 		/* Env parameters */
5403 		/* check for LOCKRANGE Extended */
5404 		/* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5405 
5406 		status = scu_command(state,
5407 				     SCU_RAM_COMMAND_STANDARD_QAM
5408 				     | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5409 				     number_of_parameters, set_param_parameters,
5410 				     1, &cmd_result);
5411 	} else {
5412 		pr_warn("Unknown QAM demodulator parameter count %d\n",
5413 			number_of_parameters);
5414 		status = -EINVAL;
5415 	}
5416 
5417 error:
5418 	if (status < 0)
5419 		pr_warn("Warning %d on %s\n", status, __func__);
5420 	return status;
5421 }
5422 
5423 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5424 		  s32 tuner_freq_offset)
5425 {
5426 	int status;
5427 	u16 cmd_result;
5428 	int qam_demod_param_count = state->qam_demod_parameter_count;
5429 
5430 	dprintk(1, "\n");
5431 	/*
5432 	 * STEP 1: reset demodulator
5433 	 *	resets FEC DI and FEC RS
5434 	 *	resets QAM block
5435 	 *	resets SCU variables
5436 	 */
5437 	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5438 	if (status < 0)
5439 		goto error;
5440 	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5441 	if (status < 0)
5442 		goto error;
5443 	status = qam_reset_qam(state);
5444 	if (status < 0)
5445 		goto error;
5446 
5447 	/*
5448 	 * STEP 2: configure demodulator
5449 	 *	-set params; resets IQM,QAM,FEC HW; initializes some
5450 	 *       SCU variables
5451 	 */
5452 	status = qam_set_symbolrate(state);
5453 	if (status < 0)
5454 		goto error;
5455 
5456 	/* Set params */
5457 	switch (state->props.modulation) {
5458 	case QAM_256:
5459 		state->m_constellation = DRX_CONSTELLATION_QAM256;
5460 		break;
5461 	case QAM_AUTO:
5462 	case QAM_64:
5463 		state->m_constellation = DRX_CONSTELLATION_QAM64;
5464 		break;
5465 	case QAM_16:
5466 		state->m_constellation = DRX_CONSTELLATION_QAM16;
5467 		break;
5468 	case QAM_32:
5469 		state->m_constellation = DRX_CONSTELLATION_QAM32;
5470 		break;
5471 	case QAM_128:
5472 		state->m_constellation = DRX_CONSTELLATION_QAM128;
5473 		break;
5474 	default:
5475 		status = -EINVAL;
5476 		break;
5477 	}
5478 	if (status < 0)
5479 		goto error;
5480 
5481 	/* Use the 4-parameter if it's requested or we're probing for
5482 	 * the correct command. */
5483 	if (state->qam_demod_parameter_count == 4
5484 		|| !state->qam_demod_parameter_count) {
5485 		qam_demod_param_count = 4;
5486 		status = qam_demodulator_command(state, qam_demod_param_count);
5487 	}
5488 
5489 	/* Use the 2-parameter command if it was requested or if we're
5490 	 * probing for the correct command and the 4-parameter command
5491 	 * failed. */
5492 	if (state->qam_demod_parameter_count == 2
5493 		|| (!state->qam_demod_parameter_count && status < 0)) {
5494 		qam_demod_param_count = 2;
5495 		status = qam_demodulator_command(state, qam_demod_param_count);
5496 	}
5497 
5498 	if (status < 0) {
5499 		dprintk(1, "Could not set demodulator parameters.\n");
5500 		dprintk(1,
5501 			"Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5502 			state->qam_demod_parameter_count,
5503 			state->microcode_name);
5504 		goto error;
5505 	} else if (!state->qam_demod_parameter_count) {
5506 		dprintk(1,
5507 			"Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5508 			qam_demod_param_count);
5509 
5510 		/*
5511 		 * One of our commands was successful. We don't need to
5512 		 * auto-probe anymore, now that we got the correct command.
5513 		 */
5514 		state->qam_demod_parameter_count = qam_demod_param_count;
5515 	}
5516 
5517 	/*
5518 	 * STEP 3: enable the system in a mode where the ADC provides valid
5519 	 * signal setup modulation independent registers
5520 	 */
5521 #if 0
5522 	status = set_frequency(channel, tuner_freq_offset));
5523 	if (status < 0)
5524 		goto error;
5525 #endif
5526 	status = set_frequency_shifter(state, intermediate_freqk_hz,
5527 				       tuner_freq_offset, true);
5528 	if (status < 0)
5529 		goto error;
5530 
5531 	/* Setup BER measurement */
5532 	status = set_qam_measurement(state, state->m_constellation,
5533 				     state->props.symbol_rate);
5534 	if (status < 0)
5535 		goto error;
5536 
5537 	/* Reset default values */
5538 	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5539 	if (status < 0)
5540 		goto error;
5541 	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5542 	if (status < 0)
5543 		goto error;
5544 
5545 	/* Reset default LC values */
5546 	status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5547 	if (status < 0)
5548 		goto error;
5549 	status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5550 	if (status < 0)
5551 		goto error;
5552 	status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5553 	if (status < 0)
5554 		goto error;
5555 	status = write16(state, QAM_LC_MODE__A, 7);
5556 	if (status < 0)
5557 		goto error;
5558 
5559 	status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5560 	if (status < 0)
5561 		goto error;
5562 	status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5563 	if (status < 0)
5564 		goto error;
5565 	status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5566 	if (status < 0)
5567 		goto error;
5568 	status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5569 	if (status < 0)
5570 		goto error;
5571 	status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5572 	if (status < 0)
5573 		goto error;
5574 	status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5575 	if (status < 0)
5576 		goto error;
5577 	status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5578 	if (status < 0)
5579 		goto error;
5580 	status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5581 	if (status < 0)
5582 		goto error;
5583 	status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5584 	if (status < 0)
5585 		goto error;
5586 	status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5587 	if (status < 0)
5588 		goto error;
5589 	status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5590 	if (status < 0)
5591 		goto error;
5592 	status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5593 	if (status < 0)
5594 		goto error;
5595 	status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5596 	if (status < 0)
5597 		goto error;
5598 	status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5599 	if (status < 0)
5600 		goto error;
5601 	status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5602 	if (status < 0)
5603 		goto error;
5604 
5605 	/* Mirroring, QAM-block starting point not inverted */
5606 	status = write16(state, QAM_SY_SP_INV__A,
5607 			 QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5608 	if (status < 0)
5609 		goto error;
5610 
5611 	/* Halt SCU to enable safe non-atomic accesses */
5612 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5613 	if (status < 0)
5614 		goto error;
5615 
5616 	/* STEP 4: modulation specific setup */
5617 	switch (state->props.modulation) {
5618 	case QAM_16:
5619 		status = set_qam16(state);
5620 		break;
5621 	case QAM_32:
5622 		status = set_qam32(state);
5623 		break;
5624 	case QAM_AUTO:
5625 	case QAM_64:
5626 		status = set_qam64(state);
5627 		break;
5628 	case QAM_128:
5629 		status = set_qam128(state);
5630 		break;
5631 	case QAM_256:
5632 		status = set_qam256(state);
5633 		break;
5634 	default:
5635 		status = -EINVAL;
5636 		break;
5637 	}
5638 	if (status < 0)
5639 		goto error;
5640 
5641 	/* Activate SCU to enable SCU commands */
5642 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5643 	if (status < 0)
5644 		goto error;
5645 
5646 	/* Re-configure MPEG output, requires knowledge of channel bitrate */
5647 	/* extAttr->currentChannel.modulation = channel->modulation; */
5648 	/* extAttr->currentChannel.symbolrate    = channel->symbolrate; */
5649 	status = mpegts_dto_setup(state, state->m_operation_mode);
5650 	if (status < 0)
5651 		goto error;
5652 
5653 	/* start processes */
5654 	status = mpegts_start(state);
5655 	if (status < 0)
5656 		goto error;
5657 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5658 	if (status < 0)
5659 		goto error;
5660 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5661 	if (status < 0)
5662 		goto error;
5663 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5664 	if (status < 0)
5665 		goto error;
5666 
5667 	/* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5668 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5669 			     | SCU_RAM_COMMAND_CMD_DEMOD_START,
5670 			     0, NULL, 1, &cmd_result);
5671 	if (status < 0)
5672 		goto error;
5673 
5674 	/* update global DRXK data container */
5675 /*?     extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5676 
5677 error:
5678 	if (status < 0)
5679 		pr_err("Error %d on %s\n", status, __func__);
5680 	return status;
5681 }
5682 
5683 static int set_qam_standard(struct drxk_state *state,
5684 			  enum operation_mode o_mode)
5685 {
5686 	int status;
5687 #ifdef DRXK_QAM_TAPS
5688 #define DRXK_QAMA_TAPS_SELECT
5689 #include "drxk_filters.h"
5690 #undef DRXK_QAMA_TAPS_SELECT
5691 #endif
5692 
5693 	dprintk(1, "\n");
5694 
5695 	/* added antenna switch */
5696 	switch_antenna_to_qam(state);
5697 
5698 	/* Ensure correct power-up mode */
5699 	status = power_up_qam(state);
5700 	if (status < 0)
5701 		goto error;
5702 	/* Reset QAM block */
5703 	status = qam_reset_qam(state);
5704 	if (status < 0)
5705 		goto error;
5706 
5707 	/* Setup IQM */
5708 
5709 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5710 	if (status < 0)
5711 		goto error;
5712 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5713 	if (status < 0)
5714 		goto error;
5715 
5716 	/* Upload IQM Channel Filter settings by
5717 		boot loader from ROM table */
5718 	switch (o_mode) {
5719 	case OM_QAM_ITU_A:
5720 		status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5721 				      DRXK_BLCC_NR_ELEMENTS_TAPS,
5722 			DRXK_BLC_TIMEOUT);
5723 		break;
5724 	case OM_QAM_ITU_C:
5725 		status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5726 				       DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5727 				       DRXK_BLDC_NR_ELEMENTS_TAPS,
5728 				       DRXK_BLC_TIMEOUT);
5729 		if (status < 0)
5730 			goto error;
5731 		status = bl_direct_cmd(state,
5732 				       IQM_CF_TAP_IM0__A,
5733 				       DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5734 				       DRXK_BLDC_NR_ELEMENTS_TAPS,
5735 				       DRXK_BLC_TIMEOUT);
5736 		break;
5737 	default:
5738 		status = -EINVAL;
5739 	}
5740 	if (status < 0)
5741 		goto error;
5742 
5743 	status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5744 	if (status < 0)
5745 		goto error;
5746 	status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5747 	if (status < 0)
5748 		goto error;
5749 	status = write16(state, IQM_CF_MIDTAP__A,
5750 		     ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5751 	if (status < 0)
5752 		goto error;
5753 
5754 	status = write16(state, IQM_RC_STRETCH__A, 21);
5755 	if (status < 0)
5756 		goto error;
5757 	status = write16(state, IQM_AF_CLP_LEN__A, 0);
5758 	if (status < 0)
5759 		goto error;
5760 	status = write16(state, IQM_AF_CLP_TH__A, 448);
5761 	if (status < 0)
5762 		goto error;
5763 	status = write16(state, IQM_AF_SNS_LEN__A, 0);
5764 	if (status < 0)
5765 		goto error;
5766 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5767 	if (status < 0)
5768 		goto error;
5769 
5770 	status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5771 	if (status < 0)
5772 		goto error;
5773 	status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5774 	if (status < 0)
5775 		goto error;
5776 	status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5777 	if (status < 0)
5778 		goto error;
5779 	status = write16(state, IQM_AF_UPD_SEL__A, 0);
5780 	if (status < 0)
5781 		goto error;
5782 
5783 	/* IQM Impulse Noise Processing Unit */
5784 	status = write16(state, IQM_CF_CLP_VAL__A, 500);
5785 	if (status < 0)
5786 		goto error;
5787 	status = write16(state, IQM_CF_DATATH__A, 1000);
5788 	if (status < 0)
5789 		goto error;
5790 	status = write16(state, IQM_CF_BYPASSDET__A, 1);
5791 	if (status < 0)
5792 		goto error;
5793 	status = write16(state, IQM_CF_DET_LCT__A, 0);
5794 	if (status < 0)
5795 		goto error;
5796 	status = write16(state, IQM_CF_WND_LEN__A, 1);
5797 	if (status < 0)
5798 		goto error;
5799 	status = write16(state, IQM_CF_PKDTH__A, 1);
5800 	if (status < 0)
5801 		goto error;
5802 	status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5803 	if (status < 0)
5804 		goto error;
5805 
5806 	/* turn on IQMAF. Must be done before setAgc**() */
5807 	status = set_iqm_af(state, true);
5808 	if (status < 0)
5809 		goto error;
5810 	status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5811 	if (status < 0)
5812 		goto error;
5813 
5814 	/* IQM will not be reset from here, sync ADC and update/init AGC */
5815 	status = adc_synchronization(state);
5816 	if (status < 0)
5817 		goto error;
5818 
5819 	/* Set the FSM step period */
5820 	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5821 	if (status < 0)
5822 		goto error;
5823 
5824 	/* Halt SCU to enable safe non-atomic accesses */
5825 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5826 	if (status < 0)
5827 		goto error;
5828 
5829 	/* No more resets of the IQM, current standard correctly set =>
5830 		now AGCs can be configured. */
5831 
5832 	status = init_agc(state, true);
5833 	if (status < 0)
5834 		goto error;
5835 	status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5836 	if (status < 0)
5837 		goto error;
5838 
5839 	/* Configure AGC's */
5840 	status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5841 	if (status < 0)
5842 		goto error;
5843 	status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5844 	if (status < 0)
5845 		goto error;
5846 
5847 	/* Activate SCU to enable SCU commands */
5848 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5849 error:
5850 	if (status < 0)
5851 		pr_err("Error %d on %s\n", status, __func__);
5852 	return status;
5853 }
5854 
5855 static int write_gpio(struct drxk_state *state)
5856 {
5857 	int status;
5858 	u16 value = 0;
5859 
5860 	dprintk(1, "\n");
5861 	/* stop lock indicator process */
5862 	status = write16(state, SCU_RAM_GPIO__A,
5863 			 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5864 	if (status < 0)
5865 		goto error;
5866 
5867 	/*  Write magic word to enable pdr reg write               */
5868 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5869 	if (status < 0)
5870 		goto error;
5871 
5872 	if (state->m_has_sawsw) {
5873 		if (state->uio_mask & 0x0001) { /* UIO-1 */
5874 			/* write to io pad configuration register - output mode */
5875 			status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5876 					 state->m_gpio_cfg);
5877 			if (status < 0)
5878 				goto error;
5879 
5880 			/* use corresponding bit in io data output registar */
5881 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5882 			if (status < 0)
5883 				goto error;
5884 			if ((state->m_gpio & 0x0001) == 0)
5885 				value &= 0x7FFF;	/* write zero to 15th bit - 1st UIO */
5886 			else
5887 				value |= 0x8000;	/* write one to 15th bit - 1st UIO */
5888 			/* write back to io data output register */
5889 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5890 			if (status < 0)
5891 				goto error;
5892 		}
5893 		if (state->uio_mask & 0x0002) { /* UIO-2 */
5894 			/* write to io pad configuration register - output mode */
5895 			status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5896 					 state->m_gpio_cfg);
5897 			if (status < 0)
5898 				goto error;
5899 
5900 			/* use corresponding bit in io data output registar */
5901 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5902 			if (status < 0)
5903 				goto error;
5904 			if ((state->m_gpio & 0x0002) == 0)
5905 				value &= 0xBFFF;	/* write zero to 14th bit - 2st UIO */
5906 			else
5907 				value |= 0x4000;	/* write one to 14th bit - 2st UIO */
5908 			/* write back to io data output register */
5909 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5910 			if (status < 0)
5911 				goto error;
5912 		}
5913 		if (state->uio_mask & 0x0004) { /* UIO-3 */
5914 			/* write to io pad configuration register - output mode */
5915 			status = write16(state, SIO_PDR_GPIO_CFG__A,
5916 					 state->m_gpio_cfg);
5917 			if (status < 0)
5918 				goto error;
5919 
5920 			/* use corresponding bit in io data output registar */
5921 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5922 			if (status < 0)
5923 				goto error;
5924 			if ((state->m_gpio & 0x0004) == 0)
5925 				value &= 0xFFFB;            /* write zero to 2nd bit - 3rd UIO */
5926 			else
5927 				value |= 0x0004;            /* write one to 2nd bit - 3rd UIO */
5928 			/* write back to io data output register */
5929 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5930 			if (status < 0)
5931 				goto error;
5932 		}
5933 	}
5934 	/*  Write magic word to disable pdr reg write               */
5935 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5936 error:
5937 	if (status < 0)
5938 		pr_err("Error %d on %s\n", status, __func__);
5939 	return status;
5940 }
5941 
5942 static int switch_antenna_to_qam(struct drxk_state *state)
5943 {
5944 	int status = 0;
5945 	bool gpio_state;
5946 
5947 	dprintk(1, "\n");
5948 
5949 	if (!state->antenna_gpio)
5950 		return 0;
5951 
5952 	gpio_state = state->m_gpio & state->antenna_gpio;
5953 
5954 	if (state->antenna_dvbt ^ gpio_state) {
5955 		/* Antenna is on DVB-T mode. Switch */
5956 		if (state->antenna_dvbt)
5957 			state->m_gpio &= ~state->antenna_gpio;
5958 		else
5959 			state->m_gpio |= state->antenna_gpio;
5960 		status = write_gpio(state);
5961 	}
5962 	if (status < 0)
5963 		pr_err("Error %d on %s\n", status, __func__);
5964 	return status;
5965 }
5966 
5967 static int switch_antenna_to_dvbt(struct drxk_state *state)
5968 {
5969 	int status = 0;
5970 	bool gpio_state;
5971 
5972 	dprintk(1, "\n");
5973 
5974 	if (!state->antenna_gpio)
5975 		return 0;
5976 
5977 	gpio_state = state->m_gpio & state->antenna_gpio;
5978 
5979 	if (!(state->antenna_dvbt ^ gpio_state)) {
5980 		/* Antenna is on DVB-C mode. Switch */
5981 		if (state->antenna_dvbt)
5982 			state->m_gpio |= state->antenna_gpio;
5983 		else
5984 			state->m_gpio &= ~state->antenna_gpio;
5985 		status = write_gpio(state);
5986 	}
5987 	if (status < 0)
5988 		pr_err("Error %d on %s\n", status, __func__);
5989 	return status;
5990 }
5991 
5992 
5993 static int power_down_device(struct drxk_state *state)
5994 {
5995 	/* Power down to requested mode */
5996 	/* Backup some register settings */
5997 	/* Set pins with possible pull-ups connected to them in input mode */
5998 	/* Analog power down */
5999 	/* ADC power down */
6000 	/* Power down device */
6001 	int status;
6002 
6003 	dprintk(1, "\n");
6004 	if (state->m_b_p_down_open_bridge) {
6005 		/* Open I2C bridge before power down of DRXK */
6006 		status = ConfigureI2CBridge(state, true);
6007 		if (status < 0)
6008 			goto error;
6009 	}
6010 	/* driver 0.9.0 */
6011 	status = dvbt_enable_ofdm_token_ring(state, false);
6012 	if (status < 0)
6013 		goto error;
6014 
6015 	status = write16(state, SIO_CC_PWD_MODE__A,
6016 			 SIO_CC_PWD_MODE_LEVEL_CLOCK);
6017 	if (status < 0)
6018 		goto error;
6019 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6020 	if (status < 0)
6021 		goto error;
6022 	state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6023 	status = hi_cfg_command(state);
6024 error:
6025 	if (status < 0)
6026 		pr_err("Error %d on %s\n", status, __func__);
6027 
6028 	return status;
6029 }
6030 
6031 static int init_drxk(struct drxk_state *state)
6032 {
6033 	int status = 0, n = 0;
6034 	enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6035 	u16 driver_version;
6036 
6037 	dprintk(1, "\n");
6038 	if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6039 		drxk_i2c_lock(state);
6040 		status = power_up_device(state);
6041 		if (status < 0)
6042 			goto error;
6043 		status = drxx_open(state);
6044 		if (status < 0)
6045 			goto error;
6046 		/* Soft reset of OFDM-, sys- and osc-clockdomain */
6047 		status = write16(state, SIO_CC_SOFT_RST__A,
6048 				 SIO_CC_SOFT_RST_OFDM__M
6049 				 | SIO_CC_SOFT_RST_SYS__M
6050 				 | SIO_CC_SOFT_RST_OSC__M);
6051 		if (status < 0)
6052 			goto error;
6053 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6054 		if (status < 0)
6055 			goto error;
6056 		/*
6057 		 * TODO is this needed? If yes, how much delay in
6058 		 * worst case scenario
6059 		 */
6060 		usleep_range(1000, 2000);
6061 		state->m_drxk_a3_patch_code = true;
6062 		status = get_device_capabilities(state);
6063 		if (status < 0)
6064 			goto error;
6065 
6066 		/* Bridge delay, uses oscilator clock */
6067 		/* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6068 		/* SDA brdige delay */
6069 		state->m_hi_cfg_bridge_delay =
6070 			(u16) ((state->m_osc_clock_freq / 1000) *
6071 				HI_I2C_BRIDGE_DELAY) / 1000;
6072 		/* Clipping */
6073 		if (state->m_hi_cfg_bridge_delay >
6074 			SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6075 			state->m_hi_cfg_bridge_delay =
6076 				SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6077 		}
6078 		/* SCL bridge delay, same as SDA for now */
6079 		state->m_hi_cfg_bridge_delay +=
6080 			state->m_hi_cfg_bridge_delay <<
6081 			SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6082 
6083 		status = init_hi(state);
6084 		if (status < 0)
6085 			goto error;
6086 		/* disable various processes */
6087 #if NOA1ROM
6088 		if (!(state->m_DRXK_A1_ROM_CODE)
6089 			&& !(state->m_DRXK_A2_ROM_CODE))
6090 #endif
6091 		{
6092 			status = write16(state, SCU_RAM_GPIO__A,
6093 					 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6094 			if (status < 0)
6095 				goto error;
6096 		}
6097 
6098 		/* disable MPEG port */
6099 		status = mpegts_disable(state);
6100 		if (status < 0)
6101 			goto error;
6102 
6103 		/* Stop AUD and SCU */
6104 		status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6105 		if (status < 0)
6106 			goto error;
6107 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6108 		if (status < 0)
6109 			goto error;
6110 
6111 		/* enable token-ring bus through OFDM block for possible ucode upload */
6112 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6113 				 SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6114 		if (status < 0)
6115 			goto error;
6116 
6117 		/* include boot loader section */
6118 		status = write16(state, SIO_BL_COMM_EXEC__A,
6119 				 SIO_BL_COMM_EXEC_ACTIVE);
6120 		if (status < 0)
6121 			goto error;
6122 		status = bl_chain_cmd(state, 0, 6, 100);
6123 		if (status < 0)
6124 			goto error;
6125 
6126 		if (state->fw) {
6127 			status = download_microcode(state, state->fw->data,
6128 						   state->fw->size);
6129 			if (status < 0)
6130 				goto error;
6131 		}
6132 
6133 		/* disable token-ring bus through OFDM block for possible ucode upload */
6134 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6135 				 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6136 		if (status < 0)
6137 			goto error;
6138 
6139 		/* Run SCU for a little while to initialize microcode version numbers */
6140 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6141 		if (status < 0)
6142 			goto error;
6143 		status = drxx_open(state);
6144 		if (status < 0)
6145 			goto error;
6146 		/* added for test */
6147 		msleep(30);
6148 
6149 		power_mode = DRXK_POWER_DOWN_OFDM;
6150 		status = ctrl_power_mode(state, &power_mode);
6151 		if (status < 0)
6152 			goto error;
6153 
6154 		/* Stamp driver version number in SCU data RAM in BCD code
6155 			Done to enable field application engineers to retrieve drxdriver version
6156 			via I2C from SCU RAM.
6157 			Not using SCU command interface for SCU register access since no
6158 			microcode may be present.
6159 			*/
6160 		driver_version =
6161 			(((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6162 			(((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6163 			((DRXK_VERSION_MAJOR % 10) << 4) +
6164 			(DRXK_VERSION_MINOR % 10);
6165 		status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6166 				 driver_version);
6167 		if (status < 0)
6168 			goto error;
6169 		driver_version =
6170 			(((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6171 			(((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6172 			(((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6173 			(DRXK_VERSION_PATCH % 10);
6174 		status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6175 				 driver_version);
6176 		if (status < 0)
6177 			goto error;
6178 
6179 		pr_info("DRXK driver version %d.%d.%d\n",
6180 			DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6181 			DRXK_VERSION_PATCH);
6182 
6183 		/*
6184 		 * Dirty fix of default values for ROM/PATCH microcode
6185 		 * Dirty because this fix makes it impossible to setup
6186 		 * suitable values before calling DRX_Open. This solution
6187 		 * requires changes to RF AGC speed to be done via the CTRL
6188 		 * function after calling DRX_Open
6189 		 */
6190 
6191 		/* m_dvbt_rf_agc_cfg.speed = 3; */
6192 
6193 		/* Reset driver debug flags to 0 */
6194 		status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6195 		if (status < 0)
6196 			goto error;
6197 		/* driver 0.9.0 */
6198 		/* Setup FEC OC:
6199 			NOTE: No more full FEC resets allowed afterwards!! */
6200 		status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6201 		if (status < 0)
6202 			goto error;
6203 		/* MPEGTS functions are still the same */
6204 		status = mpegts_dto_init(state);
6205 		if (status < 0)
6206 			goto error;
6207 		status = mpegts_stop(state);
6208 		if (status < 0)
6209 			goto error;
6210 		status = mpegts_configure_polarity(state);
6211 		if (status < 0)
6212 			goto error;
6213 		status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6214 		if (status < 0)
6215 			goto error;
6216 		/* added: configure GPIO */
6217 		status = write_gpio(state);
6218 		if (status < 0)
6219 			goto error;
6220 
6221 		state->m_drxk_state = DRXK_STOPPED;
6222 
6223 		if (state->m_b_power_down) {
6224 			status = power_down_device(state);
6225 			if (status < 0)
6226 				goto error;
6227 			state->m_drxk_state = DRXK_POWERED_DOWN;
6228 		} else
6229 			state->m_drxk_state = DRXK_STOPPED;
6230 
6231 		/* Initialize the supported delivery systems */
6232 		n = 0;
6233 		if (state->m_has_dvbc) {
6234 			state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6235 			state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6236 			strlcat(state->frontend.ops.info.name, " DVB-C",
6237 				sizeof(state->frontend.ops.info.name));
6238 		}
6239 		if (state->m_has_dvbt) {
6240 			state->frontend.ops.delsys[n++] = SYS_DVBT;
6241 			strlcat(state->frontend.ops.info.name, " DVB-T",
6242 				sizeof(state->frontend.ops.info.name));
6243 		}
6244 		drxk_i2c_unlock(state);
6245 	}
6246 error:
6247 	if (status < 0) {
6248 		state->m_drxk_state = DRXK_NO_DEV;
6249 		drxk_i2c_unlock(state);
6250 		pr_err("Error %d on %s\n", status, __func__);
6251 	}
6252 
6253 	return status;
6254 }
6255 
6256 static void load_firmware_cb(const struct firmware *fw,
6257 			     void *context)
6258 {
6259 	struct drxk_state *state = context;
6260 
6261 	dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6262 	if (!fw) {
6263 		pr_err("Could not load firmware file %s.\n",
6264 			state->microcode_name);
6265 		pr_info("Copy %s to your hotplug directory!\n",
6266 			state->microcode_name);
6267 		state->microcode_name = NULL;
6268 
6269 		/*
6270 		 * As firmware is now load asynchronous, it is not possible
6271 		 * anymore to fail at frontend attach. We might silently
6272 		 * return here, and hope that the driver won't crash.
6273 		 * We might also change all DVB callbacks to return -ENODEV
6274 		 * if the device is not initialized.
6275 		 * As the DRX-K devices have their own internal firmware,
6276 		 * let's just hope that it will match a firmware revision
6277 		 * compatible with this driver and proceed.
6278 		 */
6279 	}
6280 	state->fw = fw;
6281 
6282 	init_drxk(state);
6283 }
6284 
6285 static void drxk_release(struct dvb_frontend *fe)
6286 {
6287 	struct drxk_state *state = fe->demodulator_priv;
6288 
6289 	dprintk(1, "\n");
6290 	release_firmware(state->fw);
6291 
6292 	kfree(state);
6293 }
6294 
6295 static int drxk_sleep(struct dvb_frontend *fe)
6296 {
6297 	struct drxk_state *state = fe->demodulator_priv;
6298 
6299 	dprintk(1, "\n");
6300 
6301 	if (state->m_drxk_state == DRXK_NO_DEV)
6302 		return -ENODEV;
6303 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6304 		return 0;
6305 
6306 	shut_down(state);
6307 	return 0;
6308 }
6309 
6310 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6311 {
6312 	struct drxk_state *state = fe->demodulator_priv;
6313 
6314 	dprintk(1, ": %s\n", enable ? "enable" : "disable");
6315 
6316 	if (state->m_drxk_state == DRXK_NO_DEV)
6317 		return -ENODEV;
6318 
6319 	return ConfigureI2CBridge(state, enable ? true : false);
6320 }
6321 
6322 static int drxk_set_parameters(struct dvb_frontend *fe)
6323 {
6324 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6325 	u32 delsys  = p->delivery_system, old_delsys;
6326 	struct drxk_state *state = fe->demodulator_priv;
6327 	u32 IF;
6328 
6329 	dprintk(1, "\n");
6330 
6331 	if (state->m_drxk_state == DRXK_NO_DEV)
6332 		return -ENODEV;
6333 
6334 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6335 		return -EAGAIN;
6336 
6337 	if (!fe->ops.tuner_ops.get_if_frequency) {
6338 		pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6339 		return -EINVAL;
6340 	}
6341 
6342 	if (fe->ops.i2c_gate_ctrl)
6343 		fe->ops.i2c_gate_ctrl(fe, 1);
6344 	if (fe->ops.tuner_ops.set_params)
6345 		fe->ops.tuner_ops.set_params(fe);
6346 	if (fe->ops.i2c_gate_ctrl)
6347 		fe->ops.i2c_gate_ctrl(fe, 0);
6348 
6349 	old_delsys = state->props.delivery_system;
6350 	state->props = *p;
6351 
6352 	if (old_delsys != delsys) {
6353 		shut_down(state);
6354 		switch (delsys) {
6355 		case SYS_DVBC_ANNEX_A:
6356 		case SYS_DVBC_ANNEX_C:
6357 			if (!state->m_has_dvbc)
6358 				return -EINVAL;
6359 			state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6360 						true : false;
6361 			if (state->m_itut_annex_c)
6362 				setoperation_mode(state, OM_QAM_ITU_C);
6363 			else
6364 				setoperation_mode(state, OM_QAM_ITU_A);
6365 			break;
6366 		case SYS_DVBT:
6367 			if (!state->m_has_dvbt)
6368 				return -EINVAL;
6369 			setoperation_mode(state, OM_DVBT);
6370 			break;
6371 		default:
6372 			return -EINVAL;
6373 		}
6374 	}
6375 
6376 	fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6377 	start(state, 0, IF);
6378 
6379 	/* After set_frontend, stats aren't available */
6380 	p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6381 	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6382 	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6383 	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6384 	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6385 	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6386 	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6387 	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6388 
6389 	/* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6390 
6391 	return 0;
6392 }
6393 
6394 static int get_strength(struct drxk_state *state, u64 *strength)
6395 {
6396 	int status;
6397 	struct s_cfg_agc   rf_agc, if_agc;
6398 	u32          total_gain  = 0;
6399 	u32          atten      = 0;
6400 	u32          agc_range   = 0;
6401 	u16            scu_lvl  = 0;
6402 	u16            scu_coc  = 0;
6403 	/* FIXME: those are part of the tuner presets */
6404 	u16 tuner_rf_gain         = 50; /* Default value on az6007 driver */
6405 	u16 tuner_if_gain         = 40; /* Default value on az6007 driver */
6406 
6407 	*strength = 0;
6408 
6409 	if (is_dvbt(state)) {
6410 		rf_agc = state->m_dvbt_rf_agc_cfg;
6411 		if_agc = state->m_dvbt_if_agc_cfg;
6412 	} else if (is_qam(state)) {
6413 		rf_agc = state->m_qam_rf_agc_cfg;
6414 		if_agc = state->m_qam_if_agc_cfg;
6415 	} else {
6416 		rf_agc = state->m_atv_rf_agc_cfg;
6417 		if_agc = state->m_atv_if_agc_cfg;
6418 	}
6419 
6420 	if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6421 		/* SCU output_level */
6422 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6423 		if (status < 0)
6424 			return status;
6425 
6426 		/* SCU c.o.c. */
6427 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6428 		if (status < 0)
6429 			return status;
6430 
6431 		if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6432 			rf_agc.output_level = scu_lvl + scu_coc;
6433 		else
6434 			rf_agc.output_level = 0xffff;
6435 
6436 		/* Take RF gain into account */
6437 		total_gain += tuner_rf_gain;
6438 
6439 		/* clip output value */
6440 		if (rf_agc.output_level < rf_agc.min_output_level)
6441 			rf_agc.output_level = rf_agc.min_output_level;
6442 		if (rf_agc.output_level > rf_agc.max_output_level)
6443 			rf_agc.output_level = rf_agc.max_output_level;
6444 
6445 		agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6446 		if (agc_range > 0) {
6447 			atten += 100UL *
6448 				((u32)(tuner_rf_gain)) *
6449 				((u32)(rf_agc.output_level - rf_agc.min_output_level))
6450 				/ agc_range;
6451 		}
6452 	}
6453 
6454 	if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6455 		status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6456 				&if_agc.output_level);
6457 		if (status < 0)
6458 			return status;
6459 
6460 		status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6461 				&if_agc.top);
6462 		if (status < 0)
6463 			return status;
6464 
6465 		/* Take IF gain into account */
6466 		total_gain += (u32) tuner_if_gain;
6467 
6468 		/* clip output value */
6469 		if (if_agc.output_level < if_agc.min_output_level)
6470 			if_agc.output_level = if_agc.min_output_level;
6471 		if (if_agc.output_level > if_agc.max_output_level)
6472 			if_agc.output_level = if_agc.max_output_level;
6473 
6474 		agc_range  = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6475 		if (agc_range > 0) {
6476 			atten += 100UL *
6477 				((u32)(tuner_if_gain)) *
6478 				((u32)(if_agc.output_level - if_agc.min_output_level))
6479 				/ agc_range;
6480 		}
6481 	}
6482 
6483 	/*
6484 	 * Convert to 0..65535 scale.
6485 	 * If it can't be measured (AGC is disabled), just show 100%.
6486 	 */
6487 	if (total_gain > 0)
6488 		*strength = (65535UL * atten / total_gain / 100);
6489 	else
6490 		*strength = 65535;
6491 
6492 	return 0;
6493 }
6494 
6495 static int drxk_get_stats(struct dvb_frontend *fe)
6496 {
6497 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6498 	struct drxk_state *state = fe->demodulator_priv;
6499 	int status;
6500 	u32 stat;
6501 	u16 reg16;
6502 	u32 post_bit_count;
6503 	u32 post_bit_err_count;
6504 	u32 post_bit_error_scale;
6505 	u32 pre_bit_err_count;
6506 	u32 pre_bit_count;
6507 	u32 pkt_count;
6508 	u32 pkt_error_count;
6509 	s32 cnr;
6510 
6511 	if (state->m_drxk_state == DRXK_NO_DEV)
6512 		return -ENODEV;
6513 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6514 		return -EAGAIN;
6515 
6516 	/* get status */
6517 	state->fe_status = 0;
6518 	get_lock_status(state, &stat);
6519 	if (stat == MPEG_LOCK)
6520 		state->fe_status |= 0x1f;
6521 	if (stat == FEC_LOCK)
6522 		state->fe_status |= 0x0f;
6523 	if (stat == DEMOD_LOCK)
6524 		state->fe_status |= 0x07;
6525 
6526 	/*
6527 	 * Estimate signal strength from AGC
6528 	 */
6529 	get_strength(state, &c->strength.stat[0].uvalue);
6530 	c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6531 
6532 
6533 	if (stat >= DEMOD_LOCK) {
6534 		get_signal_to_noise(state, &cnr);
6535 		c->cnr.stat[0].svalue = cnr * 100;
6536 		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6537 	} else {
6538 		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6539 	}
6540 
6541 	if (stat < FEC_LOCK) {
6542 		c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6543 		c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6544 		c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6545 		c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6546 		c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6547 		c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6548 		return 0;
6549 	}
6550 
6551 	/* Get post BER */
6552 
6553 	/* BER measurement is valid if at least FEC lock is achieved */
6554 
6555 	/*
6556 	 * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6557 	 * written to set nr of symbols or bits over which to measure
6558 	 * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6559 	 */
6560 
6561 	/* Read registers for post/preViterbi BER calculation */
6562 	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);
6563 	if (status < 0)
6564 		goto error;
6565 	pre_bit_err_count = reg16;
6566 
6567 	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);
6568 	if (status < 0)
6569 		goto error;
6570 	pre_bit_count = reg16;
6571 
6572 	/* Number of bit-errors */
6573 	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);
6574 	if (status < 0)
6575 		goto error;
6576 	post_bit_err_count = reg16;
6577 
6578 	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);
6579 	if (status < 0)
6580 		goto error;
6581 	post_bit_error_scale = reg16;
6582 
6583 	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);
6584 	if (status < 0)
6585 		goto error;
6586 	pkt_count = reg16;
6587 
6588 	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);
6589 	if (status < 0)
6590 		goto error;
6591 	pkt_error_count = reg16;
6592 	write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6593 
6594 	post_bit_err_count *= post_bit_error_scale;
6595 
6596 	post_bit_count = pkt_count * 204 * 8;
6597 
6598 	/* Store the results */
6599 	c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6600 	c->block_error.stat[0].uvalue += pkt_error_count;
6601 	c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6602 	c->block_count.stat[0].uvalue += pkt_count;
6603 
6604 	c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6605 	c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6606 	c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6607 	c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6608 
6609 	c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6610 	c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6611 	c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6612 	c->post_bit_count.stat[0].uvalue += post_bit_count;
6613 
6614 error:
6615 	return status;
6616 }
6617 
6618 
6619 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6620 {
6621 	struct drxk_state *state = fe->demodulator_priv;
6622 	int rc;
6623 
6624 	dprintk(1, "\n");
6625 
6626 	rc = drxk_get_stats(fe);
6627 	if (rc < 0)
6628 		return rc;
6629 
6630 	*status = state->fe_status;
6631 
6632 	return 0;
6633 }
6634 
6635 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6636 				     u16 *strength)
6637 {
6638 	struct drxk_state *state = fe->demodulator_priv;
6639 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6640 
6641 	dprintk(1, "\n");
6642 
6643 	if (state->m_drxk_state == DRXK_NO_DEV)
6644 		return -ENODEV;
6645 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6646 		return -EAGAIN;
6647 
6648 	*strength = c->strength.stat[0].uvalue;
6649 	return 0;
6650 }
6651 
6652 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6653 {
6654 	struct drxk_state *state = fe->demodulator_priv;
6655 	s32 snr2;
6656 
6657 	dprintk(1, "\n");
6658 
6659 	if (state->m_drxk_state == DRXK_NO_DEV)
6660 		return -ENODEV;
6661 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6662 		return -EAGAIN;
6663 
6664 	get_signal_to_noise(state, &snr2);
6665 
6666 	/* No negative SNR, clip to zero */
6667 	if (snr2 < 0)
6668 		snr2 = 0;
6669 	*snr = snr2 & 0xffff;
6670 	return 0;
6671 }
6672 
6673 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6674 {
6675 	struct drxk_state *state = fe->demodulator_priv;
6676 	u16 err;
6677 
6678 	dprintk(1, "\n");
6679 
6680 	if (state->m_drxk_state == DRXK_NO_DEV)
6681 		return -ENODEV;
6682 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6683 		return -EAGAIN;
6684 
6685 	dvbtqam_get_acc_pkt_err(state, &err);
6686 	*ucblocks = (u32) err;
6687 	return 0;
6688 }
6689 
6690 static int drxk_get_tune_settings(struct dvb_frontend *fe,
6691 				  struct dvb_frontend_tune_settings *sets)
6692 {
6693 	struct drxk_state *state = fe->demodulator_priv;
6694 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6695 
6696 	dprintk(1, "\n");
6697 
6698 	if (state->m_drxk_state == DRXK_NO_DEV)
6699 		return -ENODEV;
6700 	if (state->m_drxk_state == DRXK_UNINITIALIZED)
6701 		return -EAGAIN;
6702 
6703 	switch (p->delivery_system) {
6704 	case SYS_DVBC_ANNEX_A:
6705 	case SYS_DVBC_ANNEX_C:
6706 	case SYS_DVBT:
6707 		sets->min_delay_ms = 3000;
6708 		sets->max_drift = 0;
6709 		sets->step_size = 0;
6710 		return 0;
6711 	default:
6712 		return -EINVAL;
6713 	}
6714 }
6715 
6716 static const struct dvb_frontend_ops drxk_ops = {
6717 	/* .delsys will be filled dynamically */
6718 	.info = {
6719 		.name = "DRXK",
6720 		.frequency_min_hz =  47 * MHz,
6721 		.frequency_max_hz = 865 * MHz,
6722 		 /* For DVB-C */
6723 		.symbol_rate_min =   870000,
6724 		.symbol_rate_max = 11700000,
6725 		/* For DVB-T */
6726 		.frequency_stepsize_hz = 166667,
6727 
6728 		.caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6729 			FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6730 			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6731 			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6732 			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6733 			FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6734 	},
6735 
6736 	.release = drxk_release,
6737 	.sleep = drxk_sleep,
6738 	.i2c_gate_ctrl = drxk_gate_ctrl,
6739 
6740 	.set_frontend = drxk_set_parameters,
6741 	.get_tune_settings = drxk_get_tune_settings,
6742 
6743 	.read_status = drxk_read_status,
6744 	.read_signal_strength = drxk_read_signal_strength,
6745 	.read_snr = drxk_read_snr,
6746 	.read_ucblocks = drxk_read_ucblocks,
6747 };
6748 
6749 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6750 				 struct i2c_adapter *i2c)
6751 {
6752 	struct dtv_frontend_properties *p;
6753 	struct drxk_state *state = NULL;
6754 	u8 adr = config->adr;
6755 	int status;
6756 
6757 	dprintk(1, "\n");
6758 	state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6759 	if (!state)
6760 		return NULL;
6761 
6762 	state->i2c = i2c;
6763 	state->demod_address = adr;
6764 	state->single_master = config->single_master;
6765 	state->microcode_name = config->microcode_name;
6766 	state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6767 	state->no_i2c_bridge = config->no_i2c_bridge;
6768 	state->antenna_gpio = config->antenna_gpio;
6769 	state->antenna_dvbt = config->antenna_dvbt;
6770 	state->m_chunk_size = config->chunk_size;
6771 	state->enable_merr_cfg = config->enable_merr_cfg;
6772 
6773 	if (config->dynamic_clk) {
6774 		state->m_dvbt_static_clk = false;
6775 		state->m_dvbc_static_clk = false;
6776 	} else {
6777 		state->m_dvbt_static_clk = true;
6778 		state->m_dvbc_static_clk = true;
6779 	}
6780 
6781 
6782 	if (config->mpeg_out_clk_strength)
6783 		state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6784 	else
6785 		state->m_ts_clockk_strength = 0x06;
6786 
6787 	if (config->parallel_ts)
6788 		state->m_enable_parallel = true;
6789 	else
6790 		state->m_enable_parallel = false;
6791 
6792 	/* NOTE: as more UIO bits will be used, add them to the mask */
6793 	state->uio_mask = config->antenna_gpio;
6794 
6795 	/* Default gpio to DVB-C */
6796 	if (!state->antenna_dvbt && state->antenna_gpio)
6797 		state->m_gpio |= state->antenna_gpio;
6798 	else
6799 		state->m_gpio &= ~state->antenna_gpio;
6800 
6801 	mutex_init(&state->mutex);
6802 
6803 	memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6804 	state->frontend.demodulator_priv = state;
6805 
6806 	init_state(state);
6807 
6808 	/* Load firmware and initialize DRX-K */
6809 	if (state->microcode_name) {
6810 		const struct firmware *fw = NULL;
6811 
6812 		status = request_firmware(&fw, state->microcode_name,
6813 					  state->i2c->dev.parent);
6814 		if (status < 0)
6815 			fw = NULL;
6816 		load_firmware_cb(fw, state);
6817 	} else if (init_drxk(state) < 0)
6818 		goto error;
6819 
6820 
6821 	/* Initialize stats */
6822 	p = &state->frontend.dtv_property_cache;
6823 	p->strength.len = 1;
6824 	p->cnr.len = 1;
6825 	p->block_error.len = 1;
6826 	p->block_count.len = 1;
6827 	p->pre_bit_error.len = 1;
6828 	p->pre_bit_count.len = 1;
6829 	p->post_bit_error.len = 1;
6830 	p->post_bit_count.len = 1;
6831 
6832 	p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6833 	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6834 	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6835 	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6836 	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6837 	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6838 	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6839 	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6840 
6841 	pr_info("frontend initialized.\n");
6842 	return &state->frontend;
6843 
6844 error:
6845 	pr_err("not found\n");
6846 	kfree(state);
6847 	return NULL;
6848 }
6849 EXPORT_SYMBOL(drxk_attach);
6850 
6851 MODULE_DESCRIPTION("DRX-K driver");
6852 MODULE_AUTHOR("Ralph Metzler");
6853 MODULE_LICENSE("GPL");
6854