1 /* 2 * drx3973d_map_firm.h 3 * 4 * Copyright (C) 2006-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 20 * 02110-1301, USA 21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html 22 */ 23 24 #ifndef __DRX3973D_MAP__H__ 25 #define __DRX3973D_MAP__H__ 26 27 /* 28 * Note: originally, this file contained 12000+ lines of data 29 * Probably a few lines for every firwmare assembler instruction. However, 30 * only a few defines were actually used. So, removed all uneeded lines. 31 * If ever needed, the other lines can be easily obtained via git history. 32 */ 33 34 #define HI_COMM_EXEC__A 0x400000 35 #define HI_COMM_MB__A 0x400002 36 #define HI_CT_REG_COMM_STATE__A 0x410001 37 #define HI_RA_RAM_SRV_RES__A 0x420031 38 #define HI_RA_RAM_SRV_CMD__A 0x420032 39 #define HI_RA_RAM_SRV_CMD_RESET 0x2 40 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 41 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 42 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 43 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 44 #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 45 #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 46 #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 47 #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 48 #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 49 #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 50 #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 51 #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 52 #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 53 #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 54 #define HI_RA_RAM_USR_BEGIN__A 0x420040 55 #define HI_IF_RAM_TRP_BPT0__AX 0x430000 56 #define HI_IF_RAM_USR_BEGIN__A 0x430200 57 #define SC_COMM_EXEC__A 0x800000 58 #define SC_COMM_EXEC_CTL_STOP 0x0 59 #define SC_COMM_STATE__A 0x800001 60 #define SC_RA_RAM_PARAM0__A 0x820040 61 #define SC_RA_RAM_PARAM1__A 0x820041 62 #define SC_RA_RAM_CMD_ADDR__A 0x820042 63 #define SC_RA_RAM_CMD__A 0x820043 64 #define SC_RA_RAM_CMD_PROC_START 0x1 65 #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 66 #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 67 #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 68 #define SC_RA_RAM_LOCKTRACK_MIN 0x1 69 #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 70 #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 71 #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 72 #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 73 #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 74 #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC 75 #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 76 #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 77 #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 78 #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 79 #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 80 #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 81 #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 82 #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 83 #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 84 #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 85 #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 86 #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 87 #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 88 #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 89 #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 90 #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 91 #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 92 #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 93 #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 94 #define SC_RA_RAM_LOCK__A 0x82004B 95 #define SC_RA_RAM_LOCK_DEMOD__M 0x1 96 #define SC_RA_RAM_LOCK_FEC__M 0x2 97 #define SC_RA_RAM_LOCK_MPEG__M 0x4 98 #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C 99 #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 100 #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 101 #define SC_RA_RAM_CONFIG__A 0x820050 102 #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 103 #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 104 #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 105 #define SC_RA_RAM_IF_SAVE__AX 0x82008E 106 #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 107 #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 108 #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 109 #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 110 #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 111 #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 112 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 113 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 114 #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 115 #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 116 #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 117 #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 118 #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 119 #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 120 #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 121 #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 122 #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 123 #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 124 #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 125 #define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 126 #define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 127 #define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 128 #define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 129 #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 130 #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 131 #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 132 #define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 133 #define SC_RA_RAM_BAND__A 0x8200EC 134 #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 135 #define SC_RA_RAM_LC_ABS_2K__PRE 0x1F 136 #define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 137 #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F 138 #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 139 #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 140 #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB 141 #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 142 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF 143 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 144 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E 145 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 146 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A 147 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 148 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB 149 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 150 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F 151 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 152 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 153 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 154 #define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 155 #define SC_RA_RAM_PROC_LOCKTRACK 0x0 156 #define FE_COMM_EXEC__A 0xC00000 157 #define FE_AD_REG_COMM_EXEC__A 0xC10000 158 #define FE_AD_REG_FDB_IN__A 0xC10012 159 #define FE_AD_REG_PD__A 0xC10013 160 #define FE_AD_REG_INVEXT__A 0xC10014 161 #define FE_AD_REG_CLKNEG__A 0xC10015 162 #define FE_AG_REG_COMM_EXEC__A 0xC20000 163 #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 164 #define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 165 #define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 166 #define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 167 #define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 168 #define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 169 #define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 170 #define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 171 #define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 172 #define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 173 #define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 174 #define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 175 #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 176 #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 177 #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 178 #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 179 #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 180 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 181 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 182 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 183 #define FE_AG_REG_AG_PWD__A 0xC20015 184 #define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 185 #define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 186 #define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 187 #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 188 #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 189 #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 190 #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 191 #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 192 #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 193 #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 194 #define FE_AG_REG_EGC_SET_LVL__M 0x1FF 195 #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 196 #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 197 #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 198 #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 199 #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 200 #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B 201 #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 202 #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D 203 #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 204 #define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 205 #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF 206 #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 207 #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 208 #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 209 #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 210 #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 211 #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF 212 #define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 213 #define FE_AG_REG_IND_WIN__A 0xC2003C 214 #define FE_AG_REG_IND_THD_LOL__A 0xC2003D 215 #define FE_AG_REG_IND_THD_HIL__A 0xC2003E 216 #define FE_AG_REG_IND_DEL__A 0xC2003F 217 #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 218 #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 219 #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 220 #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 221 #define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 222 #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 223 #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 224 #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 225 #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 226 #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 227 #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 228 #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 229 #define FE_AG_REG_PDC_MAX__A 0xC2004C 230 #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 231 #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 232 #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 233 #define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 234 #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 235 #define FE_AG_REG_TGC_SET_LVL__M 0x3F 236 #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 237 #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 238 #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 239 #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 240 #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 241 #define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 242 #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 243 #define FE_AG_REG_FGM_WRI__A 0xC20061 244 #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 245 #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 246 #define FE_FS_REG_COMM_EXEC__A 0xC30000 247 #define FE_FS_REG_ADD_INC_LOP__A 0xC30010 248 #define FE_FD_REG_COMM_EXEC__A 0xC40000 249 #define FE_FD_REG_SCL__A 0xC40010 250 #define FE_FD_REG_MAX_LEV__A 0xC40011 251 #define FE_FD_REG_NR__A 0xC40012 252 #define FE_FD_REG_MEAS_VAL__A 0xC40014 253 #define FE_IF_REG_COMM_EXEC__A 0xC50000 254 #define FE_IF_REG_INCR0__A 0xC50010 255 #define FE_IF_REG_INCR0__W 16 256 #define FE_IF_REG_INCR0__M 0xFFFF 257 #define FE_IF_REG_INCR1__A 0xC50011 258 #define FE_IF_REG_INCR1__M 0xFF 259 #define FE_CF_REG_COMM_EXEC__A 0xC60000 260 #define FE_CF_REG_SCL__A 0xC60010 261 #define FE_CF_REG_MAX_LEV__A 0xC60011 262 #define FE_CF_REG_NR__A 0xC60012 263 #define FE_CF_REG_IMP_VAL__A 0xC60013 264 #define FE_CF_REG_MEAS_VAL__A 0xC60014 265 #define FE_CU_REG_COMM_EXEC__A 0xC70000 266 #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 267 #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 268 #define FT_COMM_EXEC__A 0x1000000 269 #define FT_REG_COMM_EXEC__A 0x1010000 270 #define CP_COMM_EXEC__A 0x1400000 271 #define CP_REG_COMM_EXEC__A 0x1410000 272 #define CP_REG_INTERVAL__A 0x1410011 273 #define CP_REG_BR_SPL_OFFSET__A 0x1410023 274 #define CP_REG_BR_STR_DEL__A 0x1410024 275 #define CP_REG_RT_ANG_INC0__A 0x1410030 276 #define CP_REG_RT_ANG_INC1__A 0x1410031 277 #define CP_REG_RT_DETECT_ENA__A 0x1410032 278 #define CP_REG_RT_DETECT_TRH__A 0x1410033 279 #define CP_REG_RT_EXP_MARG__A 0x141003E 280 #define CP_REG_AC_NEXP_OFFS__A 0x1410040 281 #define CP_REG_AC_AVER_POW__A 0x1410041 282 #define CP_REG_AC_MAX_POW__A 0x1410042 283 #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 284 #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 285 #define CP_REG_AC_AMP_MODE__A 0x1410047 286 #define CP_REG_AC_AMP_FIX__A 0x1410048 287 #define CP_REG_AC_ANG_MODE__A 0x141004A 288 #define CE_COMM_EXEC__A 0x1800000 289 #define CE_REG_COMM_EXEC__A 0x1810000 290 #define CE_REG_TAPSET__A 0x1810011 291 #define CE_REG_AVG_POW__A 0x1810012 292 #define CE_REG_MAX_POW__A 0x1810013 293 #define CE_REG_ATT__A 0x1810014 294 #define CE_REG_NRED__A 0x1810015 295 #define CE_REG_NE_ERR_SELECT__A 0x1810043 296 #define CE_REG_NE_TD_CAL__A 0x1810044 297 #define CE_REG_NE_MIXAVG__A 0x1810046 298 #define CE_REG_NE_NUPD_OFS__A 0x1810047 299 #define CE_REG_PE_NEXP_OFFS__A 0x1810050 300 #define CE_REG_PE_TIMESHIFT__A 0x1810051 301 #define CE_REG_TP_A0_TAP_NEW__A 0x1810064 302 #define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 303 #define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 304 #define CE_REG_TP_A1_TAP_NEW__A 0x1810068 305 #define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 306 #define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 307 #define CE_REG_TI_NEXP_OFFS__A 0x1810070 308 #define CE_REG_FI_SHT_INCR__A 0x1810090 309 #define CE_REG_FI_EXP_NORM__A 0x1810091 310 #define CE_REG_IR_INPUTSEL__A 0x18100A0 311 #define CE_REG_IR_STARTPOS__A 0x18100A1 312 #define CE_REG_IR_NEXP_THRES__A 0x18100A2 313 #define CE_REG_FR_TREAL00__A 0x1820010 314 #define CE_REG_FR_TIMAG00__A 0x1820011 315 #define CE_REG_FR_TREAL01__A 0x1820012 316 #define CE_REG_FR_TIMAG01__A 0x1820013 317 #define CE_REG_FR_TREAL02__A 0x1820014 318 #define CE_REG_FR_TIMAG02__A 0x1820015 319 #define CE_REG_FR_TREAL03__A 0x1820016 320 #define CE_REG_FR_TIMAG03__A 0x1820017 321 #define CE_REG_FR_TREAL04__A 0x1820018 322 #define CE_REG_FR_TIMAG04__A 0x1820019 323 #define CE_REG_FR_TREAL05__A 0x182001A 324 #define CE_REG_FR_TIMAG05__A 0x182001B 325 #define CE_REG_FR_TREAL06__A 0x182001C 326 #define CE_REG_FR_TIMAG06__A 0x182001D 327 #define CE_REG_FR_TREAL07__A 0x182001E 328 #define CE_REG_FR_TIMAG07__A 0x182001F 329 #define CE_REG_FR_TREAL08__A 0x1820020 330 #define CE_REG_FR_TIMAG08__A 0x1820021 331 #define CE_REG_FR_TREAL09__A 0x1820022 332 #define CE_REG_FR_TIMAG09__A 0x1820023 333 #define CE_REG_FR_TREAL10__A 0x1820024 334 #define CE_REG_FR_TIMAG10__A 0x1820025 335 #define CE_REG_FR_TREAL11__A 0x1820026 336 #define CE_REG_FR_TIMAG11__A 0x1820027 337 #define CE_REG_FR_MID_TAP__A 0x1820028 338 #define CE_REG_FR_SQS_G00__A 0x1820029 339 #define CE_REG_FR_SQS_G01__A 0x182002A 340 #define CE_REG_FR_SQS_G02__A 0x182002B 341 #define CE_REG_FR_SQS_G03__A 0x182002C 342 #define CE_REG_FR_SQS_G04__A 0x182002D 343 #define CE_REG_FR_SQS_G05__A 0x182002E 344 #define CE_REG_FR_SQS_G06__A 0x182002F 345 #define CE_REG_FR_SQS_G07__A 0x1820030 346 #define CE_REG_FR_SQS_G08__A 0x1820031 347 #define CE_REG_FR_SQS_G09__A 0x1820032 348 #define CE_REG_FR_SQS_G10__A 0x1820033 349 #define CE_REG_FR_SQS_G11__A 0x1820034 350 #define CE_REG_FR_SQS_G12__A 0x1820035 351 #define CE_REG_FR_RIO_G00__A 0x1820036 352 #define CE_REG_FR_RIO_G01__A 0x1820037 353 #define CE_REG_FR_RIO_G02__A 0x1820038 354 #define CE_REG_FR_RIO_G03__A 0x1820039 355 #define CE_REG_FR_RIO_G04__A 0x182003A 356 #define CE_REG_FR_RIO_G05__A 0x182003B 357 #define CE_REG_FR_RIO_G06__A 0x182003C 358 #define CE_REG_FR_RIO_G07__A 0x182003D 359 #define CE_REG_FR_RIO_G08__A 0x182003E 360 #define CE_REG_FR_RIO_G09__A 0x182003F 361 #define CE_REG_FR_RIO_G10__A 0x1820040 362 #define CE_REG_FR_MODE__A 0x1820041 363 #define CE_REG_FR_SQS_TRH__A 0x1820042 364 #define CE_REG_FR_RIO_GAIN__A 0x1820043 365 #define CE_REG_FR_BYPASS__A 0x1820044 366 #define CE_REG_FR_PM_SET__A 0x1820045 367 #define CE_REG_FR_ERR_SH__A 0x1820046 368 #define CE_REG_FR_MAN_SH__A 0x1820047 369 #define CE_REG_FR_TAP_SH__A 0x1820048 370 #define EQ_COMM_EXEC__A 0x1C00000 371 #define EQ_REG_COMM_EXEC__A 0x1C10000 372 #define EQ_REG_COMM_MB__A 0x1C10002 373 #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 374 #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 375 #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 376 #define EQ_REG_SN_CEGAIN__A 0x1C1002A 377 #define EQ_REG_SN_OFFSET__A 0x1C1002B 378 #define EQ_REG_RC_SEL_CAR__A 0x1C10032 379 #define EQ_REG_RC_SEL_CAR_INIT 0x0 380 #define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 381 #define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 382 #define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 383 #define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 384 #define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 385 #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 386 #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 387 #define EQ_REG_OT_CONST__A 0x1C10046 388 #define EQ_REG_OT_ALPHA__A 0x1C10047 389 #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 390 #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 391 #define EQ_REG_OT_CSI_STEP__A 0x1C1004A 392 #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 393 #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 394 #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 395 #define EC_SB_REG_COMM_EXEC__A 0x2010000 396 #define EC_SB_REG_TR_MODE__A 0x2010010 397 #define EC_SB_REG_TR_MODE_8K 0x0 398 #define EC_SB_REG_TR_MODE_2K 0x1 399 #define EC_SB_REG_CONST__A 0x2010011 400 #define EC_SB_REG_CONST_QPSK 0x0 401 #define EC_SB_REG_CONST_16QAM 0x1 402 #define EC_SB_REG_CONST_64QAM 0x2 403 #define EC_SB_REG_ALPHA__A 0x2010012 404 #define EC_SB_REG_PRIOR__A 0x2010013 405 #define EC_SB_REG_PRIOR_HI 0x0 406 #define EC_SB_REG_PRIOR_LO 0x1 407 #define EC_SB_REG_CSI_HI__A 0x2010014 408 #define EC_SB_REG_CSI_LO__A 0x2010015 409 #define EC_SB_REG_SMB_TGL__A 0x2010016 410 #define EC_SB_REG_SNR_HI__A 0x2010017 411 #define EC_SB_REG_SNR_MID__A 0x2010018 412 #define EC_SB_REG_SNR_LO__A 0x2010019 413 #define EC_SB_REG_SCALE_MSB__A 0x201001A 414 #define EC_SB_REG_SCALE_BIT2__A 0x201001B 415 #define EC_SB_REG_SCALE_LSB__A 0x201001C 416 #define EC_SB_REG_CSI_OFS__A 0x201001D 417 #define EC_VD_REG_COMM_EXEC__A 0x2090000 418 #define EC_VD_REG_FORCE__A 0x2090010 419 #define EC_VD_REG_SET_CODERATE__A 0x2090011 420 #define EC_VD_REG_SET_CODERATE_C1_2 0x0 421 #define EC_VD_REG_SET_CODERATE_C2_3 0x1 422 #define EC_VD_REG_SET_CODERATE_C3_4 0x2 423 #define EC_VD_REG_SET_CODERATE_C5_6 0x3 424 #define EC_VD_REG_SET_CODERATE_C7_8 0x4 425 #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 426 #define EC_VD_REG_RLK_ENA__A 0x2090014 427 #define EC_OD_REG_COMM_EXEC__A 0x2110000 428 #define EC_OD_REG_SYNC__A 0x2110010 429 #define EC_OD_DEINT_RAM__A 0x2120000 430 #define EC_RS_REG_COMM_EXEC__A 0x2130000 431 #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 432 #define EC_RS_REG_VAL__A 0x2130011 433 #define EC_RS_REG_VAL_PCK 0x1 434 #define EC_RS_EC_RAM__A 0x2140000 435 #define EC_OC_REG_COMM_EXEC__A 0x2150000 436 #define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 437 #define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 438 #define EC_OC_REG_COMM_INT_STA__A 0x2150007 439 #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 440 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 441 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 442 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 443 #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 444 #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 445 #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 446 #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 447 #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 448 #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 449 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 450 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 451 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 452 #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 453 #define EC_OC_REG_OC_MPG_SIO__M 0xFFF 454 #define EC_OC_REG_OC_MON_SIO__A 0x2150013 455 #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 456 #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 457 #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 458 #define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 459 #define EC_OC_REG_TMD_TOP_MODE__A 0x215001D 460 #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E 461 #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F 462 #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 463 #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 464 #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 465 #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 466 #define EC_OC_REG_RCN_MODE__A 0x2150027 467 #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 468 #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 469 #define EC_OC_REG_RCN_CST_LOP__A 0x215002A 470 #define EC_OC_REG_RCN_CST_HIP__A 0x215002B 471 #define EC_OC_REG_RCN_SET_LVL__A 0x215002C 472 #define EC_OC_REG_RCN_GAI_LVL__A 0x215002D 473 #define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 474 #define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 475 #define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 476 #define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 477 #define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 478 #define EC_OC_REG_OCR_MPG_UOS__M 0xFFF 479 #define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 480 #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 481 #define EC_OC_REG_OCR_MON_UOS__A 0x2150039 482 #define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 483 #define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 484 #define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 485 #define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 486 #define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 487 #define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 488 #define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 489 #define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 490 #define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 491 #define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 492 #define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 493 #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 494 #define EC_OC_REG_OCR_MON_WRI__A 0x215003A 495 #define EC_OC_REG_OCR_MON_WRI_INIT 0x0 496 #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 497 #define CC_REG_OSC_MODE__A 0x2410010 498 #define CC_REG_OSC_MODE_M20 0x1 499 #define CC_REG_PLL_MODE__A 0x2410011 500 #define CC_REG_PLL_MODE_BYPASS_PLL 0x1 501 #define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 502 #define CC_REG_REF_DIVIDE__A 0x2410012 503 #define CC_REG_PWD_MODE__A 0x2410015 504 #define CC_REG_PWD_MODE_DOWN_PLL 0x2 505 #define CC_REG_UPDATE__A 0x2410017 506 #define CC_REG_UPDATE_KEY 0x3973 507 #define CC_REG_JTAGID_L__A 0x2410019 508 #define LC_COMM_EXEC__A 0x2800000 509 #define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 510 #define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 511 #define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 512 #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 513 #define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 514 #define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 515 #define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 516 #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 517 #define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 518 #define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 519 #define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 520 #define B_HI_COMM_EXEC__A 0x400000 521 #define B_HI_COMM_MB__A 0x400002 522 #define B_HI_CT_REG_COMM_STATE__A 0x410001 523 #define B_HI_RA_RAM_SRV_RES__A 0x420031 524 #define B_HI_RA_RAM_SRV_CMD__A 0x420032 525 #define B_HI_RA_RAM_SRV_CMD_RESET 0x2 526 #define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 527 #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 528 #define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 529 #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 530 #define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 531 #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 532 #define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 533 #define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 534 #define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 535 #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 536 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 537 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 538 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 539 #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 540 #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 541 #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 542 #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 543 #define B_SC_COMM_EXEC__A 0x800000 544 #define B_SC_COMM_EXEC_CTL_STOP 0x0 545 #define B_SC_COMM_STATE__A 0x800001 546 #define B_SC_RA_RAM_PARAM0__A 0x820040 547 #define B_SC_RA_RAM_PARAM1__A 0x820041 548 #define B_SC_RA_RAM_CMD_ADDR__A 0x820042 549 #define B_SC_RA_RAM_CMD__A 0x820043 550 #define B_SC_RA_RAM_CMD_PROC_START 0x1 551 #define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 552 #define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 553 #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 554 #define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 555 #define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 556 #define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 557 #define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 558 #define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 559 #define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 560 #define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC 561 #define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 562 #define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 563 #define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 564 #define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 565 #define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 566 #define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 567 #define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 568 #define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 569 #define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 570 #define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 571 #define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 572 #define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 573 #define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 574 #define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 575 #define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 576 #define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 577 #define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 578 #define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 579 #define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 580 #define B_SC_RA_RAM_LOCK__A 0x82004B 581 #define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 582 #define B_SC_RA_RAM_LOCK_FEC__M 0x2 583 #define B_SC_RA_RAM_LOCK_MPEG__M 0x4 584 #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C 585 #define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 586 #define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 587 #define B_SC_RA_RAM_CONFIG__A 0x820050 588 #define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 589 #define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 590 #define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 591 #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 592 #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 593 #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D 594 #define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E 595 #define B_SC_RA_RAM_IF_SAVE__AX 0x82008E 596 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 597 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 598 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A 599 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B 600 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C 601 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D 602 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E 603 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F 604 #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 605 #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 606 #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 607 #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 608 #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 609 #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 610 #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 611 #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 612 #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 613 #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 614 #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 615 #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 616 #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 617 #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 618 #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 619 #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 620 #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 621 #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 622 #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 623 #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 624 #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 625 #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 626 #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 627 #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 628 #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 629 #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 630 #define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 631 #define B_SC_RA_RAM_BAND__A 0x8200EC 632 #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 633 #define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F 634 #define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 635 #define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F 636 #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 637 #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 638 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 639 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 640 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D 641 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 642 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D 643 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 644 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 645 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 646 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 647 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 648 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A 649 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 650 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB 651 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 652 #define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 653 #define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 654 #define B_FE_COMM_EXEC__A 0xC00000 655 #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 656 #define B_FE_AD_REG_FDB_IN__A 0xC10012 657 #define B_FE_AD_REG_PD__A 0xC10013 658 #define B_FE_AD_REG_INVEXT__A 0xC10014 659 #define B_FE_AD_REG_CLKNEG__A 0xC10015 660 #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 661 #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 662 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 663 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 664 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 665 #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 666 #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 667 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 668 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 669 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 670 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 671 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 672 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 673 #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 674 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 675 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 676 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 677 #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 678 #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 679 #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 680 #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 681 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 682 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 683 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 684 #define B_FE_AG_REG_AG_PWD__A 0xC20015 685 #define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 686 #define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 687 #define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 688 #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 689 #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 690 #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 691 #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 692 #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 693 #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 694 #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 695 #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF 696 #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 697 #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 698 #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 699 #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 700 #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 701 #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B 702 #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 703 #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D 704 #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 705 #define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 706 #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF 707 #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 708 #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 709 #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 710 #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 711 #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 712 #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF 713 #define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 714 #define B_FE_AG_REG_IND_WIN__A 0xC2003C 715 #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D 716 #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E 717 #define B_FE_AG_REG_IND_DEL__A 0xC2003F 718 #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 719 #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 720 #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 721 #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 722 #define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 723 #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 724 #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 725 #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 726 #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 727 #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 728 #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 729 #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 730 #define B_FE_AG_REG_PDC_MAX__A 0xC2004C 731 #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 732 #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 733 #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 734 #define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 735 #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 736 #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F 737 #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 738 #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 739 #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 740 #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 741 #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 742 #define B_FE_AG_REG_FGM_WRI__A 0xC20061 743 #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 744 #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 745 #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 746 #define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 747 #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 748 #define B_FE_FD_REG_SCL__A 0xC40010 749 #define B_FE_FD_REG_MAX_LEV__A 0xC40011 750 #define B_FE_FD_REG_NR__A 0xC40012 751 #define B_FE_FD_REG_MEAS_VAL__A 0xC40014 752 #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 753 #define B_FE_IF_REG_INCR0__A 0xC50010 754 #define B_FE_IF_REG_INCR0__W 16 755 #define B_FE_IF_REG_INCR0__M 0xFFFF 756 #define B_FE_IF_REG_INCR1__A 0xC50011 757 #define B_FE_IF_REG_INCR1__M 0xFF 758 #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 759 #define B_FE_CF_REG_SCL__A 0xC60010 760 #define B_FE_CF_REG_MAX_LEV__A 0xC60011 761 #define B_FE_CF_REG_NR__A 0xC60012 762 #define B_FE_CF_REG_IMP_VAL__A 0xC60013 763 #define B_FE_CF_REG_MEAS_VAL__A 0xC60014 764 #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 765 #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 766 #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 767 #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 768 #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 769 #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 770 #define B_FT_COMM_EXEC__A 0x1000000 771 #define B_FT_REG_COMM_EXEC__A 0x1010000 772 #define B_CP_COMM_EXEC__A 0x1400000 773 #define B_CP_REG_COMM_EXEC__A 0x1410000 774 #define B_CP_REG_INTERVAL__A 0x1410011 775 #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 776 #define B_CP_REG_BR_STR_DEL__A 0x1410024 777 #define B_CP_REG_RT_ANG_INC0__A 0x1410030 778 #define B_CP_REG_RT_ANG_INC1__A 0x1410031 779 #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 780 #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 781 #define B_CP_REG_AC_AVER_POW__A 0x1410041 782 #define B_CP_REG_AC_MAX_POW__A 0x1410042 783 #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 784 #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 785 #define B_CP_REG_AC_AMP_MODE__A 0x1410047 786 #define B_CP_REG_AC_AMP_FIX__A 0x1410048 787 #define B_CP_REG_AC_ANG_MODE__A 0x141004A 788 #define B_CE_COMM_EXEC__A 0x1800000 789 #define B_CE_REG_COMM_EXEC__A 0x1810000 790 #define B_CE_REG_TAPSET__A 0x1810011 791 #define B_CE_REG_AVG_POW__A 0x1810012 792 #define B_CE_REG_MAX_POW__A 0x1810013 793 #define B_CE_REG_ATT__A 0x1810014 794 #define B_CE_REG_NRED__A 0x1810015 795 #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 796 #define B_CE_REG_NE_TD_CAL__A 0x1810044 797 #define B_CE_REG_NE_MIXAVG__A 0x1810046 798 #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 799 #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 800 #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 801 #define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 802 #define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 803 #define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 804 #define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 805 #define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 806 #define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 807 #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 808 #define B_CE_REG_FI_SHT_INCR__A 0x1810090 809 #define B_CE_REG_FI_EXP_NORM__A 0x1810091 810 #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 811 #define B_CE_REG_IR_STARTPOS__A 0x18100A1 812 #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 813 #define B_CE_REG_FR_TREAL00__A 0x1820010 814 #define B_CE_REG_FR_TIMAG00__A 0x1820011 815 #define B_CE_REG_FR_TREAL01__A 0x1820012 816 #define B_CE_REG_FR_TIMAG01__A 0x1820013 817 #define B_CE_REG_FR_TREAL02__A 0x1820014 818 #define B_CE_REG_FR_TIMAG02__A 0x1820015 819 #define B_CE_REG_FR_TREAL03__A 0x1820016 820 #define B_CE_REG_FR_TIMAG03__A 0x1820017 821 #define B_CE_REG_FR_TREAL04__A 0x1820018 822 #define B_CE_REG_FR_TIMAG04__A 0x1820019 823 #define B_CE_REG_FR_TREAL05__A 0x182001A 824 #define B_CE_REG_FR_TIMAG05__A 0x182001B 825 #define B_CE_REG_FR_TREAL06__A 0x182001C 826 #define B_CE_REG_FR_TIMAG06__A 0x182001D 827 #define B_CE_REG_FR_TREAL07__A 0x182001E 828 #define B_CE_REG_FR_TIMAG07__A 0x182001F 829 #define B_CE_REG_FR_TREAL08__A 0x1820020 830 #define B_CE_REG_FR_TIMAG08__A 0x1820021 831 #define B_CE_REG_FR_TREAL09__A 0x1820022 832 #define B_CE_REG_FR_TIMAG09__A 0x1820023 833 #define B_CE_REG_FR_TREAL10__A 0x1820024 834 #define B_CE_REG_FR_TIMAG10__A 0x1820025 835 #define B_CE_REG_FR_TREAL11__A 0x1820026 836 #define B_CE_REG_FR_TIMAG11__A 0x1820027 837 #define B_CE_REG_FR_MID_TAP__A 0x1820028 838 #define B_CE_REG_FR_SQS_G00__A 0x1820029 839 #define B_CE_REG_FR_SQS_G01__A 0x182002A 840 #define B_CE_REG_FR_SQS_G02__A 0x182002B 841 #define B_CE_REG_FR_SQS_G03__A 0x182002C 842 #define B_CE_REG_FR_SQS_G04__A 0x182002D 843 #define B_CE_REG_FR_SQS_G05__A 0x182002E 844 #define B_CE_REG_FR_SQS_G06__A 0x182002F 845 #define B_CE_REG_FR_SQS_G07__A 0x1820030 846 #define B_CE_REG_FR_SQS_G08__A 0x1820031 847 #define B_CE_REG_FR_SQS_G09__A 0x1820032 848 #define B_CE_REG_FR_SQS_G10__A 0x1820033 849 #define B_CE_REG_FR_SQS_G11__A 0x1820034 850 #define B_CE_REG_FR_SQS_G12__A 0x1820035 851 #define B_CE_REG_FR_RIO_G00__A 0x1820036 852 #define B_CE_REG_FR_RIO_G01__A 0x1820037 853 #define B_CE_REG_FR_RIO_G02__A 0x1820038 854 #define B_CE_REG_FR_RIO_G03__A 0x1820039 855 #define B_CE_REG_FR_RIO_G04__A 0x182003A 856 #define B_CE_REG_FR_RIO_G05__A 0x182003B 857 #define B_CE_REG_FR_RIO_G06__A 0x182003C 858 #define B_CE_REG_FR_RIO_G07__A 0x182003D 859 #define B_CE_REG_FR_RIO_G08__A 0x182003E 860 #define B_CE_REG_FR_RIO_G09__A 0x182003F 861 #define B_CE_REG_FR_RIO_G10__A 0x1820040 862 #define B_CE_REG_FR_MODE__A 0x1820041 863 #define B_CE_REG_FR_SQS_TRH__A 0x1820042 864 #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 865 #define B_CE_REG_FR_BYPASS__A 0x1820044 866 #define B_CE_REG_FR_PM_SET__A 0x1820045 867 #define B_CE_REG_FR_ERR_SH__A 0x1820046 868 #define B_CE_REG_FR_MAN_SH__A 0x1820047 869 #define B_CE_REG_FR_TAP_SH__A 0x1820048 870 #define B_EQ_COMM_EXEC__A 0x1C00000 871 #define B_EQ_REG_COMM_EXEC__A 0x1C10000 872 #define B_EQ_REG_COMM_MB__A 0x1C10002 873 #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 874 #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 875 #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 876 #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A 877 #define B_EQ_REG_SN_OFFSET__A 0x1C1002B 878 #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 879 #define B_EQ_REG_RC_SEL_CAR_INIT 0x2 880 #define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 881 #define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 882 #define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 883 #define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 884 #define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 885 #define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 886 #define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 887 #define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 888 #define B_EQ_REG_OT_CONST__A 0x1C10046 889 #define B_EQ_REG_OT_ALPHA__A 0x1C10047 890 #define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 891 #define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 892 #define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A 893 #define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 894 #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 895 #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 896 #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 897 #define B_EC_SB_REG_TR_MODE__A 0x2010010 898 #define B_EC_SB_REG_TR_MODE_8K 0x0 899 #define B_EC_SB_REG_TR_MODE_2K 0x1 900 #define B_EC_SB_REG_CONST__A 0x2010011 901 #define B_EC_SB_REG_CONST_QPSK 0x0 902 #define B_EC_SB_REG_CONST_16QAM 0x1 903 #define B_EC_SB_REG_CONST_64QAM 0x2 904 #define B_EC_SB_REG_ALPHA__A 0x2010012 905 #define B_EC_SB_REG_PRIOR__A 0x2010013 906 #define B_EC_SB_REG_PRIOR_HI 0x0 907 #define B_EC_SB_REG_PRIOR_LO 0x1 908 #define B_EC_SB_REG_CSI_HI__A 0x2010014 909 #define B_EC_SB_REG_CSI_LO__A 0x2010015 910 #define B_EC_SB_REG_SMB_TGL__A 0x2010016 911 #define B_EC_SB_REG_SNR_HI__A 0x2010017 912 #define B_EC_SB_REG_SNR_MID__A 0x2010018 913 #define B_EC_SB_REG_SNR_LO__A 0x2010019 914 #define B_EC_SB_REG_SCALE_MSB__A 0x201001A 915 #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B 916 #define B_EC_SB_REG_SCALE_LSB__A 0x201001C 917 #define B_EC_SB_REG_CSI_OFS0__A 0x201001D 918 #define B_EC_SB_REG_CSI_OFS1__A 0x201001E 919 #define B_EC_SB_REG_CSI_OFS2__A 0x201001F 920 #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 921 #define B_EC_VD_REG_FORCE__A 0x2090010 922 #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 923 #define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 924 #define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 925 #define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 926 #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 927 #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 928 #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 929 #define B_EC_VD_REG_RLK_ENA__A 0x2090014 930 #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 931 #define B_EC_OD_REG_SYNC__A 0x2110664 932 #define B_EC_OD_DEINT_RAM__A 0x2120000 933 #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 934 #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 935 #define B_EC_RS_REG_VAL__A 0x2130011 936 #define B_EC_RS_REG_VAL_PCK 0x1 937 #define B_EC_RS_EC_RAM__A 0x2140000 938 #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 939 #define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 940 #define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 941 #define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 942 #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 943 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 944 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 945 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 946 #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 947 #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 948 #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 949 #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 950 #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 951 #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 952 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 953 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 954 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 955 #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 956 #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF 957 #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 958 #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 959 #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 960 #define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 961 #define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D 962 #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E 963 #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F 964 #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 965 #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 966 #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 967 #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 968 #define B_EC_OC_REG_RCN_MODE__A 0x2150027 969 #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 970 #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 971 #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A 972 #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B 973 #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C 974 #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D 975 #define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 976 #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 977 #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 978 #define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 979 #define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 980 #define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF 981 #define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 982 #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 983 #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 984 #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 985 #define B_EC_OC_REG_DTO_PER__A 0x2150048 986 #define B_EC_OC_REG_DTO_BUR__A 0x2150049 987 #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A 988 #define B_CC_REG_OSC_MODE__A 0x2410010 989 #define B_CC_REG_OSC_MODE_M20 0x1 990 #define B_CC_REG_PLL_MODE__A 0x2410011 991 #define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 992 #define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 993 #define B_CC_REG_REF_DIVIDE__A 0x2410012 994 #define B_CC_REG_PWD_MODE__A 0x2410015 995 #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 996 #define B_CC_REG_UPDATE__A 0x2410017 997 #define B_CC_REG_UPDATE_KEY 0x3973 998 #define B_CC_REG_JTAGID_L__A 0x2410019 999 #define B_CC_REG_DIVERSITY__A 0x241001B 1000 #define B_LC_COMM_EXEC__A 0x2800000 1001 #define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 1002 #define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 1003 #define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 1004 #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 1005 #define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 1006 #define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 1007 #define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 1008 #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 1009 #define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 1010 #define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 1011 #define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 1012 1013 #endif 1014