1 /* 2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1 3 * 4 * Copyright (C) 2003-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/i2c.h> 27 #include <asm/div64.h> 28 29 #include "dvb_frontend.h" 30 #include "drxd.h" 31 #include "drxd_firm.h" 32 33 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw" 34 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw" 35 36 #define CHUNK_SIZE 48 37 38 #define DRX_I2C_RMW 0x10 39 #define DRX_I2C_BROADCAST 0x20 40 #define DRX_I2C_CLEARCRC 0x80 41 #define DRX_I2C_SINGLE_MASTER 0xC0 42 #define DRX_I2C_MODEFLAGS 0xC0 43 #define DRX_I2C_FLAGS 0xF0 44 45 #define DEFAULT_LOCK_TIMEOUT 1100 46 47 #define DRX_CHANNEL_AUTO 0 48 #define DRX_CHANNEL_HIGH 1 49 #define DRX_CHANNEL_LOW 2 50 51 #define DRX_LOCK_MPEG 1 52 #define DRX_LOCK_FEC 2 53 #define DRX_LOCK_DEMOD 4 54 55 /****************************************************************************/ 56 57 enum CSCDState { 58 CSCD_INIT = 0, 59 CSCD_SET, 60 CSCD_SAVED 61 }; 62 63 enum CDrxdState { 64 DRXD_UNINITIALIZED = 0, 65 DRXD_STOPPED, 66 DRXD_STARTED 67 }; 68 69 enum AGC_CTRL_MODE { 70 AGC_CTRL_AUTO = 0, 71 AGC_CTRL_USER, 72 AGC_CTRL_OFF 73 }; 74 75 enum OperationMode { 76 OM_Default, 77 OM_DVBT_Diversity_Front, 78 OM_DVBT_Diversity_End 79 }; 80 81 struct SCfgAgc { 82 enum AGC_CTRL_MODE ctrlMode; 83 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 84 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 85 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 86 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 87 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ 88 89 u16 R1; 90 u16 R2; 91 u16 R3; 92 }; 93 94 struct SNoiseCal { 95 int cpOpt; 96 short cpNexpOfs; 97 short tdCal2k; 98 short tdCal8k; 99 }; 100 101 enum app_env { 102 APPENV_STATIC = 0, 103 APPENV_PORTABLE = 1, 104 APPENV_MOBILE = 2 105 }; 106 107 enum EIFFilter { 108 IFFILTER_SAW = 0, 109 IFFILTER_DISCRETE = 1 110 }; 111 112 struct drxd_state { 113 struct dvb_frontend frontend; 114 struct dvb_frontend_ops ops; 115 struct dtv_frontend_properties props; 116 117 const struct firmware *fw; 118 struct device *dev; 119 120 struct i2c_adapter *i2c; 121 void *priv; 122 struct drxd_config config; 123 124 int i2c_access; 125 int init_done; 126 struct mutex mutex; 127 128 u8 chip_adr; 129 u16 hi_cfg_timing_div; 130 u16 hi_cfg_bridge_delay; 131 u16 hi_cfg_wakeup_key; 132 u16 hi_cfg_ctrl; 133 134 u16 intermediate_freq; 135 u16 osc_clock_freq; 136 137 enum CSCDState cscd_state; 138 enum CDrxdState drxd_state; 139 140 u16 sys_clock_freq; 141 s16 osc_clock_deviation; 142 u16 expected_sys_clock_freq; 143 144 u16 insert_rs_byte; 145 u16 enable_parallel; 146 147 int operation_mode; 148 149 struct SCfgAgc if_agc_cfg; 150 struct SCfgAgc rf_agc_cfg; 151 152 struct SNoiseCal noise_cal; 153 154 u32 fe_fs_add_incr; 155 u32 org_fe_fs_add_incr; 156 u16 current_fe_if_incr; 157 158 u16 m_FeAgRegAgPwd; 159 u16 m_FeAgRegAgAgcSio; 160 161 u16 m_EcOcRegOcModeLop; 162 u16 m_EcOcRegSncSncLvl; 163 u8 *m_InitAtomicRead; 164 u8 *m_HiI2cPatch; 165 166 u8 *m_ResetCEFR; 167 u8 *m_InitFE_1; 168 u8 *m_InitFE_2; 169 u8 *m_InitCP; 170 u8 *m_InitCE; 171 u8 *m_InitEQ; 172 u8 *m_InitSC; 173 u8 *m_InitEC; 174 u8 *m_ResetECRAM; 175 u8 *m_InitDiversityFront; 176 u8 *m_InitDiversityEnd; 177 u8 *m_DisableDiversity; 178 u8 *m_StartDiversityFront; 179 u8 *m_StartDiversityEnd; 180 181 u8 *m_DiversityDelay8MHZ; 182 u8 *m_DiversityDelay6MHZ; 183 184 u8 *microcode; 185 u32 microcode_length; 186 187 int type_A; 188 int PGA; 189 int diversity; 190 int tuner_mirrors; 191 192 enum app_env app_env_default; 193 enum app_env app_env_diversity; 194 195 }; 196 197 /****************************************************************************/ 198 /* I2C **********************************************************************/ 199 /****************************************************************************/ 200 201 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len) 202 { 203 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len }; 204 205 if (i2c_transfer(adap, &msg, 1) != 1) 206 return -1; 207 return 0; 208 } 209 210 static int i2c_read(struct i2c_adapter *adap, 211 u8 adr, u8 *msg, int len, u8 *answ, int alen) 212 { 213 struct i2c_msg msgs[2] = { 214 { 215 .addr = adr, .flags = 0, 216 .buf = msg, .len = len 217 }, { 218 .addr = adr, .flags = I2C_M_RD, 219 .buf = answ, .len = alen 220 } 221 }; 222 if (i2c_transfer(adap, msgs, 2) != 2) 223 return -1; 224 return 0; 225 } 226 227 static inline u32 MulDiv32(u32 a, u32 b, u32 c) 228 { 229 u64 tmp64; 230 231 tmp64 = (u64)a * (u64)b; 232 do_div(tmp64, c); 233 234 return (u32) tmp64; 235 } 236 237 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) 238 { 239 u8 adr = state->config.demod_address; 240 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, 241 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 242 }; 243 u8 mm2[2]; 244 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) 245 return -1; 246 if (data) 247 *data = mm2[0] | (mm2[1] << 8); 248 return mm2[0] | (mm2[1] << 8); 249 } 250 251 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) 252 { 253 u8 adr = state->config.demod_address; 254 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, 255 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 256 }; 257 u8 mm2[4]; 258 259 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) 260 return -1; 261 if (data) 262 *data = 263 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24); 264 return 0; 265 } 266 267 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) 268 { 269 u8 adr = state->config.demod_address; 270 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, 271 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, 272 data & 0xff, (data >> 8) & 0xff 273 }; 274 275 if (i2c_write(state->i2c, adr, mm, 6) < 0) 276 return -1; 277 return 0; 278 } 279 280 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) 281 { 282 u8 adr = state->config.demod_address; 283 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, 284 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, 285 data & 0xff, (data >> 8) & 0xff, 286 (data >> 16) & 0xff, (data >> 24) & 0xff 287 }; 288 289 if (i2c_write(state->i2c, adr, mm, 8) < 0) 290 return -1; 291 return 0; 292 } 293 294 static int write_chunk(struct drxd_state *state, 295 u32 reg, u8 *data, u32 len, u8 flags) 296 { 297 u8 adr = state->config.demod_address; 298 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, 299 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 300 }; 301 int i; 302 303 for (i = 0; i < len; i++) 304 mm[4 + i] = data[i]; 305 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { 306 printk(KERN_ERR "error in write_chunk\n"); 307 return -1; 308 } 309 return 0; 310 } 311 312 static int WriteBlock(struct drxd_state *state, 313 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) 314 { 315 while (BlockSize > 0) { 316 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; 317 318 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) 319 return -1; 320 pBlock += Chunk; 321 Address += (Chunk >> 1); 322 BlockSize -= Chunk; 323 } 324 return 0; 325 } 326 327 static int WriteTable(struct drxd_state *state, u8 * pTable) 328 { 329 int status = 0; 330 331 if (pTable == NULL) 332 return 0; 333 334 while (!status) { 335 u16 Length; 336 u32 Address = pTable[0] | (pTable[1] << 8) | 337 (pTable[2] << 16) | (pTable[3] << 24); 338 339 if (Address == 0xFFFFFFFF) 340 break; 341 pTable += sizeof(u32); 342 343 Length = pTable[0] | (pTable[1] << 8); 344 pTable += sizeof(u16); 345 if (!Length) 346 break; 347 status = WriteBlock(state, Address, Length * 2, pTable, 0); 348 pTable += (Length * 2); 349 } 350 return status; 351 } 352 353 /****************************************************************************/ 354 /****************************************************************************/ 355 /****************************************************************************/ 356 357 static int ResetCEFR(struct drxd_state *state) 358 { 359 return WriteTable(state, state->m_ResetCEFR); 360 } 361 362 static int InitCP(struct drxd_state *state) 363 { 364 return WriteTable(state, state->m_InitCP); 365 } 366 367 static int InitCE(struct drxd_state *state) 368 { 369 int status; 370 enum app_env AppEnv = state->app_env_default; 371 372 do { 373 status = WriteTable(state, state->m_InitCE); 374 if (status < 0) 375 break; 376 377 if (state->operation_mode == OM_DVBT_Diversity_Front || 378 state->operation_mode == OM_DVBT_Diversity_End) { 379 AppEnv = state->app_env_diversity; 380 } 381 if (AppEnv == APPENV_STATIC) { 382 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); 383 if (status < 0) 384 break; 385 } else if (AppEnv == APPENV_PORTABLE) { 386 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); 387 if (status < 0) 388 break; 389 } else if (AppEnv == APPENV_MOBILE && state->type_A) { 390 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); 391 if (status < 0) 392 break; 393 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { 394 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); 395 if (status < 0) 396 break; 397 } 398 399 /* start ce */ 400 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); 401 if (status < 0) 402 break; 403 } while (0); 404 return status; 405 } 406 407 static int StopOC(struct drxd_state *state) 408 { 409 int status = 0; 410 u16 ocSyncLvl = 0; 411 u16 ocModeLop = state->m_EcOcRegOcModeLop; 412 u16 dtoIncLop = 0; 413 u16 dtoIncHip = 0; 414 415 do { 416 /* Store output configuration */ 417 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); 418 if (status < 0) 419 break; 420 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */ 421 state->m_EcOcRegSncSncLvl = ocSyncLvl; 422 /* m_EcOcRegOcModeLop = ocModeLop; */ 423 424 /* Flush FIFO (byte-boundary) at fixed rate */ 425 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); 426 if (status < 0) 427 break; 428 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); 429 if (status < 0) 430 break; 431 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); 432 if (status < 0) 433 break; 434 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); 435 if (status < 0) 436 break; 437 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); 438 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; 439 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); 440 if (status < 0) 441 break; 442 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); 443 if (status < 0) 444 break; 445 446 msleep(1); 447 /* Output pins to '0' */ 448 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); 449 if (status < 0) 450 break; 451 452 /* Force the OC out of sync */ 453 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); 454 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); 455 if (status < 0) 456 break; 457 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); 458 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; 459 ocModeLop |= 0x2; /* Magically-out-of-sync */ 460 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); 461 if (status < 0) 462 break; 463 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); 464 if (status < 0) 465 break; 466 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); 467 if (status < 0) 468 break; 469 } while (0); 470 471 return status; 472 } 473 474 static int StartOC(struct drxd_state *state) 475 { 476 int status = 0; 477 478 do { 479 /* Stop OC */ 480 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); 481 if (status < 0) 482 break; 483 484 /* Restore output configuration */ 485 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); 486 if (status < 0) 487 break; 488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); 489 if (status < 0) 490 break; 491 492 /* Output pins active again */ 493 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); 494 if (status < 0) 495 break; 496 497 /* Start OC */ 498 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); 499 if (status < 0) 500 break; 501 } while (0); 502 return status; 503 } 504 505 static int InitEQ(struct drxd_state *state) 506 { 507 return WriteTable(state, state->m_InitEQ); 508 } 509 510 static int InitEC(struct drxd_state *state) 511 { 512 return WriteTable(state, state->m_InitEC); 513 } 514 515 static int InitSC(struct drxd_state *state) 516 { 517 return WriteTable(state, state->m_InitSC); 518 } 519 520 static int InitAtomicRead(struct drxd_state *state) 521 { 522 return WriteTable(state, state->m_InitAtomicRead); 523 } 524 525 static int CorrectSysClockDeviation(struct drxd_state *state); 526 527 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) 528 { 529 u16 ScRaRamLock = 0; 530 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M | 531 SC_RA_RAM_LOCK_FEC__M | 532 SC_RA_RAM_LOCK_DEMOD__M); 533 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M | 534 SC_RA_RAM_LOCK_DEMOD__M); 535 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M; 536 537 int status; 538 539 *pLockStatus = 0; 540 541 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); 542 if (status < 0) { 543 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); 544 return status; 545 } 546 547 if (state->drxd_state != DRXD_STARTED) 548 return 0; 549 550 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { 551 *pLockStatus |= DRX_LOCK_MPEG; 552 CorrectSysClockDeviation(state); 553 } 554 555 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) 556 *pLockStatus |= DRX_LOCK_FEC; 557 558 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) 559 *pLockStatus |= DRX_LOCK_DEMOD; 560 return 0; 561 } 562 563 /****************************************************************************/ 564 565 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) 566 { 567 int status; 568 569 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) 570 return -1; 571 572 if (cfg->ctrlMode == AGC_CTRL_USER) { 573 do { 574 u16 FeAgRegPm1AgcWri; 575 u16 FeAgRegAgModeLop; 576 577 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); 578 if (status < 0) 579 break; 580 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 581 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; 582 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); 583 if (status < 0) 584 break; 585 586 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & 587 FE_AG_REG_PM1_AGC_WRI__M); 588 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); 589 if (status < 0) 590 break; 591 } while (0); 592 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { 593 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || 594 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || 595 ((cfg->speed) > DRXD_FE_CTRL_MAX) || 596 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) 597 ) 598 return -1; 599 do { 600 u16 FeAgRegAgModeLop; 601 u16 FeAgRegEgcSetLvl; 602 u16 slope, offset; 603 604 /* == Mode == */ 605 606 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); 607 if (status < 0) 608 break; 609 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 610 FeAgRegAgModeLop |= 611 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; 612 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); 613 if (status < 0) 614 break; 615 616 /* == Settle level == */ 617 618 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & 619 FE_AG_REG_EGC_SET_LVL__M); 620 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); 621 if (status < 0) 622 break; 623 624 /* == Min/Max == */ 625 626 slope = (u16) ((cfg->maxOutputLevel - 627 cfg->minOutputLevel) / 2); 628 offset = (u16) ((cfg->maxOutputLevel + 629 cfg->minOutputLevel) / 2 - 511); 630 631 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); 632 if (status < 0) 633 break; 634 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); 635 if (status < 0) 636 break; 637 638 /* == Speed == */ 639 { 640 const u16 maxRur = 8; 641 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 }; 642 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16, 643 17, 18, 18, 19, 644 20, 21, 22, 23, 645 24, 26, 27, 28, 646 29, 31 647 }; 648 649 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) / 650 (maxRur + 1); 651 u16 fineSpeed = (u16) (cfg->speed - 652 ((cfg->speed / 653 fineSteps) * 654 fineSteps)); 655 u16 invRurCount = (u16) (cfg->speed / 656 fineSteps); 657 u16 rurCount; 658 if (invRurCount > maxRur) { 659 rurCount = 0; 660 fineSpeed += fineSteps; 661 } else { 662 rurCount = maxRur - invRurCount; 663 } 664 665 /* 666 fastInc = default * 667 (2^(fineSpeed/fineSteps)) 668 => range[default...2*default> 669 slowInc = default * 670 (2^(fineSpeed/fineSteps)) 671 */ 672 { 673 u16 fastIncrDec = 674 fastIncrDecLUT[fineSpeed / 675 ((fineSteps / 676 (14 + 1)) + 1)]; 677 u16 slowIncrDec = 678 slowIncrDecLUT[fineSpeed / 679 (fineSteps / 680 (3 + 1))]; 681 682 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); 683 if (status < 0) 684 break; 685 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); 686 if (status < 0) 687 break; 688 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); 689 if (status < 0) 690 break; 691 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); 692 if (status < 0) 693 break; 694 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); 695 if (status < 0) 696 break; 697 } 698 } 699 } while (0); 700 701 } else { 702 /* No OFF mode for IF control */ 703 return -1; 704 } 705 return status; 706 } 707 708 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) 709 { 710 int status = 0; 711 712 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) 713 return -1; 714 715 if (cfg->ctrlMode == AGC_CTRL_USER) { 716 do { 717 u16 AgModeLop = 0; 718 u16 level = (cfg->outputLevel); 719 720 if (level == DRXD_FE_CTRL_MAX) 721 level++; 722 723 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); 724 if (status < 0) 725 break; 726 727 /*==== Mode ====*/ 728 729 /* Powerdown PD2, WRI source */ 730 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 731 state->m_FeAgRegAgPwd |= 732 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 733 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); 734 if (status < 0) 735 break; 736 737 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 738 if (status < 0) 739 break; 740 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 741 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 742 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 743 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 744 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 745 if (status < 0) 746 break; 747 748 /* enable AGC2 pin */ 749 { 750 u16 FeAgRegAgAgcSio = 0; 751 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 752 if (status < 0) 753 break; 754 FeAgRegAgAgcSio &= 755 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 756 FeAgRegAgAgcSio |= 757 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 758 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 759 if (status < 0) 760 break; 761 } 762 763 } while (0); 764 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { 765 u16 AgModeLop = 0; 766 767 do { 768 u16 level; 769 /* Automatic control */ 770 /* Powerup PD2, AGC2 as output, TGC source */ 771 (state->m_FeAgRegAgPwd) &= 772 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 773 (state->m_FeAgRegAgPwd) |= 774 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 775 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); 776 if (status < 0) 777 break; 778 779 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 780 if (status < 0) 781 break; 782 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 783 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 784 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 785 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC); 786 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 787 if (status < 0) 788 break; 789 /* Settle level */ 790 level = (((cfg->settleLevel) >> 4) & 791 FE_AG_REG_TGC_SET_LVL__M); 792 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); 793 if (status < 0) 794 break; 795 796 /* Min/max: don't care */ 797 798 /* Speed: TODO */ 799 800 /* enable AGC2 pin */ 801 { 802 u16 FeAgRegAgAgcSio = 0; 803 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 804 if (status < 0) 805 break; 806 FeAgRegAgAgcSio &= 807 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 808 FeAgRegAgAgcSio |= 809 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 810 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 811 if (status < 0) 812 break; 813 } 814 815 } while (0); 816 } else { 817 u16 AgModeLop = 0; 818 819 do { 820 /* No RF AGC control */ 821 /* Powerdown PD2, AGC2 as output, WRI source */ 822 (state->m_FeAgRegAgPwd) &= 823 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 824 (state->m_FeAgRegAgPwd) |= 825 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; 826 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); 827 if (status < 0) 828 break; 829 830 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 831 if (status < 0) 832 break; 833 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 834 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 835 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 836 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 837 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 838 if (status < 0) 839 break; 840 841 /* set FeAgRegAgAgcSio AGC2 (RF) as input */ 842 { 843 u16 FeAgRegAgAgcSio = 0; 844 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 845 if (status < 0) 846 break; 847 FeAgRegAgAgcSio &= 848 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 849 FeAgRegAgAgcSio |= 850 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; 851 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 852 if (status < 0) 853 break; 854 } 855 } while (0); 856 } 857 return status; 858 } 859 860 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) 861 { 862 int status = 0; 863 864 *pValue = 0; 865 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { 866 u16 Value; 867 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); 868 Value &= FE_AG_REG_GC1_AGC_DAT__M; 869 if (status >= 0) { 870 /* 3.3V 871 | 872 R1 873 | 874 Vin - R3 - * -- Vout 875 | 876 R2 877 | 878 GND 879 */ 880 u32 R1 = state->if_agc_cfg.R1; 881 u32 R2 = state->if_agc_cfg.R2; 882 u32 R3 = state->if_agc_cfg.R3; 883 884 u32 Vmax, Rpar, Vmin, Vout; 885 886 if (R2 == 0 && (R1 == 0 || R3 == 0)) 887 return 0; 888 889 Vmax = (3300 * R2) / (R1 + R2); 890 Rpar = (R2 * R3) / (R3 + R2); 891 Vmin = (3300 * Rpar) / (R1 + Rpar); 892 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024; 893 894 *pValue = Vout; 895 } 896 } 897 return status; 898 } 899 900 static int load_firmware(struct drxd_state *state, const char *fw_name) 901 { 902 const struct firmware *fw; 903 904 if (request_firmware(&fw, fw_name, state->dev) < 0) { 905 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name); 906 return -EIO; 907 } 908 909 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); 910 if (state->microcode == NULL) { 911 release_firmware(fw); 912 printk(KERN_ERR "drxd: firmware load failure: no memory\n"); 913 return -ENOMEM; 914 } 915 916 state->microcode_length = fw->size; 917 release_firmware(fw); 918 return 0; 919 } 920 921 static int DownloadMicrocode(struct drxd_state *state, 922 const u8 *pMCImage, u32 Length) 923 { 924 u8 *pSrc; 925 u32 Address; 926 u16 nBlocks; 927 u16 BlockSize; 928 u32 offset = 0; 929 int i, status = 0; 930 931 pSrc = (u8 *) pMCImage; 932 /* We're not using Flags */ 933 /* Flags = (pSrc[0] << 8) | pSrc[1]; */ 934 pSrc += sizeof(u16); 935 offset += sizeof(u16); 936 nBlocks = (pSrc[0] << 8) | pSrc[1]; 937 pSrc += sizeof(u16); 938 offset += sizeof(u16); 939 940 for (i = 0; i < nBlocks; i++) { 941 Address = (pSrc[0] << 24) | (pSrc[1] << 16) | 942 (pSrc[2] << 8) | pSrc[3]; 943 pSrc += sizeof(u32); 944 offset += sizeof(u32); 945 946 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); 947 pSrc += sizeof(u16); 948 offset += sizeof(u16); 949 950 /* We're not using Flags */ 951 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */ 952 pSrc += sizeof(u16); 953 offset += sizeof(u16); 954 955 /* We're not using BlockCRC */ 956 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */ 957 pSrc += sizeof(u16); 958 offset += sizeof(u16); 959 960 status = WriteBlock(state, Address, BlockSize, 961 pSrc, DRX_I2C_CLEARCRC); 962 if (status < 0) 963 break; 964 pSrc += BlockSize; 965 offset += BlockSize; 966 } 967 968 return status; 969 } 970 971 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) 972 { 973 u32 nrRetries = 0; 974 u16 waitCmd; 975 int status; 976 977 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); 978 if (status < 0) 979 return status; 980 981 do { 982 nrRetries += 1; 983 if (nrRetries > DRXD_MAX_RETRIES) { 984 status = -1; 985 break; 986 } 987 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); 988 } while (waitCmd != 0); 989 990 if (status >= 0) 991 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); 992 return status; 993 } 994 995 static int HI_CfgCommand(struct drxd_state *state) 996 { 997 int status = 0; 998 999 mutex_lock(&state->mutex); 1000 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1001 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); 1002 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); 1003 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); 1004 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); 1005 1006 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1007 1008 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == 1009 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) 1010 status = Write16(state, HI_RA_RAM_SRV_CMD__A, 1011 HI_RA_RAM_SRV_CMD_CONFIG, 0); 1012 else 1013 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); 1014 mutex_unlock(&state->mutex); 1015 return status; 1016 } 1017 1018 static int InitHI(struct drxd_state *state) 1019 { 1020 state->hi_cfg_wakeup_key = (state->chip_adr); 1021 /* port/bridge/power down ctrl */ 1022 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; 1023 return HI_CfgCommand(state); 1024 } 1025 1026 static int HI_ResetCommand(struct drxd_state *state) 1027 { 1028 int status; 1029 1030 mutex_lock(&state->mutex); 1031 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, 1032 HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1033 if (status == 0) 1034 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); 1035 mutex_unlock(&state->mutex); 1036 msleep(1); 1037 return status; 1038 } 1039 1040 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) 1041 { 1042 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); 1043 if (bEnableBridge) 1044 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; 1045 else 1046 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; 1047 1048 return HI_CfgCommand(state); 1049 } 1050 1051 #define HI_TR_WRITE 0x9 1052 #define HI_TR_READ 0xA 1053 #define HI_TR_READ_WRITE 0xB 1054 #define HI_TR_BROADCAST 0x4 1055 1056 #if 0 1057 static int AtomicReadBlock(struct drxd_state *state, 1058 u32 Addr, u16 DataSize, u8 *pData, u8 Flags) 1059 { 1060 int status; 1061 int i = 0; 1062 1063 /* Parameter check */ 1064 if ((!pData) || ((DataSize & 1) != 0)) 1065 return -1; 1066 1067 mutex_lock(&state->mutex); 1068 1069 do { 1070 /* Instruct HI to read n bytes */ 1071 /* TODO use proper names forthese egisters */ 1072 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0); 1073 if (status < 0) 1074 break; 1075 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0); 1076 if (status < 0) 1077 break; 1078 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0); 1079 if (status < 0) 1080 break; 1081 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0); 1082 if (status < 0) 1083 break; 1084 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0); 1085 if (status < 0) 1086 break; 1087 1088 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0); 1089 if (status < 0) 1090 break; 1091 1092 } while (0); 1093 1094 if (status >= 0) { 1095 for (i = 0; i < (DataSize / 2); i += 1) { 1096 u16 word; 1097 1098 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i), 1099 &word, 0); 1100 if (status < 0) 1101 break; 1102 pData[2 * i] = (u8) (word & 0xFF); 1103 pData[(2 * i) + 1] = (u8) (word >> 8); 1104 } 1105 } 1106 mutex_unlock(&state->mutex); 1107 return status; 1108 } 1109 1110 static int AtomicReadReg32(struct drxd_state *state, 1111 u32 Addr, u32 *pData, u8 Flags) 1112 { 1113 u8 buf[sizeof(u32)]; 1114 int status; 1115 1116 if (!pData) 1117 return -1; 1118 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags); 1119 *pData = (((u32) buf[0]) << 0) + 1120 (((u32) buf[1]) << 8) + 1121 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); 1122 return status; 1123 } 1124 #endif 1125 1126 static int StopAllProcessors(struct drxd_state *state) 1127 { 1128 return Write16(state, HI_COMM_EXEC__A, 1129 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST); 1130 } 1131 1132 static int EnableAndResetMB(struct drxd_state *state) 1133 { 1134 if (state->type_A) { 1135 /* disable? monitor bus observe @ EC_OC */ 1136 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); 1137 } 1138 1139 /* do inverse broadcast, followed by explicit write to HI */ 1140 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); 1141 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); 1142 return 0; 1143 } 1144 1145 static int InitCC(struct drxd_state *state) 1146 { 1147 if (state->osc_clock_freq == 0 || 1148 state->osc_clock_freq > 20000 || 1149 (state->osc_clock_freq % 4000) != 0) { 1150 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); 1151 return -1; 1152 } 1153 1154 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); 1155 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | 1156 CC_REG_PLL_MODE_PUMP_CUR_12, 0); 1157 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); 1158 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); 1159 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); 1160 1161 return 0; 1162 } 1163 1164 static int ResetECOD(struct drxd_state *state) 1165 { 1166 int status = 0; 1167 1168 if (state->type_A) 1169 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); 1170 else 1171 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); 1172 1173 if (!(status < 0)) 1174 status = WriteTable(state, state->m_ResetECRAM); 1175 if (!(status < 0)) 1176 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); 1177 return status; 1178 } 1179 1180 /* Configure PGA switch */ 1181 1182 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) 1183 { 1184 int status; 1185 u16 AgModeLop = 0; 1186 u16 AgModeHip = 0; 1187 do { 1188 if (pgaSwitch) { 1189 /* PGA on */ 1190 /* fine gain */ 1191 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 1192 if (status < 0) 1193 break; 1194 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1195 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; 1196 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 1197 if (status < 0) 1198 break; 1199 1200 /* coarse gain */ 1201 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); 1202 if (status < 0) 1203 break; 1204 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1205 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC; 1206 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); 1207 if (status < 0) 1208 break; 1209 1210 /* enable fine and coarse gain, enable AAF, 1211 no ext resistor */ 1212 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000); 1213 if (status < 0) 1214 break; 1215 } else { 1216 /* PGA off, bypass */ 1217 1218 /* fine gain */ 1219 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 1220 if (status < 0) 1221 break; 1222 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1223 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC; 1224 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 1225 if (status < 0) 1226 break; 1227 1228 /* coarse gain */ 1229 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); 1230 if (status < 0) 1231 break; 1232 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1233 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC; 1234 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); 1235 if (status < 0) 1236 break; 1237 1238 /* disable fine and coarse gain, enable AAF, 1239 no ext resistor */ 1240 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000); 1241 if (status < 0) 1242 break; 1243 } 1244 } while (0); 1245 return status; 1246 } 1247 1248 static int InitFE(struct drxd_state *state) 1249 { 1250 int status; 1251 1252 do { 1253 status = WriteTable(state, state->m_InitFE_1); 1254 if (status < 0) 1255 break; 1256 1257 if (state->type_A) { 1258 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, 1259 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1260 0); 1261 } else { 1262 if (state->PGA) 1263 status = SetCfgPga(state, 0); 1264 else 1265 status = 1266 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, 1267 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1268 0); 1269 } 1270 1271 if (status < 0) 1272 break; 1273 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); 1274 if (status < 0) 1275 break; 1276 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); 1277 if (status < 0) 1278 break; 1279 1280 status = WriteTable(state, state->m_InitFE_2); 1281 if (status < 0) 1282 break; 1283 1284 } while (0); 1285 1286 return status; 1287 } 1288 1289 static int InitFT(struct drxd_state *state) 1290 { 1291 /* 1292 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk 1293 SC stuff 1294 */ 1295 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); 1296 } 1297 1298 static int SC_WaitForReady(struct drxd_state *state) 1299 { 1300 u16 curCmd; 1301 int i; 1302 1303 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) { 1304 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); 1305 if (status == 0 || curCmd == 0) 1306 return status; 1307 } 1308 return -1; 1309 } 1310 1311 static int SC_SendCommand(struct drxd_state *state, u16 cmd) 1312 { 1313 int status = 0; 1314 u16 errCode; 1315 1316 Write16(state, SC_RA_RAM_CMD__A, cmd, 0); 1317 SC_WaitForReady(state); 1318 1319 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); 1320 1321 if (errCode == 0xFFFF) { 1322 printk(KERN_ERR "Command Error\n"); 1323 status = -1; 1324 } 1325 1326 return status; 1327 } 1328 1329 static int SC_ProcStartCommand(struct drxd_state *state, 1330 u16 subCmd, u16 param0, u16 param1) 1331 { 1332 int status = 0; 1333 u16 scExec; 1334 1335 mutex_lock(&state->mutex); 1336 do { 1337 Read16(state, SC_COMM_EXEC__A, &scExec, 0); 1338 if (scExec != 1) { 1339 status = -1; 1340 break; 1341 } 1342 SC_WaitForReady(state); 1343 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); 1344 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); 1345 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); 1346 1347 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); 1348 } while (0); 1349 mutex_unlock(&state->mutex); 1350 return status; 1351 } 1352 1353 static int SC_SetPrefParamCommand(struct drxd_state *state, 1354 u16 subCmd, u16 param0, u16 param1) 1355 { 1356 int status; 1357 1358 mutex_lock(&state->mutex); 1359 do { 1360 status = SC_WaitForReady(state); 1361 if (status < 0) 1362 break; 1363 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); 1364 if (status < 0) 1365 break; 1366 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); 1367 if (status < 0) 1368 break; 1369 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); 1370 if (status < 0) 1371 break; 1372 1373 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); 1374 if (status < 0) 1375 break; 1376 } while (0); 1377 mutex_unlock(&state->mutex); 1378 return status; 1379 } 1380 1381 #if 0 1382 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result) 1383 { 1384 int status = 0; 1385 1386 mutex_lock(&state->mutex); 1387 do { 1388 status = SC_WaitForReady(state); 1389 if (status < 0) 1390 break; 1391 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM); 1392 if (status < 0) 1393 break; 1394 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0); 1395 if (status < 0) 1396 break; 1397 } while (0); 1398 mutex_unlock(&state->mutex); 1399 return status; 1400 } 1401 #endif 1402 1403 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) 1404 { 1405 int status; 1406 1407 do { 1408 u16 EcOcRegIprInvMpg = 0; 1409 u16 EcOcRegOcModeLop = 0; 1410 u16 EcOcRegOcModeHip = 0; 1411 u16 EcOcRegOcMpgSio = 0; 1412 1413 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */ 1414 1415 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1416 if (bEnableOutput) { 1417 EcOcRegOcModeHip |= 1418 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; 1419 } else 1420 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1421 EcOcRegOcModeLop |= 1422 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1423 } else { 1424 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; 1425 1426 if (bEnableOutput) 1427 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M)); 1428 else 1429 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1430 1431 /* Don't Insert RS Byte */ 1432 if (state->insert_rs_byte) { 1433 EcOcRegOcModeLop &= 1434 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); 1435 EcOcRegOcModeHip &= 1436 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1437 EcOcRegOcModeHip |= 1438 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE; 1439 } else { 1440 EcOcRegOcModeLop |= 1441 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1442 EcOcRegOcModeHip &= 1443 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1444 EcOcRegOcModeHip |= 1445 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE; 1446 } 1447 1448 /* Mode = Parallel */ 1449 if (state->enable_parallel) 1450 EcOcRegOcModeLop &= 1451 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M)); 1452 else 1453 EcOcRegOcModeLop |= 1454 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL; 1455 } 1456 /* Invert Data */ 1457 /* EcOcRegIprInvMpg |= 0x00FF; */ 1458 EcOcRegIprInvMpg &= (~(0x00FF)); 1459 1460 /* Invert Error ( we don't use the pin ) */ 1461 /* EcOcRegIprInvMpg |= 0x0100; */ 1462 EcOcRegIprInvMpg &= (~(0x0100)); 1463 1464 /* Invert Start ( we don't use the pin ) */ 1465 /* EcOcRegIprInvMpg |= 0x0200; */ 1466 EcOcRegIprInvMpg &= (~(0x0200)); 1467 1468 /* Invert Valid ( we don't use the pin ) */ 1469 /* EcOcRegIprInvMpg |= 0x0400; */ 1470 EcOcRegIprInvMpg &= (~(0x0400)); 1471 1472 /* Invert Clock */ 1473 /* EcOcRegIprInvMpg |= 0x0800; */ 1474 EcOcRegIprInvMpg &= (~(0x0800)); 1475 1476 /* EcOcRegOcModeLop =0x05; */ 1477 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); 1478 if (status < 0) 1479 break; 1480 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); 1481 if (status < 0) 1482 break; 1483 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); 1484 if (status < 0) 1485 break; 1486 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); 1487 if (status < 0) 1488 break; 1489 } while (0); 1490 return status; 1491 } 1492 1493 static int SetDeviceTypeId(struct drxd_state *state) 1494 { 1495 int status = 0; 1496 u16 deviceId = 0; 1497 1498 do { 1499 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); 1500 if (status < 0) 1501 break; 1502 /* TODO: why twice? */ 1503 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); 1504 if (status < 0) 1505 break; 1506 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId); 1507 1508 state->type_A = 0; 1509 state->PGA = 0; 1510 state->diversity = 0; 1511 if (deviceId == 0) { /* on A2 only 3975 available */ 1512 state->type_A = 1; 1513 printk(KERN_INFO "DRX3975D-A2\n"); 1514 } else { 1515 deviceId >>= 12; 1516 printk(KERN_INFO "DRX397%dD-B1\n", deviceId); 1517 switch (deviceId) { 1518 case 4: 1519 state->diversity = 1; 1520 /* fall through */ 1521 case 3: 1522 case 7: 1523 state->PGA = 1; 1524 break; 1525 case 6: 1526 state->diversity = 1; 1527 /* fall through */ 1528 case 5: 1529 case 8: 1530 break; 1531 default: 1532 status = -1; 1533 break; 1534 } 1535 } 1536 } while (0); 1537 1538 if (status < 0) 1539 return status; 1540 1541 /* Init Table selection */ 1542 state->m_InitAtomicRead = DRXD_InitAtomicRead; 1543 state->m_InitSC = DRXD_InitSC; 1544 state->m_ResetECRAM = DRXD_ResetECRAM; 1545 if (state->type_A) { 1546 state->m_ResetCEFR = DRXD_ResetCEFR; 1547 state->m_InitFE_1 = DRXD_InitFEA2_1; 1548 state->m_InitFE_2 = DRXD_InitFEA2_2; 1549 state->m_InitCP = DRXD_InitCPA2; 1550 state->m_InitCE = DRXD_InitCEA2; 1551 state->m_InitEQ = DRXD_InitEQA2; 1552 state->m_InitEC = DRXD_InitECA2; 1553 if (load_firmware(state, DRX_FW_FILENAME_A2)) 1554 return -EIO; 1555 } else { 1556 state->m_ResetCEFR = NULL; 1557 state->m_InitFE_1 = DRXD_InitFEB1_1; 1558 state->m_InitFE_2 = DRXD_InitFEB1_2; 1559 state->m_InitCP = DRXD_InitCPB1; 1560 state->m_InitCE = DRXD_InitCEB1; 1561 state->m_InitEQ = DRXD_InitEQB1; 1562 state->m_InitEC = DRXD_InitECB1; 1563 if (load_firmware(state, DRX_FW_FILENAME_B1)) 1564 return -EIO; 1565 } 1566 if (state->diversity) { 1567 state->m_InitDiversityFront = DRXD_InitDiversityFront; 1568 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; 1569 state->m_DisableDiversity = DRXD_DisableDiversity; 1570 state->m_StartDiversityFront = DRXD_StartDiversityFront; 1571 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; 1572 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; 1573 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; 1574 } else { 1575 state->m_InitDiversityFront = NULL; 1576 state->m_InitDiversityEnd = NULL; 1577 state->m_DisableDiversity = NULL; 1578 state->m_StartDiversityFront = NULL; 1579 state->m_StartDiversityEnd = NULL; 1580 state->m_DiversityDelay8MHZ = NULL; 1581 state->m_DiversityDelay6MHZ = NULL; 1582 } 1583 1584 return status; 1585 } 1586 1587 static int CorrectSysClockDeviation(struct drxd_state *state) 1588 { 1589 int status; 1590 s32 incr = 0; 1591 s32 nomincr = 0; 1592 u32 bandwidth = 0; 1593 u32 sysClockInHz = 0; 1594 u32 sysClockFreq = 0; /* in kHz */ 1595 s16 oscClockDeviation; 1596 s16 Diff; 1597 1598 do { 1599 /* Retrieve bandwidth and incr, sanity check */ 1600 1601 /* These accesses should be AtomicReadReg32, but that 1602 causes trouble (at least for diversity */ 1603 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); 1604 if (status < 0) 1605 break; 1606 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); 1607 if (status < 0) 1608 break; 1609 1610 if (state->type_A) { 1611 if ((nomincr - incr < -500) || (nomincr - incr > 500)) 1612 break; 1613 } else { 1614 if ((nomincr - incr < -2000) || (nomincr - incr > 2000)) 1615 break; 1616 } 1617 1618 switch (state->props.bandwidth_hz) { 1619 case 8000000: 1620 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 1621 break; 1622 case 7000000: 1623 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 1624 break; 1625 case 6000000: 1626 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 1627 break; 1628 default: 1629 return -1; 1630 break; 1631 } 1632 1633 /* Compute new sysclock value 1634 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */ 1635 incr += (1 << 23); 1636 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21); 1637 sysClockFreq = (u32) (sysClockInHz / 1000); 1638 /* rounding */ 1639 if ((sysClockInHz % 1000) > 500) 1640 sysClockFreq++; 1641 1642 /* Compute clock deviation in ppm */ 1643 oscClockDeviation = (u16) ((((s32) (sysClockFreq) - 1644 (s32) 1645 (state->expected_sys_clock_freq)) * 1646 1000000L) / 1647 (s32) 1648 (state->expected_sys_clock_freq)); 1649 1650 Diff = oscClockDeviation - state->osc_clock_deviation; 1651 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */ 1652 if (Diff >= -200 && Diff <= 200) { 1653 state->sys_clock_freq = (u16) sysClockFreq; 1654 if (oscClockDeviation != state->osc_clock_deviation) { 1655 if (state->config.osc_deviation) { 1656 state->config.osc_deviation(state->priv, 1657 oscClockDeviation, 1658 1); 1659 state->osc_clock_deviation = 1660 oscClockDeviation; 1661 } 1662 } 1663 /* switch OFF SRMM scan in SC */ 1664 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); 1665 if (status < 0) 1666 break; 1667 /* overrule FE_IF internal value for 1668 proper re-locking */ 1669 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); 1670 if (status < 0) 1671 break; 1672 state->cscd_state = CSCD_SAVED; 1673 } 1674 } while (0); 1675 1676 return status; 1677 } 1678 1679 static int DRX_Stop(struct drxd_state *state) 1680 { 1681 int status; 1682 1683 if (state->drxd_state != DRXD_STARTED) 1684 return 0; 1685 1686 do { 1687 if (state->cscd_state != CSCD_SAVED) { 1688 u32 lock; 1689 status = DRX_GetLockStatus(state, &lock); 1690 if (status < 0) 1691 break; 1692 } 1693 1694 status = StopOC(state); 1695 if (status < 0) 1696 break; 1697 1698 state->drxd_state = DRXD_STOPPED; 1699 1700 status = ConfigureMPEGOutput(state, 0); 1701 if (status < 0) 1702 break; 1703 1704 if (state->type_A) { 1705 /* Stop relevant processors off the device */ 1706 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); 1707 if (status < 0) 1708 break; 1709 1710 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1711 if (status < 0) 1712 break; 1713 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1714 if (status < 0) 1715 break; 1716 } else { 1717 /* Stop all processors except HI & CC & FE */ 1718 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1719 if (status < 0) 1720 break; 1721 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1722 if (status < 0) 1723 break; 1724 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1725 if (status < 0) 1726 break; 1727 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1728 if (status < 0) 1729 break; 1730 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1731 if (status < 0) 1732 break; 1733 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1734 if (status < 0) 1735 break; 1736 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); 1737 if (status < 0) 1738 break; 1739 } 1740 1741 } while (0); 1742 return status; 1743 } 1744 1745 #if 0 /* Currently unused */ 1746 static int SetOperationMode(struct drxd_state *state, int oMode) 1747 { 1748 int status; 1749 1750 do { 1751 if (state->drxd_state != DRXD_STOPPED) { 1752 status = -1; 1753 break; 1754 } 1755 1756 if (oMode == state->operation_mode) { 1757 status = 0; 1758 break; 1759 } 1760 1761 if (oMode != OM_Default && !state->diversity) { 1762 status = -1; 1763 break; 1764 } 1765 1766 switch (oMode) { 1767 case OM_DVBT_Diversity_Front: 1768 status = WriteTable(state, state->m_InitDiversityFront); 1769 break; 1770 case OM_DVBT_Diversity_End: 1771 status = WriteTable(state, state->m_InitDiversityEnd); 1772 break; 1773 case OM_Default: 1774 /* We need to check how to 1775 get DRXD out of diversity */ 1776 default: 1777 status = WriteTable(state, state->m_DisableDiversity); 1778 break; 1779 } 1780 } while (0); 1781 1782 if (!status) 1783 state->operation_mode = oMode; 1784 return status; 1785 } 1786 #endif 1787 1788 static int StartDiversity(struct drxd_state *state) 1789 { 1790 int status = 0; 1791 u16 rcControl; 1792 1793 do { 1794 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1795 status = WriteTable(state, state->m_StartDiversityFront); 1796 if (status < 0) 1797 break; 1798 } else if (state->operation_mode == OM_DVBT_Diversity_End) { 1799 status = WriteTable(state, state->m_StartDiversityEnd); 1800 if (status < 0) 1801 break; 1802 if (state->props.bandwidth_hz == 8000000) { 1803 status = WriteTable(state, state->m_DiversityDelay8MHZ); 1804 if (status < 0) 1805 break; 1806 } else { 1807 status = WriteTable(state, state->m_DiversityDelay6MHZ); 1808 if (status < 0) 1809 break; 1810 } 1811 1812 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); 1813 if (status < 0) 1814 break; 1815 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); 1816 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | 1817 /* combining enabled */ 1818 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | 1819 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | 1820 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; 1821 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); 1822 if (status < 0) 1823 break; 1824 } 1825 } while (0); 1826 return status; 1827 } 1828 1829 static int SetFrequencyShift(struct drxd_state *state, 1830 u32 offsetFreq, int channelMirrored) 1831 { 1832 int negativeShift = (state->tuner_mirrors == channelMirrored); 1833 1834 /* Handle all mirroring 1835 * 1836 * Note: ADC mirroring (aliasing) is implictly handled by limiting 1837 * feFsRegAddInc to 28 bits below 1838 * (if the result before masking is more than 28 bits, this means 1839 * that the ADC is mirroring. 1840 * The masking is in fact the aliasing of the ADC) 1841 * 1842 */ 1843 1844 /* Compute register value, unsigned computation */ 1845 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + 1846 offsetFreq, 1847 1 << 28, state->sys_clock_freq); 1848 /* Remove integer part */ 1849 state->fe_fs_add_incr &= 0x0FFFFFFFL; 1850 if (negativeShift) 1851 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); 1852 1853 /* Save the frequency shift without tunerOffset compensation 1854 for CtrlGetChannel. */ 1855 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, 1856 1 << 28, state->sys_clock_freq); 1857 /* Remove integer part */ 1858 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; 1859 if (negativeShift) 1860 state->org_fe_fs_add_incr = ((1L << 28) - 1861 state->org_fe_fs_add_incr); 1862 1863 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, 1864 state->fe_fs_add_incr, 0); 1865 } 1866 1867 static int SetCfgNoiseCalibration(struct drxd_state *state, 1868 struct SNoiseCal *noiseCal) 1869 { 1870 u16 beOptEna; 1871 int status = 0; 1872 1873 do { 1874 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); 1875 if (status < 0) 1876 break; 1877 if (noiseCal->cpOpt) { 1878 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1879 } else { 1880 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1881 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); 1882 if (status < 0) 1883 break; 1884 } 1885 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); 1886 if (status < 0) 1887 break; 1888 1889 if (!state->type_A) { 1890 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); 1891 if (status < 0) 1892 break; 1893 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); 1894 if (status < 0) 1895 break; 1896 } 1897 } while (0); 1898 1899 return status; 1900 } 1901 1902 static int DRX_Start(struct drxd_state *state, s32 off) 1903 { 1904 struct dtv_frontend_properties *p = &state->props; 1905 int status; 1906 1907 u16 transmissionParams = 0; 1908 u16 operationMode = 0; 1909 u16 qpskTdTpsPwr = 0; 1910 u16 qam16TdTpsPwr = 0; 1911 u16 qam64TdTpsPwr = 0; 1912 u32 feIfIncr = 0; 1913 u32 bandwidth = 0; 1914 int mirrorFreqSpect; 1915 1916 u16 qpskSnCeGain = 0; 1917 u16 qam16SnCeGain = 0; 1918 u16 qam64SnCeGain = 0; 1919 u16 qpskIsGainMan = 0; 1920 u16 qam16IsGainMan = 0; 1921 u16 qam64IsGainMan = 0; 1922 u16 qpskIsGainExp = 0; 1923 u16 qam16IsGainExp = 0; 1924 u16 qam64IsGainExp = 0; 1925 u16 bandwidthParam = 0; 1926 1927 if (off < 0) 1928 off = (off - 500) / 1000; 1929 else 1930 off = (off + 500) / 1000; 1931 1932 do { 1933 if (state->drxd_state != DRXD_STOPPED) 1934 return -1; 1935 status = ResetECOD(state); 1936 if (status < 0) 1937 break; 1938 if (state->type_A) { 1939 status = InitSC(state); 1940 if (status < 0) 1941 break; 1942 } else { 1943 status = InitFT(state); 1944 if (status < 0) 1945 break; 1946 status = InitCP(state); 1947 if (status < 0) 1948 break; 1949 status = InitCE(state); 1950 if (status < 0) 1951 break; 1952 status = InitEQ(state); 1953 if (status < 0) 1954 break; 1955 status = InitSC(state); 1956 if (status < 0) 1957 break; 1958 } 1959 1960 /* Restore current IF & RF AGC settings */ 1961 1962 status = SetCfgIfAgc(state, &state->if_agc_cfg); 1963 if (status < 0) 1964 break; 1965 status = SetCfgRfAgc(state, &state->rf_agc_cfg); 1966 if (status < 0) 1967 break; 1968 1969 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); 1970 1971 switch (p->transmission_mode) { 1972 default: /* Not set, detect it automatically */ 1973 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M; 1974 /* try first guess DRX_FFTMODE_8K */ 1975 /* fall through */ 1976 case TRANSMISSION_MODE_8K: 1977 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; 1978 if (state->type_A) { 1979 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); 1980 if (status < 0) 1981 break; 1982 qpskSnCeGain = 99; 1983 qam16SnCeGain = 83; 1984 qam64SnCeGain = 67; 1985 } 1986 break; 1987 case TRANSMISSION_MODE_2K: 1988 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; 1989 if (state->type_A) { 1990 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); 1991 if (status < 0) 1992 break; 1993 qpskSnCeGain = 97; 1994 qam16SnCeGain = 71; 1995 qam64SnCeGain = 65; 1996 } 1997 break; 1998 } 1999 2000 switch (p->guard_interval) { 2001 case GUARD_INTERVAL_1_4: 2002 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 2003 break; 2004 case GUARD_INTERVAL_1_8: 2005 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8; 2006 break; 2007 case GUARD_INTERVAL_1_16: 2008 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16; 2009 break; 2010 case GUARD_INTERVAL_1_32: 2011 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32; 2012 break; 2013 default: /* Not set, detect it automatically */ 2014 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M; 2015 /* try first guess 1/4 */ 2016 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 2017 break; 2018 } 2019 2020 switch (p->hierarchy) { 2021 case HIERARCHY_1: 2022 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; 2023 if (state->type_A) { 2024 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); 2025 if (status < 0) 2026 break; 2027 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); 2028 if (status < 0) 2029 break; 2030 2031 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2032 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; 2033 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1; 2034 2035 qpskIsGainMan = 2036 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2037 qam16IsGainMan = 2038 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 2039 qam64IsGainMan = 2040 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 2041 2042 qpskIsGainExp = 2043 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2044 qam16IsGainExp = 2045 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 2046 qam64IsGainExp = 2047 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 2048 } 2049 break; 2050 2051 case HIERARCHY_2: 2052 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; 2053 if (state->type_A) { 2054 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); 2055 if (status < 0) 2056 break; 2057 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); 2058 if (status < 0) 2059 break; 2060 2061 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2062 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; 2063 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2; 2064 2065 qpskIsGainMan = 2066 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2067 qam16IsGainMan = 2068 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE; 2069 qam64IsGainMan = 2070 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE; 2071 2072 qpskIsGainExp = 2073 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2074 qam16IsGainExp = 2075 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE; 2076 qam64IsGainExp = 2077 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE; 2078 } 2079 break; 2080 case HIERARCHY_4: 2081 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; 2082 if (state->type_A) { 2083 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); 2084 if (status < 0) 2085 break; 2086 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); 2087 if (status < 0) 2088 break; 2089 2090 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2091 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; 2092 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4; 2093 2094 qpskIsGainMan = 2095 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2096 qam16IsGainMan = 2097 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE; 2098 qam64IsGainMan = 2099 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE; 2100 2101 qpskIsGainExp = 2102 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2103 qam16IsGainExp = 2104 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE; 2105 qam64IsGainExp = 2106 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE; 2107 } 2108 break; 2109 case HIERARCHY_AUTO: 2110 default: 2111 /* Not set, detect it automatically, start with none */ 2112 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; 2113 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; 2114 if (state->type_A) { 2115 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); 2116 if (status < 0) 2117 break; 2118 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); 2119 if (status < 0) 2120 break; 2121 2122 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; 2123 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; 2124 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN; 2125 2126 qpskIsGainMan = 2127 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE; 2128 qam16IsGainMan = 2129 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 2130 qam64IsGainMan = 2131 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 2132 2133 qpskIsGainExp = 2134 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE; 2135 qam16IsGainExp = 2136 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 2137 qam64IsGainExp = 2138 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 2139 } 2140 break; 2141 } 2142 status = status; 2143 if (status < 0) 2144 break; 2145 2146 switch (p->modulation) { 2147 default: 2148 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M; 2149 /* try first guess DRX_CONSTELLATION_QAM64 */ 2150 /* fall through */ 2151 case QAM_64: 2152 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; 2153 if (state->type_A) { 2154 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); 2155 if (status < 0) 2156 break; 2157 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); 2158 if (status < 0) 2159 break; 2160 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); 2161 if (status < 0) 2162 break; 2163 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); 2164 if (status < 0) 2165 break; 2166 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); 2167 if (status < 0) 2168 break; 2169 2170 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); 2171 if (status < 0) 2172 break; 2173 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); 2174 if (status < 0) 2175 break; 2176 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); 2177 if (status < 0) 2178 break; 2179 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); 2180 if (status < 0) 2181 break; 2182 } 2183 break; 2184 case QPSK: 2185 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; 2186 if (state->type_A) { 2187 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); 2188 if (status < 0) 2189 break; 2190 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); 2191 if (status < 0) 2192 break; 2193 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); 2194 if (status < 0) 2195 break; 2196 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); 2197 if (status < 0) 2198 break; 2199 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); 2200 if (status < 0) 2201 break; 2202 2203 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); 2204 if (status < 0) 2205 break; 2206 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); 2207 if (status < 0) 2208 break; 2209 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); 2210 if (status < 0) 2211 break; 2212 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); 2213 if (status < 0) 2214 break; 2215 } 2216 break; 2217 2218 case QAM_16: 2219 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; 2220 if (state->type_A) { 2221 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); 2222 if (status < 0) 2223 break; 2224 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); 2225 if (status < 0) 2226 break; 2227 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); 2228 if (status < 0) 2229 break; 2230 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); 2231 if (status < 0) 2232 break; 2233 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); 2234 if (status < 0) 2235 break; 2236 2237 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); 2238 if (status < 0) 2239 break; 2240 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); 2241 if (status < 0) 2242 break; 2243 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); 2244 if (status < 0) 2245 break; 2246 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); 2247 if (status < 0) 2248 break; 2249 } 2250 break; 2251 2252 } 2253 status = status; 2254 if (status < 0) 2255 break; 2256 2257 switch (DRX_CHANNEL_HIGH) { 2258 default: 2259 case DRX_CHANNEL_AUTO: 2260 case DRX_CHANNEL_LOW: 2261 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; 2262 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); 2263 if (status < 0) 2264 break; 2265 break; 2266 case DRX_CHANNEL_HIGH: 2267 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; 2268 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); 2269 if (status < 0) 2270 break; 2271 break; 2272 2273 } 2274 2275 switch (p->code_rate_HP) { 2276 case FEC_1_2: 2277 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; 2278 if (state->type_A) { 2279 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); 2280 if (status < 0) 2281 break; 2282 } 2283 break; 2284 default: 2285 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M; 2286 /* fall through */ 2287 case FEC_2_3: 2288 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; 2289 if (state->type_A) { 2290 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); 2291 if (status < 0) 2292 break; 2293 } 2294 break; 2295 case FEC_3_4: 2296 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; 2297 if (state->type_A) { 2298 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); 2299 if (status < 0) 2300 break; 2301 } 2302 break; 2303 case FEC_5_6: 2304 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; 2305 if (state->type_A) { 2306 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); 2307 if (status < 0) 2308 break; 2309 } 2310 break; 2311 case FEC_7_8: 2312 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; 2313 if (state->type_A) { 2314 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); 2315 if (status < 0) 2316 break; 2317 } 2318 break; 2319 } 2320 status = status; 2321 if (status < 0) 2322 break; 2323 2324 /* First determine real bandwidth (Hz) */ 2325 /* Also set delay for impulse noise cruncher (only A2) */ 2326 /* Also set parameters for EC_OC fix, note 2327 EC_OC_REG_TMD_HIL_MAR is changed 2328 by SC for fix for some 8K,1/8 guard but is restored by 2329 InitEC and ResetEC 2330 functions */ 2331 switch (p->bandwidth_hz) { 2332 case 0: 2333 p->bandwidth_hz = 8000000; 2334 /* fall through */ 2335 case 8000000: 2336 /* (64/7)*(8/8)*1000000 */ 2337 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 2338 2339 bandwidthParam = 0; 2340 status = Write16(state, 2341 FE_AG_REG_IND_DEL__A, 50, 0x0000); 2342 break; 2343 case 7000000: 2344 /* (64/7)*(7/8)*1000000 */ 2345 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 2346 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */ 2347 status = Write16(state, 2348 FE_AG_REG_IND_DEL__A, 59, 0x0000); 2349 break; 2350 case 6000000: 2351 /* (64/7)*(6/8)*1000000 */ 2352 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 2353 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */ 2354 status = Write16(state, 2355 FE_AG_REG_IND_DEL__A, 71, 0x0000); 2356 break; 2357 default: 2358 status = -EINVAL; 2359 } 2360 if (status < 0) 2361 break; 2362 2363 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); 2364 if (status < 0) 2365 break; 2366 2367 { 2368 u16 sc_config; 2369 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); 2370 if (status < 0) 2371 break; 2372 2373 /* enable SLAVE mode in 2k 1/32 to 2374 prevent timing change glitches */ 2375 if ((p->transmission_mode == TRANSMISSION_MODE_2K) && 2376 (p->guard_interval == GUARD_INTERVAL_1_32)) { 2377 /* enable slave */ 2378 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M; 2379 } else { 2380 /* disable slave */ 2381 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; 2382 } 2383 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); 2384 if (status < 0) 2385 break; 2386 } 2387 2388 status = SetCfgNoiseCalibration(state, &state->noise_cal); 2389 if (status < 0) 2390 break; 2391 2392 if (state->cscd_state == CSCD_INIT) { 2393 /* switch on SRMM scan in SC */ 2394 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); 2395 if (status < 0) 2396 break; 2397 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/ 2398 state->cscd_state = CSCD_SET; 2399 } 2400 2401 /* Now compute FE_IF_REG_INCR */ 2402 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => 2403 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ 2404 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, 2405 (1ULL << 21), bandwidth) - (1 << 23); 2406 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); 2407 if (status < 0) 2408 break; 2409 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000); 2410 if (status < 0) 2411 break; 2412 /* Bandwidth setting done */ 2413 2414 /* Mirror & frequency offset */ 2415 SetFrequencyShift(state, off, mirrorFreqSpect); 2416 2417 /* Start SC, write channel settings to SC */ 2418 2419 /* Enable SC after setting all other parameters */ 2420 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); 2421 if (status < 0) 2422 break; 2423 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); 2424 if (status < 0) 2425 break; 2426 2427 /* Write SC parameter registers, operation mode */ 2428 #if 1 2429 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M | 2430 SC_RA_RAM_OP_AUTO_GUARD__M | 2431 SC_RA_RAM_OP_AUTO_CONST__M | 2432 SC_RA_RAM_OP_AUTO_HIER__M | 2433 SC_RA_RAM_OP_AUTO_RATE__M); 2434 #endif 2435 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); 2436 if (status < 0) 2437 break; 2438 2439 /* Start correct processes to get in lock */ 2440 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN); 2441 if (status < 0) 2442 break; 2443 2444 status = StartOC(state); 2445 if (status < 0) 2446 break; 2447 2448 if (state->operation_mode != OM_Default) { 2449 status = StartDiversity(state); 2450 if (status < 0) 2451 break; 2452 } 2453 2454 state->drxd_state = DRXD_STARTED; 2455 } while (0); 2456 2457 return status; 2458 } 2459 2460 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) 2461 { 2462 u32 ulRfAgcOutputLevel = 0xffffffff; 2463 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */ 2464 u32 ulRfAgcMinLevel = 0; /* Currently unused */ 2465 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */ 2466 u32 ulRfAgcSpeed = 0; /* Currently unused */ 2467 u32 ulRfAgcMode = 0; /*2; Off */ 2468 u32 ulRfAgcR1 = 820; 2469 u32 ulRfAgcR2 = 2200; 2470 u32 ulRfAgcR3 = 150; 2471 u32 ulIfAgcMode = 0; /* Auto */ 2472 u32 ulIfAgcOutputLevel = 0xffffffff; 2473 u32 ulIfAgcSettleLevel = 0xffffffff; 2474 u32 ulIfAgcMinLevel = 0xffffffff; 2475 u32 ulIfAgcMaxLevel = 0xffffffff; 2476 u32 ulIfAgcSpeed = 0xffffffff; 2477 u32 ulIfAgcR1 = 820; 2478 u32 ulIfAgcR2 = 2200; 2479 u32 ulIfAgcR3 = 150; 2480 u32 ulClock = state->config.clock; 2481 u32 ulSerialMode = 0; 2482 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ 2483 u32 ulHiI2cDelay = HI_I2C_DELAY; 2484 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY; 2485 u32 ulHiI2cPatch = 0; 2486 u32 ulEnvironment = APPENV_PORTABLE; 2487 u32 ulEnvironmentDiversity = APPENV_MOBILE; 2488 u32 ulIFFilter = IFFILTER_SAW; 2489 2490 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2491 state->if_agc_cfg.outputLevel = 0; 2492 state->if_agc_cfg.settleLevel = 140; 2493 state->if_agc_cfg.minOutputLevel = 0; 2494 state->if_agc_cfg.maxOutputLevel = 1023; 2495 state->if_agc_cfg.speed = 904; 2496 2497 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { 2498 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; 2499 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); 2500 } 2501 2502 if (ulIfAgcMode == 0 && 2503 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2504 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2505 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2506 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) { 2507 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2508 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); 2509 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); 2510 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); 2511 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); 2512 } 2513 2514 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); 2515 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); 2516 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); 2517 2518 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); 2519 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); 2520 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); 2521 2522 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2523 /* rest of the RFAgcCfg structure currently unused */ 2524 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { 2525 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; 2526 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); 2527 } 2528 2529 if (ulRfAgcMode == 0 && 2530 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2531 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2532 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2533 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) { 2534 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2535 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); 2536 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); 2537 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); 2538 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); 2539 } 2540 2541 if (ulRfAgcMode == 2) 2542 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; 2543 2544 if (ulEnvironment <= 2) 2545 state->app_env_default = (enum app_env) 2546 (ulEnvironment); 2547 if (ulEnvironmentDiversity <= 2) 2548 state->app_env_diversity = (enum app_env) 2549 (ulEnvironmentDiversity); 2550 2551 if (ulIFFilter == IFFILTER_DISCRETE) { 2552 /* discrete filter */ 2553 state->noise_cal.cpOpt = 0; 2554 state->noise_cal.cpNexpOfs = 40; 2555 state->noise_cal.tdCal2k = -40; 2556 state->noise_cal.tdCal8k = -24; 2557 } else { 2558 /* SAW filter */ 2559 state->noise_cal.cpOpt = 1; 2560 state->noise_cal.cpNexpOfs = 0; 2561 state->noise_cal.tdCal2k = -21; 2562 state->noise_cal.tdCal8k = -24; 2563 } 2564 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); 2565 2566 state->chip_adr = (state->config.demod_address << 1) | 1; 2567 switch (ulHiI2cPatch) { 2568 case 1: 2569 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; 2570 break; 2571 case 3: 2572 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; 2573 break; 2574 default: 2575 state->m_HiI2cPatch = NULL; 2576 } 2577 2578 /* modify tuner and clock attributes */ 2579 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); 2580 /* expected system clock frequency in kHz */ 2581 state->expected_sys_clock_freq = 48000; 2582 /* real system clock frequency in kHz */ 2583 state->sys_clock_freq = 48000; 2584 state->osc_clock_freq = (u16) ulClock; 2585 state->osc_clock_deviation = 0; 2586 state->cscd_state = CSCD_INIT; 2587 state->drxd_state = DRXD_UNINITIALIZED; 2588 2589 state->PGA = 0; 2590 state->type_A = 0; 2591 state->tuner_mirrors = 0; 2592 2593 /* modify MPEG output attributes */ 2594 state->insert_rs_byte = state->config.insert_rs_byte; 2595 state->enable_parallel = (ulSerialMode != 1); 2596 2597 /* Timing div, 250ns/Psys */ 2598 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ 2599 2600 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * 2601 ulHiI2cDelay) / 1000; 2602 /* Bridge delay, uses oscilator clock */ 2603 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ 2604 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * 2605 ulHiI2cBridgeDelay) / 1000; 2606 2607 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2608 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ 2609 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; 2610 return 0; 2611 } 2612 2613 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) 2614 { 2615 int status = 0; 2616 u32 driverVersion; 2617 2618 if (state->init_done) 2619 return 0; 2620 2621 CDRXD(state, state->config.IF ? state->config.IF : 36000000); 2622 2623 do { 2624 state->operation_mode = OM_Default; 2625 2626 status = SetDeviceTypeId(state); 2627 if (status < 0) 2628 break; 2629 2630 /* Apply I2c address patch to B1 */ 2631 if (!state->type_A && state->m_HiI2cPatch != NULL) { 2632 status = WriteTable(state, state->m_HiI2cPatch); 2633 if (status < 0) 2634 break; 2635 } 2636 2637 if (state->type_A) { 2638 /* HI firmware patch for UIO readout, 2639 avoid clearing of result register */ 2640 status = Write16(state, 0x43012D, 0x047f, 0); 2641 if (status < 0) 2642 break; 2643 } 2644 2645 status = HI_ResetCommand(state); 2646 if (status < 0) 2647 break; 2648 2649 status = StopAllProcessors(state); 2650 if (status < 0) 2651 break; 2652 status = InitCC(state); 2653 if (status < 0) 2654 break; 2655 2656 state->osc_clock_deviation = 0; 2657 2658 if (state->config.osc_deviation) 2659 state->osc_clock_deviation = 2660 state->config.osc_deviation(state->priv, 0, 0); 2661 { 2662 /* Handle clock deviation */ 2663 s32 devB; 2664 s32 devA = (s32) (state->osc_clock_deviation) * 2665 (s32) (state->expected_sys_clock_freq); 2666 /* deviation in kHz */ 2667 s32 deviation = (devA / (1000000L)); 2668 /* rounding, signed */ 2669 if (devA > 0) 2670 devB = (2); 2671 else 2672 devB = (-2); 2673 if ((devB * (devA % 1000000L) > 1000000L)) { 2674 /* add +1 or -1 */ 2675 deviation += (devB / 2); 2676 } 2677 2678 state->sys_clock_freq = 2679 (u16) ((state->expected_sys_clock_freq) + 2680 deviation); 2681 } 2682 status = InitHI(state); 2683 if (status < 0) 2684 break; 2685 status = InitAtomicRead(state); 2686 if (status < 0) 2687 break; 2688 2689 status = EnableAndResetMB(state); 2690 if (status < 0) 2691 break; 2692 if (state->type_A) { 2693 status = ResetCEFR(state); 2694 if (status < 0) 2695 break; 2696 } 2697 if (fw) { 2698 status = DownloadMicrocode(state, fw, fw_size); 2699 if (status < 0) 2700 break; 2701 } else { 2702 status = DownloadMicrocode(state, state->microcode, state->microcode_length); 2703 if (status < 0) 2704 break; 2705 } 2706 2707 if (state->PGA) { 2708 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; 2709 SetCfgPga(state, 0); /* PGA = 0 dB */ 2710 } else { 2711 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2712 } 2713 2714 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; 2715 2716 status = InitFE(state); 2717 if (status < 0) 2718 break; 2719 status = InitFT(state); 2720 if (status < 0) 2721 break; 2722 status = InitCP(state); 2723 if (status < 0) 2724 break; 2725 status = InitCE(state); 2726 if (status < 0) 2727 break; 2728 status = InitEQ(state); 2729 if (status < 0) 2730 break; 2731 status = InitEC(state); 2732 if (status < 0) 2733 break; 2734 status = InitSC(state); 2735 if (status < 0) 2736 break; 2737 2738 status = SetCfgIfAgc(state, &state->if_agc_cfg); 2739 if (status < 0) 2740 break; 2741 status = SetCfgRfAgc(state, &state->rf_agc_cfg); 2742 if (status < 0) 2743 break; 2744 2745 state->cscd_state = CSCD_INIT; 2746 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 2747 if (status < 0) 2748 break; 2749 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 2750 if (status < 0) 2751 break; 2752 2753 driverVersion = (((VERSION_MAJOR / 10) << 4) + 2754 (VERSION_MAJOR % 10)) << 24; 2755 driverVersion += (((VERSION_MINOR / 10) << 4) + 2756 (VERSION_MINOR % 10)) << 16; 2757 driverVersion += ((VERSION_PATCH / 1000) << 12) + 2758 ((VERSION_PATCH / 100) << 8) + 2759 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10); 2760 2761 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); 2762 if (status < 0) 2763 break; 2764 2765 status = StopOC(state); 2766 if (status < 0) 2767 break; 2768 2769 state->drxd_state = DRXD_STOPPED; 2770 state->init_done = 1; 2771 status = 0; 2772 } while (0); 2773 return status; 2774 } 2775 2776 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) 2777 { 2778 DRX_GetLockStatus(state, pLockStatus); 2779 2780 /*if (*pLockStatus&DRX_LOCK_MPEG) */ 2781 if (*pLockStatus & DRX_LOCK_FEC) { 2782 ConfigureMPEGOutput(state, 1); 2783 /* Get status again, in case we have MPEG lock now */ 2784 /*DRX_GetLockStatus(state, pLockStatus); */ 2785 } 2786 2787 return 0; 2788 } 2789 2790 /****************************************************************************/ 2791 /****************************************************************************/ 2792 /****************************************************************************/ 2793 2794 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength) 2795 { 2796 struct drxd_state *state = fe->demodulator_priv; 2797 u32 value; 2798 int res; 2799 2800 res = ReadIFAgc(state, &value); 2801 if (res < 0) 2802 *strength = 0; 2803 else 2804 *strength = 0xffff - (value << 4); 2805 return 0; 2806 } 2807 2808 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status) 2809 { 2810 struct drxd_state *state = fe->demodulator_priv; 2811 u32 lock; 2812 2813 DRXD_status(state, &lock); 2814 *status = 0; 2815 /* No MPEG lock in V255 firmware, bug ? */ 2816 #if 1 2817 if (lock & DRX_LOCK_MPEG) 2818 *status |= FE_HAS_LOCK; 2819 #else 2820 if (lock & DRX_LOCK_FEC) 2821 *status |= FE_HAS_LOCK; 2822 #endif 2823 if (lock & DRX_LOCK_FEC) 2824 *status |= FE_HAS_VITERBI | FE_HAS_SYNC; 2825 if (lock & DRX_LOCK_DEMOD) 2826 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; 2827 2828 return 0; 2829 } 2830 2831 static int drxd_init(struct dvb_frontend *fe) 2832 { 2833 struct drxd_state *state = fe->demodulator_priv; 2834 2835 return DRXD_init(state, NULL, 0); 2836 } 2837 2838 static int drxd_config_i2c(struct dvb_frontend *fe, int onoff) 2839 { 2840 struct drxd_state *state = fe->demodulator_priv; 2841 2842 if (state->config.disable_i2c_gate_ctrl == 1) 2843 return 0; 2844 2845 return DRX_ConfigureI2CBridge(state, onoff); 2846 } 2847 2848 static int drxd_get_tune_settings(struct dvb_frontend *fe, 2849 struct dvb_frontend_tune_settings *sets) 2850 { 2851 sets->min_delay_ms = 10000; 2852 sets->max_drift = 0; 2853 sets->step_size = 0; 2854 return 0; 2855 } 2856 2857 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber) 2858 { 2859 *ber = 0; 2860 return 0; 2861 } 2862 2863 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr) 2864 { 2865 *snr = 0; 2866 return 0; 2867 } 2868 2869 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 2870 { 2871 *ucblocks = 0; 2872 return 0; 2873 } 2874 2875 static int drxd_sleep(struct dvb_frontend *fe) 2876 { 2877 struct drxd_state *state = fe->demodulator_priv; 2878 2879 ConfigureMPEGOutput(state, 0); 2880 return 0; 2881 } 2882 2883 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 2884 { 2885 return drxd_config_i2c(fe, enable); 2886 } 2887 2888 static int drxd_set_frontend(struct dvb_frontend *fe) 2889 { 2890 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 2891 struct drxd_state *state = fe->demodulator_priv; 2892 s32 off = 0; 2893 2894 state->props = *p; 2895 DRX_Stop(state); 2896 2897 if (fe->ops.tuner_ops.set_params) { 2898 fe->ops.tuner_ops.set_params(fe); 2899 if (fe->ops.i2c_gate_ctrl) 2900 fe->ops.i2c_gate_ctrl(fe, 0); 2901 } 2902 2903 msleep(200); 2904 2905 return DRX_Start(state, off); 2906 } 2907 2908 static void drxd_release(struct dvb_frontend *fe) 2909 { 2910 struct drxd_state *state = fe->demodulator_priv; 2911 2912 kfree(state); 2913 } 2914 2915 static const struct dvb_frontend_ops drxd_ops = { 2916 .delsys = { SYS_DVBT}, 2917 .info = { 2918 .name = "Micronas DRXD DVB-T", 2919 .frequency_min = 47125000, 2920 .frequency_max = 855250000, 2921 .frequency_stepsize = 166667, 2922 .frequency_tolerance = 0, 2923 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 2924 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 2925 FE_CAN_FEC_AUTO | 2926 FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2927 FE_CAN_QAM_AUTO | 2928 FE_CAN_TRANSMISSION_MODE_AUTO | 2929 FE_CAN_GUARD_INTERVAL_AUTO | 2930 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS}, 2931 2932 .release = drxd_release, 2933 .init = drxd_init, 2934 .sleep = drxd_sleep, 2935 .i2c_gate_ctrl = drxd_i2c_gate_ctrl, 2936 2937 .set_frontend = drxd_set_frontend, 2938 .get_tune_settings = drxd_get_tune_settings, 2939 2940 .read_status = drxd_read_status, 2941 .read_ber = drxd_read_ber, 2942 .read_signal_strength = drxd_read_signal_strength, 2943 .read_snr = drxd_read_snr, 2944 .read_ucblocks = drxd_read_ucblocks, 2945 }; 2946 2947 struct dvb_frontend *drxd_attach(const struct drxd_config *config, 2948 void *priv, struct i2c_adapter *i2c, 2949 struct device *dev) 2950 { 2951 struct drxd_state *state = NULL; 2952 2953 state = kzalloc(sizeof(*state), GFP_KERNEL); 2954 if (!state) 2955 return NULL; 2956 2957 state->ops = drxd_ops; 2958 state->dev = dev; 2959 state->config = *config; 2960 state->i2c = i2c; 2961 state->priv = priv; 2962 2963 mutex_init(&state->mutex); 2964 2965 if (Read16(state, 0, NULL, 0) < 0) 2966 goto error; 2967 2968 state->frontend.ops = drxd_ops; 2969 state->frontend.demodulator_priv = state; 2970 ConfigureMPEGOutput(state, 0); 2971 /* add few initialization to allow gate control */ 2972 CDRXD(state, state->config.IF ? state->config.IF : 36000000); 2973 InitHI(state); 2974 2975 return &state->frontend; 2976 2977 error: 2978 printk(KERN_ERR "drxd: not found\n"); 2979 kfree(state); 2980 return NULL; 2981 } 2982 EXPORT_SYMBOL(drxd_attach); 2983 2984 MODULE_DESCRIPTION("DRXD driver"); 2985 MODULE_AUTHOR("Micronas"); 2986 MODULE_LICENSE("GPL"); 2987