1 /* 2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1 3 * 4 * Copyright (C) 2003-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/i2c.h> 27 #include <asm/div64.h> 28 29 #include "dvb_frontend.h" 30 #include "drxd.h" 31 #include "drxd_firm.h" 32 33 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw" 34 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw" 35 36 #define CHUNK_SIZE 48 37 38 #define DRX_I2C_RMW 0x10 39 #define DRX_I2C_BROADCAST 0x20 40 #define DRX_I2C_CLEARCRC 0x80 41 #define DRX_I2C_SINGLE_MASTER 0xC0 42 #define DRX_I2C_MODEFLAGS 0xC0 43 #define DRX_I2C_FLAGS 0xF0 44 45 #define DEFAULT_LOCK_TIMEOUT 1100 46 47 #define DRX_CHANNEL_AUTO 0 48 #define DRX_CHANNEL_HIGH 1 49 #define DRX_CHANNEL_LOW 2 50 51 #define DRX_LOCK_MPEG 1 52 #define DRX_LOCK_FEC 2 53 #define DRX_LOCK_DEMOD 4 54 55 /****************************************************************************/ 56 57 enum CSCDState { 58 CSCD_INIT = 0, 59 CSCD_SET, 60 CSCD_SAVED 61 }; 62 63 enum CDrxdState { 64 DRXD_UNINITIALIZED = 0, 65 DRXD_STOPPED, 66 DRXD_STARTED 67 }; 68 69 enum AGC_CTRL_MODE { 70 AGC_CTRL_AUTO = 0, 71 AGC_CTRL_USER, 72 AGC_CTRL_OFF 73 }; 74 75 enum OperationMode { 76 OM_Default, 77 OM_DVBT_Diversity_Front, 78 OM_DVBT_Diversity_End 79 }; 80 81 struct SCfgAgc { 82 enum AGC_CTRL_MODE ctrlMode; 83 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 84 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 85 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 86 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 87 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ 88 89 u16 R1; 90 u16 R2; 91 u16 R3; 92 }; 93 94 struct SNoiseCal { 95 int cpOpt; 96 short cpNexpOfs; 97 short tdCal2k; 98 short tdCal8k; 99 }; 100 101 enum app_env { 102 APPENV_STATIC = 0, 103 APPENV_PORTABLE = 1, 104 APPENV_MOBILE = 2 105 }; 106 107 enum EIFFilter { 108 IFFILTER_SAW = 0, 109 IFFILTER_DISCRETE = 1 110 }; 111 112 struct drxd_state { 113 struct dvb_frontend frontend; 114 struct dvb_frontend_ops ops; 115 struct dtv_frontend_properties props; 116 117 const struct firmware *fw; 118 struct device *dev; 119 120 struct i2c_adapter *i2c; 121 void *priv; 122 struct drxd_config config; 123 124 int i2c_access; 125 int init_done; 126 struct mutex mutex; 127 128 u8 chip_adr; 129 u16 hi_cfg_timing_div; 130 u16 hi_cfg_bridge_delay; 131 u16 hi_cfg_wakeup_key; 132 u16 hi_cfg_ctrl; 133 134 u16 intermediate_freq; 135 u16 osc_clock_freq; 136 137 enum CSCDState cscd_state; 138 enum CDrxdState drxd_state; 139 140 u16 sys_clock_freq; 141 s16 osc_clock_deviation; 142 u16 expected_sys_clock_freq; 143 144 u16 insert_rs_byte; 145 u16 enable_parallel; 146 147 int operation_mode; 148 149 struct SCfgAgc if_agc_cfg; 150 struct SCfgAgc rf_agc_cfg; 151 152 struct SNoiseCal noise_cal; 153 154 u32 fe_fs_add_incr; 155 u32 org_fe_fs_add_incr; 156 u16 current_fe_if_incr; 157 158 u16 m_FeAgRegAgPwd; 159 u16 m_FeAgRegAgAgcSio; 160 161 u16 m_EcOcRegOcModeLop; 162 u16 m_EcOcRegSncSncLvl; 163 u8 *m_InitAtomicRead; 164 u8 *m_HiI2cPatch; 165 166 u8 *m_ResetCEFR; 167 u8 *m_InitFE_1; 168 u8 *m_InitFE_2; 169 u8 *m_InitCP; 170 u8 *m_InitCE; 171 u8 *m_InitEQ; 172 u8 *m_InitSC; 173 u8 *m_InitEC; 174 u8 *m_ResetECRAM; 175 u8 *m_InitDiversityFront; 176 u8 *m_InitDiversityEnd; 177 u8 *m_DisableDiversity; 178 u8 *m_StartDiversityFront; 179 u8 *m_StartDiversityEnd; 180 181 u8 *m_DiversityDelay8MHZ; 182 u8 *m_DiversityDelay6MHZ; 183 184 u8 *microcode; 185 u32 microcode_length; 186 187 int type_A; 188 int PGA; 189 int diversity; 190 int tuner_mirrors; 191 192 enum app_env app_env_default; 193 enum app_env app_env_diversity; 194 195 }; 196 197 /****************************************************************************/ 198 /* I2C **********************************************************************/ 199 /****************************************************************************/ 200 201 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len) 202 { 203 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len }; 204 205 if (i2c_transfer(adap, &msg, 1) != 1) 206 return -1; 207 return 0; 208 } 209 210 static int i2c_read(struct i2c_adapter *adap, 211 u8 adr, u8 *msg, int len, u8 *answ, int alen) 212 { 213 struct i2c_msg msgs[2] = { 214 { 215 .addr = adr, .flags = 0, 216 .buf = msg, .len = len 217 }, { 218 .addr = adr, .flags = I2C_M_RD, 219 .buf = answ, .len = alen 220 } 221 }; 222 if (i2c_transfer(adap, msgs, 2) != 2) 223 return -1; 224 return 0; 225 } 226 227 static inline u32 MulDiv32(u32 a, u32 b, u32 c) 228 { 229 u64 tmp64; 230 231 tmp64 = (u64)a * (u64)b; 232 do_div(tmp64, c); 233 234 return (u32) tmp64; 235 } 236 237 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) 238 { 239 u8 adr = state->config.demod_address; 240 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, 241 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 242 }; 243 u8 mm2[2]; 244 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) 245 return -1; 246 if (data) 247 *data = mm2[0] | (mm2[1] << 8); 248 return mm2[0] | (mm2[1] << 8); 249 } 250 251 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) 252 { 253 u8 adr = state->config.demod_address; 254 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, 255 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 256 }; 257 u8 mm2[4]; 258 259 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) 260 return -1; 261 if (data) 262 *data = 263 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24); 264 return 0; 265 } 266 267 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) 268 { 269 u8 adr = state->config.demod_address; 270 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, 271 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, 272 data & 0xff, (data >> 8) & 0xff 273 }; 274 275 if (i2c_write(state->i2c, adr, mm, 6) < 0) 276 return -1; 277 return 0; 278 } 279 280 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) 281 { 282 u8 adr = state->config.demod_address; 283 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, 284 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, 285 data & 0xff, (data >> 8) & 0xff, 286 (data >> 16) & 0xff, (data >> 24) & 0xff 287 }; 288 289 if (i2c_write(state->i2c, adr, mm, 8) < 0) 290 return -1; 291 return 0; 292 } 293 294 static int write_chunk(struct drxd_state *state, 295 u32 reg, u8 *data, u32 len, u8 flags) 296 { 297 u8 adr = state->config.demod_address; 298 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, 299 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 300 }; 301 int i; 302 303 for (i = 0; i < len; i++) 304 mm[4 + i] = data[i]; 305 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { 306 printk(KERN_ERR "error in write_chunk\n"); 307 return -1; 308 } 309 return 0; 310 } 311 312 static int WriteBlock(struct drxd_state *state, 313 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) 314 { 315 while (BlockSize > 0) { 316 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; 317 318 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) 319 return -1; 320 pBlock += Chunk; 321 Address += (Chunk >> 1); 322 BlockSize -= Chunk; 323 } 324 return 0; 325 } 326 327 static int WriteTable(struct drxd_state *state, u8 * pTable) 328 { 329 int status = 0; 330 331 if (!pTable) 332 return 0; 333 334 while (!status) { 335 u16 Length; 336 u32 Address = pTable[0] | (pTable[1] << 8) | 337 (pTable[2] << 16) | (pTable[3] << 24); 338 339 if (Address == 0xFFFFFFFF) 340 break; 341 pTable += sizeof(u32); 342 343 Length = pTable[0] | (pTable[1] << 8); 344 pTable += sizeof(u16); 345 if (!Length) 346 break; 347 status = WriteBlock(state, Address, Length * 2, pTable, 0); 348 pTable += (Length * 2); 349 } 350 return status; 351 } 352 353 /****************************************************************************/ 354 /****************************************************************************/ 355 /****************************************************************************/ 356 357 static int ResetCEFR(struct drxd_state *state) 358 { 359 return WriteTable(state, state->m_ResetCEFR); 360 } 361 362 static int InitCP(struct drxd_state *state) 363 { 364 return WriteTable(state, state->m_InitCP); 365 } 366 367 static int InitCE(struct drxd_state *state) 368 { 369 int status; 370 enum app_env AppEnv = state->app_env_default; 371 372 do { 373 status = WriteTable(state, state->m_InitCE); 374 if (status < 0) 375 break; 376 377 if (state->operation_mode == OM_DVBT_Diversity_Front || 378 state->operation_mode == OM_DVBT_Diversity_End) { 379 AppEnv = state->app_env_diversity; 380 } 381 if (AppEnv == APPENV_STATIC) { 382 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); 383 if (status < 0) 384 break; 385 } else if (AppEnv == APPENV_PORTABLE) { 386 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); 387 if (status < 0) 388 break; 389 } else if (AppEnv == APPENV_MOBILE && state->type_A) { 390 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); 391 if (status < 0) 392 break; 393 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { 394 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); 395 if (status < 0) 396 break; 397 } 398 399 /* start ce */ 400 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); 401 if (status < 0) 402 break; 403 } while (0); 404 return status; 405 } 406 407 static int StopOC(struct drxd_state *state) 408 { 409 int status = 0; 410 u16 ocSyncLvl = 0; 411 u16 ocModeLop = state->m_EcOcRegOcModeLop; 412 u16 dtoIncLop = 0; 413 u16 dtoIncHip = 0; 414 415 do { 416 /* Store output configuration */ 417 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); 418 if (status < 0) 419 break; 420 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */ 421 state->m_EcOcRegSncSncLvl = ocSyncLvl; 422 /* m_EcOcRegOcModeLop = ocModeLop; */ 423 424 /* Flush FIFO (byte-boundary) at fixed rate */ 425 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); 426 if (status < 0) 427 break; 428 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); 429 if (status < 0) 430 break; 431 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); 432 if (status < 0) 433 break; 434 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); 435 if (status < 0) 436 break; 437 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); 438 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; 439 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); 440 if (status < 0) 441 break; 442 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); 443 if (status < 0) 444 break; 445 446 msleep(1); 447 /* Output pins to '0' */ 448 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); 449 if (status < 0) 450 break; 451 452 /* Force the OC out of sync */ 453 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); 454 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); 455 if (status < 0) 456 break; 457 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); 458 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; 459 ocModeLop |= 0x2; /* Magically-out-of-sync */ 460 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); 461 if (status < 0) 462 break; 463 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); 464 if (status < 0) 465 break; 466 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); 467 if (status < 0) 468 break; 469 } while (0); 470 471 return status; 472 } 473 474 static int StartOC(struct drxd_state *state) 475 { 476 int status = 0; 477 478 do { 479 /* Stop OC */ 480 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); 481 if (status < 0) 482 break; 483 484 /* Restore output configuration */ 485 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); 486 if (status < 0) 487 break; 488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); 489 if (status < 0) 490 break; 491 492 /* Output pins active again */ 493 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); 494 if (status < 0) 495 break; 496 497 /* Start OC */ 498 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); 499 if (status < 0) 500 break; 501 } while (0); 502 return status; 503 } 504 505 static int InitEQ(struct drxd_state *state) 506 { 507 return WriteTable(state, state->m_InitEQ); 508 } 509 510 static int InitEC(struct drxd_state *state) 511 { 512 return WriteTable(state, state->m_InitEC); 513 } 514 515 static int InitSC(struct drxd_state *state) 516 { 517 return WriteTable(state, state->m_InitSC); 518 } 519 520 static int InitAtomicRead(struct drxd_state *state) 521 { 522 return WriteTable(state, state->m_InitAtomicRead); 523 } 524 525 static int CorrectSysClockDeviation(struct drxd_state *state); 526 527 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) 528 { 529 u16 ScRaRamLock = 0; 530 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M | 531 SC_RA_RAM_LOCK_FEC__M | 532 SC_RA_RAM_LOCK_DEMOD__M); 533 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M | 534 SC_RA_RAM_LOCK_DEMOD__M); 535 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M; 536 537 int status; 538 539 *pLockStatus = 0; 540 541 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); 542 if (status < 0) { 543 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); 544 return status; 545 } 546 547 if (state->drxd_state != DRXD_STARTED) 548 return 0; 549 550 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { 551 *pLockStatus |= DRX_LOCK_MPEG; 552 CorrectSysClockDeviation(state); 553 } 554 555 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) 556 *pLockStatus |= DRX_LOCK_FEC; 557 558 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) 559 *pLockStatus |= DRX_LOCK_DEMOD; 560 return 0; 561 } 562 563 /****************************************************************************/ 564 565 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) 566 { 567 int status; 568 569 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) 570 return -1; 571 572 if (cfg->ctrlMode == AGC_CTRL_USER) { 573 do { 574 u16 FeAgRegPm1AgcWri; 575 u16 FeAgRegAgModeLop; 576 577 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); 578 if (status < 0) 579 break; 580 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 581 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; 582 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); 583 if (status < 0) 584 break; 585 586 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & 587 FE_AG_REG_PM1_AGC_WRI__M); 588 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); 589 if (status < 0) 590 break; 591 } while (0); 592 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { 593 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || 594 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || 595 ((cfg->speed) > DRXD_FE_CTRL_MAX) || 596 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) 597 ) 598 return -1; 599 do { 600 u16 FeAgRegAgModeLop; 601 u16 FeAgRegEgcSetLvl; 602 u16 slope, offset; 603 604 /* == Mode == */ 605 606 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); 607 if (status < 0) 608 break; 609 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 610 FeAgRegAgModeLop |= 611 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; 612 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); 613 if (status < 0) 614 break; 615 616 /* == Settle level == */ 617 618 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & 619 FE_AG_REG_EGC_SET_LVL__M); 620 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); 621 if (status < 0) 622 break; 623 624 /* == Min/Max == */ 625 626 slope = (u16) ((cfg->maxOutputLevel - 627 cfg->minOutputLevel) / 2); 628 offset = (u16) ((cfg->maxOutputLevel + 629 cfg->minOutputLevel) / 2 - 511); 630 631 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); 632 if (status < 0) 633 break; 634 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); 635 if (status < 0) 636 break; 637 638 /* == Speed == */ 639 { 640 const u16 maxRur = 8; 641 static const u16 slowIncrDecLUT[] = { 642 3, 4, 4, 5, 6 }; 643 static const u16 fastIncrDecLUT[] = { 644 14, 15, 15, 16, 645 17, 18, 18, 19, 646 20, 21, 22, 23, 647 24, 26, 27, 28, 648 29, 31 649 }; 650 651 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) / 652 (maxRur + 1); 653 u16 fineSpeed = (u16) (cfg->speed - 654 ((cfg->speed / 655 fineSteps) * 656 fineSteps)); 657 u16 invRurCount = (u16) (cfg->speed / 658 fineSteps); 659 u16 rurCount; 660 if (invRurCount > maxRur) { 661 rurCount = 0; 662 fineSpeed += fineSteps; 663 } else { 664 rurCount = maxRur - invRurCount; 665 } 666 667 /* 668 fastInc = default * 669 (2^(fineSpeed/fineSteps)) 670 => range[default...2*default> 671 slowInc = default * 672 (2^(fineSpeed/fineSteps)) 673 */ 674 { 675 u16 fastIncrDec = 676 fastIncrDecLUT[fineSpeed / 677 ((fineSteps / 678 (14 + 1)) + 1)]; 679 u16 slowIncrDec = 680 slowIncrDecLUT[fineSpeed / 681 (fineSteps / 682 (3 + 1))]; 683 684 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); 685 if (status < 0) 686 break; 687 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); 688 if (status < 0) 689 break; 690 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); 691 if (status < 0) 692 break; 693 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); 694 if (status < 0) 695 break; 696 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); 697 if (status < 0) 698 break; 699 } 700 } 701 } while (0); 702 703 } else { 704 /* No OFF mode for IF control */ 705 return -1; 706 } 707 return status; 708 } 709 710 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) 711 { 712 int status = 0; 713 714 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) 715 return -1; 716 717 if (cfg->ctrlMode == AGC_CTRL_USER) { 718 do { 719 u16 AgModeLop = 0; 720 u16 level = (cfg->outputLevel); 721 722 if (level == DRXD_FE_CTRL_MAX) 723 level++; 724 725 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); 726 if (status < 0) 727 break; 728 729 /*==== Mode ====*/ 730 731 /* Powerdown PD2, WRI source */ 732 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 733 state->m_FeAgRegAgPwd |= 734 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 735 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); 736 if (status < 0) 737 break; 738 739 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 740 if (status < 0) 741 break; 742 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 743 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 744 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 745 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 746 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 747 if (status < 0) 748 break; 749 750 /* enable AGC2 pin */ 751 { 752 u16 FeAgRegAgAgcSio = 0; 753 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 754 if (status < 0) 755 break; 756 FeAgRegAgAgcSio &= 757 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 758 FeAgRegAgAgcSio |= 759 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 760 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 761 if (status < 0) 762 break; 763 } 764 765 } while (0); 766 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { 767 u16 AgModeLop = 0; 768 769 do { 770 u16 level; 771 /* Automatic control */ 772 /* Powerup PD2, AGC2 as output, TGC source */ 773 (state->m_FeAgRegAgPwd) &= 774 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 775 (state->m_FeAgRegAgPwd) |= 776 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 777 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); 778 if (status < 0) 779 break; 780 781 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 782 if (status < 0) 783 break; 784 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 785 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 786 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 787 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC); 788 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 789 if (status < 0) 790 break; 791 /* Settle level */ 792 level = (((cfg->settleLevel) >> 4) & 793 FE_AG_REG_TGC_SET_LVL__M); 794 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); 795 if (status < 0) 796 break; 797 798 /* Min/max: don't care */ 799 800 /* Speed: TODO */ 801 802 /* enable AGC2 pin */ 803 { 804 u16 FeAgRegAgAgcSio = 0; 805 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 806 if (status < 0) 807 break; 808 FeAgRegAgAgcSio &= 809 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 810 FeAgRegAgAgcSio |= 811 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 812 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 813 if (status < 0) 814 break; 815 } 816 817 } while (0); 818 } else { 819 u16 AgModeLop = 0; 820 821 do { 822 /* No RF AGC control */ 823 /* Powerdown PD2, AGC2 as output, WRI source */ 824 (state->m_FeAgRegAgPwd) &= 825 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 826 (state->m_FeAgRegAgPwd) |= 827 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; 828 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); 829 if (status < 0) 830 break; 831 832 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 833 if (status < 0) 834 break; 835 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 836 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 837 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 838 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 839 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 840 if (status < 0) 841 break; 842 843 /* set FeAgRegAgAgcSio AGC2 (RF) as input */ 844 { 845 u16 FeAgRegAgAgcSio = 0; 846 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 847 if (status < 0) 848 break; 849 FeAgRegAgAgcSio &= 850 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 851 FeAgRegAgAgcSio |= 852 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; 853 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 854 if (status < 0) 855 break; 856 } 857 } while (0); 858 } 859 return status; 860 } 861 862 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) 863 { 864 int status = 0; 865 866 *pValue = 0; 867 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { 868 u16 Value; 869 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); 870 Value &= FE_AG_REG_GC1_AGC_DAT__M; 871 if (status >= 0) { 872 /* 3.3V 873 | 874 R1 875 | 876 Vin - R3 - * -- Vout 877 | 878 R2 879 | 880 GND 881 */ 882 u32 R1 = state->if_agc_cfg.R1; 883 u32 R2 = state->if_agc_cfg.R2; 884 u32 R3 = state->if_agc_cfg.R3; 885 886 u32 Vmax, Rpar, Vmin, Vout; 887 888 if (R2 == 0 && (R1 == 0 || R3 == 0)) 889 return 0; 890 891 Vmax = (3300 * R2) / (R1 + R2); 892 Rpar = (R2 * R3) / (R3 + R2); 893 Vmin = (3300 * Rpar) / (R1 + Rpar); 894 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024; 895 896 *pValue = Vout; 897 } 898 } 899 return status; 900 } 901 902 static int load_firmware(struct drxd_state *state, const char *fw_name) 903 { 904 const struct firmware *fw; 905 906 if (request_firmware(&fw, fw_name, state->dev) < 0) { 907 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name); 908 return -EIO; 909 } 910 911 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); 912 if (!state->microcode) { 913 release_firmware(fw); 914 return -ENOMEM; 915 } 916 917 state->microcode_length = fw->size; 918 release_firmware(fw); 919 return 0; 920 } 921 922 static int DownloadMicrocode(struct drxd_state *state, 923 const u8 *pMCImage, u32 Length) 924 { 925 u8 *pSrc; 926 u32 Address; 927 u16 nBlocks; 928 u16 BlockSize; 929 u32 offset = 0; 930 int i, status = 0; 931 932 pSrc = (u8 *) pMCImage; 933 /* We're not using Flags */ 934 /* Flags = (pSrc[0] << 8) | pSrc[1]; */ 935 pSrc += sizeof(u16); 936 offset += sizeof(u16); 937 nBlocks = (pSrc[0] << 8) | pSrc[1]; 938 pSrc += sizeof(u16); 939 offset += sizeof(u16); 940 941 for (i = 0; i < nBlocks; i++) { 942 Address = (pSrc[0] << 24) | (pSrc[1] << 16) | 943 (pSrc[2] << 8) | pSrc[3]; 944 pSrc += sizeof(u32); 945 offset += sizeof(u32); 946 947 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); 948 pSrc += sizeof(u16); 949 offset += sizeof(u16); 950 951 /* We're not using Flags */ 952 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */ 953 pSrc += sizeof(u16); 954 offset += sizeof(u16); 955 956 /* We're not using BlockCRC */ 957 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */ 958 pSrc += sizeof(u16); 959 offset += sizeof(u16); 960 961 status = WriteBlock(state, Address, BlockSize, 962 pSrc, DRX_I2C_CLEARCRC); 963 if (status < 0) 964 break; 965 pSrc += BlockSize; 966 offset += BlockSize; 967 } 968 969 return status; 970 } 971 972 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) 973 { 974 u32 nrRetries = 0; 975 u16 waitCmd; 976 int status; 977 978 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); 979 if (status < 0) 980 return status; 981 982 do { 983 nrRetries += 1; 984 if (nrRetries > DRXD_MAX_RETRIES) { 985 status = -1; 986 break; 987 } 988 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); 989 } while (waitCmd != 0); 990 991 if (status >= 0) 992 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); 993 return status; 994 } 995 996 static int HI_CfgCommand(struct drxd_state *state) 997 { 998 int status = 0; 999 1000 mutex_lock(&state->mutex); 1001 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1002 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); 1003 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); 1004 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); 1005 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); 1006 1007 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1008 1009 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == 1010 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) 1011 status = Write16(state, HI_RA_RAM_SRV_CMD__A, 1012 HI_RA_RAM_SRV_CMD_CONFIG, 0); 1013 else 1014 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); 1015 mutex_unlock(&state->mutex); 1016 return status; 1017 } 1018 1019 static int InitHI(struct drxd_state *state) 1020 { 1021 state->hi_cfg_wakeup_key = (state->chip_adr); 1022 /* port/bridge/power down ctrl */ 1023 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; 1024 return HI_CfgCommand(state); 1025 } 1026 1027 static int HI_ResetCommand(struct drxd_state *state) 1028 { 1029 int status; 1030 1031 mutex_lock(&state->mutex); 1032 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, 1033 HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1034 if (status == 0) 1035 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); 1036 mutex_unlock(&state->mutex); 1037 msleep(1); 1038 return status; 1039 } 1040 1041 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) 1042 { 1043 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); 1044 if (bEnableBridge) 1045 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; 1046 else 1047 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; 1048 1049 return HI_CfgCommand(state); 1050 } 1051 1052 #define HI_TR_WRITE 0x9 1053 #define HI_TR_READ 0xA 1054 #define HI_TR_READ_WRITE 0xB 1055 #define HI_TR_BROADCAST 0x4 1056 1057 #if 0 1058 static int AtomicReadBlock(struct drxd_state *state, 1059 u32 Addr, u16 DataSize, u8 *pData, u8 Flags) 1060 { 1061 int status; 1062 int i = 0; 1063 1064 /* Parameter check */ 1065 if ((!pData) || ((DataSize & 1) != 0)) 1066 return -1; 1067 1068 mutex_lock(&state->mutex); 1069 1070 do { 1071 /* Instruct HI to read n bytes */ 1072 /* TODO use proper names forthese egisters */ 1073 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0); 1074 if (status < 0) 1075 break; 1076 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0); 1077 if (status < 0) 1078 break; 1079 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0); 1080 if (status < 0) 1081 break; 1082 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0); 1083 if (status < 0) 1084 break; 1085 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0); 1086 if (status < 0) 1087 break; 1088 1089 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0); 1090 if (status < 0) 1091 break; 1092 1093 } while (0); 1094 1095 if (status >= 0) { 1096 for (i = 0; i < (DataSize / 2); i += 1) { 1097 u16 word; 1098 1099 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i), 1100 &word, 0); 1101 if (status < 0) 1102 break; 1103 pData[2 * i] = (u8) (word & 0xFF); 1104 pData[(2 * i) + 1] = (u8) (word >> 8); 1105 } 1106 } 1107 mutex_unlock(&state->mutex); 1108 return status; 1109 } 1110 1111 static int AtomicReadReg32(struct drxd_state *state, 1112 u32 Addr, u32 *pData, u8 Flags) 1113 { 1114 u8 buf[sizeof(u32)]; 1115 int status; 1116 1117 if (!pData) 1118 return -1; 1119 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags); 1120 *pData = (((u32) buf[0]) << 0) + 1121 (((u32) buf[1]) << 8) + 1122 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); 1123 return status; 1124 } 1125 #endif 1126 1127 static int StopAllProcessors(struct drxd_state *state) 1128 { 1129 return Write16(state, HI_COMM_EXEC__A, 1130 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST); 1131 } 1132 1133 static int EnableAndResetMB(struct drxd_state *state) 1134 { 1135 if (state->type_A) { 1136 /* disable? monitor bus observe @ EC_OC */ 1137 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); 1138 } 1139 1140 /* do inverse broadcast, followed by explicit write to HI */ 1141 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); 1142 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); 1143 return 0; 1144 } 1145 1146 static int InitCC(struct drxd_state *state) 1147 { 1148 if (state->osc_clock_freq == 0 || 1149 state->osc_clock_freq > 20000 || 1150 (state->osc_clock_freq % 4000) != 0) { 1151 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); 1152 return -1; 1153 } 1154 1155 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); 1156 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | 1157 CC_REG_PLL_MODE_PUMP_CUR_12, 0); 1158 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); 1159 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); 1160 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); 1161 1162 return 0; 1163 } 1164 1165 static int ResetECOD(struct drxd_state *state) 1166 { 1167 int status = 0; 1168 1169 if (state->type_A) 1170 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); 1171 else 1172 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); 1173 1174 if (!(status < 0)) 1175 status = WriteTable(state, state->m_ResetECRAM); 1176 if (!(status < 0)) 1177 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); 1178 return status; 1179 } 1180 1181 /* Configure PGA switch */ 1182 1183 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) 1184 { 1185 int status; 1186 u16 AgModeLop = 0; 1187 u16 AgModeHip = 0; 1188 do { 1189 if (pgaSwitch) { 1190 /* PGA on */ 1191 /* fine gain */ 1192 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 1193 if (status < 0) 1194 break; 1195 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1196 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; 1197 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 1198 if (status < 0) 1199 break; 1200 1201 /* coarse gain */ 1202 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); 1203 if (status < 0) 1204 break; 1205 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1206 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC; 1207 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); 1208 if (status < 0) 1209 break; 1210 1211 /* enable fine and coarse gain, enable AAF, 1212 no ext resistor */ 1213 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000); 1214 if (status < 0) 1215 break; 1216 } else { 1217 /* PGA off, bypass */ 1218 1219 /* fine gain */ 1220 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 1221 if (status < 0) 1222 break; 1223 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1224 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC; 1225 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 1226 if (status < 0) 1227 break; 1228 1229 /* coarse gain */ 1230 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); 1231 if (status < 0) 1232 break; 1233 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1234 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC; 1235 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); 1236 if (status < 0) 1237 break; 1238 1239 /* disable fine and coarse gain, enable AAF, 1240 no ext resistor */ 1241 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000); 1242 if (status < 0) 1243 break; 1244 } 1245 } while (0); 1246 return status; 1247 } 1248 1249 static int InitFE(struct drxd_state *state) 1250 { 1251 int status; 1252 1253 do { 1254 status = WriteTable(state, state->m_InitFE_1); 1255 if (status < 0) 1256 break; 1257 1258 if (state->type_A) { 1259 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, 1260 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1261 0); 1262 } else { 1263 if (state->PGA) 1264 status = SetCfgPga(state, 0); 1265 else 1266 status = 1267 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, 1268 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1269 0); 1270 } 1271 1272 if (status < 0) 1273 break; 1274 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); 1275 if (status < 0) 1276 break; 1277 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); 1278 if (status < 0) 1279 break; 1280 1281 status = WriteTable(state, state->m_InitFE_2); 1282 if (status < 0) 1283 break; 1284 1285 } while (0); 1286 1287 return status; 1288 } 1289 1290 static int InitFT(struct drxd_state *state) 1291 { 1292 /* 1293 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk 1294 SC stuff 1295 */ 1296 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); 1297 } 1298 1299 static int SC_WaitForReady(struct drxd_state *state) 1300 { 1301 u16 curCmd; 1302 int i; 1303 1304 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) { 1305 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); 1306 if (status == 0 || curCmd == 0) 1307 return status; 1308 } 1309 return -1; 1310 } 1311 1312 static int SC_SendCommand(struct drxd_state *state, u16 cmd) 1313 { 1314 int status = 0; 1315 u16 errCode; 1316 1317 Write16(state, SC_RA_RAM_CMD__A, cmd, 0); 1318 SC_WaitForReady(state); 1319 1320 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); 1321 1322 if (errCode == 0xFFFF) { 1323 printk(KERN_ERR "Command Error\n"); 1324 status = -1; 1325 } 1326 1327 return status; 1328 } 1329 1330 static int SC_ProcStartCommand(struct drxd_state *state, 1331 u16 subCmd, u16 param0, u16 param1) 1332 { 1333 int status = 0; 1334 u16 scExec; 1335 1336 mutex_lock(&state->mutex); 1337 do { 1338 Read16(state, SC_COMM_EXEC__A, &scExec, 0); 1339 if (scExec != 1) { 1340 status = -1; 1341 break; 1342 } 1343 SC_WaitForReady(state); 1344 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); 1345 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); 1346 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); 1347 1348 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); 1349 } while (0); 1350 mutex_unlock(&state->mutex); 1351 return status; 1352 } 1353 1354 static int SC_SetPrefParamCommand(struct drxd_state *state, 1355 u16 subCmd, u16 param0, u16 param1) 1356 { 1357 int status; 1358 1359 mutex_lock(&state->mutex); 1360 do { 1361 status = SC_WaitForReady(state); 1362 if (status < 0) 1363 break; 1364 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); 1365 if (status < 0) 1366 break; 1367 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); 1368 if (status < 0) 1369 break; 1370 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); 1371 if (status < 0) 1372 break; 1373 1374 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); 1375 if (status < 0) 1376 break; 1377 } while (0); 1378 mutex_unlock(&state->mutex); 1379 return status; 1380 } 1381 1382 #if 0 1383 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result) 1384 { 1385 int status = 0; 1386 1387 mutex_lock(&state->mutex); 1388 do { 1389 status = SC_WaitForReady(state); 1390 if (status < 0) 1391 break; 1392 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM); 1393 if (status < 0) 1394 break; 1395 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0); 1396 if (status < 0) 1397 break; 1398 } while (0); 1399 mutex_unlock(&state->mutex); 1400 return status; 1401 } 1402 #endif 1403 1404 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) 1405 { 1406 int status; 1407 1408 do { 1409 u16 EcOcRegIprInvMpg = 0; 1410 u16 EcOcRegOcModeLop = 0; 1411 u16 EcOcRegOcModeHip = 0; 1412 u16 EcOcRegOcMpgSio = 0; 1413 1414 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */ 1415 1416 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1417 if (bEnableOutput) { 1418 EcOcRegOcModeHip |= 1419 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; 1420 } else 1421 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1422 EcOcRegOcModeLop |= 1423 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1424 } else { 1425 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; 1426 1427 if (bEnableOutput) 1428 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M)); 1429 else 1430 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1431 1432 /* Don't Insert RS Byte */ 1433 if (state->insert_rs_byte) { 1434 EcOcRegOcModeLop &= 1435 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); 1436 EcOcRegOcModeHip &= 1437 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1438 EcOcRegOcModeHip |= 1439 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE; 1440 } else { 1441 EcOcRegOcModeLop |= 1442 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1443 EcOcRegOcModeHip &= 1444 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1445 EcOcRegOcModeHip |= 1446 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE; 1447 } 1448 1449 /* Mode = Parallel */ 1450 if (state->enable_parallel) 1451 EcOcRegOcModeLop &= 1452 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M)); 1453 else 1454 EcOcRegOcModeLop |= 1455 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL; 1456 } 1457 /* Invert Data */ 1458 /* EcOcRegIprInvMpg |= 0x00FF; */ 1459 EcOcRegIprInvMpg &= (~(0x00FF)); 1460 1461 /* Invert Error ( we don't use the pin ) */ 1462 /* EcOcRegIprInvMpg |= 0x0100; */ 1463 EcOcRegIprInvMpg &= (~(0x0100)); 1464 1465 /* Invert Start ( we don't use the pin ) */ 1466 /* EcOcRegIprInvMpg |= 0x0200; */ 1467 EcOcRegIprInvMpg &= (~(0x0200)); 1468 1469 /* Invert Valid ( we don't use the pin ) */ 1470 /* EcOcRegIprInvMpg |= 0x0400; */ 1471 EcOcRegIprInvMpg &= (~(0x0400)); 1472 1473 /* Invert Clock */ 1474 /* EcOcRegIprInvMpg |= 0x0800; */ 1475 EcOcRegIprInvMpg &= (~(0x0800)); 1476 1477 /* EcOcRegOcModeLop =0x05; */ 1478 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); 1479 if (status < 0) 1480 break; 1481 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); 1482 if (status < 0) 1483 break; 1484 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); 1485 if (status < 0) 1486 break; 1487 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); 1488 if (status < 0) 1489 break; 1490 } while (0); 1491 return status; 1492 } 1493 1494 static int SetDeviceTypeId(struct drxd_state *state) 1495 { 1496 int status = 0; 1497 u16 deviceId = 0; 1498 1499 do { 1500 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); 1501 if (status < 0) 1502 break; 1503 /* TODO: why twice? */ 1504 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); 1505 if (status < 0) 1506 break; 1507 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId); 1508 1509 state->type_A = 0; 1510 state->PGA = 0; 1511 state->diversity = 0; 1512 if (deviceId == 0) { /* on A2 only 3975 available */ 1513 state->type_A = 1; 1514 printk(KERN_INFO "DRX3975D-A2\n"); 1515 } else { 1516 deviceId >>= 12; 1517 printk(KERN_INFO "DRX397%dD-B1\n", deviceId); 1518 switch (deviceId) { 1519 case 4: 1520 state->diversity = 1; 1521 /* fall through */ 1522 case 3: 1523 case 7: 1524 state->PGA = 1; 1525 break; 1526 case 6: 1527 state->diversity = 1; 1528 /* fall through */ 1529 case 5: 1530 case 8: 1531 break; 1532 default: 1533 status = -1; 1534 break; 1535 } 1536 } 1537 } while (0); 1538 1539 if (status < 0) 1540 return status; 1541 1542 /* Init Table selection */ 1543 state->m_InitAtomicRead = DRXD_InitAtomicRead; 1544 state->m_InitSC = DRXD_InitSC; 1545 state->m_ResetECRAM = DRXD_ResetECRAM; 1546 if (state->type_A) { 1547 state->m_ResetCEFR = DRXD_ResetCEFR; 1548 state->m_InitFE_1 = DRXD_InitFEA2_1; 1549 state->m_InitFE_2 = DRXD_InitFEA2_2; 1550 state->m_InitCP = DRXD_InitCPA2; 1551 state->m_InitCE = DRXD_InitCEA2; 1552 state->m_InitEQ = DRXD_InitEQA2; 1553 state->m_InitEC = DRXD_InitECA2; 1554 if (load_firmware(state, DRX_FW_FILENAME_A2)) 1555 return -EIO; 1556 } else { 1557 state->m_ResetCEFR = NULL; 1558 state->m_InitFE_1 = DRXD_InitFEB1_1; 1559 state->m_InitFE_2 = DRXD_InitFEB1_2; 1560 state->m_InitCP = DRXD_InitCPB1; 1561 state->m_InitCE = DRXD_InitCEB1; 1562 state->m_InitEQ = DRXD_InitEQB1; 1563 state->m_InitEC = DRXD_InitECB1; 1564 if (load_firmware(state, DRX_FW_FILENAME_B1)) 1565 return -EIO; 1566 } 1567 if (state->diversity) { 1568 state->m_InitDiversityFront = DRXD_InitDiversityFront; 1569 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; 1570 state->m_DisableDiversity = DRXD_DisableDiversity; 1571 state->m_StartDiversityFront = DRXD_StartDiversityFront; 1572 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; 1573 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; 1574 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; 1575 } else { 1576 state->m_InitDiversityFront = NULL; 1577 state->m_InitDiversityEnd = NULL; 1578 state->m_DisableDiversity = NULL; 1579 state->m_StartDiversityFront = NULL; 1580 state->m_StartDiversityEnd = NULL; 1581 state->m_DiversityDelay8MHZ = NULL; 1582 state->m_DiversityDelay6MHZ = NULL; 1583 } 1584 1585 return status; 1586 } 1587 1588 static int CorrectSysClockDeviation(struct drxd_state *state) 1589 { 1590 int status; 1591 s32 incr = 0; 1592 s32 nomincr = 0; 1593 u32 bandwidth = 0; 1594 u32 sysClockInHz = 0; 1595 u32 sysClockFreq = 0; /* in kHz */ 1596 s16 oscClockDeviation; 1597 s16 Diff; 1598 1599 do { 1600 /* Retrieve bandwidth and incr, sanity check */ 1601 1602 /* These accesses should be AtomicReadReg32, but that 1603 causes trouble (at least for diversity */ 1604 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); 1605 if (status < 0) 1606 break; 1607 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); 1608 if (status < 0) 1609 break; 1610 1611 if (state->type_A) { 1612 if ((nomincr - incr < -500) || (nomincr - incr > 500)) 1613 break; 1614 } else { 1615 if ((nomincr - incr < -2000) || (nomincr - incr > 2000)) 1616 break; 1617 } 1618 1619 switch (state->props.bandwidth_hz) { 1620 case 8000000: 1621 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 1622 break; 1623 case 7000000: 1624 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 1625 break; 1626 case 6000000: 1627 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 1628 break; 1629 default: 1630 return -1; 1631 break; 1632 } 1633 1634 /* Compute new sysclock value 1635 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */ 1636 incr += (1 << 23); 1637 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21); 1638 sysClockFreq = (u32) (sysClockInHz / 1000); 1639 /* rounding */ 1640 if ((sysClockInHz % 1000) > 500) 1641 sysClockFreq++; 1642 1643 /* Compute clock deviation in ppm */ 1644 oscClockDeviation = (u16) ((((s32) (sysClockFreq) - 1645 (s32) 1646 (state->expected_sys_clock_freq)) * 1647 1000000L) / 1648 (s32) 1649 (state->expected_sys_clock_freq)); 1650 1651 Diff = oscClockDeviation - state->osc_clock_deviation; 1652 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */ 1653 if (Diff >= -200 && Diff <= 200) { 1654 state->sys_clock_freq = (u16) sysClockFreq; 1655 if (oscClockDeviation != state->osc_clock_deviation) { 1656 if (state->config.osc_deviation) { 1657 state->config.osc_deviation(state->priv, 1658 oscClockDeviation, 1659 1); 1660 state->osc_clock_deviation = 1661 oscClockDeviation; 1662 } 1663 } 1664 /* switch OFF SRMM scan in SC */ 1665 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); 1666 if (status < 0) 1667 break; 1668 /* overrule FE_IF internal value for 1669 proper re-locking */ 1670 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); 1671 if (status < 0) 1672 break; 1673 state->cscd_state = CSCD_SAVED; 1674 } 1675 } while (0); 1676 1677 return status; 1678 } 1679 1680 static int DRX_Stop(struct drxd_state *state) 1681 { 1682 int status; 1683 1684 if (state->drxd_state != DRXD_STARTED) 1685 return 0; 1686 1687 do { 1688 if (state->cscd_state != CSCD_SAVED) { 1689 u32 lock; 1690 status = DRX_GetLockStatus(state, &lock); 1691 if (status < 0) 1692 break; 1693 } 1694 1695 status = StopOC(state); 1696 if (status < 0) 1697 break; 1698 1699 state->drxd_state = DRXD_STOPPED; 1700 1701 status = ConfigureMPEGOutput(state, 0); 1702 if (status < 0) 1703 break; 1704 1705 if (state->type_A) { 1706 /* Stop relevant processors off the device */ 1707 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); 1708 if (status < 0) 1709 break; 1710 1711 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1712 if (status < 0) 1713 break; 1714 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1715 if (status < 0) 1716 break; 1717 } else { 1718 /* Stop all processors except HI & CC & FE */ 1719 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1720 if (status < 0) 1721 break; 1722 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1723 if (status < 0) 1724 break; 1725 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1726 if (status < 0) 1727 break; 1728 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1729 if (status < 0) 1730 break; 1731 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1732 if (status < 0) 1733 break; 1734 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1735 if (status < 0) 1736 break; 1737 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); 1738 if (status < 0) 1739 break; 1740 } 1741 1742 } while (0); 1743 return status; 1744 } 1745 1746 #if 0 /* Currently unused */ 1747 static int SetOperationMode(struct drxd_state *state, int oMode) 1748 { 1749 int status; 1750 1751 do { 1752 if (state->drxd_state != DRXD_STOPPED) { 1753 status = -1; 1754 break; 1755 } 1756 1757 if (oMode == state->operation_mode) { 1758 status = 0; 1759 break; 1760 } 1761 1762 if (oMode != OM_Default && !state->diversity) { 1763 status = -1; 1764 break; 1765 } 1766 1767 switch (oMode) { 1768 case OM_DVBT_Diversity_Front: 1769 status = WriteTable(state, state->m_InitDiversityFront); 1770 break; 1771 case OM_DVBT_Diversity_End: 1772 status = WriteTable(state, state->m_InitDiversityEnd); 1773 break; 1774 case OM_Default: 1775 /* We need to check how to 1776 get DRXD out of diversity */ 1777 default: 1778 status = WriteTable(state, state->m_DisableDiversity); 1779 break; 1780 } 1781 } while (0); 1782 1783 if (!status) 1784 state->operation_mode = oMode; 1785 return status; 1786 } 1787 #endif 1788 1789 static int StartDiversity(struct drxd_state *state) 1790 { 1791 int status = 0; 1792 u16 rcControl; 1793 1794 do { 1795 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1796 status = WriteTable(state, state->m_StartDiversityFront); 1797 if (status < 0) 1798 break; 1799 } else if (state->operation_mode == OM_DVBT_Diversity_End) { 1800 status = WriteTable(state, state->m_StartDiversityEnd); 1801 if (status < 0) 1802 break; 1803 if (state->props.bandwidth_hz == 8000000) { 1804 status = WriteTable(state, state->m_DiversityDelay8MHZ); 1805 if (status < 0) 1806 break; 1807 } else { 1808 status = WriteTable(state, state->m_DiversityDelay6MHZ); 1809 if (status < 0) 1810 break; 1811 } 1812 1813 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); 1814 if (status < 0) 1815 break; 1816 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); 1817 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | 1818 /* combining enabled */ 1819 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | 1820 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | 1821 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; 1822 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); 1823 if (status < 0) 1824 break; 1825 } 1826 } while (0); 1827 return status; 1828 } 1829 1830 static int SetFrequencyShift(struct drxd_state *state, 1831 u32 offsetFreq, int channelMirrored) 1832 { 1833 int negativeShift = (state->tuner_mirrors == channelMirrored); 1834 1835 /* Handle all mirroring 1836 * 1837 * Note: ADC mirroring (aliasing) is implictly handled by limiting 1838 * feFsRegAddInc to 28 bits below 1839 * (if the result before masking is more than 28 bits, this means 1840 * that the ADC is mirroring. 1841 * The masking is in fact the aliasing of the ADC) 1842 * 1843 */ 1844 1845 /* Compute register value, unsigned computation */ 1846 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + 1847 offsetFreq, 1848 1 << 28, state->sys_clock_freq); 1849 /* Remove integer part */ 1850 state->fe_fs_add_incr &= 0x0FFFFFFFL; 1851 if (negativeShift) 1852 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); 1853 1854 /* Save the frequency shift without tunerOffset compensation 1855 for CtrlGetChannel. */ 1856 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, 1857 1 << 28, state->sys_clock_freq); 1858 /* Remove integer part */ 1859 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; 1860 if (negativeShift) 1861 state->org_fe_fs_add_incr = ((1L << 28) - 1862 state->org_fe_fs_add_incr); 1863 1864 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, 1865 state->fe_fs_add_incr, 0); 1866 } 1867 1868 static int SetCfgNoiseCalibration(struct drxd_state *state, 1869 struct SNoiseCal *noiseCal) 1870 { 1871 u16 beOptEna; 1872 int status = 0; 1873 1874 do { 1875 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); 1876 if (status < 0) 1877 break; 1878 if (noiseCal->cpOpt) { 1879 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1880 } else { 1881 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1882 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); 1883 if (status < 0) 1884 break; 1885 } 1886 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); 1887 if (status < 0) 1888 break; 1889 1890 if (!state->type_A) { 1891 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); 1892 if (status < 0) 1893 break; 1894 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); 1895 if (status < 0) 1896 break; 1897 } 1898 } while (0); 1899 1900 return status; 1901 } 1902 1903 static int DRX_Start(struct drxd_state *state, s32 off) 1904 { 1905 struct dtv_frontend_properties *p = &state->props; 1906 int status; 1907 1908 u16 transmissionParams = 0; 1909 u16 operationMode = 0; 1910 u16 qpskTdTpsPwr = 0; 1911 u16 qam16TdTpsPwr = 0; 1912 u16 qam64TdTpsPwr = 0; 1913 u32 feIfIncr = 0; 1914 u32 bandwidth = 0; 1915 int mirrorFreqSpect; 1916 1917 u16 qpskSnCeGain = 0; 1918 u16 qam16SnCeGain = 0; 1919 u16 qam64SnCeGain = 0; 1920 u16 qpskIsGainMan = 0; 1921 u16 qam16IsGainMan = 0; 1922 u16 qam64IsGainMan = 0; 1923 u16 qpskIsGainExp = 0; 1924 u16 qam16IsGainExp = 0; 1925 u16 qam64IsGainExp = 0; 1926 u16 bandwidthParam = 0; 1927 1928 if (off < 0) 1929 off = (off - 500) / 1000; 1930 else 1931 off = (off + 500) / 1000; 1932 1933 do { 1934 if (state->drxd_state != DRXD_STOPPED) 1935 return -1; 1936 status = ResetECOD(state); 1937 if (status < 0) 1938 break; 1939 if (state->type_A) { 1940 status = InitSC(state); 1941 if (status < 0) 1942 break; 1943 } else { 1944 status = InitFT(state); 1945 if (status < 0) 1946 break; 1947 status = InitCP(state); 1948 if (status < 0) 1949 break; 1950 status = InitCE(state); 1951 if (status < 0) 1952 break; 1953 status = InitEQ(state); 1954 if (status < 0) 1955 break; 1956 status = InitSC(state); 1957 if (status < 0) 1958 break; 1959 } 1960 1961 /* Restore current IF & RF AGC settings */ 1962 1963 status = SetCfgIfAgc(state, &state->if_agc_cfg); 1964 if (status < 0) 1965 break; 1966 status = SetCfgRfAgc(state, &state->rf_agc_cfg); 1967 if (status < 0) 1968 break; 1969 1970 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); 1971 1972 switch (p->transmission_mode) { 1973 default: /* Not set, detect it automatically */ 1974 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M; 1975 /* try first guess DRX_FFTMODE_8K */ 1976 /* fall through */ 1977 case TRANSMISSION_MODE_8K: 1978 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; 1979 if (state->type_A) { 1980 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); 1981 if (status < 0) 1982 break; 1983 qpskSnCeGain = 99; 1984 qam16SnCeGain = 83; 1985 qam64SnCeGain = 67; 1986 } 1987 break; 1988 case TRANSMISSION_MODE_2K: 1989 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; 1990 if (state->type_A) { 1991 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); 1992 if (status < 0) 1993 break; 1994 qpskSnCeGain = 97; 1995 qam16SnCeGain = 71; 1996 qam64SnCeGain = 65; 1997 } 1998 break; 1999 } 2000 2001 switch (p->guard_interval) { 2002 case GUARD_INTERVAL_1_4: 2003 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 2004 break; 2005 case GUARD_INTERVAL_1_8: 2006 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8; 2007 break; 2008 case GUARD_INTERVAL_1_16: 2009 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16; 2010 break; 2011 case GUARD_INTERVAL_1_32: 2012 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32; 2013 break; 2014 default: /* Not set, detect it automatically */ 2015 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M; 2016 /* try first guess 1/4 */ 2017 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 2018 break; 2019 } 2020 2021 switch (p->hierarchy) { 2022 case HIERARCHY_1: 2023 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; 2024 if (state->type_A) { 2025 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); 2026 if (status < 0) 2027 break; 2028 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); 2029 if (status < 0) 2030 break; 2031 2032 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2033 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; 2034 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1; 2035 2036 qpskIsGainMan = 2037 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2038 qam16IsGainMan = 2039 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 2040 qam64IsGainMan = 2041 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 2042 2043 qpskIsGainExp = 2044 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2045 qam16IsGainExp = 2046 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 2047 qam64IsGainExp = 2048 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 2049 } 2050 break; 2051 2052 case HIERARCHY_2: 2053 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; 2054 if (state->type_A) { 2055 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); 2056 if (status < 0) 2057 break; 2058 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); 2059 if (status < 0) 2060 break; 2061 2062 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2063 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; 2064 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2; 2065 2066 qpskIsGainMan = 2067 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2068 qam16IsGainMan = 2069 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE; 2070 qam64IsGainMan = 2071 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE; 2072 2073 qpskIsGainExp = 2074 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2075 qam16IsGainExp = 2076 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE; 2077 qam64IsGainExp = 2078 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE; 2079 } 2080 break; 2081 case HIERARCHY_4: 2082 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; 2083 if (state->type_A) { 2084 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); 2085 if (status < 0) 2086 break; 2087 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); 2088 if (status < 0) 2089 break; 2090 2091 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2092 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; 2093 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4; 2094 2095 qpskIsGainMan = 2096 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2097 qam16IsGainMan = 2098 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE; 2099 qam64IsGainMan = 2100 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE; 2101 2102 qpskIsGainExp = 2103 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2104 qam16IsGainExp = 2105 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE; 2106 qam64IsGainExp = 2107 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE; 2108 } 2109 break; 2110 case HIERARCHY_AUTO: 2111 default: 2112 /* Not set, detect it automatically, start with none */ 2113 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; 2114 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; 2115 if (state->type_A) { 2116 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); 2117 if (status < 0) 2118 break; 2119 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); 2120 if (status < 0) 2121 break; 2122 2123 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; 2124 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; 2125 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN; 2126 2127 qpskIsGainMan = 2128 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE; 2129 qam16IsGainMan = 2130 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 2131 qam64IsGainMan = 2132 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 2133 2134 qpskIsGainExp = 2135 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE; 2136 qam16IsGainExp = 2137 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 2138 qam64IsGainExp = 2139 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 2140 } 2141 break; 2142 } 2143 status = status; 2144 if (status < 0) 2145 break; 2146 2147 switch (p->modulation) { 2148 default: 2149 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M; 2150 /* try first guess DRX_CONSTELLATION_QAM64 */ 2151 /* fall through */ 2152 case QAM_64: 2153 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; 2154 if (state->type_A) { 2155 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); 2156 if (status < 0) 2157 break; 2158 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); 2159 if (status < 0) 2160 break; 2161 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); 2162 if (status < 0) 2163 break; 2164 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); 2165 if (status < 0) 2166 break; 2167 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); 2168 if (status < 0) 2169 break; 2170 2171 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); 2172 if (status < 0) 2173 break; 2174 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); 2175 if (status < 0) 2176 break; 2177 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); 2178 if (status < 0) 2179 break; 2180 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); 2181 if (status < 0) 2182 break; 2183 } 2184 break; 2185 case QPSK: 2186 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; 2187 if (state->type_A) { 2188 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); 2189 if (status < 0) 2190 break; 2191 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); 2192 if (status < 0) 2193 break; 2194 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); 2195 if (status < 0) 2196 break; 2197 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); 2198 if (status < 0) 2199 break; 2200 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); 2201 if (status < 0) 2202 break; 2203 2204 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); 2205 if (status < 0) 2206 break; 2207 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); 2208 if (status < 0) 2209 break; 2210 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); 2211 if (status < 0) 2212 break; 2213 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); 2214 if (status < 0) 2215 break; 2216 } 2217 break; 2218 2219 case QAM_16: 2220 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; 2221 if (state->type_A) { 2222 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); 2223 if (status < 0) 2224 break; 2225 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); 2226 if (status < 0) 2227 break; 2228 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); 2229 if (status < 0) 2230 break; 2231 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); 2232 if (status < 0) 2233 break; 2234 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); 2235 if (status < 0) 2236 break; 2237 2238 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); 2239 if (status < 0) 2240 break; 2241 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); 2242 if (status < 0) 2243 break; 2244 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); 2245 if (status < 0) 2246 break; 2247 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); 2248 if (status < 0) 2249 break; 2250 } 2251 break; 2252 2253 } 2254 status = status; 2255 if (status < 0) 2256 break; 2257 2258 switch (DRX_CHANNEL_HIGH) { 2259 default: 2260 case DRX_CHANNEL_AUTO: 2261 case DRX_CHANNEL_LOW: 2262 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; 2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); 2264 if (status < 0) 2265 break; 2266 break; 2267 case DRX_CHANNEL_HIGH: 2268 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; 2269 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); 2270 if (status < 0) 2271 break; 2272 break; 2273 2274 } 2275 2276 switch (p->code_rate_HP) { 2277 case FEC_1_2: 2278 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; 2279 if (state->type_A) { 2280 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); 2281 if (status < 0) 2282 break; 2283 } 2284 break; 2285 default: 2286 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M; 2287 /* fall through */ 2288 case FEC_2_3: 2289 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; 2290 if (state->type_A) { 2291 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); 2292 if (status < 0) 2293 break; 2294 } 2295 break; 2296 case FEC_3_4: 2297 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; 2298 if (state->type_A) { 2299 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); 2300 if (status < 0) 2301 break; 2302 } 2303 break; 2304 case FEC_5_6: 2305 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; 2306 if (state->type_A) { 2307 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); 2308 if (status < 0) 2309 break; 2310 } 2311 break; 2312 case FEC_7_8: 2313 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; 2314 if (state->type_A) { 2315 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); 2316 if (status < 0) 2317 break; 2318 } 2319 break; 2320 } 2321 status = status; 2322 if (status < 0) 2323 break; 2324 2325 /* First determine real bandwidth (Hz) */ 2326 /* Also set delay for impulse noise cruncher (only A2) */ 2327 /* Also set parameters for EC_OC fix, note 2328 EC_OC_REG_TMD_HIL_MAR is changed 2329 by SC for fix for some 8K,1/8 guard but is restored by 2330 InitEC and ResetEC 2331 functions */ 2332 switch (p->bandwidth_hz) { 2333 case 0: 2334 p->bandwidth_hz = 8000000; 2335 /* fall through */ 2336 case 8000000: 2337 /* (64/7)*(8/8)*1000000 */ 2338 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 2339 2340 bandwidthParam = 0; 2341 status = Write16(state, 2342 FE_AG_REG_IND_DEL__A, 50, 0x0000); 2343 break; 2344 case 7000000: 2345 /* (64/7)*(7/8)*1000000 */ 2346 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 2347 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */ 2348 status = Write16(state, 2349 FE_AG_REG_IND_DEL__A, 59, 0x0000); 2350 break; 2351 case 6000000: 2352 /* (64/7)*(6/8)*1000000 */ 2353 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 2354 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */ 2355 status = Write16(state, 2356 FE_AG_REG_IND_DEL__A, 71, 0x0000); 2357 break; 2358 default: 2359 status = -EINVAL; 2360 } 2361 if (status < 0) 2362 break; 2363 2364 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); 2365 if (status < 0) 2366 break; 2367 2368 { 2369 u16 sc_config; 2370 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); 2371 if (status < 0) 2372 break; 2373 2374 /* enable SLAVE mode in 2k 1/32 to 2375 prevent timing change glitches */ 2376 if ((p->transmission_mode == TRANSMISSION_MODE_2K) && 2377 (p->guard_interval == GUARD_INTERVAL_1_32)) { 2378 /* enable slave */ 2379 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M; 2380 } else { 2381 /* disable slave */ 2382 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; 2383 } 2384 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); 2385 if (status < 0) 2386 break; 2387 } 2388 2389 status = SetCfgNoiseCalibration(state, &state->noise_cal); 2390 if (status < 0) 2391 break; 2392 2393 if (state->cscd_state == CSCD_INIT) { 2394 /* switch on SRMM scan in SC */ 2395 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); 2396 if (status < 0) 2397 break; 2398 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/ 2399 state->cscd_state = CSCD_SET; 2400 } 2401 2402 /* Now compute FE_IF_REG_INCR */ 2403 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => 2404 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ 2405 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, 2406 (1ULL << 21), bandwidth) - (1 << 23); 2407 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); 2408 if (status < 0) 2409 break; 2410 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000); 2411 if (status < 0) 2412 break; 2413 /* Bandwidth setting done */ 2414 2415 /* Mirror & frequency offset */ 2416 SetFrequencyShift(state, off, mirrorFreqSpect); 2417 2418 /* Start SC, write channel settings to SC */ 2419 2420 /* Enable SC after setting all other parameters */ 2421 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); 2422 if (status < 0) 2423 break; 2424 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); 2425 if (status < 0) 2426 break; 2427 2428 /* Write SC parameter registers, operation mode */ 2429 #if 1 2430 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M | 2431 SC_RA_RAM_OP_AUTO_GUARD__M | 2432 SC_RA_RAM_OP_AUTO_CONST__M | 2433 SC_RA_RAM_OP_AUTO_HIER__M | 2434 SC_RA_RAM_OP_AUTO_RATE__M); 2435 #endif 2436 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); 2437 if (status < 0) 2438 break; 2439 2440 /* Start correct processes to get in lock */ 2441 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN); 2442 if (status < 0) 2443 break; 2444 2445 status = StartOC(state); 2446 if (status < 0) 2447 break; 2448 2449 if (state->operation_mode != OM_Default) { 2450 status = StartDiversity(state); 2451 if (status < 0) 2452 break; 2453 } 2454 2455 state->drxd_state = DRXD_STARTED; 2456 } while (0); 2457 2458 return status; 2459 } 2460 2461 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) 2462 { 2463 u32 ulRfAgcOutputLevel = 0xffffffff; 2464 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */ 2465 u32 ulRfAgcMinLevel = 0; /* Currently unused */ 2466 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */ 2467 u32 ulRfAgcSpeed = 0; /* Currently unused */ 2468 u32 ulRfAgcMode = 0; /*2; Off */ 2469 u32 ulRfAgcR1 = 820; 2470 u32 ulRfAgcR2 = 2200; 2471 u32 ulRfAgcR3 = 150; 2472 u32 ulIfAgcMode = 0; /* Auto */ 2473 u32 ulIfAgcOutputLevel = 0xffffffff; 2474 u32 ulIfAgcSettleLevel = 0xffffffff; 2475 u32 ulIfAgcMinLevel = 0xffffffff; 2476 u32 ulIfAgcMaxLevel = 0xffffffff; 2477 u32 ulIfAgcSpeed = 0xffffffff; 2478 u32 ulIfAgcR1 = 820; 2479 u32 ulIfAgcR2 = 2200; 2480 u32 ulIfAgcR3 = 150; 2481 u32 ulClock = state->config.clock; 2482 u32 ulSerialMode = 0; 2483 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ 2484 u32 ulHiI2cDelay = HI_I2C_DELAY; 2485 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY; 2486 u32 ulHiI2cPatch = 0; 2487 u32 ulEnvironment = APPENV_PORTABLE; 2488 u32 ulEnvironmentDiversity = APPENV_MOBILE; 2489 u32 ulIFFilter = IFFILTER_SAW; 2490 2491 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2492 state->if_agc_cfg.outputLevel = 0; 2493 state->if_agc_cfg.settleLevel = 140; 2494 state->if_agc_cfg.minOutputLevel = 0; 2495 state->if_agc_cfg.maxOutputLevel = 1023; 2496 state->if_agc_cfg.speed = 904; 2497 2498 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { 2499 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; 2500 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); 2501 } 2502 2503 if (ulIfAgcMode == 0 && 2504 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2505 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2506 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2507 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) { 2508 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2509 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); 2510 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); 2511 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); 2512 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); 2513 } 2514 2515 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); 2516 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); 2517 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); 2518 2519 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); 2520 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); 2521 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); 2522 2523 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2524 /* rest of the RFAgcCfg structure currently unused */ 2525 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { 2526 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; 2527 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); 2528 } 2529 2530 if (ulRfAgcMode == 0 && 2531 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2532 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2533 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2534 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) { 2535 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2536 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); 2537 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); 2538 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); 2539 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); 2540 } 2541 2542 if (ulRfAgcMode == 2) 2543 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; 2544 2545 if (ulEnvironment <= 2) 2546 state->app_env_default = (enum app_env) 2547 (ulEnvironment); 2548 if (ulEnvironmentDiversity <= 2) 2549 state->app_env_diversity = (enum app_env) 2550 (ulEnvironmentDiversity); 2551 2552 if (ulIFFilter == IFFILTER_DISCRETE) { 2553 /* discrete filter */ 2554 state->noise_cal.cpOpt = 0; 2555 state->noise_cal.cpNexpOfs = 40; 2556 state->noise_cal.tdCal2k = -40; 2557 state->noise_cal.tdCal8k = -24; 2558 } else { 2559 /* SAW filter */ 2560 state->noise_cal.cpOpt = 1; 2561 state->noise_cal.cpNexpOfs = 0; 2562 state->noise_cal.tdCal2k = -21; 2563 state->noise_cal.tdCal8k = -24; 2564 } 2565 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); 2566 2567 state->chip_adr = (state->config.demod_address << 1) | 1; 2568 switch (ulHiI2cPatch) { 2569 case 1: 2570 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; 2571 break; 2572 case 3: 2573 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; 2574 break; 2575 default: 2576 state->m_HiI2cPatch = NULL; 2577 } 2578 2579 /* modify tuner and clock attributes */ 2580 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); 2581 /* expected system clock frequency in kHz */ 2582 state->expected_sys_clock_freq = 48000; 2583 /* real system clock frequency in kHz */ 2584 state->sys_clock_freq = 48000; 2585 state->osc_clock_freq = (u16) ulClock; 2586 state->osc_clock_deviation = 0; 2587 state->cscd_state = CSCD_INIT; 2588 state->drxd_state = DRXD_UNINITIALIZED; 2589 2590 state->PGA = 0; 2591 state->type_A = 0; 2592 state->tuner_mirrors = 0; 2593 2594 /* modify MPEG output attributes */ 2595 state->insert_rs_byte = state->config.insert_rs_byte; 2596 state->enable_parallel = (ulSerialMode != 1); 2597 2598 /* Timing div, 250ns/Psys */ 2599 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ 2600 2601 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * 2602 ulHiI2cDelay) / 1000; 2603 /* Bridge delay, uses oscilator clock */ 2604 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ 2605 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * 2606 ulHiI2cBridgeDelay) / 1000; 2607 2608 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2609 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ 2610 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; 2611 return 0; 2612 } 2613 2614 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) 2615 { 2616 int status = 0; 2617 u32 driverVersion; 2618 2619 if (state->init_done) 2620 return 0; 2621 2622 CDRXD(state, state->config.IF ? state->config.IF : 36000000); 2623 2624 do { 2625 state->operation_mode = OM_Default; 2626 2627 status = SetDeviceTypeId(state); 2628 if (status < 0) 2629 break; 2630 2631 /* Apply I2c address patch to B1 */ 2632 if (!state->type_A && state->m_HiI2cPatch) { 2633 status = WriteTable(state, state->m_HiI2cPatch); 2634 if (status < 0) 2635 break; 2636 } 2637 2638 if (state->type_A) { 2639 /* HI firmware patch for UIO readout, 2640 avoid clearing of result register */ 2641 status = Write16(state, 0x43012D, 0x047f, 0); 2642 if (status < 0) 2643 break; 2644 } 2645 2646 status = HI_ResetCommand(state); 2647 if (status < 0) 2648 break; 2649 2650 status = StopAllProcessors(state); 2651 if (status < 0) 2652 break; 2653 status = InitCC(state); 2654 if (status < 0) 2655 break; 2656 2657 state->osc_clock_deviation = 0; 2658 2659 if (state->config.osc_deviation) 2660 state->osc_clock_deviation = 2661 state->config.osc_deviation(state->priv, 0, 0); 2662 { 2663 /* Handle clock deviation */ 2664 s32 devB; 2665 s32 devA = (s32) (state->osc_clock_deviation) * 2666 (s32) (state->expected_sys_clock_freq); 2667 /* deviation in kHz */ 2668 s32 deviation = (devA / (1000000L)); 2669 /* rounding, signed */ 2670 if (devA > 0) 2671 devB = (2); 2672 else 2673 devB = (-2); 2674 if ((devB * (devA % 1000000L) > 1000000L)) { 2675 /* add +1 or -1 */ 2676 deviation += (devB / 2); 2677 } 2678 2679 state->sys_clock_freq = 2680 (u16) ((state->expected_sys_clock_freq) + 2681 deviation); 2682 } 2683 status = InitHI(state); 2684 if (status < 0) 2685 break; 2686 status = InitAtomicRead(state); 2687 if (status < 0) 2688 break; 2689 2690 status = EnableAndResetMB(state); 2691 if (status < 0) 2692 break; 2693 if (state->type_A) { 2694 status = ResetCEFR(state); 2695 if (status < 0) 2696 break; 2697 } 2698 if (fw) { 2699 status = DownloadMicrocode(state, fw, fw_size); 2700 if (status < 0) 2701 break; 2702 } else { 2703 status = DownloadMicrocode(state, state->microcode, state->microcode_length); 2704 if (status < 0) 2705 break; 2706 } 2707 2708 if (state->PGA) { 2709 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; 2710 SetCfgPga(state, 0); /* PGA = 0 dB */ 2711 } else { 2712 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2713 } 2714 2715 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; 2716 2717 status = InitFE(state); 2718 if (status < 0) 2719 break; 2720 status = InitFT(state); 2721 if (status < 0) 2722 break; 2723 status = InitCP(state); 2724 if (status < 0) 2725 break; 2726 status = InitCE(state); 2727 if (status < 0) 2728 break; 2729 status = InitEQ(state); 2730 if (status < 0) 2731 break; 2732 status = InitEC(state); 2733 if (status < 0) 2734 break; 2735 status = InitSC(state); 2736 if (status < 0) 2737 break; 2738 2739 status = SetCfgIfAgc(state, &state->if_agc_cfg); 2740 if (status < 0) 2741 break; 2742 status = SetCfgRfAgc(state, &state->rf_agc_cfg); 2743 if (status < 0) 2744 break; 2745 2746 state->cscd_state = CSCD_INIT; 2747 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 2748 if (status < 0) 2749 break; 2750 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 2751 if (status < 0) 2752 break; 2753 2754 driverVersion = (((VERSION_MAJOR / 10) << 4) + 2755 (VERSION_MAJOR % 10)) << 24; 2756 driverVersion += (((VERSION_MINOR / 10) << 4) + 2757 (VERSION_MINOR % 10)) << 16; 2758 driverVersion += ((VERSION_PATCH / 1000) << 12) + 2759 ((VERSION_PATCH / 100) << 8) + 2760 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10); 2761 2762 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); 2763 if (status < 0) 2764 break; 2765 2766 status = StopOC(state); 2767 if (status < 0) 2768 break; 2769 2770 state->drxd_state = DRXD_STOPPED; 2771 state->init_done = 1; 2772 status = 0; 2773 } while (0); 2774 return status; 2775 } 2776 2777 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) 2778 { 2779 DRX_GetLockStatus(state, pLockStatus); 2780 2781 /*if (*pLockStatus&DRX_LOCK_MPEG) */ 2782 if (*pLockStatus & DRX_LOCK_FEC) { 2783 ConfigureMPEGOutput(state, 1); 2784 /* Get status again, in case we have MPEG lock now */ 2785 /*DRX_GetLockStatus(state, pLockStatus); */ 2786 } 2787 2788 return 0; 2789 } 2790 2791 /****************************************************************************/ 2792 /****************************************************************************/ 2793 /****************************************************************************/ 2794 2795 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength) 2796 { 2797 struct drxd_state *state = fe->demodulator_priv; 2798 u32 value; 2799 int res; 2800 2801 res = ReadIFAgc(state, &value); 2802 if (res < 0) 2803 *strength = 0; 2804 else 2805 *strength = 0xffff - (value << 4); 2806 return 0; 2807 } 2808 2809 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status) 2810 { 2811 struct drxd_state *state = fe->demodulator_priv; 2812 u32 lock; 2813 2814 DRXD_status(state, &lock); 2815 *status = 0; 2816 /* No MPEG lock in V255 firmware, bug ? */ 2817 #if 1 2818 if (lock & DRX_LOCK_MPEG) 2819 *status |= FE_HAS_LOCK; 2820 #else 2821 if (lock & DRX_LOCK_FEC) 2822 *status |= FE_HAS_LOCK; 2823 #endif 2824 if (lock & DRX_LOCK_FEC) 2825 *status |= FE_HAS_VITERBI | FE_HAS_SYNC; 2826 if (lock & DRX_LOCK_DEMOD) 2827 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; 2828 2829 return 0; 2830 } 2831 2832 static int drxd_init(struct dvb_frontend *fe) 2833 { 2834 struct drxd_state *state = fe->demodulator_priv; 2835 2836 return DRXD_init(state, NULL, 0); 2837 } 2838 2839 static int drxd_config_i2c(struct dvb_frontend *fe, int onoff) 2840 { 2841 struct drxd_state *state = fe->demodulator_priv; 2842 2843 if (state->config.disable_i2c_gate_ctrl == 1) 2844 return 0; 2845 2846 return DRX_ConfigureI2CBridge(state, onoff); 2847 } 2848 2849 static int drxd_get_tune_settings(struct dvb_frontend *fe, 2850 struct dvb_frontend_tune_settings *sets) 2851 { 2852 sets->min_delay_ms = 10000; 2853 sets->max_drift = 0; 2854 sets->step_size = 0; 2855 return 0; 2856 } 2857 2858 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber) 2859 { 2860 *ber = 0; 2861 return 0; 2862 } 2863 2864 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr) 2865 { 2866 *snr = 0; 2867 return 0; 2868 } 2869 2870 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 2871 { 2872 *ucblocks = 0; 2873 return 0; 2874 } 2875 2876 static int drxd_sleep(struct dvb_frontend *fe) 2877 { 2878 struct drxd_state *state = fe->demodulator_priv; 2879 2880 ConfigureMPEGOutput(state, 0); 2881 return 0; 2882 } 2883 2884 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 2885 { 2886 return drxd_config_i2c(fe, enable); 2887 } 2888 2889 static int drxd_set_frontend(struct dvb_frontend *fe) 2890 { 2891 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 2892 struct drxd_state *state = fe->demodulator_priv; 2893 s32 off = 0; 2894 2895 state->props = *p; 2896 DRX_Stop(state); 2897 2898 if (fe->ops.tuner_ops.set_params) { 2899 fe->ops.tuner_ops.set_params(fe); 2900 if (fe->ops.i2c_gate_ctrl) 2901 fe->ops.i2c_gate_ctrl(fe, 0); 2902 } 2903 2904 msleep(200); 2905 2906 return DRX_Start(state, off); 2907 } 2908 2909 static void drxd_release(struct dvb_frontend *fe) 2910 { 2911 struct drxd_state *state = fe->demodulator_priv; 2912 2913 kfree(state); 2914 } 2915 2916 static const struct dvb_frontend_ops drxd_ops = { 2917 .delsys = { SYS_DVBT}, 2918 .info = { 2919 .name = "Micronas DRXD DVB-T", 2920 .frequency_min = 47125000, 2921 .frequency_max = 855250000, 2922 .frequency_stepsize = 166667, 2923 .frequency_tolerance = 0, 2924 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 2925 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 2926 FE_CAN_FEC_AUTO | 2927 FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2928 FE_CAN_QAM_AUTO | 2929 FE_CAN_TRANSMISSION_MODE_AUTO | 2930 FE_CAN_GUARD_INTERVAL_AUTO | 2931 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS}, 2932 2933 .release = drxd_release, 2934 .init = drxd_init, 2935 .sleep = drxd_sleep, 2936 .i2c_gate_ctrl = drxd_i2c_gate_ctrl, 2937 2938 .set_frontend = drxd_set_frontend, 2939 .get_tune_settings = drxd_get_tune_settings, 2940 2941 .read_status = drxd_read_status, 2942 .read_ber = drxd_read_ber, 2943 .read_signal_strength = drxd_read_signal_strength, 2944 .read_snr = drxd_read_snr, 2945 .read_ucblocks = drxd_read_ucblocks, 2946 }; 2947 2948 struct dvb_frontend *drxd_attach(const struct drxd_config *config, 2949 void *priv, struct i2c_adapter *i2c, 2950 struct device *dev) 2951 { 2952 struct drxd_state *state = NULL; 2953 2954 state = kzalloc(sizeof(*state), GFP_KERNEL); 2955 if (!state) 2956 return NULL; 2957 2958 state->ops = drxd_ops; 2959 state->dev = dev; 2960 state->config = *config; 2961 state->i2c = i2c; 2962 state->priv = priv; 2963 2964 mutex_init(&state->mutex); 2965 2966 if (Read16(state, 0, NULL, 0) < 0) 2967 goto error; 2968 2969 state->frontend.ops = drxd_ops; 2970 state->frontend.demodulator_priv = state; 2971 ConfigureMPEGOutput(state, 0); 2972 /* add few initialization to allow gate control */ 2973 CDRXD(state, state->config.IF ? state->config.IF : 36000000); 2974 InitHI(state); 2975 2976 return &state->frontend; 2977 2978 error: 2979 printk(KERN_ERR "drxd: not found\n"); 2980 kfree(state); 2981 return NULL; 2982 } 2983 EXPORT_SYMBOL(drxd_attach); 2984 2985 MODULE_DESCRIPTION("DRXD driver"); 2986 MODULE_AUTHOR("Micronas"); 2987 MODULE_LICENSE("GPL"); 2988