1 /* 2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1 3 * 4 * Copyright (C) 2003-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/i2c.h> 27 #include <asm/div64.h> 28 29 #include "dvb_frontend.h" 30 #include "drxd.h" 31 #include "drxd_firm.h" 32 33 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw" 34 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw" 35 36 #define CHUNK_SIZE 48 37 38 #define DRX_I2C_RMW 0x10 39 #define DRX_I2C_BROADCAST 0x20 40 #define DRX_I2C_CLEARCRC 0x80 41 #define DRX_I2C_SINGLE_MASTER 0xC0 42 #define DRX_I2C_MODEFLAGS 0xC0 43 #define DRX_I2C_FLAGS 0xF0 44 45 #define DEFAULT_LOCK_TIMEOUT 1100 46 47 #define DRX_CHANNEL_AUTO 0 48 #define DRX_CHANNEL_HIGH 1 49 #define DRX_CHANNEL_LOW 2 50 51 #define DRX_LOCK_MPEG 1 52 #define DRX_LOCK_FEC 2 53 #define DRX_LOCK_DEMOD 4 54 55 /****************************************************************************/ 56 57 enum CSCDState { 58 CSCD_INIT = 0, 59 CSCD_SET, 60 CSCD_SAVED 61 }; 62 63 enum CDrxdState { 64 DRXD_UNINITIALIZED = 0, 65 DRXD_STOPPED, 66 DRXD_STARTED 67 }; 68 69 enum AGC_CTRL_MODE { 70 AGC_CTRL_AUTO = 0, 71 AGC_CTRL_USER, 72 AGC_CTRL_OFF 73 }; 74 75 enum OperationMode { 76 OM_Default, 77 OM_DVBT_Diversity_Front, 78 OM_DVBT_Diversity_End 79 }; 80 81 struct SCfgAgc { 82 enum AGC_CTRL_MODE ctrlMode; 83 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 84 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 85 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 86 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 87 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ 88 89 u16 R1; 90 u16 R2; 91 u16 R3; 92 }; 93 94 struct SNoiseCal { 95 int cpOpt; 96 short cpNexpOfs; 97 short tdCal2k; 98 short tdCal8k; 99 }; 100 101 enum app_env { 102 APPENV_STATIC = 0, 103 APPENV_PORTABLE = 1, 104 APPENV_MOBILE = 2 105 }; 106 107 enum EIFFilter { 108 IFFILTER_SAW = 0, 109 IFFILTER_DISCRETE = 1 110 }; 111 112 struct drxd_state { 113 struct dvb_frontend frontend; 114 struct dvb_frontend_ops ops; 115 struct dtv_frontend_properties props; 116 117 const struct firmware *fw; 118 struct device *dev; 119 120 struct i2c_adapter *i2c; 121 void *priv; 122 struct drxd_config config; 123 124 int i2c_access; 125 int init_done; 126 struct mutex mutex; 127 128 u8 chip_adr; 129 u16 hi_cfg_timing_div; 130 u16 hi_cfg_bridge_delay; 131 u16 hi_cfg_wakeup_key; 132 u16 hi_cfg_ctrl; 133 134 u16 intermediate_freq; 135 u16 osc_clock_freq; 136 137 enum CSCDState cscd_state; 138 enum CDrxdState drxd_state; 139 140 u16 sys_clock_freq; 141 s16 osc_clock_deviation; 142 u16 expected_sys_clock_freq; 143 144 u16 insert_rs_byte; 145 u16 enable_parallel; 146 147 int operation_mode; 148 149 struct SCfgAgc if_agc_cfg; 150 struct SCfgAgc rf_agc_cfg; 151 152 struct SNoiseCal noise_cal; 153 154 u32 fe_fs_add_incr; 155 u32 org_fe_fs_add_incr; 156 u16 current_fe_if_incr; 157 158 u16 m_FeAgRegAgPwd; 159 u16 m_FeAgRegAgAgcSio; 160 161 u16 m_EcOcRegOcModeLop; 162 u16 m_EcOcRegSncSncLvl; 163 u8 *m_InitAtomicRead; 164 u8 *m_HiI2cPatch; 165 166 u8 *m_ResetCEFR; 167 u8 *m_InitFE_1; 168 u8 *m_InitFE_2; 169 u8 *m_InitCP; 170 u8 *m_InitCE; 171 u8 *m_InitEQ; 172 u8 *m_InitSC; 173 u8 *m_InitEC; 174 u8 *m_ResetECRAM; 175 u8 *m_InitDiversityFront; 176 u8 *m_InitDiversityEnd; 177 u8 *m_DisableDiversity; 178 u8 *m_StartDiversityFront; 179 u8 *m_StartDiversityEnd; 180 181 u8 *m_DiversityDelay8MHZ; 182 u8 *m_DiversityDelay6MHZ; 183 184 u8 *microcode; 185 u32 microcode_length; 186 187 int type_A; 188 int PGA; 189 int diversity; 190 int tuner_mirrors; 191 192 enum app_env app_env_default; 193 enum app_env app_env_diversity; 194 195 }; 196 197 /****************************************************************************/ 198 /* I2C **********************************************************************/ 199 /****************************************************************************/ 200 201 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len) 202 { 203 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len }; 204 205 if (i2c_transfer(adap, &msg, 1) != 1) 206 return -1; 207 return 0; 208 } 209 210 static int i2c_read(struct i2c_adapter *adap, 211 u8 adr, u8 *msg, int len, u8 *answ, int alen) 212 { 213 struct i2c_msg msgs[2] = { 214 { 215 .addr = adr, .flags = 0, 216 .buf = msg, .len = len 217 }, { 218 .addr = adr, .flags = I2C_M_RD, 219 .buf = answ, .len = alen 220 } 221 }; 222 if (i2c_transfer(adap, msgs, 2) != 2) 223 return -1; 224 return 0; 225 } 226 227 static inline u32 MulDiv32(u32 a, u32 b, u32 c) 228 { 229 u64 tmp64; 230 231 tmp64 = (u64)a * (u64)b; 232 do_div(tmp64, c); 233 234 return (u32) tmp64; 235 } 236 237 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) 238 { 239 u8 adr = state->config.demod_address; 240 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, 241 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 242 }; 243 u8 mm2[2]; 244 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) 245 return -1; 246 if (data) 247 *data = mm2[0] | (mm2[1] << 8); 248 return mm2[0] | (mm2[1] << 8); 249 } 250 251 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) 252 { 253 u8 adr = state->config.demod_address; 254 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, 255 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 256 }; 257 u8 mm2[4]; 258 259 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) 260 return -1; 261 if (data) 262 *data = 263 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24); 264 return 0; 265 } 266 267 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) 268 { 269 u8 adr = state->config.demod_address; 270 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, 271 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, 272 data & 0xff, (data >> 8) & 0xff 273 }; 274 275 if (i2c_write(state->i2c, adr, mm, 6) < 0) 276 return -1; 277 return 0; 278 } 279 280 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) 281 { 282 u8 adr = state->config.demod_address; 283 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, 284 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, 285 data & 0xff, (data >> 8) & 0xff, 286 (data >> 16) & 0xff, (data >> 24) & 0xff 287 }; 288 289 if (i2c_write(state->i2c, adr, mm, 8) < 0) 290 return -1; 291 return 0; 292 } 293 294 static int write_chunk(struct drxd_state *state, 295 u32 reg, u8 *data, u32 len, u8 flags) 296 { 297 u8 adr = state->config.demod_address; 298 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, 299 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff 300 }; 301 int i; 302 303 for (i = 0; i < len; i++) 304 mm[4 + i] = data[i]; 305 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { 306 printk(KERN_ERR "error in write_chunk\n"); 307 return -1; 308 } 309 return 0; 310 } 311 312 static int WriteBlock(struct drxd_state *state, 313 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) 314 { 315 while (BlockSize > 0) { 316 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; 317 318 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) 319 return -1; 320 pBlock += Chunk; 321 Address += (Chunk >> 1); 322 BlockSize -= Chunk; 323 } 324 return 0; 325 } 326 327 static int WriteTable(struct drxd_state *state, u8 * pTable) 328 { 329 int status = 0; 330 331 if (pTable == NULL) 332 return 0; 333 334 while (!status) { 335 u16 Length; 336 u32 Address = pTable[0] | (pTable[1] << 8) | 337 (pTable[2] << 16) | (pTable[3] << 24); 338 339 if (Address == 0xFFFFFFFF) 340 break; 341 pTable += sizeof(u32); 342 343 Length = pTable[0] | (pTable[1] << 8); 344 pTable += sizeof(u16); 345 if (!Length) 346 break; 347 status = WriteBlock(state, Address, Length * 2, pTable, 0); 348 pTable += (Length * 2); 349 } 350 return status; 351 } 352 353 /****************************************************************************/ 354 /****************************************************************************/ 355 /****************************************************************************/ 356 357 static int ResetCEFR(struct drxd_state *state) 358 { 359 return WriteTable(state, state->m_ResetCEFR); 360 } 361 362 static int InitCP(struct drxd_state *state) 363 { 364 return WriteTable(state, state->m_InitCP); 365 } 366 367 static int InitCE(struct drxd_state *state) 368 { 369 int status; 370 enum app_env AppEnv = state->app_env_default; 371 372 do { 373 status = WriteTable(state, state->m_InitCE); 374 if (status < 0) 375 break; 376 377 if (state->operation_mode == OM_DVBT_Diversity_Front || 378 state->operation_mode == OM_DVBT_Diversity_End) { 379 AppEnv = state->app_env_diversity; 380 } 381 if (AppEnv == APPENV_STATIC) { 382 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); 383 if (status < 0) 384 break; 385 } else if (AppEnv == APPENV_PORTABLE) { 386 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); 387 if (status < 0) 388 break; 389 } else if (AppEnv == APPENV_MOBILE && state->type_A) { 390 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); 391 if (status < 0) 392 break; 393 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { 394 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); 395 if (status < 0) 396 break; 397 } 398 399 /* start ce */ 400 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); 401 if (status < 0) 402 break; 403 } while (0); 404 return status; 405 } 406 407 static int StopOC(struct drxd_state *state) 408 { 409 int status = 0; 410 u16 ocSyncLvl = 0; 411 u16 ocModeLop = state->m_EcOcRegOcModeLop; 412 u16 dtoIncLop = 0; 413 u16 dtoIncHip = 0; 414 415 do { 416 /* Store output configuration */ 417 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); 418 if (status < 0) 419 break; 420 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */ 421 state->m_EcOcRegSncSncLvl = ocSyncLvl; 422 /* m_EcOcRegOcModeLop = ocModeLop; */ 423 424 /* Flush FIFO (byte-boundary) at fixed rate */ 425 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); 426 if (status < 0) 427 break; 428 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); 429 if (status < 0) 430 break; 431 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); 432 if (status < 0) 433 break; 434 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); 435 if (status < 0) 436 break; 437 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); 438 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; 439 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); 440 if (status < 0) 441 break; 442 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); 443 if (status < 0) 444 break; 445 446 msleep(1); 447 /* Output pins to '0' */ 448 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); 449 if (status < 0) 450 break; 451 452 /* Force the OC out of sync */ 453 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); 454 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); 455 if (status < 0) 456 break; 457 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); 458 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; 459 ocModeLop |= 0x2; /* Magically-out-of-sync */ 460 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); 461 if (status < 0) 462 break; 463 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); 464 if (status < 0) 465 break; 466 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); 467 if (status < 0) 468 break; 469 } while (0); 470 471 return status; 472 } 473 474 static int StartOC(struct drxd_state *state) 475 { 476 int status = 0; 477 478 do { 479 /* Stop OC */ 480 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); 481 if (status < 0) 482 break; 483 484 /* Restore output configuration */ 485 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); 486 if (status < 0) 487 break; 488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); 489 if (status < 0) 490 break; 491 492 /* Output pins active again */ 493 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); 494 if (status < 0) 495 break; 496 497 /* Start OC */ 498 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); 499 if (status < 0) 500 break; 501 } while (0); 502 return status; 503 } 504 505 static int InitEQ(struct drxd_state *state) 506 { 507 return WriteTable(state, state->m_InitEQ); 508 } 509 510 static int InitEC(struct drxd_state *state) 511 { 512 return WriteTable(state, state->m_InitEC); 513 } 514 515 static int InitSC(struct drxd_state *state) 516 { 517 return WriteTable(state, state->m_InitSC); 518 } 519 520 static int InitAtomicRead(struct drxd_state *state) 521 { 522 return WriteTable(state, state->m_InitAtomicRead); 523 } 524 525 static int CorrectSysClockDeviation(struct drxd_state *state); 526 527 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) 528 { 529 u16 ScRaRamLock = 0; 530 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M | 531 SC_RA_RAM_LOCK_FEC__M | 532 SC_RA_RAM_LOCK_DEMOD__M); 533 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M | 534 SC_RA_RAM_LOCK_DEMOD__M); 535 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M; 536 537 int status; 538 539 *pLockStatus = 0; 540 541 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); 542 if (status < 0) { 543 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); 544 return status; 545 } 546 547 if (state->drxd_state != DRXD_STARTED) 548 return 0; 549 550 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { 551 *pLockStatus |= DRX_LOCK_MPEG; 552 CorrectSysClockDeviation(state); 553 } 554 555 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) 556 *pLockStatus |= DRX_LOCK_FEC; 557 558 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) 559 *pLockStatus |= DRX_LOCK_DEMOD; 560 return 0; 561 } 562 563 /****************************************************************************/ 564 565 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) 566 { 567 int status; 568 569 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) 570 return -1; 571 572 if (cfg->ctrlMode == AGC_CTRL_USER) { 573 do { 574 u16 FeAgRegPm1AgcWri; 575 u16 FeAgRegAgModeLop; 576 577 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); 578 if (status < 0) 579 break; 580 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 581 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; 582 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); 583 if (status < 0) 584 break; 585 586 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & 587 FE_AG_REG_PM1_AGC_WRI__M); 588 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); 589 if (status < 0) 590 break; 591 } while (0); 592 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { 593 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || 594 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || 595 ((cfg->speed) > DRXD_FE_CTRL_MAX) || 596 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) 597 ) 598 return -1; 599 do { 600 u16 FeAgRegAgModeLop; 601 u16 FeAgRegEgcSetLvl; 602 u16 slope, offset; 603 604 /* == Mode == */ 605 606 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); 607 if (status < 0) 608 break; 609 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 610 FeAgRegAgModeLop |= 611 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; 612 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); 613 if (status < 0) 614 break; 615 616 /* == Settle level == */ 617 618 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & 619 FE_AG_REG_EGC_SET_LVL__M); 620 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); 621 if (status < 0) 622 break; 623 624 /* == Min/Max == */ 625 626 slope = (u16) ((cfg->maxOutputLevel - 627 cfg->minOutputLevel) / 2); 628 offset = (u16) ((cfg->maxOutputLevel + 629 cfg->minOutputLevel) / 2 - 511); 630 631 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); 632 if (status < 0) 633 break; 634 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); 635 if (status < 0) 636 break; 637 638 /* == Speed == */ 639 { 640 const u16 maxRur = 8; 641 static const u16 slowIncrDecLUT[] = { 642 3, 4, 4, 5, 6 }; 643 const u16 fastIncrDecLUT[] = { 644 14, 15, 15, 16, 645 17, 18, 18, 19, 646 20, 21, 22, 23, 647 24, 26, 27, 28, 648 29, 31 649 }; 650 651 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) / 652 (maxRur + 1); 653 u16 fineSpeed = (u16) (cfg->speed - 654 ((cfg->speed / 655 fineSteps) * 656 fineSteps)); 657 u16 invRurCount = (u16) (cfg->speed / 658 fineSteps); 659 u16 rurCount; 660 if (invRurCount > maxRur) { 661 rurCount = 0; 662 fineSpeed += fineSteps; 663 } else { 664 rurCount = maxRur - invRurCount; 665 } 666 667 /* 668 fastInc = default * 669 (2^(fineSpeed/fineSteps)) 670 => range[default...2*default> 671 slowInc = default * 672 (2^(fineSpeed/fineSteps)) 673 */ 674 { 675 u16 fastIncrDec = 676 fastIncrDecLUT[fineSpeed / 677 ((fineSteps / 678 (14 + 1)) + 1)]; 679 u16 slowIncrDec = 680 slowIncrDecLUT[fineSpeed / 681 (fineSteps / 682 (3 + 1))]; 683 684 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); 685 if (status < 0) 686 break; 687 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); 688 if (status < 0) 689 break; 690 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); 691 if (status < 0) 692 break; 693 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); 694 if (status < 0) 695 break; 696 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); 697 if (status < 0) 698 break; 699 } 700 } 701 } while (0); 702 703 } else { 704 /* No OFF mode for IF control */ 705 return -1; 706 } 707 return status; 708 } 709 710 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) 711 { 712 int status = 0; 713 714 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) 715 return -1; 716 717 if (cfg->ctrlMode == AGC_CTRL_USER) { 718 do { 719 u16 AgModeLop = 0; 720 u16 level = (cfg->outputLevel); 721 722 if (level == DRXD_FE_CTRL_MAX) 723 level++; 724 725 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); 726 if (status < 0) 727 break; 728 729 /*==== Mode ====*/ 730 731 /* Powerdown PD2, WRI source */ 732 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 733 state->m_FeAgRegAgPwd |= 734 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 735 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); 736 if (status < 0) 737 break; 738 739 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 740 if (status < 0) 741 break; 742 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 743 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 744 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 745 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 746 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 747 if (status < 0) 748 break; 749 750 /* enable AGC2 pin */ 751 { 752 u16 FeAgRegAgAgcSio = 0; 753 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 754 if (status < 0) 755 break; 756 FeAgRegAgAgcSio &= 757 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 758 FeAgRegAgAgcSio |= 759 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 760 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 761 if (status < 0) 762 break; 763 } 764 765 } while (0); 766 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { 767 u16 AgModeLop = 0; 768 769 do { 770 u16 level; 771 /* Automatic control */ 772 /* Powerup PD2, AGC2 as output, TGC source */ 773 (state->m_FeAgRegAgPwd) &= 774 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 775 (state->m_FeAgRegAgPwd) |= 776 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 777 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); 778 if (status < 0) 779 break; 780 781 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 782 if (status < 0) 783 break; 784 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 785 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 786 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 787 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC); 788 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 789 if (status < 0) 790 break; 791 /* Settle level */ 792 level = (((cfg->settleLevel) >> 4) & 793 FE_AG_REG_TGC_SET_LVL__M); 794 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); 795 if (status < 0) 796 break; 797 798 /* Min/max: don't care */ 799 800 /* Speed: TODO */ 801 802 /* enable AGC2 pin */ 803 { 804 u16 FeAgRegAgAgcSio = 0; 805 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 806 if (status < 0) 807 break; 808 FeAgRegAgAgcSio &= 809 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 810 FeAgRegAgAgcSio |= 811 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 812 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 813 if (status < 0) 814 break; 815 } 816 817 } while (0); 818 } else { 819 u16 AgModeLop = 0; 820 821 do { 822 /* No RF AGC control */ 823 /* Powerdown PD2, AGC2 as output, WRI source */ 824 (state->m_FeAgRegAgPwd) &= 825 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 826 (state->m_FeAgRegAgPwd) |= 827 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; 828 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); 829 if (status < 0) 830 break; 831 832 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 833 if (status < 0) 834 break; 835 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 836 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 837 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 838 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 839 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 840 if (status < 0) 841 break; 842 843 /* set FeAgRegAgAgcSio AGC2 (RF) as input */ 844 { 845 u16 FeAgRegAgAgcSio = 0; 846 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); 847 if (status < 0) 848 break; 849 FeAgRegAgAgcSio &= 850 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 851 FeAgRegAgAgcSio |= 852 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; 853 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); 854 if (status < 0) 855 break; 856 } 857 } while (0); 858 } 859 return status; 860 } 861 862 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) 863 { 864 int status = 0; 865 866 *pValue = 0; 867 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { 868 u16 Value; 869 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); 870 Value &= FE_AG_REG_GC1_AGC_DAT__M; 871 if (status >= 0) { 872 /* 3.3V 873 | 874 R1 875 | 876 Vin - R3 - * -- Vout 877 | 878 R2 879 | 880 GND 881 */ 882 u32 R1 = state->if_agc_cfg.R1; 883 u32 R2 = state->if_agc_cfg.R2; 884 u32 R3 = state->if_agc_cfg.R3; 885 886 u32 Vmax, Rpar, Vmin, Vout; 887 888 if (R2 == 0 && (R1 == 0 || R3 == 0)) 889 return 0; 890 891 Vmax = (3300 * R2) / (R1 + R2); 892 Rpar = (R2 * R3) / (R3 + R2); 893 Vmin = (3300 * Rpar) / (R1 + Rpar); 894 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024; 895 896 *pValue = Vout; 897 } 898 } 899 return status; 900 } 901 902 static int load_firmware(struct drxd_state *state, const char *fw_name) 903 { 904 const struct firmware *fw; 905 906 if (request_firmware(&fw, fw_name, state->dev) < 0) { 907 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name); 908 return -EIO; 909 } 910 911 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); 912 if (state->microcode == NULL) { 913 release_firmware(fw); 914 printk(KERN_ERR "drxd: firmware load failure: no memory\n"); 915 return -ENOMEM; 916 } 917 918 state->microcode_length = fw->size; 919 release_firmware(fw); 920 return 0; 921 } 922 923 static int DownloadMicrocode(struct drxd_state *state, 924 const u8 *pMCImage, u32 Length) 925 { 926 u8 *pSrc; 927 u32 Address; 928 u16 nBlocks; 929 u16 BlockSize; 930 u32 offset = 0; 931 int i, status = 0; 932 933 pSrc = (u8 *) pMCImage; 934 /* We're not using Flags */ 935 /* Flags = (pSrc[0] << 8) | pSrc[1]; */ 936 pSrc += sizeof(u16); 937 offset += sizeof(u16); 938 nBlocks = (pSrc[0] << 8) | pSrc[1]; 939 pSrc += sizeof(u16); 940 offset += sizeof(u16); 941 942 for (i = 0; i < nBlocks; i++) { 943 Address = (pSrc[0] << 24) | (pSrc[1] << 16) | 944 (pSrc[2] << 8) | pSrc[3]; 945 pSrc += sizeof(u32); 946 offset += sizeof(u32); 947 948 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); 949 pSrc += sizeof(u16); 950 offset += sizeof(u16); 951 952 /* We're not using Flags */ 953 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */ 954 pSrc += sizeof(u16); 955 offset += sizeof(u16); 956 957 /* We're not using BlockCRC */ 958 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */ 959 pSrc += sizeof(u16); 960 offset += sizeof(u16); 961 962 status = WriteBlock(state, Address, BlockSize, 963 pSrc, DRX_I2C_CLEARCRC); 964 if (status < 0) 965 break; 966 pSrc += BlockSize; 967 offset += BlockSize; 968 } 969 970 return status; 971 } 972 973 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) 974 { 975 u32 nrRetries = 0; 976 u16 waitCmd; 977 int status; 978 979 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); 980 if (status < 0) 981 return status; 982 983 do { 984 nrRetries += 1; 985 if (nrRetries > DRXD_MAX_RETRIES) { 986 status = -1; 987 break; 988 } 989 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); 990 } while (waitCmd != 0); 991 992 if (status >= 0) 993 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); 994 return status; 995 } 996 997 static int HI_CfgCommand(struct drxd_state *state) 998 { 999 int status = 0; 1000 1001 mutex_lock(&state->mutex); 1002 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1003 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); 1004 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); 1005 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); 1006 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); 1007 1008 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1009 1010 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == 1011 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) 1012 status = Write16(state, HI_RA_RAM_SRV_CMD__A, 1013 HI_RA_RAM_SRV_CMD_CONFIG, 0); 1014 else 1015 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); 1016 mutex_unlock(&state->mutex); 1017 return status; 1018 } 1019 1020 static int InitHI(struct drxd_state *state) 1021 { 1022 state->hi_cfg_wakeup_key = (state->chip_adr); 1023 /* port/bridge/power down ctrl */ 1024 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; 1025 return HI_CfgCommand(state); 1026 } 1027 1028 static int HI_ResetCommand(struct drxd_state *state) 1029 { 1030 int status; 1031 1032 mutex_lock(&state->mutex); 1033 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, 1034 HI_RA_RAM_SRV_RST_KEY_ACT, 0); 1035 if (status == 0) 1036 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); 1037 mutex_unlock(&state->mutex); 1038 msleep(1); 1039 return status; 1040 } 1041 1042 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) 1043 { 1044 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); 1045 if (bEnableBridge) 1046 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; 1047 else 1048 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; 1049 1050 return HI_CfgCommand(state); 1051 } 1052 1053 #define HI_TR_WRITE 0x9 1054 #define HI_TR_READ 0xA 1055 #define HI_TR_READ_WRITE 0xB 1056 #define HI_TR_BROADCAST 0x4 1057 1058 #if 0 1059 static int AtomicReadBlock(struct drxd_state *state, 1060 u32 Addr, u16 DataSize, u8 *pData, u8 Flags) 1061 { 1062 int status; 1063 int i = 0; 1064 1065 /* Parameter check */ 1066 if ((!pData) || ((DataSize & 1) != 0)) 1067 return -1; 1068 1069 mutex_lock(&state->mutex); 1070 1071 do { 1072 /* Instruct HI to read n bytes */ 1073 /* TODO use proper names forthese egisters */ 1074 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0); 1075 if (status < 0) 1076 break; 1077 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0); 1078 if (status < 0) 1079 break; 1080 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0); 1081 if (status < 0) 1082 break; 1083 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0); 1084 if (status < 0) 1085 break; 1086 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0); 1087 if (status < 0) 1088 break; 1089 1090 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0); 1091 if (status < 0) 1092 break; 1093 1094 } while (0); 1095 1096 if (status >= 0) { 1097 for (i = 0; i < (DataSize / 2); i += 1) { 1098 u16 word; 1099 1100 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i), 1101 &word, 0); 1102 if (status < 0) 1103 break; 1104 pData[2 * i] = (u8) (word & 0xFF); 1105 pData[(2 * i) + 1] = (u8) (word >> 8); 1106 } 1107 } 1108 mutex_unlock(&state->mutex); 1109 return status; 1110 } 1111 1112 static int AtomicReadReg32(struct drxd_state *state, 1113 u32 Addr, u32 *pData, u8 Flags) 1114 { 1115 u8 buf[sizeof(u32)]; 1116 int status; 1117 1118 if (!pData) 1119 return -1; 1120 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags); 1121 *pData = (((u32) buf[0]) << 0) + 1122 (((u32) buf[1]) << 8) + 1123 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); 1124 return status; 1125 } 1126 #endif 1127 1128 static int StopAllProcessors(struct drxd_state *state) 1129 { 1130 return Write16(state, HI_COMM_EXEC__A, 1131 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST); 1132 } 1133 1134 static int EnableAndResetMB(struct drxd_state *state) 1135 { 1136 if (state->type_A) { 1137 /* disable? monitor bus observe @ EC_OC */ 1138 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); 1139 } 1140 1141 /* do inverse broadcast, followed by explicit write to HI */ 1142 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); 1143 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); 1144 return 0; 1145 } 1146 1147 static int InitCC(struct drxd_state *state) 1148 { 1149 if (state->osc_clock_freq == 0 || 1150 state->osc_clock_freq > 20000 || 1151 (state->osc_clock_freq % 4000) != 0) { 1152 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); 1153 return -1; 1154 } 1155 1156 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); 1157 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | 1158 CC_REG_PLL_MODE_PUMP_CUR_12, 0); 1159 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); 1160 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); 1161 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); 1162 1163 return 0; 1164 } 1165 1166 static int ResetECOD(struct drxd_state *state) 1167 { 1168 int status = 0; 1169 1170 if (state->type_A) 1171 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); 1172 else 1173 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); 1174 1175 if (!(status < 0)) 1176 status = WriteTable(state, state->m_ResetECRAM); 1177 if (!(status < 0)) 1178 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); 1179 return status; 1180 } 1181 1182 /* Configure PGA switch */ 1183 1184 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) 1185 { 1186 int status; 1187 u16 AgModeLop = 0; 1188 u16 AgModeHip = 0; 1189 do { 1190 if (pgaSwitch) { 1191 /* PGA on */ 1192 /* fine gain */ 1193 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 1194 if (status < 0) 1195 break; 1196 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1197 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; 1198 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 1199 if (status < 0) 1200 break; 1201 1202 /* coarse gain */ 1203 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); 1204 if (status < 0) 1205 break; 1206 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1207 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC; 1208 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); 1209 if (status < 0) 1210 break; 1211 1212 /* enable fine and coarse gain, enable AAF, 1213 no ext resistor */ 1214 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000); 1215 if (status < 0) 1216 break; 1217 } else { 1218 /* PGA off, bypass */ 1219 1220 /* fine gain */ 1221 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); 1222 if (status < 0) 1223 break; 1224 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1225 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC; 1226 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); 1227 if (status < 0) 1228 break; 1229 1230 /* coarse gain */ 1231 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); 1232 if (status < 0) 1233 break; 1234 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1235 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC; 1236 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); 1237 if (status < 0) 1238 break; 1239 1240 /* disable fine and coarse gain, enable AAF, 1241 no ext resistor */ 1242 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000); 1243 if (status < 0) 1244 break; 1245 } 1246 } while (0); 1247 return status; 1248 } 1249 1250 static int InitFE(struct drxd_state *state) 1251 { 1252 int status; 1253 1254 do { 1255 status = WriteTable(state, state->m_InitFE_1); 1256 if (status < 0) 1257 break; 1258 1259 if (state->type_A) { 1260 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, 1261 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1262 0); 1263 } else { 1264 if (state->PGA) 1265 status = SetCfgPga(state, 0); 1266 else 1267 status = 1268 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, 1269 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1270 0); 1271 } 1272 1273 if (status < 0) 1274 break; 1275 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); 1276 if (status < 0) 1277 break; 1278 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); 1279 if (status < 0) 1280 break; 1281 1282 status = WriteTable(state, state->m_InitFE_2); 1283 if (status < 0) 1284 break; 1285 1286 } while (0); 1287 1288 return status; 1289 } 1290 1291 static int InitFT(struct drxd_state *state) 1292 { 1293 /* 1294 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk 1295 SC stuff 1296 */ 1297 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); 1298 } 1299 1300 static int SC_WaitForReady(struct drxd_state *state) 1301 { 1302 u16 curCmd; 1303 int i; 1304 1305 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) { 1306 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); 1307 if (status == 0 || curCmd == 0) 1308 return status; 1309 } 1310 return -1; 1311 } 1312 1313 static int SC_SendCommand(struct drxd_state *state, u16 cmd) 1314 { 1315 int status = 0; 1316 u16 errCode; 1317 1318 Write16(state, SC_RA_RAM_CMD__A, cmd, 0); 1319 SC_WaitForReady(state); 1320 1321 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); 1322 1323 if (errCode == 0xFFFF) { 1324 printk(KERN_ERR "Command Error\n"); 1325 status = -1; 1326 } 1327 1328 return status; 1329 } 1330 1331 static int SC_ProcStartCommand(struct drxd_state *state, 1332 u16 subCmd, u16 param0, u16 param1) 1333 { 1334 int status = 0; 1335 u16 scExec; 1336 1337 mutex_lock(&state->mutex); 1338 do { 1339 Read16(state, SC_COMM_EXEC__A, &scExec, 0); 1340 if (scExec != 1) { 1341 status = -1; 1342 break; 1343 } 1344 SC_WaitForReady(state); 1345 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); 1346 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); 1347 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); 1348 1349 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); 1350 } while (0); 1351 mutex_unlock(&state->mutex); 1352 return status; 1353 } 1354 1355 static int SC_SetPrefParamCommand(struct drxd_state *state, 1356 u16 subCmd, u16 param0, u16 param1) 1357 { 1358 int status; 1359 1360 mutex_lock(&state->mutex); 1361 do { 1362 status = SC_WaitForReady(state); 1363 if (status < 0) 1364 break; 1365 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); 1366 if (status < 0) 1367 break; 1368 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); 1369 if (status < 0) 1370 break; 1371 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); 1372 if (status < 0) 1373 break; 1374 1375 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); 1376 if (status < 0) 1377 break; 1378 } while (0); 1379 mutex_unlock(&state->mutex); 1380 return status; 1381 } 1382 1383 #if 0 1384 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result) 1385 { 1386 int status = 0; 1387 1388 mutex_lock(&state->mutex); 1389 do { 1390 status = SC_WaitForReady(state); 1391 if (status < 0) 1392 break; 1393 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM); 1394 if (status < 0) 1395 break; 1396 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0); 1397 if (status < 0) 1398 break; 1399 } while (0); 1400 mutex_unlock(&state->mutex); 1401 return status; 1402 } 1403 #endif 1404 1405 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) 1406 { 1407 int status; 1408 1409 do { 1410 u16 EcOcRegIprInvMpg = 0; 1411 u16 EcOcRegOcModeLop = 0; 1412 u16 EcOcRegOcModeHip = 0; 1413 u16 EcOcRegOcMpgSio = 0; 1414 1415 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */ 1416 1417 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1418 if (bEnableOutput) { 1419 EcOcRegOcModeHip |= 1420 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; 1421 } else 1422 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1423 EcOcRegOcModeLop |= 1424 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1425 } else { 1426 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; 1427 1428 if (bEnableOutput) 1429 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M)); 1430 else 1431 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1432 1433 /* Don't Insert RS Byte */ 1434 if (state->insert_rs_byte) { 1435 EcOcRegOcModeLop &= 1436 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); 1437 EcOcRegOcModeHip &= 1438 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1439 EcOcRegOcModeHip |= 1440 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE; 1441 } else { 1442 EcOcRegOcModeLop |= 1443 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1444 EcOcRegOcModeHip &= 1445 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1446 EcOcRegOcModeHip |= 1447 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE; 1448 } 1449 1450 /* Mode = Parallel */ 1451 if (state->enable_parallel) 1452 EcOcRegOcModeLop &= 1453 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M)); 1454 else 1455 EcOcRegOcModeLop |= 1456 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL; 1457 } 1458 /* Invert Data */ 1459 /* EcOcRegIprInvMpg |= 0x00FF; */ 1460 EcOcRegIprInvMpg &= (~(0x00FF)); 1461 1462 /* Invert Error ( we don't use the pin ) */ 1463 /* EcOcRegIprInvMpg |= 0x0100; */ 1464 EcOcRegIprInvMpg &= (~(0x0100)); 1465 1466 /* Invert Start ( we don't use the pin ) */ 1467 /* EcOcRegIprInvMpg |= 0x0200; */ 1468 EcOcRegIprInvMpg &= (~(0x0200)); 1469 1470 /* Invert Valid ( we don't use the pin ) */ 1471 /* EcOcRegIprInvMpg |= 0x0400; */ 1472 EcOcRegIprInvMpg &= (~(0x0400)); 1473 1474 /* Invert Clock */ 1475 /* EcOcRegIprInvMpg |= 0x0800; */ 1476 EcOcRegIprInvMpg &= (~(0x0800)); 1477 1478 /* EcOcRegOcModeLop =0x05; */ 1479 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); 1480 if (status < 0) 1481 break; 1482 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); 1483 if (status < 0) 1484 break; 1485 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); 1486 if (status < 0) 1487 break; 1488 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); 1489 if (status < 0) 1490 break; 1491 } while (0); 1492 return status; 1493 } 1494 1495 static int SetDeviceTypeId(struct drxd_state *state) 1496 { 1497 int status = 0; 1498 u16 deviceId = 0; 1499 1500 do { 1501 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); 1502 if (status < 0) 1503 break; 1504 /* TODO: why twice? */ 1505 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); 1506 if (status < 0) 1507 break; 1508 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId); 1509 1510 state->type_A = 0; 1511 state->PGA = 0; 1512 state->diversity = 0; 1513 if (deviceId == 0) { /* on A2 only 3975 available */ 1514 state->type_A = 1; 1515 printk(KERN_INFO "DRX3975D-A2\n"); 1516 } else { 1517 deviceId >>= 12; 1518 printk(KERN_INFO "DRX397%dD-B1\n", deviceId); 1519 switch (deviceId) { 1520 case 4: 1521 state->diversity = 1; 1522 /* fall through */ 1523 case 3: 1524 case 7: 1525 state->PGA = 1; 1526 break; 1527 case 6: 1528 state->diversity = 1; 1529 /* fall through */ 1530 case 5: 1531 case 8: 1532 break; 1533 default: 1534 status = -1; 1535 break; 1536 } 1537 } 1538 } while (0); 1539 1540 if (status < 0) 1541 return status; 1542 1543 /* Init Table selection */ 1544 state->m_InitAtomicRead = DRXD_InitAtomicRead; 1545 state->m_InitSC = DRXD_InitSC; 1546 state->m_ResetECRAM = DRXD_ResetECRAM; 1547 if (state->type_A) { 1548 state->m_ResetCEFR = DRXD_ResetCEFR; 1549 state->m_InitFE_1 = DRXD_InitFEA2_1; 1550 state->m_InitFE_2 = DRXD_InitFEA2_2; 1551 state->m_InitCP = DRXD_InitCPA2; 1552 state->m_InitCE = DRXD_InitCEA2; 1553 state->m_InitEQ = DRXD_InitEQA2; 1554 state->m_InitEC = DRXD_InitECA2; 1555 if (load_firmware(state, DRX_FW_FILENAME_A2)) 1556 return -EIO; 1557 } else { 1558 state->m_ResetCEFR = NULL; 1559 state->m_InitFE_1 = DRXD_InitFEB1_1; 1560 state->m_InitFE_2 = DRXD_InitFEB1_2; 1561 state->m_InitCP = DRXD_InitCPB1; 1562 state->m_InitCE = DRXD_InitCEB1; 1563 state->m_InitEQ = DRXD_InitEQB1; 1564 state->m_InitEC = DRXD_InitECB1; 1565 if (load_firmware(state, DRX_FW_FILENAME_B1)) 1566 return -EIO; 1567 } 1568 if (state->diversity) { 1569 state->m_InitDiversityFront = DRXD_InitDiversityFront; 1570 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; 1571 state->m_DisableDiversity = DRXD_DisableDiversity; 1572 state->m_StartDiversityFront = DRXD_StartDiversityFront; 1573 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; 1574 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; 1575 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; 1576 } else { 1577 state->m_InitDiversityFront = NULL; 1578 state->m_InitDiversityEnd = NULL; 1579 state->m_DisableDiversity = NULL; 1580 state->m_StartDiversityFront = NULL; 1581 state->m_StartDiversityEnd = NULL; 1582 state->m_DiversityDelay8MHZ = NULL; 1583 state->m_DiversityDelay6MHZ = NULL; 1584 } 1585 1586 return status; 1587 } 1588 1589 static int CorrectSysClockDeviation(struct drxd_state *state) 1590 { 1591 int status; 1592 s32 incr = 0; 1593 s32 nomincr = 0; 1594 u32 bandwidth = 0; 1595 u32 sysClockInHz = 0; 1596 u32 sysClockFreq = 0; /* in kHz */ 1597 s16 oscClockDeviation; 1598 s16 Diff; 1599 1600 do { 1601 /* Retrieve bandwidth and incr, sanity check */ 1602 1603 /* These accesses should be AtomicReadReg32, but that 1604 causes trouble (at least for diversity */ 1605 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); 1606 if (status < 0) 1607 break; 1608 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); 1609 if (status < 0) 1610 break; 1611 1612 if (state->type_A) { 1613 if ((nomincr - incr < -500) || (nomincr - incr > 500)) 1614 break; 1615 } else { 1616 if ((nomincr - incr < -2000) || (nomincr - incr > 2000)) 1617 break; 1618 } 1619 1620 switch (state->props.bandwidth_hz) { 1621 case 8000000: 1622 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 1623 break; 1624 case 7000000: 1625 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 1626 break; 1627 case 6000000: 1628 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 1629 break; 1630 default: 1631 return -1; 1632 break; 1633 } 1634 1635 /* Compute new sysclock value 1636 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */ 1637 incr += (1 << 23); 1638 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21); 1639 sysClockFreq = (u32) (sysClockInHz / 1000); 1640 /* rounding */ 1641 if ((sysClockInHz % 1000) > 500) 1642 sysClockFreq++; 1643 1644 /* Compute clock deviation in ppm */ 1645 oscClockDeviation = (u16) ((((s32) (sysClockFreq) - 1646 (s32) 1647 (state->expected_sys_clock_freq)) * 1648 1000000L) / 1649 (s32) 1650 (state->expected_sys_clock_freq)); 1651 1652 Diff = oscClockDeviation - state->osc_clock_deviation; 1653 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */ 1654 if (Diff >= -200 && Diff <= 200) { 1655 state->sys_clock_freq = (u16) sysClockFreq; 1656 if (oscClockDeviation != state->osc_clock_deviation) { 1657 if (state->config.osc_deviation) { 1658 state->config.osc_deviation(state->priv, 1659 oscClockDeviation, 1660 1); 1661 state->osc_clock_deviation = 1662 oscClockDeviation; 1663 } 1664 } 1665 /* switch OFF SRMM scan in SC */ 1666 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); 1667 if (status < 0) 1668 break; 1669 /* overrule FE_IF internal value for 1670 proper re-locking */ 1671 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); 1672 if (status < 0) 1673 break; 1674 state->cscd_state = CSCD_SAVED; 1675 } 1676 } while (0); 1677 1678 return status; 1679 } 1680 1681 static int DRX_Stop(struct drxd_state *state) 1682 { 1683 int status; 1684 1685 if (state->drxd_state != DRXD_STARTED) 1686 return 0; 1687 1688 do { 1689 if (state->cscd_state != CSCD_SAVED) { 1690 u32 lock; 1691 status = DRX_GetLockStatus(state, &lock); 1692 if (status < 0) 1693 break; 1694 } 1695 1696 status = StopOC(state); 1697 if (status < 0) 1698 break; 1699 1700 state->drxd_state = DRXD_STOPPED; 1701 1702 status = ConfigureMPEGOutput(state, 0); 1703 if (status < 0) 1704 break; 1705 1706 if (state->type_A) { 1707 /* Stop relevant processors off the device */ 1708 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); 1709 if (status < 0) 1710 break; 1711 1712 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1713 if (status < 0) 1714 break; 1715 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1716 if (status < 0) 1717 break; 1718 } else { 1719 /* Stop all processors except HI & CC & FE */ 1720 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1721 if (status < 0) 1722 break; 1723 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1724 if (status < 0) 1725 break; 1726 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1727 if (status < 0) 1728 break; 1729 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1730 if (status < 0) 1731 break; 1732 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1733 if (status < 0) 1734 break; 1735 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 1736 if (status < 0) 1737 break; 1738 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); 1739 if (status < 0) 1740 break; 1741 } 1742 1743 } while (0); 1744 return status; 1745 } 1746 1747 #if 0 /* Currently unused */ 1748 static int SetOperationMode(struct drxd_state *state, int oMode) 1749 { 1750 int status; 1751 1752 do { 1753 if (state->drxd_state != DRXD_STOPPED) { 1754 status = -1; 1755 break; 1756 } 1757 1758 if (oMode == state->operation_mode) { 1759 status = 0; 1760 break; 1761 } 1762 1763 if (oMode != OM_Default && !state->diversity) { 1764 status = -1; 1765 break; 1766 } 1767 1768 switch (oMode) { 1769 case OM_DVBT_Diversity_Front: 1770 status = WriteTable(state, state->m_InitDiversityFront); 1771 break; 1772 case OM_DVBT_Diversity_End: 1773 status = WriteTable(state, state->m_InitDiversityEnd); 1774 break; 1775 case OM_Default: 1776 /* We need to check how to 1777 get DRXD out of diversity */ 1778 default: 1779 status = WriteTable(state, state->m_DisableDiversity); 1780 break; 1781 } 1782 } while (0); 1783 1784 if (!status) 1785 state->operation_mode = oMode; 1786 return status; 1787 } 1788 #endif 1789 1790 static int StartDiversity(struct drxd_state *state) 1791 { 1792 int status = 0; 1793 u16 rcControl; 1794 1795 do { 1796 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1797 status = WriteTable(state, state->m_StartDiversityFront); 1798 if (status < 0) 1799 break; 1800 } else if (state->operation_mode == OM_DVBT_Diversity_End) { 1801 status = WriteTable(state, state->m_StartDiversityEnd); 1802 if (status < 0) 1803 break; 1804 if (state->props.bandwidth_hz == 8000000) { 1805 status = WriteTable(state, state->m_DiversityDelay8MHZ); 1806 if (status < 0) 1807 break; 1808 } else { 1809 status = WriteTable(state, state->m_DiversityDelay6MHZ); 1810 if (status < 0) 1811 break; 1812 } 1813 1814 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); 1815 if (status < 0) 1816 break; 1817 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); 1818 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | 1819 /* combining enabled */ 1820 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | 1821 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | 1822 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; 1823 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); 1824 if (status < 0) 1825 break; 1826 } 1827 } while (0); 1828 return status; 1829 } 1830 1831 static int SetFrequencyShift(struct drxd_state *state, 1832 u32 offsetFreq, int channelMirrored) 1833 { 1834 int negativeShift = (state->tuner_mirrors == channelMirrored); 1835 1836 /* Handle all mirroring 1837 * 1838 * Note: ADC mirroring (aliasing) is implictly handled by limiting 1839 * feFsRegAddInc to 28 bits below 1840 * (if the result before masking is more than 28 bits, this means 1841 * that the ADC is mirroring. 1842 * The masking is in fact the aliasing of the ADC) 1843 * 1844 */ 1845 1846 /* Compute register value, unsigned computation */ 1847 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + 1848 offsetFreq, 1849 1 << 28, state->sys_clock_freq); 1850 /* Remove integer part */ 1851 state->fe_fs_add_incr &= 0x0FFFFFFFL; 1852 if (negativeShift) 1853 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); 1854 1855 /* Save the frequency shift without tunerOffset compensation 1856 for CtrlGetChannel. */ 1857 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, 1858 1 << 28, state->sys_clock_freq); 1859 /* Remove integer part */ 1860 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; 1861 if (negativeShift) 1862 state->org_fe_fs_add_incr = ((1L << 28) - 1863 state->org_fe_fs_add_incr); 1864 1865 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, 1866 state->fe_fs_add_incr, 0); 1867 } 1868 1869 static int SetCfgNoiseCalibration(struct drxd_state *state, 1870 struct SNoiseCal *noiseCal) 1871 { 1872 u16 beOptEna; 1873 int status = 0; 1874 1875 do { 1876 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); 1877 if (status < 0) 1878 break; 1879 if (noiseCal->cpOpt) { 1880 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1881 } else { 1882 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1883 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); 1884 if (status < 0) 1885 break; 1886 } 1887 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); 1888 if (status < 0) 1889 break; 1890 1891 if (!state->type_A) { 1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); 1893 if (status < 0) 1894 break; 1895 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); 1896 if (status < 0) 1897 break; 1898 } 1899 } while (0); 1900 1901 return status; 1902 } 1903 1904 static int DRX_Start(struct drxd_state *state, s32 off) 1905 { 1906 struct dtv_frontend_properties *p = &state->props; 1907 int status; 1908 1909 u16 transmissionParams = 0; 1910 u16 operationMode = 0; 1911 u16 qpskTdTpsPwr = 0; 1912 u16 qam16TdTpsPwr = 0; 1913 u16 qam64TdTpsPwr = 0; 1914 u32 feIfIncr = 0; 1915 u32 bandwidth = 0; 1916 int mirrorFreqSpect; 1917 1918 u16 qpskSnCeGain = 0; 1919 u16 qam16SnCeGain = 0; 1920 u16 qam64SnCeGain = 0; 1921 u16 qpskIsGainMan = 0; 1922 u16 qam16IsGainMan = 0; 1923 u16 qam64IsGainMan = 0; 1924 u16 qpskIsGainExp = 0; 1925 u16 qam16IsGainExp = 0; 1926 u16 qam64IsGainExp = 0; 1927 u16 bandwidthParam = 0; 1928 1929 if (off < 0) 1930 off = (off - 500) / 1000; 1931 else 1932 off = (off + 500) / 1000; 1933 1934 do { 1935 if (state->drxd_state != DRXD_STOPPED) 1936 return -1; 1937 status = ResetECOD(state); 1938 if (status < 0) 1939 break; 1940 if (state->type_A) { 1941 status = InitSC(state); 1942 if (status < 0) 1943 break; 1944 } else { 1945 status = InitFT(state); 1946 if (status < 0) 1947 break; 1948 status = InitCP(state); 1949 if (status < 0) 1950 break; 1951 status = InitCE(state); 1952 if (status < 0) 1953 break; 1954 status = InitEQ(state); 1955 if (status < 0) 1956 break; 1957 status = InitSC(state); 1958 if (status < 0) 1959 break; 1960 } 1961 1962 /* Restore current IF & RF AGC settings */ 1963 1964 status = SetCfgIfAgc(state, &state->if_agc_cfg); 1965 if (status < 0) 1966 break; 1967 status = SetCfgRfAgc(state, &state->rf_agc_cfg); 1968 if (status < 0) 1969 break; 1970 1971 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); 1972 1973 switch (p->transmission_mode) { 1974 default: /* Not set, detect it automatically */ 1975 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M; 1976 /* try first guess DRX_FFTMODE_8K */ 1977 /* fall through */ 1978 case TRANSMISSION_MODE_8K: 1979 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; 1980 if (state->type_A) { 1981 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); 1982 if (status < 0) 1983 break; 1984 qpskSnCeGain = 99; 1985 qam16SnCeGain = 83; 1986 qam64SnCeGain = 67; 1987 } 1988 break; 1989 case TRANSMISSION_MODE_2K: 1990 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; 1991 if (state->type_A) { 1992 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); 1993 if (status < 0) 1994 break; 1995 qpskSnCeGain = 97; 1996 qam16SnCeGain = 71; 1997 qam64SnCeGain = 65; 1998 } 1999 break; 2000 } 2001 2002 switch (p->guard_interval) { 2003 case GUARD_INTERVAL_1_4: 2004 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 2005 break; 2006 case GUARD_INTERVAL_1_8: 2007 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8; 2008 break; 2009 case GUARD_INTERVAL_1_16: 2010 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16; 2011 break; 2012 case GUARD_INTERVAL_1_32: 2013 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32; 2014 break; 2015 default: /* Not set, detect it automatically */ 2016 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M; 2017 /* try first guess 1/4 */ 2018 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 2019 break; 2020 } 2021 2022 switch (p->hierarchy) { 2023 case HIERARCHY_1: 2024 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; 2025 if (state->type_A) { 2026 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); 2027 if (status < 0) 2028 break; 2029 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); 2030 if (status < 0) 2031 break; 2032 2033 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2034 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; 2035 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1; 2036 2037 qpskIsGainMan = 2038 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2039 qam16IsGainMan = 2040 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 2041 qam64IsGainMan = 2042 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 2043 2044 qpskIsGainExp = 2045 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2046 qam16IsGainExp = 2047 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 2048 qam64IsGainExp = 2049 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 2050 } 2051 break; 2052 2053 case HIERARCHY_2: 2054 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; 2055 if (state->type_A) { 2056 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); 2057 if (status < 0) 2058 break; 2059 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); 2060 if (status < 0) 2061 break; 2062 2063 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2064 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; 2065 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2; 2066 2067 qpskIsGainMan = 2068 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2069 qam16IsGainMan = 2070 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE; 2071 qam64IsGainMan = 2072 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE; 2073 2074 qpskIsGainExp = 2075 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2076 qam16IsGainExp = 2077 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE; 2078 qam64IsGainExp = 2079 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE; 2080 } 2081 break; 2082 case HIERARCHY_4: 2083 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; 2084 if (state->type_A) { 2085 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); 2086 if (status < 0) 2087 break; 2088 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); 2089 if (status < 0) 2090 break; 2091 2092 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2093 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; 2094 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4; 2095 2096 qpskIsGainMan = 2097 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 2098 qam16IsGainMan = 2099 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE; 2100 qam64IsGainMan = 2101 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE; 2102 2103 qpskIsGainExp = 2104 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 2105 qam16IsGainExp = 2106 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE; 2107 qam64IsGainExp = 2108 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE; 2109 } 2110 break; 2111 case HIERARCHY_AUTO: 2112 default: 2113 /* Not set, detect it automatically, start with none */ 2114 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; 2115 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; 2116 if (state->type_A) { 2117 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); 2118 if (status < 0) 2119 break; 2120 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); 2121 if (status < 0) 2122 break; 2123 2124 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; 2125 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; 2126 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN; 2127 2128 qpskIsGainMan = 2129 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE; 2130 qam16IsGainMan = 2131 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 2132 qam64IsGainMan = 2133 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 2134 2135 qpskIsGainExp = 2136 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE; 2137 qam16IsGainExp = 2138 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 2139 qam64IsGainExp = 2140 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 2141 } 2142 break; 2143 } 2144 status = status; 2145 if (status < 0) 2146 break; 2147 2148 switch (p->modulation) { 2149 default: 2150 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M; 2151 /* try first guess DRX_CONSTELLATION_QAM64 */ 2152 /* fall through */ 2153 case QAM_64: 2154 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; 2155 if (state->type_A) { 2156 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); 2157 if (status < 0) 2158 break; 2159 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); 2160 if (status < 0) 2161 break; 2162 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); 2163 if (status < 0) 2164 break; 2165 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); 2166 if (status < 0) 2167 break; 2168 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); 2169 if (status < 0) 2170 break; 2171 2172 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); 2173 if (status < 0) 2174 break; 2175 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); 2176 if (status < 0) 2177 break; 2178 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); 2179 if (status < 0) 2180 break; 2181 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); 2182 if (status < 0) 2183 break; 2184 } 2185 break; 2186 case QPSK: 2187 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; 2188 if (state->type_A) { 2189 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); 2190 if (status < 0) 2191 break; 2192 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); 2193 if (status < 0) 2194 break; 2195 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); 2196 if (status < 0) 2197 break; 2198 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); 2199 if (status < 0) 2200 break; 2201 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); 2202 if (status < 0) 2203 break; 2204 2205 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); 2206 if (status < 0) 2207 break; 2208 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); 2209 if (status < 0) 2210 break; 2211 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); 2212 if (status < 0) 2213 break; 2214 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); 2215 if (status < 0) 2216 break; 2217 } 2218 break; 2219 2220 case QAM_16: 2221 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; 2222 if (state->type_A) { 2223 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); 2224 if (status < 0) 2225 break; 2226 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); 2227 if (status < 0) 2228 break; 2229 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); 2230 if (status < 0) 2231 break; 2232 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); 2233 if (status < 0) 2234 break; 2235 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); 2236 if (status < 0) 2237 break; 2238 2239 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); 2240 if (status < 0) 2241 break; 2242 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); 2243 if (status < 0) 2244 break; 2245 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); 2246 if (status < 0) 2247 break; 2248 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); 2249 if (status < 0) 2250 break; 2251 } 2252 break; 2253 2254 } 2255 status = status; 2256 if (status < 0) 2257 break; 2258 2259 switch (DRX_CHANNEL_HIGH) { 2260 default: 2261 case DRX_CHANNEL_AUTO: 2262 case DRX_CHANNEL_LOW: 2263 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; 2264 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); 2265 if (status < 0) 2266 break; 2267 break; 2268 case DRX_CHANNEL_HIGH: 2269 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; 2270 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); 2271 if (status < 0) 2272 break; 2273 break; 2274 2275 } 2276 2277 switch (p->code_rate_HP) { 2278 case FEC_1_2: 2279 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; 2280 if (state->type_A) { 2281 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); 2282 if (status < 0) 2283 break; 2284 } 2285 break; 2286 default: 2287 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M; 2288 /* fall through */ 2289 case FEC_2_3: 2290 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; 2291 if (state->type_A) { 2292 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); 2293 if (status < 0) 2294 break; 2295 } 2296 break; 2297 case FEC_3_4: 2298 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; 2299 if (state->type_A) { 2300 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); 2301 if (status < 0) 2302 break; 2303 } 2304 break; 2305 case FEC_5_6: 2306 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; 2307 if (state->type_A) { 2308 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); 2309 if (status < 0) 2310 break; 2311 } 2312 break; 2313 case FEC_7_8: 2314 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; 2315 if (state->type_A) { 2316 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); 2317 if (status < 0) 2318 break; 2319 } 2320 break; 2321 } 2322 status = status; 2323 if (status < 0) 2324 break; 2325 2326 /* First determine real bandwidth (Hz) */ 2327 /* Also set delay for impulse noise cruncher (only A2) */ 2328 /* Also set parameters for EC_OC fix, note 2329 EC_OC_REG_TMD_HIL_MAR is changed 2330 by SC for fix for some 8K,1/8 guard but is restored by 2331 InitEC and ResetEC 2332 functions */ 2333 switch (p->bandwidth_hz) { 2334 case 0: 2335 p->bandwidth_hz = 8000000; 2336 /* fall through */ 2337 case 8000000: 2338 /* (64/7)*(8/8)*1000000 */ 2339 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 2340 2341 bandwidthParam = 0; 2342 status = Write16(state, 2343 FE_AG_REG_IND_DEL__A, 50, 0x0000); 2344 break; 2345 case 7000000: 2346 /* (64/7)*(7/8)*1000000 */ 2347 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 2348 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */ 2349 status = Write16(state, 2350 FE_AG_REG_IND_DEL__A, 59, 0x0000); 2351 break; 2352 case 6000000: 2353 /* (64/7)*(6/8)*1000000 */ 2354 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 2355 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */ 2356 status = Write16(state, 2357 FE_AG_REG_IND_DEL__A, 71, 0x0000); 2358 break; 2359 default: 2360 status = -EINVAL; 2361 } 2362 if (status < 0) 2363 break; 2364 2365 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); 2366 if (status < 0) 2367 break; 2368 2369 { 2370 u16 sc_config; 2371 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); 2372 if (status < 0) 2373 break; 2374 2375 /* enable SLAVE mode in 2k 1/32 to 2376 prevent timing change glitches */ 2377 if ((p->transmission_mode == TRANSMISSION_MODE_2K) && 2378 (p->guard_interval == GUARD_INTERVAL_1_32)) { 2379 /* enable slave */ 2380 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M; 2381 } else { 2382 /* disable slave */ 2383 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; 2384 } 2385 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); 2386 if (status < 0) 2387 break; 2388 } 2389 2390 status = SetCfgNoiseCalibration(state, &state->noise_cal); 2391 if (status < 0) 2392 break; 2393 2394 if (state->cscd_state == CSCD_INIT) { 2395 /* switch on SRMM scan in SC */ 2396 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); 2397 if (status < 0) 2398 break; 2399 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/ 2400 state->cscd_state = CSCD_SET; 2401 } 2402 2403 /* Now compute FE_IF_REG_INCR */ 2404 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => 2405 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ 2406 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, 2407 (1ULL << 21), bandwidth) - (1 << 23); 2408 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); 2409 if (status < 0) 2410 break; 2411 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000); 2412 if (status < 0) 2413 break; 2414 /* Bandwidth setting done */ 2415 2416 /* Mirror & frequency offset */ 2417 SetFrequencyShift(state, off, mirrorFreqSpect); 2418 2419 /* Start SC, write channel settings to SC */ 2420 2421 /* Enable SC after setting all other parameters */ 2422 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); 2423 if (status < 0) 2424 break; 2425 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); 2426 if (status < 0) 2427 break; 2428 2429 /* Write SC parameter registers, operation mode */ 2430 #if 1 2431 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M | 2432 SC_RA_RAM_OP_AUTO_GUARD__M | 2433 SC_RA_RAM_OP_AUTO_CONST__M | 2434 SC_RA_RAM_OP_AUTO_HIER__M | 2435 SC_RA_RAM_OP_AUTO_RATE__M); 2436 #endif 2437 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); 2438 if (status < 0) 2439 break; 2440 2441 /* Start correct processes to get in lock */ 2442 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN); 2443 if (status < 0) 2444 break; 2445 2446 status = StartOC(state); 2447 if (status < 0) 2448 break; 2449 2450 if (state->operation_mode != OM_Default) { 2451 status = StartDiversity(state); 2452 if (status < 0) 2453 break; 2454 } 2455 2456 state->drxd_state = DRXD_STARTED; 2457 } while (0); 2458 2459 return status; 2460 } 2461 2462 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) 2463 { 2464 u32 ulRfAgcOutputLevel = 0xffffffff; 2465 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */ 2466 u32 ulRfAgcMinLevel = 0; /* Currently unused */ 2467 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */ 2468 u32 ulRfAgcSpeed = 0; /* Currently unused */ 2469 u32 ulRfAgcMode = 0; /*2; Off */ 2470 u32 ulRfAgcR1 = 820; 2471 u32 ulRfAgcR2 = 2200; 2472 u32 ulRfAgcR3 = 150; 2473 u32 ulIfAgcMode = 0; /* Auto */ 2474 u32 ulIfAgcOutputLevel = 0xffffffff; 2475 u32 ulIfAgcSettleLevel = 0xffffffff; 2476 u32 ulIfAgcMinLevel = 0xffffffff; 2477 u32 ulIfAgcMaxLevel = 0xffffffff; 2478 u32 ulIfAgcSpeed = 0xffffffff; 2479 u32 ulIfAgcR1 = 820; 2480 u32 ulIfAgcR2 = 2200; 2481 u32 ulIfAgcR3 = 150; 2482 u32 ulClock = state->config.clock; 2483 u32 ulSerialMode = 0; 2484 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ 2485 u32 ulHiI2cDelay = HI_I2C_DELAY; 2486 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY; 2487 u32 ulHiI2cPatch = 0; 2488 u32 ulEnvironment = APPENV_PORTABLE; 2489 u32 ulEnvironmentDiversity = APPENV_MOBILE; 2490 u32 ulIFFilter = IFFILTER_SAW; 2491 2492 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2493 state->if_agc_cfg.outputLevel = 0; 2494 state->if_agc_cfg.settleLevel = 140; 2495 state->if_agc_cfg.minOutputLevel = 0; 2496 state->if_agc_cfg.maxOutputLevel = 1023; 2497 state->if_agc_cfg.speed = 904; 2498 2499 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { 2500 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; 2501 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); 2502 } 2503 2504 if (ulIfAgcMode == 0 && 2505 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2506 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2507 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2508 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) { 2509 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2510 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); 2511 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); 2512 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); 2513 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); 2514 } 2515 2516 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); 2517 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); 2518 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); 2519 2520 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); 2521 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); 2522 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); 2523 2524 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2525 /* rest of the RFAgcCfg structure currently unused */ 2526 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { 2527 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; 2528 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); 2529 } 2530 2531 if (ulRfAgcMode == 0 && 2532 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2533 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2534 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2535 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) { 2536 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2537 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); 2538 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); 2539 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); 2540 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); 2541 } 2542 2543 if (ulRfAgcMode == 2) 2544 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; 2545 2546 if (ulEnvironment <= 2) 2547 state->app_env_default = (enum app_env) 2548 (ulEnvironment); 2549 if (ulEnvironmentDiversity <= 2) 2550 state->app_env_diversity = (enum app_env) 2551 (ulEnvironmentDiversity); 2552 2553 if (ulIFFilter == IFFILTER_DISCRETE) { 2554 /* discrete filter */ 2555 state->noise_cal.cpOpt = 0; 2556 state->noise_cal.cpNexpOfs = 40; 2557 state->noise_cal.tdCal2k = -40; 2558 state->noise_cal.tdCal8k = -24; 2559 } else { 2560 /* SAW filter */ 2561 state->noise_cal.cpOpt = 1; 2562 state->noise_cal.cpNexpOfs = 0; 2563 state->noise_cal.tdCal2k = -21; 2564 state->noise_cal.tdCal8k = -24; 2565 } 2566 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); 2567 2568 state->chip_adr = (state->config.demod_address << 1) | 1; 2569 switch (ulHiI2cPatch) { 2570 case 1: 2571 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; 2572 break; 2573 case 3: 2574 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; 2575 break; 2576 default: 2577 state->m_HiI2cPatch = NULL; 2578 } 2579 2580 /* modify tuner and clock attributes */ 2581 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); 2582 /* expected system clock frequency in kHz */ 2583 state->expected_sys_clock_freq = 48000; 2584 /* real system clock frequency in kHz */ 2585 state->sys_clock_freq = 48000; 2586 state->osc_clock_freq = (u16) ulClock; 2587 state->osc_clock_deviation = 0; 2588 state->cscd_state = CSCD_INIT; 2589 state->drxd_state = DRXD_UNINITIALIZED; 2590 2591 state->PGA = 0; 2592 state->type_A = 0; 2593 state->tuner_mirrors = 0; 2594 2595 /* modify MPEG output attributes */ 2596 state->insert_rs_byte = state->config.insert_rs_byte; 2597 state->enable_parallel = (ulSerialMode != 1); 2598 2599 /* Timing div, 250ns/Psys */ 2600 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ 2601 2602 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * 2603 ulHiI2cDelay) / 1000; 2604 /* Bridge delay, uses oscilator clock */ 2605 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ 2606 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * 2607 ulHiI2cBridgeDelay) / 1000; 2608 2609 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2610 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ 2611 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; 2612 return 0; 2613 } 2614 2615 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) 2616 { 2617 int status = 0; 2618 u32 driverVersion; 2619 2620 if (state->init_done) 2621 return 0; 2622 2623 CDRXD(state, state->config.IF ? state->config.IF : 36000000); 2624 2625 do { 2626 state->operation_mode = OM_Default; 2627 2628 status = SetDeviceTypeId(state); 2629 if (status < 0) 2630 break; 2631 2632 /* Apply I2c address patch to B1 */ 2633 if (!state->type_A && state->m_HiI2cPatch != NULL) { 2634 status = WriteTable(state, state->m_HiI2cPatch); 2635 if (status < 0) 2636 break; 2637 } 2638 2639 if (state->type_A) { 2640 /* HI firmware patch for UIO readout, 2641 avoid clearing of result register */ 2642 status = Write16(state, 0x43012D, 0x047f, 0); 2643 if (status < 0) 2644 break; 2645 } 2646 2647 status = HI_ResetCommand(state); 2648 if (status < 0) 2649 break; 2650 2651 status = StopAllProcessors(state); 2652 if (status < 0) 2653 break; 2654 status = InitCC(state); 2655 if (status < 0) 2656 break; 2657 2658 state->osc_clock_deviation = 0; 2659 2660 if (state->config.osc_deviation) 2661 state->osc_clock_deviation = 2662 state->config.osc_deviation(state->priv, 0, 0); 2663 { 2664 /* Handle clock deviation */ 2665 s32 devB; 2666 s32 devA = (s32) (state->osc_clock_deviation) * 2667 (s32) (state->expected_sys_clock_freq); 2668 /* deviation in kHz */ 2669 s32 deviation = (devA / (1000000L)); 2670 /* rounding, signed */ 2671 if (devA > 0) 2672 devB = (2); 2673 else 2674 devB = (-2); 2675 if ((devB * (devA % 1000000L) > 1000000L)) { 2676 /* add +1 or -1 */ 2677 deviation += (devB / 2); 2678 } 2679 2680 state->sys_clock_freq = 2681 (u16) ((state->expected_sys_clock_freq) + 2682 deviation); 2683 } 2684 status = InitHI(state); 2685 if (status < 0) 2686 break; 2687 status = InitAtomicRead(state); 2688 if (status < 0) 2689 break; 2690 2691 status = EnableAndResetMB(state); 2692 if (status < 0) 2693 break; 2694 if (state->type_A) { 2695 status = ResetCEFR(state); 2696 if (status < 0) 2697 break; 2698 } 2699 if (fw) { 2700 status = DownloadMicrocode(state, fw, fw_size); 2701 if (status < 0) 2702 break; 2703 } else { 2704 status = DownloadMicrocode(state, state->microcode, state->microcode_length); 2705 if (status < 0) 2706 break; 2707 } 2708 2709 if (state->PGA) { 2710 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; 2711 SetCfgPga(state, 0); /* PGA = 0 dB */ 2712 } else { 2713 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2714 } 2715 2716 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; 2717 2718 status = InitFE(state); 2719 if (status < 0) 2720 break; 2721 status = InitFT(state); 2722 if (status < 0) 2723 break; 2724 status = InitCP(state); 2725 if (status < 0) 2726 break; 2727 status = InitCE(state); 2728 if (status < 0) 2729 break; 2730 status = InitEQ(state); 2731 if (status < 0) 2732 break; 2733 status = InitEC(state); 2734 if (status < 0) 2735 break; 2736 status = InitSC(state); 2737 if (status < 0) 2738 break; 2739 2740 status = SetCfgIfAgc(state, &state->if_agc_cfg); 2741 if (status < 0) 2742 break; 2743 status = SetCfgRfAgc(state, &state->rf_agc_cfg); 2744 if (status < 0) 2745 break; 2746 2747 state->cscd_state = CSCD_INIT; 2748 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 2749 if (status < 0) 2750 break; 2751 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); 2752 if (status < 0) 2753 break; 2754 2755 driverVersion = (((VERSION_MAJOR / 10) << 4) + 2756 (VERSION_MAJOR % 10)) << 24; 2757 driverVersion += (((VERSION_MINOR / 10) << 4) + 2758 (VERSION_MINOR % 10)) << 16; 2759 driverVersion += ((VERSION_PATCH / 1000) << 12) + 2760 ((VERSION_PATCH / 100) << 8) + 2761 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10); 2762 2763 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); 2764 if (status < 0) 2765 break; 2766 2767 status = StopOC(state); 2768 if (status < 0) 2769 break; 2770 2771 state->drxd_state = DRXD_STOPPED; 2772 state->init_done = 1; 2773 status = 0; 2774 } while (0); 2775 return status; 2776 } 2777 2778 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) 2779 { 2780 DRX_GetLockStatus(state, pLockStatus); 2781 2782 /*if (*pLockStatus&DRX_LOCK_MPEG) */ 2783 if (*pLockStatus & DRX_LOCK_FEC) { 2784 ConfigureMPEGOutput(state, 1); 2785 /* Get status again, in case we have MPEG lock now */ 2786 /*DRX_GetLockStatus(state, pLockStatus); */ 2787 } 2788 2789 return 0; 2790 } 2791 2792 /****************************************************************************/ 2793 /****************************************************************************/ 2794 /****************************************************************************/ 2795 2796 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength) 2797 { 2798 struct drxd_state *state = fe->demodulator_priv; 2799 u32 value; 2800 int res; 2801 2802 res = ReadIFAgc(state, &value); 2803 if (res < 0) 2804 *strength = 0; 2805 else 2806 *strength = 0xffff - (value << 4); 2807 return 0; 2808 } 2809 2810 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status) 2811 { 2812 struct drxd_state *state = fe->demodulator_priv; 2813 u32 lock; 2814 2815 DRXD_status(state, &lock); 2816 *status = 0; 2817 /* No MPEG lock in V255 firmware, bug ? */ 2818 #if 1 2819 if (lock & DRX_LOCK_MPEG) 2820 *status |= FE_HAS_LOCK; 2821 #else 2822 if (lock & DRX_LOCK_FEC) 2823 *status |= FE_HAS_LOCK; 2824 #endif 2825 if (lock & DRX_LOCK_FEC) 2826 *status |= FE_HAS_VITERBI | FE_HAS_SYNC; 2827 if (lock & DRX_LOCK_DEMOD) 2828 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; 2829 2830 return 0; 2831 } 2832 2833 static int drxd_init(struct dvb_frontend *fe) 2834 { 2835 struct drxd_state *state = fe->demodulator_priv; 2836 2837 return DRXD_init(state, NULL, 0); 2838 } 2839 2840 static int drxd_config_i2c(struct dvb_frontend *fe, int onoff) 2841 { 2842 struct drxd_state *state = fe->demodulator_priv; 2843 2844 if (state->config.disable_i2c_gate_ctrl == 1) 2845 return 0; 2846 2847 return DRX_ConfigureI2CBridge(state, onoff); 2848 } 2849 2850 static int drxd_get_tune_settings(struct dvb_frontend *fe, 2851 struct dvb_frontend_tune_settings *sets) 2852 { 2853 sets->min_delay_ms = 10000; 2854 sets->max_drift = 0; 2855 sets->step_size = 0; 2856 return 0; 2857 } 2858 2859 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber) 2860 { 2861 *ber = 0; 2862 return 0; 2863 } 2864 2865 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr) 2866 { 2867 *snr = 0; 2868 return 0; 2869 } 2870 2871 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 2872 { 2873 *ucblocks = 0; 2874 return 0; 2875 } 2876 2877 static int drxd_sleep(struct dvb_frontend *fe) 2878 { 2879 struct drxd_state *state = fe->demodulator_priv; 2880 2881 ConfigureMPEGOutput(state, 0); 2882 return 0; 2883 } 2884 2885 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 2886 { 2887 return drxd_config_i2c(fe, enable); 2888 } 2889 2890 static int drxd_set_frontend(struct dvb_frontend *fe) 2891 { 2892 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 2893 struct drxd_state *state = fe->demodulator_priv; 2894 s32 off = 0; 2895 2896 state->props = *p; 2897 DRX_Stop(state); 2898 2899 if (fe->ops.tuner_ops.set_params) { 2900 fe->ops.tuner_ops.set_params(fe); 2901 if (fe->ops.i2c_gate_ctrl) 2902 fe->ops.i2c_gate_ctrl(fe, 0); 2903 } 2904 2905 msleep(200); 2906 2907 return DRX_Start(state, off); 2908 } 2909 2910 static void drxd_release(struct dvb_frontend *fe) 2911 { 2912 struct drxd_state *state = fe->demodulator_priv; 2913 2914 kfree(state); 2915 } 2916 2917 static const struct dvb_frontend_ops drxd_ops = { 2918 .delsys = { SYS_DVBT}, 2919 .info = { 2920 .name = "Micronas DRXD DVB-T", 2921 .frequency_min = 47125000, 2922 .frequency_max = 855250000, 2923 .frequency_stepsize = 166667, 2924 .frequency_tolerance = 0, 2925 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 2926 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 2927 FE_CAN_FEC_AUTO | 2928 FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2929 FE_CAN_QAM_AUTO | 2930 FE_CAN_TRANSMISSION_MODE_AUTO | 2931 FE_CAN_GUARD_INTERVAL_AUTO | 2932 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS}, 2933 2934 .release = drxd_release, 2935 .init = drxd_init, 2936 .sleep = drxd_sleep, 2937 .i2c_gate_ctrl = drxd_i2c_gate_ctrl, 2938 2939 .set_frontend = drxd_set_frontend, 2940 .get_tune_settings = drxd_get_tune_settings, 2941 2942 .read_status = drxd_read_status, 2943 .read_ber = drxd_read_ber, 2944 .read_signal_strength = drxd_read_signal_strength, 2945 .read_snr = drxd_read_snr, 2946 .read_ucblocks = drxd_read_ucblocks, 2947 }; 2948 2949 struct dvb_frontend *drxd_attach(const struct drxd_config *config, 2950 void *priv, struct i2c_adapter *i2c, 2951 struct device *dev) 2952 { 2953 struct drxd_state *state = NULL; 2954 2955 state = kzalloc(sizeof(*state), GFP_KERNEL); 2956 if (!state) 2957 return NULL; 2958 2959 state->ops = drxd_ops; 2960 state->dev = dev; 2961 state->config = *config; 2962 state->i2c = i2c; 2963 state->priv = priv; 2964 2965 mutex_init(&state->mutex); 2966 2967 if (Read16(state, 0, NULL, 0) < 0) 2968 goto error; 2969 2970 state->frontend.ops = drxd_ops; 2971 state->frontend.demodulator_priv = state; 2972 ConfigureMPEGOutput(state, 0); 2973 /* add few initialization to allow gate control */ 2974 CDRXD(state, state->config.IF ? state->config.IF : 36000000); 2975 InitHI(state); 2976 2977 return &state->frontend; 2978 2979 error: 2980 printk(KERN_ERR "drxd: not found\n"); 2981 kfree(state); 2982 return NULL; 2983 } 2984 EXPORT_SYMBOL(drxd_attach); 2985 2986 MODULE_DESCRIPTION("DRXD driver"); 2987 MODULE_AUTHOR("Micronas"); 2988 MODULE_LICENSE("GPL"); 2989