1 #ifndef DIBX000_COMMON_H 2 #define DIBX000_COMMON_H 3 4 enum dibx000_i2c_interface { 5 DIBX000_I2C_INTERFACE_TUNER = 0, 6 DIBX000_I2C_INTERFACE_GPIO_1_2 = 1, 7 DIBX000_I2C_INTERFACE_GPIO_3_4 = 2, 8 DIBX000_I2C_INTERFACE_GPIO_6_7 = 3 9 }; 10 11 struct dibx000_i2c_master { 12 #define DIB3000MC 1 13 #define DIB7000 2 14 #define DIB7000P 11 15 #define DIB7000MC 12 16 #define DIB8000 13 17 u16 device_rev; 18 19 enum dibx000_i2c_interface selected_interface; 20 21 /* struct i2c_adapter tuner_i2c_adap; */ 22 struct i2c_adapter gated_tuner_i2c_adap; 23 struct i2c_adapter master_i2c_adap_gpio12; 24 struct i2c_adapter master_i2c_adap_gpio34; 25 struct i2c_adapter master_i2c_adap_gpio67; 26 27 struct i2c_adapter *i2c_adap; 28 u8 i2c_addr; 29 30 u16 base_reg; 31 32 /* for the I2C transfer */ 33 struct i2c_msg msg[34]; 34 u8 i2c_write_buffer[8]; 35 u8 i2c_read_buffer[2]; 36 struct mutex i2c_buffer_lock; 37 }; 38 39 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, 40 u16 device_rev, struct i2c_adapter *i2c_adap, 41 u8 i2c_addr); 42 extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master 43 *mst, 44 enum dibx000_i2c_interface 45 intf, int gating); 46 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst); 47 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst); 48 extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed); 49 50 #define BAND_LBAND 0x01 51 #define BAND_UHF 0x02 52 #define BAND_VHF 0x04 53 #define BAND_SBAND 0x08 54 #define BAND_FM 0x10 55 #define BAND_CBAND 0x20 56 57 #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \ 58 (freq_kHz) <= 115000 ? BAND_FM : \ 59 (freq_kHz) <= 250000 ? BAND_VHF : \ 60 (freq_kHz) <= 863000 ? BAND_UHF : \ 61 (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND ) 62 63 struct dibx000_agc_config { 64 /* defines the capabilities of this AGC-setting - using the BAND_-defines */ 65 u8 band_caps; 66 67 u16 setup; 68 69 u16 inv_gain; 70 u16 time_stabiliz; 71 72 u8 alpha_level; 73 u16 thlock; 74 75 u8 wbd_inv; 76 u16 wbd_ref; 77 u8 wbd_sel; 78 u8 wbd_alpha; 79 80 u16 agc1_max; 81 u16 agc1_min; 82 u16 agc2_max; 83 u16 agc2_min; 84 85 u8 agc1_pt1; 86 u8 agc1_pt2; 87 u8 agc1_pt3; 88 89 u8 agc1_slope1; 90 u8 agc1_slope2; 91 92 u8 agc2_pt1; 93 u8 agc2_pt2; 94 95 u8 agc2_slope1; 96 u8 agc2_slope2; 97 98 u8 alpha_mant; 99 u8 alpha_exp; 100 101 u8 beta_mant; 102 u8 beta_exp; 103 104 u8 perform_agc_softsplit; 105 106 struct { 107 u16 min; 108 u16 max; 109 u16 min_thres; 110 u16 max_thres; 111 } split; 112 }; 113 114 struct dibx000_bandwidth_config { 115 u32 internal; 116 u32 sampling; 117 118 u8 pll_prediv; 119 u8 pll_ratio; 120 u8 pll_range; 121 u8 pll_reset; 122 u8 pll_bypass; 123 124 u8 enable_refdiv; 125 u8 bypclk_div; 126 u8 IO_CLK_en_core; 127 u8 ADClkSrc; 128 u8 modulo; 129 130 u16 sad_cfg; 131 132 u32 ifreq; 133 u32 timf; 134 135 u32 xtal_hz; 136 }; 137 138 enum dibx000_adc_states { 139 DIBX000_SLOW_ADC_ON = 0, 140 DIBX000_SLOW_ADC_OFF, 141 DIBX000_ADC_ON, 142 DIBX000_ADC_OFF, 143 DIBX000_VBG_ENABLE, 144 DIBX000_VBG_DISABLE, 145 }; 146 147 #define BANDWIDTH_TO_KHZ(v) ((v) / 1000) 148 #define BANDWIDTH_TO_HZ(v) ((v) * 1000) 149 150 /* Chip output mode. */ 151 #define OUTMODE_HIGH_Z 0 152 #define OUTMODE_MPEG2_PAR_GATED_CLK 1 153 #define OUTMODE_MPEG2_PAR_CONT_CLK 2 154 #define OUTMODE_MPEG2_SERIAL 7 155 #define OUTMODE_DIVERSITY 4 156 #define OUTMODE_MPEG2_FIFO 5 157 #define OUTMODE_ANALOG_ADC 6 158 159 #define INPUT_MODE_OFF 0x11 160 #define INPUT_MODE_DIVERSITY 0x12 161 #define INPUT_MODE_MPEG 0x13 162 163 enum frontend_tune_state { 164 CT_TUNER_START = 10, 165 CT_TUNER_STEP_0, 166 CT_TUNER_STEP_1, 167 CT_TUNER_STEP_2, 168 CT_TUNER_STEP_3, 169 CT_TUNER_STEP_4, 170 CT_TUNER_STEP_5, 171 CT_TUNER_STEP_6, 172 CT_TUNER_STEP_7, 173 CT_TUNER_STOP, 174 175 CT_AGC_START = 20, 176 CT_AGC_STEP_0, 177 CT_AGC_STEP_1, 178 CT_AGC_STEP_2, 179 CT_AGC_STEP_3, 180 CT_AGC_STEP_4, 181 CT_AGC_STOP, 182 183 CT_DEMOD_START = 30, 184 CT_DEMOD_STEP_1, 185 CT_DEMOD_STEP_2, 186 CT_DEMOD_STEP_3, 187 CT_DEMOD_STEP_4, 188 CT_DEMOD_STEP_5, 189 CT_DEMOD_STEP_6, 190 CT_DEMOD_STEP_7, 191 CT_DEMOD_STEP_8, 192 CT_DEMOD_STEP_9, 193 CT_DEMOD_STEP_10, 194 CT_DEMOD_STEP_11, 195 CT_DEMOD_SEARCH_NEXT = 51, 196 CT_DEMOD_STEP_LOCKED, 197 CT_DEMOD_STOP, 198 199 CT_DONE = 100, 200 CT_SHUTDOWN, 201 202 }; 203 204 struct dvb_frontend_parametersContext { 205 #define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01 206 #define CHANNEL_STATUS_PARAMETERS_SET 0x02 207 u8 status; 208 u32 tune_time_estimation[2]; 209 s32 tps_available; 210 u16 tps[9]; 211 }; 212 213 #define FE_STATUS_TUNE_FAILED 0 214 #define FE_STATUS_TUNE_TIMED_OUT -1 215 #define FE_STATUS_TUNE_TIME_TOO_SHORT -2 216 #define FE_STATUS_TUNE_PENDING -3 217 #define FE_STATUS_STD_SUCCESS -4 218 #define FE_STATUS_FFT_SUCCESS -5 219 #define FE_STATUS_DEMOD_SUCCESS -6 220 #define FE_STATUS_LOCKED -7 221 #define FE_STATUS_DATA_LOCKED -8 222 223 #define FE_CALLBACK_TIME_NEVER 0xffffffff 224 225 #define ABS(x) ((x < 0) ? (-x) : (x)) 226 227 #define DATA_BUS_ACCESS_MODE_8BIT 0x01 228 #define DATA_BUS_ACCESS_MODE_16BIT 0x02 229 #define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10 230 231 struct dibGPIOFunction { 232 #define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1 233 #define BOARD_GPIO_COMPONENT_DEMOD 2 234 u8 component; 235 236 #define BOARD_GPIO_FUNCTION_BOARD_ON 1 237 #define BOARD_GPIO_FUNCTION_BOARD_OFF 2 238 #define BOARD_GPIO_FUNCTION_COMPONENT_ON 3 239 #define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4 240 #define BOARD_GPIO_FUNCTION_SUBBAND_PWM 5 241 #define BOARD_GPIO_FUNCTION_SUBBAND_GPIO 6 242 u8 function; 243 244 /* mask, direction and value are used specify which GPIO to change GPIO0 245 * is LSB and possible GPIO31 is MSB. The same bit-position as in the 246 * mask is used for the direction and the value. Direction == 1 is OUT, 247 * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN 248 * value has no meaning. 249 * 250 * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be 251 * used to do the PWM. Direction gives the PWModulator to be used. 252 * Value gives the PWM value in device-dependent scale. 253 */ 254 u32 mask; 255 u32 direction; 256 u32 value; 257 }; 258 259 #define MAX_NB_SUBBANDS 8 260 struct dibSubbandSelection { 261 u8 size; /* Actual number of subbands. */ 262 struct { 263 u16 f_mhz; 264 struct dibGPIOFunction gpio; 265 } subband[MAX_NB_SUBBANDS]; 266 }; 267 268 #define DEMOD_TIMF_SET 0x00 269 #define DEMOD_TIMF_GET 0x01 270 #define DEMOD_TIMF_UPDATE 0x02 271 272 #define MPEG_ON_DIBTX 1 273 #define DIV_ON_DIBTX 2 274 #define ADC_ON_DIBTX 3 275 #define DEMOUT_ON_HOSTBUS 4 276 #define DIBTX_ON_HOSTBUS 5 277 #define MPEG_ON_HOSTBUS 6 278 279 #endif 280