1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
4  *
5  * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
6  */
7 
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/i2c.h>
13 #include <linux/mutex.h>
14 #include <asm/div64.h>
15 
16 #include <media/dvb_math.h>
17 
18 #include <media/dvb_frontend.h>
19 
20 #include "dib8000.h"
21 
22 #define LAYER_ALL -1
23 #define LAYER_A   1
24 #define LAYER_B   2
25 #define LAYER_C   3
26 
27 #define MAX_NUMBER_OF_FRONTENDS 6
28 /* #define DIB8000_AGC_FREEZE */
29 
30 static int debug;
31 module_param(debug, int, 0644);
32 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
33 
34 #define dprintk(fmt, arg...) do {					\
35 	if (debug)							\
36 		printk(KERN_DEBUG pr_fmt("%s: " fmt),			\
37 		       __func__, ##arg);				\
38 } while (0)
39 
40 struct i2c_device {
41 	struct i2c_adapter *adap;
42 	u8 addr;
43 	u8 *i2c_write_buffer;
44 	u8 *i2c_read_buffer;
45 	struct mutex *i2c_buffer_lock;
46 };
47 
48 enum param_loop_step {
49 	LOOP_TUNE_1,
50 	LOOP_TUNE_2
51 };
52 
53 enum dib8000_autosearch_step {
54 	AS_START = 0,
55 	AS_SEARCHING_FFT,
56 	AS_SEARCHING_GUARD,
57 	AS_DONE = 100,
58 };
59 
60 enum timeout_mode {
61 	SYMBOL_DEPENDENT_OFF = 0,
62 	SYMBOL_DEPENDENT_ON,
63 };
64 
65 struct dib8000_state {
66 	struct dib8000_config cfg;
67 
68 	struct i2c_device i2c;
69 
70 	struct dibx000_i2c_master i2c_master;
71 
72 	u16 wbd_ref;
73 
74 	u8 current_band;
75 	u32 current_bandwidth;
76 	struct dibx000_agc_config *current_agc;
77 	u32 timf;
78 	u32 timf_default;
79 
80 	u8 div_force_off:1;
81 	u8 div_state:1;
82 	u16 div_sync_wait;
83 
84 	u8 agc_state;
85 	u8 differential_constellation;
86 	u8 diversity_onoff;
87 
88 	s16 ber_monitored_layer;
89 	u16 gpio_dir;
90 	u16 gpio_val;
91 
92 	u16 revision;
93 	u8 isdbt_cfg_loaded;
94 	enum frontend_tune_state tune_state;
95 	s32 status;
96 
97 	struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
98 
99 	/* for the I2C transfer */
100 	struct i2c_msg msg[2];
101 	u8 i2c_write_buffer[4];
102 	u8 i2c_read_buffer[2];
103 	struct mutex i2c_buffer_lock;
104 	u8 input_mode_mpeg;
105 
106 	u16 tuner_enable;
107 	struct i2c_adapter dib8096p_tuner_adap;
108 	u16 current_demod_bw;
109 
110 	u16 seg_mask;
111 	u16 seg_diff_mask;
112 	u16 mode;
113 	u8 layer_b_nb_seg;
114 	u8 layer_c_nb_seg;
115 
116 	u8 channel_parameters_set;
117 	u16 autosearch_state;
118 	u16 found_nfft;
119 	u16 found_guard;
120 	u8 subchannel;
121 	u8 symbol_duration;
122 	unsigned long timeout;
123 	u8 longest_intlv_layer;
124 	u16 output_mode;
125 
126 	/* for DVBv5 stats */
127 	s64 init_ucb;
128 	unsigned long per_jiffies_stats;
129 	unsigned long ber_jiffies_stats;
130 	unsigned long ber_jiffies_stats_layer[3];
131 
132 #ifdef DIB8000_AGC_FREEZE
133 	u16 agc1_max;
134 	u16 agc1_min;
135 	u16 agc2_max;
136 	u16 agc2_min;
137 #endif
138 };
139 
140 enum dib8000_power_mode {
141 	DIB8000_POWER_ALL = 0,
142 	DIB8000_POWER_INTERFACE_ONLY,
143 };
144 
145 static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
146 {
147 	u16 ret;
148 	struct i2c_msg msg[2] = {
149 		{.addr = i2c->addr >> 1, .flags = 0, .len = 2},
150 		{.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
151 	};
152 
153 	if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
154 		dprintk("could not acquire lock\n");
155 		return 0;
156 	}
157 
158 	msg[0].buf    = i2c->i2c_write_buffer;
159 	msg[0].buf[0] = reg >> 8;
160 	msg[0].buf[1] = reg & 0xff;
161 	msg[1].buf    = i2c->i2c_read_buffer;
162 
163 	if (i2c_transfer(i2c->adap, msg, 2) != 2)
164 		dprintk("i2c read error on %d\n", reg);
165 
166 	ret = (msg[1].buf[0] << 8) | msg[1].buf[1];
167 	mutex_unlock(i2c->i2c_buffer_lock);
168 	return ret;
169 }
170 
171 static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg)
172 {
173 	u16 ret;
174 
175 	state->i2c_write_buffer[0] = reg >> 8;
176 	state->i2c_write_buffer[1] = reg & 0xff;
177 
178 	memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
179 	state->msg[0].addr = state->i2c.addr >> 1;
180 	state->msg[0].flags = 0;
181 	state->msg[0].buf = state->i2c_write_buffer;
182 	state->msg[0].len = 2;
183 	state->msg[1].addr = state->i2c.addr >> 1;
184 	state->msg[1].flags = I2C_M_RD;
185 	state->msg[1].buf = state->i2c_read_buffer;
186 	state->msg[1].len = 2;
187 
188 	if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
189 		dprintk("i2c read error on %d\n", reg);
190 
191 	ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
192 
193 	return ret;
194 }
195 
196 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
197 {
198 	u16 ret;
199 
200 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
201 		dprintk("could not acquire lock\n");
202 		return 0;
203 	}
204 
205 	ret = __dib8000_read_word(state, reg);
206 
207 	mutex_unlock(&state->i2c_buffer_lock);
208 
209 	return ret;
210 }
211 
212 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
213 {
214 	u16 rw[2];
215 
216 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
217 		dprintk("could not acquire lock\n");
218 		return 0;
219 	}
220 
221 	rw[0] = __dib8000_read_word(state, reg + 0);
222 	rw[1] = __dib8000_read_word(state, reg + 1);
223 
224 	mutex_unlock(&state->i2c_buffer_lock);
225 
226 	return ((rw[0] << 16) | (rw[1]));
227 }
228 
229 static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
230 {
231 	struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
232 	int ret = 0;
233 
234 	if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
235 		dprintk("could not acquire lock\n");
236 		return -EINVAL;
237 	}
238 
239 	msg.buf    = i2c->i2c_write_buffer;
240 	msg.buf[0] = (reg >> 8) & 0xff;
241 	msg.buf[1] = reg & 0xff;
242 	msg.buf[2] = (val >> 8) & 0xff;
243 	msg.buf[3] = val & 0xff;
244 
245 	ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
246 	mutex_unlock(i2c->i2c_buffer_lock);
247 
248 	return ret;
249 }
250 
251 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
252 {
253 	int ret;
254 
255 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
256 		dprintk("could not acquire lock\n");
257 		return -EINVAL;
258 	}
259 
260 	state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
261 	state->i2c_write_buffer[1] = reg & 0xff;
262 	state->i2c_write_buffer[2] = (val >> 8) & 0xff;
263 	state->i2c_write_buffer[3] = val & 0xff;
264 
265 	memset(&state->msg[0], 0, sizeof(struct i2c_msg));
266 	state->msg[0].addr = state->i2c.addr >> 1;
267 	state->msg[0].flags = 0;
268 	state->msg[0].buf = state->i2c_write_buffer;
269 	state->msg[0].len = 4;
270 
271 	ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
272 			-EREMOTEIO : 0);
273 	mutex_unlock(&state->i2c_buffer_lock);
274 
275 	return ret;
276 }
277 
278 static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
279 	(769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
280 		(920 << 5) | 0x09
281 };
282 
283 static const s16 coeff_2k_sb_1seg[8] = {
284 	(692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
285 };
286 
287 static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
288 	(832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
289 		(-931 << 5) | 0x0f
290 };
291 
292 static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
293 	(622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
294 		(982 << 5) | 0x0c
295 };
296 
297 static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
298 	(699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
299 		(-720 << 5) | 0x0d
300 };
301 
302 static const s16 coeff_2k_sb_3seg[8] = {
303 	(664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
304 		(-610 << 5) | 0x0a
305 };
306 
307 static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
308 	(-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
309 		(-922 << 5) | 0x0d
310 };
311 
312 static const s16 coeff_4k_sb_1seg[8] = {
313 	(638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
314 		(-655 << 5) | 0x0a
315 };
316 
317 static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
318 	(-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
319 		(-958 << 5) | 0x13
320 };
321 
322 static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
323 	(-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
324 		(-568 << 5) | 0x0f
325 };
326 
327 static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
328 	(-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
329 		(-848 << 5) | 0x13
330 };
331 
332 static const s16 coeff_4k_sb_3seg[8] = {
333 	(612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
334 		(-869 << 5) | 0x13
335 };
336 
337 static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
338 	(-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
339 		(-598 << 5) | 0x10
340 };
341 
342 static const s16 coeff_8k_sb_1seg[8] = {
343 	(673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
344 		(585 << 5) | 0x0f
345 };
346 
347 static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
348 	(863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
349 		(0 << 5) | 0x14
350 };
351 
352 static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
353 	(-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
354 		(-877 << 5) | 0x15
355 };
356 
357 static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
358 	(-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
359 		(-921 << 5) | 0x14
360 };
361 
362 static const s16 coeff_8k_sb_3seg[8] = {
363 	(514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
364 		(690 << 5) | 0x14
365 };
366 
367 static const s16 ana_fe_coeff_3seg[24] = {
368 	81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
369 };
370 
371 static const s16 ana_fe_coeff_1seg[24] = {
372 	249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
373 };
374 
375 static const s16 ana_fe_coeff_13seg[24] = {
376 	396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
377 };
378 
379 static u16 fft_to_mode(struct dib8000_state *state)
380 {
381 	u16 mode;
382 	switch (state->fe[0]->dtv_property_cache.transmission_mode) {
383 	case TRANSMISSION_MODE_2K:
384 		mode = 1;
385 		break;
386 	case TRANSMISSION_MODE_4K:
387 		mode = 2;
388 		break;
389 	default:
390 	case TRANSMISSION_MODE_AUTO:
391 	case TRANSMISSION_MODE_8K:
392 		mode = 3;
393 		break;
394 	}
395 	return mode;
396 }
397 
398 static void dib8000_set_acquisition_mode(struct dib8000_state *state)
399 {
400 	u16 nud = dib8000_read_word(state, 298);
401 	nud |= (1 << 3) | (1 << 0);
402 	dprintk("acquisition mode activated\n");
403 	dib8000_write_word(state, 298, nud);
404 }
405 static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
406 {
407 	struct dib8000_state *state = fe->demodulator_priv;
408 	u16 outreg, fifo_threshold, smo_mode, sram = 0x0205;	/* by default SDRAM deintlv is enabled */
409 
410 	state->output_mode = mode;
411 	outreg = 0;
412 	fifo_threshold = 1792;
413 	smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
414 
415 	dprintk("-I-	Setting output mode for demod %p to %d\n",
416 			&state->fe[0], mode);
417 
418 	switch (mode) {
419 	case OUTMODE_MPEG2_PAR_GATED_CLK:	// STBs with parallel gated clock
420 		outreg = (1 << 10);	/* 0x0400 */
421 		break;
422 	case OUTMODE_MPEG2_PAR_CONT_CLK:	// STBs with parallel continues clock
423 		outreg = (1 << 10) | (1 << 6);	/* 0x0440 */
424 		break;
425 	case OUTMODE_MPEG2_SERIAL:	// STBs with serial input
426 		outreg = (1 << 10) | (2 << 6) | (0 << 1);	/* 0x0482 */
427 		break;
428 	case OUTMODE_DIVERSITY:
429 		if (state->cfg.hostbus_diversity) {
430 			outreg = (1 << 10) | (4 << 6);	/* 0x0500 */
431 			sram &= 0xfdff;
432 		} else
433 			sram |= 0x0c00;
434 		break;
435 	case OUTMODE_MPEG2_FIFO:	// e.g. USB feeding
436 		smo_mode |= (3 << 1);
437 		fifo_threshold = 512;
438 		outreg = (1 << 10) | (5 << 6);
439 		break;
440 	case OUTMODE_HIGH_Z:	// disable
441 		outreg = 0;
442 		break;
443 
444 	case OUTMODE_ANALOG_ADC:
445 		outreg = (1 << 10) | (3 << 6);
446 		dib8000_set_acquisition_mode(state);
447 		break;
448 
449 	default:
450 		dprintk("Unhandled output_mode passed to be set for demod %p\n",
451 				&state->fe[0]);
452 		return -EINVAL;
453 	}
454 
455 	if (state->cfg.output_mpeg2_in_188_bytes)
456 		smo_mode |= (1 << 5);
457 
458 	dib8000_write_word(state, 299, smo_mode);
459 	dib8000_write_word(state, 300, fifo_threshold);	/* synchronous fread */
460 	dib8000_write_word(state, 1286, outreg);
461 	dib8000_write_word(state, 1291, sram);
462 
463 	return 0;
464 }
465 
466 static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
467 {
468 	struct dib8000_state *state = fe->demodulator_priv;
469 	u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;
470 
471 	dprintk("set diversity input to %i\n", onoff);
472 	if (!state->differential_constellation) {
473 		dib8000_write_word(state, 272, 1 << 9);	//dvsy_off_lmod4 = 1
474 		dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2);	// sync_enable = 1; comb_mode = 2
475 	} else {
476 		dib8000_write_word(state, 272, 0);	//dvsy_off_lmod4 = 0
477 		dib8000_write_word(state, 273, sync_wait);	// sync_enable = 0; comb_mode = 0
478 	}
479 	state->diversity_onoff = onoff;
480 
481 	switch (onoff) {
482 	case 0:		/* only use the internal way - not the diversity input */
483 		dib8000_write_word(state, 270, 1);
484 		dib8000_write_word(state, 271, 0);
485 		break;
486 	case 1:		/* both ways */
487 		dib8000_write_word(state, 270, 6);
488 		dib8000_write_word(state, 271, 6);
489 		break;
490 	case 2:		/* only the diversity input */
491 		dib8000_write_word(state, 270, 0);
492 		dib8000_write_word(state, 271, 1);
493 		break;
494 	}
495 
496 	if (state->revision == 0x8002) {
497 		tmp = dib8000_read_word(state, 903);
498 		dib8000_write_word(state, 903, tmp & ~(1 << 3));
499 		msleep(30);
500 		dib8000_write_word(state, 903, tmp | (1 << 3));
501 	}
502 	return 0;
503 }
504 
505 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
506 {
507 	/* by default everything is going to be powered off */
508 	u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
509 		reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
510 		reg_1280;
511 
512 	if (state->revision != 0x8090)
513 		reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
514 	else
515 		reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
516 
517 	/* now, depending on the requested mode, we power on */
518 	switch (mode) {
519 		/* power up everything in the demod */
520 	case DIB8000_POWER_ALL:
521 		reg_774 = 0x0000;
522 		reg_775 = 0x0000;
523 		reg_776 = 0x0000;
524 		reg_900 &= 0xfffc;
525 		if (state->revision != 0x8090)
526 			reg_1280 &= 0x00ff;
527 		else
528 			reg_1280 &= 0x707f;
529 		break;
530 	case DIB8000_POWER_INTERFACE_ONLY:
531 		if (state->revision != 0x8090)
532 			reg_1280 &= 0x00ff;
533 		else
534 			reg_1280 &= 0xfa7b;
535 		break;
536 	}
537 
538 	dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x\n", reg_774, reg_775, reg_776, reg_900, reg_1280);
539 	dib8000_write_word(state, 774, reg_774);
540 	dib8000_write_word(state, 775, reg_775);
541 	dib8000_write_word(state, 776, reg_776);
542 	dib8000_write_word(state, 900, reg_900);
543 	dib8000_write_word(state, 1280, reg_1280);
544 }
545 
546 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
547 {
548 	int ret = 0;
549 	u16 reg, reg_907 = dib8000_read_word(state, 907);
550 	u16 reg_908 = dib8000_read_word(state, 908);
551 
552 	switch (no) {
553 	case DIBX000_SLOW_ADC_ON:
554 		if (state->revision != 0x8090) {
555 			reg_908 |= (1 << 1) | (1 << 0);
556 			ret |= dib8000_write_word(state, 908, reg_908);
557 			reg_908 &= ~(1 << 1);
558 		} else {
559 			reg = dib8000_read_word(state, 1925);
560 			/* en_slowAdc = 1 & reset_sladc = 1 */
561 			dib8000_write_word(state, 1925, reg |
562 					(1<<4) | (1<<2));
563 
564 			/* read access to make it works... strange ... */
565 			reg = dib8000_read_word(state, 1925);
566 			msleep(20);
567 			/* en_slowAdc = 1 & reset_sladc = 0 */
568 			dib8000_write_word(state, 1925, reg & ~(1<<4));
569 
570 			reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
571 					| (0x3 << 12));
572 			/* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
573 			   (Vin2 = Vcm) */
574 			dib8000_write_word(state, 921, reg | (1 << 14)
575 					| (3 << 12));
576 		}
577 		break;
578 
579 	case DIBX000_SLOW_ADC_OFF:
580 		if (state->revision == 0x8090) {
581 			reg = dib8000_read_word(state, 1925);
582 			/* reset_sladc = 1 en_slowAdc = 0 */
583 			dib8000_write_word(state, 1925,
584 					(reg & ~(1<<2)) | (1<<4));
585 		}
586 		reg_908 |= (1 << 1) | (1 << 0);
587 		break;
588 
589 	case DIBX000_ADC_ON:
590 		reg_907 &= 0x0fff;
591 		reg_908 &= 0x0003;
592 		break;
593 
594 	case DIBX000_ADC_OFF:	// leave the VBG voltage on
595 		reg_907 = (1 << 13) | (1 << 12);
596 		reg_908 = (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1);
597 		break;
598 
599 	case DIBX000_VBG_ENABLE:
600 		reg_907 &= ~(1 << 15);
601 		break;
602 
603 	case DIBX000_VBG_DISABLE:
604 		reg_907 |= (1 << 15);
605 		break;
606 
607 	default:
608 		break;
609 	}
610 
611 	ret |= dib8000_write_word(state, 907, reg_907);
612 	ret |= dib8000_write_word(state, 908, reg_908);
613 
614 	return ret;
615 }
616 
617 static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
618 {
619 	struct dib8000_state *state = fe->demodulator_priv;
620 	u32 timf;
621 
622 	if (bw == 0)
623 		bw = 6000;
624 
625 	if (state->timf == 0) {
626 		dprintk("using default timf\n");
627 		timf = state->timf_default;
628 	} else {
629 		dprintk("using updated timf\n");
630 		timf = state->timf;
631 	}
632 
633 	dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
634 	dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
635 
636 	return 0;
637 }
638 
639 static int dib8000_sad_calib(struct dib8000_state *state)
640 {
641 	u8 sad_sel = 3;
642 
643 	if (state->revision == 0x8090) {
644 		dib8000_write_word(state, 922, (sad_sel << 2));
645 		dib8000_write_word(state, 923, 2048);
646 
647 		dib8000_write_word(state, 922, (sad_sel << 2) | 0x1);
648 		dib8000_write_word(state, 922, (sad_sel << 2));
649 	} else {
650 		/* internal */
651 		dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
652 		dib8000_write_word(state, 924, 776);
653 
654 		/* do the calibration */
655 		dib8000_write_word(state, 923, (1 << 0));
656 		dib8000_write_word(state, 923, (0 << 0));
657 	}
658 
659 	msleep(1);
660 	return 0;
661 }
662 
663 static int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
664 {
665 	struct dib8000_state *state = fe->demodulator_priv;
666 	if (value > 4095)
667 		value = 4095;
668 	state->wbd_ref = value;
669 	return dib8000_write_word(state, 106, value);
670 }
671 
672 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
673 {
674 	dprintk("ifreq: %d %x, inversion: %d\n", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
675 	if (state->revision != 0x8090) {
676 		dib8000_write_word(state, 23,
677 				(u16) (((bw->internal * 1000) >> 16) & 0xffff));
678 		dib8000_write_word(state, 24,
679 				(u16) ((bw->internal * 1000) & 0xffff));
680 	} else {
681 		dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
682 		dib8000_write_word(state, 24,
683 				(u16) ((bw->internal  / 2 * 1000) & 0xffff));
684 	}
685 	dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
686 	dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
687 	dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
688 
689 	if (state->revision != 0x8090)
690 		dib8000_write_word(state, 922, bw->sad_cfg);
691 }
692 
693 static void dib8000_reset_pll(struct dib8000_state *state)
694 {
695 	const struct dibx000_bandwidth_config *pll = state->cfg.pll;
696 	u16 clk_cfg1, reg;
697 
698 	if (state->revision != 0x8090) {
699 		dib8000_write_word(state, 901,
700 				(pll->pll_prediv << 8) | (pll->pll_ratio << 0));
701 
702 		clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
703 			(pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
704 			(1 << 3) | (pll->pll_range << 1) |
705 			(pll->pll_reset << 0);
706 
707 		dib8000_write_word(state, 902, clk_cfg1);
708 		clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
709 		dib8000_write_word(state, 902, clk_cfg1);
710 
711 		dprintk("clk_cfg1: 0x%04x\n", clk_cfg1);
712 
713 		/* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
714 		if (state->cfg.pll->ADClkSrc == 0)
715 			dib8000_write_word(state, 904,
716 					(0 << 15) | (0 << 12) | (0 << 10) |
717 					(pll->modulo << 8) |
718 					(pll->ADClkSrc << 7) | (0 << 1));
719 		else if (state->cfg.refclksel != 0)
720 			dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
721 					((state->cfg.refclksel & 0x3) << 10) |
722 					(pll->modulo << 8) |
723 					(pll->ADClkSrc << 7) | (0 << 1));
724 		else
725 			dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
726 					(3 << 10) | (pll->modulo << 8) |
727 					(pll->ADClkSrc << 7) | (0 << 1));
728 	} else {
729 		dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
730 				(pll->pll_range<<12) | (pll->pll_ratio<<6) |
731 				(pll->pll_prediv));
732 
733 		reg = dib8000_read_word(state, 1857);
734 		dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
735 
736 		reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
737 		dib8000_write_word(state, 1858, reg | 1);
738 
739 		dib8000_write_word(state, 904, (pll->modulo << 8));
740 	}
741 
742 	dib8000_reset_pll_common(state, pll);
743 }
744 
745 static int dib8000_update_pll(struct dvb_frontend *fe,
746 		struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio)
747 {
748 	struct dib8000_state *state = fe->demodulator_priv;
749 	u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
750 	u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
751 	u32 internal, xtal;
752 
753 	/* get back old values */
754 	prediv = reg_1856 & 0x3f;
755 	loopdiv = (reg_1856 >> 6) & 0x3f;
756 
757 	if ((pll == NULL) || (pll->pll_prediv == prediv &&
758 				pll->pll_ratio == loopdiv))
759 		return -EINVAL;
760 
761 	dprintk("Updating pll (prediv: old =  %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
762 	if (state->revision == 0x8090) {
763 		reg_1856 &= 0xf000;
764 		reg_1857 = dib8000_read_word(state, 1857);
765 		/* disable PLL */
766 		dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
767 
768 		dib8000_write_word(state, 1856, reg_1856 |
769 				((pll->pll_ratio & 0x3f) << 6) |
770 				(pll->pll_prediv & 0x3f));
771 
772 		/* write new system clk into P_sec_len */
773 		internal = dib8000_read32(state, 23) / 1000;
774 		dprintk("Old Internal = %d\n", internal);
775 		xtal = 2 * (internal / loopdiv) * prediv;
776 		internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
777 		dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d\n", xtal, internal/1000, internal/2000, internal/8000);
778 		dprintk("New Internal = %d\n", internal);
779 
780 		dib8000_write_word(state, 23,
781 				(u16) (((internal / 2) >> 16) & 0xffff));
782 		dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
783 		/* enable PLL */
784 		dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
785 
786 		while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
787 			dprintk("Waiting for PLL to lock\n");
788 
789 		/* verify */
790 		reg_1856 = dib8000_read_word(state, 1856);
791 		dprintk("PLL Updated with prediv = %d and loopdiv = %d\n",
792 				reg_1856&0x3f, (reg_1856>>6)&0x3f);
793 	} else {
794 		if (bw != state->current_demod_bw) {
795 			/** Bandwidth change => force PLL update **/
796 			dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
797 
798 			if (state->cfg.pll->pll_prediv != oldprediv) {
799 				/** Full PLL change only if prediv is changed **/
800 
801 				/** full update => bypass and reconfigure **/
802 				dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
803 				dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */
804 				dib8000_reset_pll(state);
805 				dib8000_write_word(state, 898, 0x0004); /* sad */
806 			} else
807 				ratio = state->cfg.pll->pll_ratio;
808 
809 			state->current_demod_bw = bw;
810 		}
811 
812 		if (ratio != 0) {
813 			/** ratio update => only change ratio **/
814 			dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);
815 			dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */
816 		}
817 	}
818 
819 	return 0;
820 }
821 
822 static int dib8000_reset_gpio(struct dib8000_state *st)
823 {
824 	/* reset the GPIOs */
825 	dib8000_write_word(st, 1029, st->cfg.gpio_dir);
826 	dib8000_write_word(st, 1030, st->cfg.gpio_val);
827 
828 	/* TODO 782 is P_gpio_od */
829 
830 	dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
831 
832 	dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
833 	return 0;
834 }
835 
836 static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
837 {
838 	st->cfg.gpio_dir = dib8000_read_word(st, 1029);
839 	st->cfg.gpio_dir &= ~(1 << num);	/* reset the direction bit */
840 	st->cfg.gpio_dir |= (dir & 0x1) << num;	/* set the new direction */
841 	dib8000_write_word(st, 1029, st->cfg.gpio_dir);
842 
843 	st->cfg.gpio_val = dib8000_read_word(st, 1030);
844 	st->cfg.gpio_val &= ~(1 << num);	/* reset the direction bit */
845 	st->cfg.gpio_val |= (val & 0x01) << num;	/* set the new value */
846 	dib8000_write_word(st, 1030, st->cfg.gpio_val);
847 
848 	dprintk("gpio dir: %x: gpio val: %x\n", st->cfg.gpio_dir, st->cfg.gpio_val);
849 
850 	return 0;
851 }
852 
853 static int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
854 {
855 	struct dib8000_state *state = fe->demodulator_priv;
856 	return dib8000_cfg_gpio(state, num, dir, val);
857 }
858 
859 static const u16 dib8000_defaults[] = {
860 	/* auto search configuration - lock0 by default waiting
861 	 * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
862 	3, 7,
863 	0x0004,
864 	0x0400,
865 	0x0814,
866 
867 	12, 11,
868 	0x001b,
869 	0x7740,
870 	0x005b,
871 	0x8d80,
872 	0x01c9,
873 	0xc380,
874 	0x0000,
875 	0x0080,
876 	0x0000,
877 	0x0090,
878 	0x0001,
879 	0xd4c0,
880 
881 	/*1, 32,
882 		0x6680 // P_corm_thres Lock algorithms configuration */
883 
884 	11, 80,			/* set ADC level to -16 */
885 	(1 << 13) - 825 - 117,
886 	(1 << 13) - 837 - 117,
887 	(1 << 13) - 811 - 117,
888 	(1 << 13) - 766 - 117,
889 	(1 << 13) - 737 - 117,
890 	(1 << 13) - 693 - 117,
891 	(1 << 13) - 648 - 117,
892 	(1 << 13) - 619 - 117,
893 	(1 << 13) - 575 - 117,
894 	(1 << 13) - 531 - 117,
895 	(1 << 13) - 501 - 117,
896 
897 	4, 108,
898 	0,
899 	0,
900 	0,
901 	0,
902 
903 	1, 175,
904 	0x0410,
905 	1, 179,
906 	8192,			// P_fft_nb_to_cut
907 
908 	6, 181,
909 	0x2800,			// P_coff_corthres_ ( 2k 4k 8k ) 0x2800
910 	0x2800,
911 	0x2800,
912 	0x2800,			// P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
913 	0x2800,
914 	0x2800,
915 
916 	2, 193,
917 	0x0666,			// P_pha3_thres
918 	0x0000,			// P_cti_use_cpe, P_cti_use_prog
919 
920 	2, 205,
921 	0x200f,			// P_cspu_regul, P_cspu_win_cut
922 	0x000f,			// P_des_shift_work
923 
924 	5, 215,
925 	0x023d,			// P_adp_regul_cnt
926 	0x00a4,			// P_adp_noise_cnt
927 	0x00a4,			// P_adp_regul_ext
928 	0x7ff0,			// P_adp_noise_ext
929 	0x3ccc,			// P_adp_fil
930 
931 	1, 230,
932 	0x0000,			// P_2d_byp_ti_num
933 
934 	1, 263,
935 	0x800,			//P_equal_thres_wgn
936 
937 	1, 268,
938 	(2 << 9) | 39,		// P_equal_ctrl_synchro, P_equal_speedmode
939 
940 	1, 270,
941 	0x0001,			// P_div_lock0_wait
942 	1, 285,
943 	0x0020,			//p_fec_
944 	1, 299,
945 	0x0062,			/* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
946 
947 	1, 338,
948 	(1 << 12) |		// P_ctrl_corm_thres4pre_freq_inh=1
949 		(1 << 10) |
950 		(0 << 9) |		/* P_ctrl_pre_freq_inh=0 */
951 		(3 << 5) |		/* P_ctrl_pre_freq_step=3 */
952 		(1 << 0),		/* P_pre_freq_win_len=1 */
953 
954 	0,
955 };
956 
957 static u16 dib8000_identify(struct i2c_device *client)
958 {
959 	u16 value;
960 
961 	//because of glitches sometimes
962 	value = dib8000_i2c_read16(client, 896);
963 
964 	if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
965 		dprintk("wrong Vendor ID (read=0x%x)\n", value);
966 		return 0;
967 	}
968 
969 	value = dib8000_i2c_read16(client, 897);
970 	if (value != 0x8000 && value != 0x8001 &&
971 			value != 0x8002 && value != 0x8090) {
972 		dprintk("wrong Device ID (%x)\n", value);
973 		return 0;
974 	}
975 
976 	switch (value) {
977 	case 0x8000:
978 		dprintk("found DiB8000A\n");
979 		break;
980 	case 0x8001:
981 		dprintk("found DiB8000B\n");
982 		break;
983 	case 0x8002:
984 		dprintk("found DiB8000C\n");
985 		break;
986 	case 0x8090:
987 		dprintk("found DiB8096P\n");
988 		break;
989 	}
990 	return value;
991 }
992 
993 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 *unc);
994 
995 static void dib8000_reset_stats(struct dvb_frontend *fe)
996 {
997 	struct dib8000_state *state = fe->demodulator_priv;
998 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
999 	u32 ucb;
1000 
1001 	memset(&c->strength, 0, sizeof(c->strength));
1002 	memset(&c->cnr, 0, sizeof(c->cnr));
1003 	memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
1004 	memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
1005 	memset(&c->block_error, 0, sizeof(c->block_error));
1006 
1007 	c->strength.len = 1;
1008 	c->cnr.len = 1;
1009 	c->block_error.len = 1;
1010 	c->block_count.len = 1;
1011 	c->post_bit_error.len = 1;
1012 	c->post_bit_count.len = 1;
1013 
1014 	c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1015 	c->strength.stat[0].uvalue = 0;
1016 
1017 	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1018 	c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1019 	c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1020 	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1021 	c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1022 
1023 	dib8000_read_unc_blocks(fe, &ucb);
1024 
1025 	state->init_ucb = -ucb;
1026 	state->ber_jiffies_stats = 0;
1027 	state->per_jiffies_stats = 0;
1028 	memset(&state->ber_jiffies_stats_layer, 0,
1029 	       sizeof(state->ber_jiffies_stats_layer));
1030 }
1031 
1032 static int dib8000_reset(struct dvb_frontend *fe)
1033 {
1034 	struct dib8000_state *state = fe->demodulator_priv;
1035 
1036 	if ((state->revision = dib8000_identify(&state->i2c)) == 0)
1037 		return -EINVAL;
1038 
1039 	/* sram lead in, rdy */
1040 	if (state->revision != 0x8090)
1041 		dib8000_write_word(state, 1287, 0x0003);
1042 
1043 	if (state->revision == 0x8000)
1044 		dprintk("error : dib8000 MA not supported\n");
1045 
1046 	dibx000_reset_i2c_master(&state->i2c_master);
1047 
1048 	dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1049 
1050 	/* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
1051 	dib8000_set_adc_state(state, DIBX000_ADC_OFF);
1052 
1053 	/* restart all parts */
1054 	dib8000_write_word(state, 770, 0xffff);
1055 	dib8000_write_word(state, 771, 0xffff);
1056 	dib8000_write_word(state, 772, 0xfffc);
1057 	dib8000_write_word(state, 898, 0x000c);	/* restart sad */
1058 	if (state->revision == 0x8090)
1059 		dib8000_write_word(state, 1280, 0x0045);
1060 	else
1061 		dib8000_write_word(state, 1280, 0x004d);
1062 	dib8000_write_word(state, 1281, 0x000c);
1063 
1064 	dib8000_write_word(state, 770, 0x0000);
1065 	dib8000_write_word(state, 771, 0x0000);
1066 	dib8000_write_word(state, 772, 0x0000);
1067 	dib8000_write_word(state, 898, 0x0004);	// sad
1068 	dib8000_write_word(state, 1280, 0x0000);
1069 	dib8000_write_word(state, 1281, 0x0000);
1070 
1071 	/* drives */
1072 	if (state->revision != 0x8090) {
1073 		if (state->cfg.drives)
1074 			dib8000_write_word(state, 906, state->cfg.drives);
1075 		else {
1076 			dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.\n");
1077 			/* min drive SDRAM - not optimal - adjust */
1078 			dib8000_write_word(state, 906, 0x2d98);
1079 		}
1080 	}
1081 
1082 	dib8000_reset_pll(state);
1083 	if (state->revision != 0x8090)
1084 		dib8000_write_word(state, 898, 0x0004);
1085 
1086 	if (dib8000_reset_gpio(state) != 0)
1087 		dprintk("GPIO reset was not successful.\n");
1088 
1089 	if ((state->revision != 0x8090) &&
1090 			(dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
1091 		dprintk("OUTPUT_MODE could not be reset.\n");
1092 
1093 	state->current_agc = NULL;
1094 
1095 	// P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
1096 	/* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
1097 	if (state->cfg.pll->ifreq == 0)
1098 		dib8000_write_word(state, 40, 0x0755);	/* P_iqc_corr_inh = 0 enable IQcorr block */
1099 	else
1100 		dib8000_write_word(state, 40, 0x1f55);	/* P_iqc_corr_inh = 1 disable IQcorr block */
1101 
1102 	{
1103 		u16 l = 0, r;
1104 		const u16 *n;
1105 		n = dib8000_defaults;
1106 		l = *n++;
1107 		while (l) {
1108 			r = *n++;
1109 			do {
1110 				dib8000_write_word(state, r, *n++);
1111 				r++;
1112 			} while (--l);
1113 			l = *n++;
1114 		}
1115 	}
1116 
1117 	state->isdbt_cfg_loaded = 0;
1118 
1119 	//div_cfg override for special configs
1120 	if ((state->revision != 8090) && (state->cfg.div_cfg != 0))
1121 		dib8000_write_word(state, 903, state->cfg.div_cfg);
1122 
1123 	/* unforce divstr regardless whether i2c enumeration was done or not */
1124 	dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
1125 
1126 	dib8000_set_bandwidth(fe, 6000);
1127 
1128 	dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1129 	dib8000_sad_calib(state);
1130 	if (state->revision != 0x8090)
1131 		dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
1132 
1133 	/* ber_rs_len = 3 */
1134 	dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));
1135 
1136 	dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
1137 
1138 	dib8000_reset_stats(fe);
1139 
1140 	return 0;
1141 }
1142 
1143 static void dib8000_restart_agc(struct dib8000_state *state)
1144 {
1145 	// P_restart_iqc & P_restart_agc
1146 	dib8000_write_word(state, 770, 0x0a00);
1147 	dib8000_write_word(state, 770, 0x0000);
1148 }
1149 
1150 static int dib8000_update_lna(struct dib8000_state *state)
1151 {
1152 	u16 dyn_gain;
1153 
1154 	if (state->cfg.update_lna) {
1155 		// read dyn_gain here (because it is demod-dependent and not tuner)
1156 		dyn_gain = dib8000_read_word(state, 390);
1157 
1158 		if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
1159 			dib8000_restart_agc(state);
1160 			return 1;
1161 		}
1162 	}
1163 	return 0;
1164 }
1165 
1166 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
1167 {
1168 	struct dibx000_agc_config *agc = NULL;
1169 	int i;
1170 	u16 reg;
1171 
1172 	if (state->current_band == band && state->current_agc != NULL)
1173 		return 0;
1174 	state->current_band = band;
1175 
1176 	for (i = 0; i < state->cfg.agc_config_count; i++)
1177 		if (state->cfg.agc[i].band_caps & band) {
1178 			agc = &state->cfg.agc[i];
1179 			break;
1180 		}
1181 
1182 	if (agc == NULL) {
1183 		dprintk("no valid AGC configuration found for band 0x%02x\n", band);
1184 		return -EINVAL;
1185 	}
1186 
1187 	state->current_agc = agc;
1188 
1189 	/* AGC */
1190 	dib8000_write_word(state, 76, agc->setup);
1191 	dib8000_write_word(state, 77, agc->inv_gain);
1192 	dib8000_write_word(state, 78, agc->time_stabiliz);
1193 	dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
1194 
1195 	// Demod AGC loop configuration
1196 	dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
1197 	dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
1198 
1199 	dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
1200 		state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
1201 
1202 	/* AGC continued */
1203 	if (state->wbd_ref != 0)
1204 		dib8000_write_word(state, 106, state->wbd_ref);
1205 	else			// use default
1206 		dib8000_write_word(state, 106, agc->wbd_ref);
1207 
1208 	if (state->revision == 0x8090) {
1209 		reg = dib8000_read_word(state, 922) & (0x3 << 2);
1210 		dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
1211 	}
1212 
1213 	dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
1214 	dib8000_write_word(state, 108, agc->agc1_max);
1215 	dib8000_write_word(state, 109, agc->agc1_min);
1216 	dib8000_write_word(state, 110, agc->agc2_max);
1217 	dib8000_write_word(state, 111, agc->agc2_min);
1218 	dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
1219 	dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
1220 	dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
1221 	dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
1222 
1223 	dib8000_write_word(state, 75, agc->agc1_pt3);
1224 	if (state->revision != 0x8090)
1225 		dib8000_write_word(state, 923,
1226 				(dib8000_read_word(state, 923) & 0xffe3) |
1227 				(agc->wbd_inv << 4) | (agc->wbd_sel << 2));
1228 
1229 	return 0;
1230 }
1231 
1232 static void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
1233 {
1234 	struct dib8000_state *state = fe->demodulator_priv;
1235 	dib8000_set_adc_state(state, DIBX000_ADC_ON);
1236 	dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
1237 }
1238 
1239 static int dib8000_agc_soft_split(struct dib8000_state *state)
1240 {
1241 	u16 agc, split_offset;
1242 
1243 	if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
1244 		return 0;
1245 
1246 	// n_agc_global
1247 	agc = dib8000_read_word(state, 390);
1248 
1249 	if (agc > state->current_agc->split.min_thres)
1250 		split_offset = state->current_agc->split.min;
1251 	else if (agc < state->current_agc->split.max_thres)
1252 		split_offset = state->current_agc->split.max;
1253 	else
1254 		split_offset = state->current_agc->split.max *
1255 			(agc - state->current_agc->split.min_thres) /
1256 			(state->current_agc->split.max_thres - state->current_agc->split.min_thres);
1257 
1258 	dprintk("AGC split_offset: %d\n", split_offset);
1259 
1260 	// P_agc_force_split and P_agc_split_offset
1261 	dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
1262 	return 5000;
1263 }
1264 
1265 static int dib8000_agc_startup(struct dvb_frontend *fe)
1266 {
1267 	struct dib8000_state *state = fe->demodulator_priv;
1268 	enum frontend_tune_state *tune_state = &state->tune_state;
1269 	int ret = 0;
1270 	u16 reg;
1271 	u32 upd_demod_gain_period = 0x8000;
1272 
1273 	switch (*tune_state) {
1274 	case CT_AGC_START:
1275 		// set power-up level: interf+analog+AGC
1276 
1277 		if (state->revision != 0x8090)
1278 			dib8000_set_adc_state(state, DIBX000_ADC_ON);
1279 		else {
1280 			dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1281 
1282 			reg = dib8000_read_word(state, 1947)&0xff00;
1283 			dib8000_write_word(state, 1946,
1284 					upd_demod_gain_period & 0xFFFF);
1285 			/* bit 14 = enDemodGain */
1286 			dib8000_write_word(state, 1947, reg | (1<<14) |
1287 					((upd_demod_gain_period >> 16) & 0xFF));
1288 
1289 			/* enable adc i & q */
1290 			reg = dib8000_read_word(state, 1920);
1291 			dib8000_write_word(state, 1920, (reg | 0x3) &
1292 					(~(1 << 7)));
1293 		}
1294 
1295 		if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
1296 			*tune_state = CT_AGC_STOP;
1297 			state->status = FE_STATUS_TUNE_FAILED;
1298 			break;
1299 		}
1300 
1301 		ret = 70;
1302 		*tune_state = CT_AGC_STEP_0;
1303 		break;
1304 
1305 	case CT_AGC_STEP_0:
1306 		//AGC initialization
1307 		if (state->cfg.agc_control)
1308 			state->cfg.agc_control(fe, 1);
1309 
1310 		dib8000_restart_agc(state);
1311 
1312 		// wait AGC rough lock time
1313 		ret = 50;
1314 		*tune_state = CT_AGC_STEP_1;
1315 		break;
1316 
1317 	case CT_AGC_STEP_1:
1318 		// wait AGC accurate lock time
1319 		ret = 70;
1320 
1321 		if (dib8000_update_lna(state))
1322 			// wait only AGC rough lock time
1323 			ret = 50;
1324 		else
1325 			*tune_state = CT_AGC_STEP_2;
1326 		break;
1327 
1328 	case CT_AGC_STEP_2:
1329 		dib8000_agc_soft_split(state);
1330 
1331 		if (state->cfg.agc_control)
1332 			state->cfg.agc_control(fe, 0);
1333 
1334 		*tune_state = CT_AGC_STOP;
1335 		break;
1336 	default:
1337 		ret = dib8000_agc_soft_split(state);
1338 		break;
1339 	}
1340 	return ret;
1341 
1342 }
1343 
1344 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
1345 {
1346 	u16 reg;
1347 
1348 	drive &= 0x7;
1349 
1350 	/* drive host bus 2, 3, 4 */
1351 	reg = dib8000_read_word(state, 1798) &
1352 		~(0x7 | (0x7 << 6) | (0x7 << 12));
1353 	reg |= (drive<<12) | (drive<<6) | drive;
1354 	dib8000_write_word(state, 1798, reg);
1355 
1356 	/* drive host bus 5,6 */
1357 	reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1358 	reg |= (drive<<8) | (drive<<2);
1359 	dib8000_write_word(state, 1799, reg);
1360 
1361 	/* drive host bus 7, 8, 9 */
1362 	reg = dib8000_read_word(state, 1800) &
1363 		~(0x7 | (0x7 << 6) | (0x7 << 12));
1364 	reg |= (drive<<12) | (drive<<6) | drive;
1365 	dib8000_write_word(state, 1800, reg);
1366 
1367 	/* drive host bus 10, 11 */
1368 	reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1369 	reg |= (drive<<8) | (drive<<2);
1370 	dib8000_write_word(state, 1801, reg);
1371 
1372 	/* drive host bus 12, 13, 14 */
1373 	reg = dib8000_read_word(state, 1802) &
1374 		~(0x7 | (0x7 << 6) | (0x7 << 12));
1375 	reg |= (drive<<12) | (drive<<6) | drive;
1376 	dib8000_write_word(state, 1802, reg);
1377 }
1378 
1379 static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
1380 		u32 insertExtSynchro, u32 syncSize)
1381 {
1382 	u32 quantif = 3;
1383 	u32 nom = (insertExtSynchro * P_Kin+syncSize);
1384 	u32 denom = P_Kout;
1385 	u32 syncFreq = ((nom << quantif) / denom);
1386 
1387 	if ((syncFreq & ((1 << quantif) - 1)) != 0)
1388 		syncFreq = (syncFreq >> quantif) + 1;
1389 	else
1390 		syncFreq = (syncFreq >> quantif);
1391 
1392 	if (syncFreq != 0)
1393 		syncFreq = syncFreq - 1;
1394 
1395 	return syncFreq;
1396 }
1397 
1398 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
1399 		u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
1400 		u32 syncWord, u32 syncSize)
1401 {
1402 	dprintk("Configure DibStream Tx\n");
1403 
1404 	dib8000_write_word(state, 1615, 1);
1405 	dib8000_write_word(state, 1603, P_Kin);
1406 	dib8000_write_word(state, 1605, P_Kout);
1407 	dib8000_write_word(state, 1606, insertExtSynchro);
1408 	dib8000_write_word(state, 1608, synchroMode);
1409 	dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1410 	dib8000_write_word(state, 1610, syncWord & 0xffff);
1411 	dib8000_write_word(state, 1612, syncSize);
1412 	dib8000_write_word(state, 1615, 0);
1413 }
1414 
1415 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
1416 		u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
1417 		u32 syncWord, u32 syncSize, u32 dataOutRate)
1418 {
1419 	u32 syncFreq;
1420 
1421 	dprintk("Configure DibStream Rx synchroMode = %d\n", synchroMode);
1422 
1423 	if ((P_Kin != 0) && (P_Kout != 0)) {
1424 		syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
1425 				insertExtSynchro, syncSize);
1426 		dib8000_write_word(state, 1542, syncFreq);
1427 	}
1428 
1429 	dib8000_write_word(state, 1554, 1);
1430 	dib8000_write_word(state, 1536, P_Kin);
1431 	dib8000_write_word(state, 1537, P_Kout);
1432 	dib8000_write_word(state, 1539, synchroMode);
1433 	dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
1434 	dib8000_write_word(state, 1541, syncWord & 0xffff);
1435 	dib8000_write_word(state, 1543, syncSize);
1436 	dib8000_write_word(state, 1544, dataOutRate);
1437 	dib8000_write_word(state, 1554, 0);
1438 }
1439 
1440 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
1441 {
1442 	u16 reg_1287;
1443 
1444 	reg_1287 = dib8000_read_word(state, 1287);
1445 
1446 	switch (onoff) {
1447 	case 1:
1448 			reg_1287 &= ~(1 << 8);
1449 			break;
1450 	case 0:
1451 			reg_1287 |= (1 << 8);
1452 			break;
1453 	}
1454 
1455 	dib8000_write_word(state, 1287, reg_1287);
1456 }
1457 
1458 static void dib8096p_configMpegMux(struct dib8000_state *state,
1459 		u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
1460 {
1461 	u16 reg_1287;
1462 
1463 	dprintk("Enable Mpeg mux\n");
1464 
1465 	dib8096p_enMpegMux(state, 0);
1466 
1467 	/* If the input mode is MPEG do not divide the serial clock */
1468 	if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
1469 		enSerialClkDiv2 = 0;
1470 
1471 	reg_1287 = ((pulseWidth & 0x1f) << 3) |
1472 		((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
1473 	dib8000_write_word(state, 1287, reg_1287);
1474 
1475 	dib8096p_enMpegMux(state, 1);
1476 }
1477 
1478 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
1479 {
1480 	u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
1481 
1482 	switch (mode) {
1483 	case MPEG_ON_DIBTX:
1484 			dprintk("SET MPEG ON DIBSTREAM TX\n");
1485 			dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
1486 			reg_1288 |= (1 << 9); break;
1487 	case DIV_ON_DIBTX:
1488 			dprintk("SET DIV_OUT ON DIBSTREAM TX\n");
1489 			dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
1490 			reg_1288 |= (1 << 8); break;
1491 	case ADC_ON_DIBTX:
1492 			dprintk("SET ADC_OUT ON DIBSTREAM TX\n");
1493 			dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
1494 			reg_1288 |= (1 << 7); break;
1495 	default:
1496 			break;
1497 	}
1498 	dib8000_write_word(state, 1288, reg_1288);
1499 }
1500 
1501 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
1502 {
1503 	u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
1504 
1505 	switch (mode) {
1506 	case DEMOUT_ON_HOSTBUS:
1507 			dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n");
1508 			dib8096p_enMpegMux(state, 0);
1509 			reg_1288 |= (1 << 6);
1510 			break;
1511 	case DIBTX_ON_HOSTBUS:
1512 			dprintk("SET DIBSTREAM TX ON HOST BUS\n");
1513 			dib8096p_enMpegMux(state, 0);
1514 			reg_1288 |= (1 << 5);
1515 			break;
1516 	case MPEG_ON_HOSTBUS:
1517 			dprintk("SET MPEG MUX ON HOST BUS\n");
1518 			reg_1288 |= (1 << 4);
1519 			break;
1520 	default:
1521 			break;
1522 	}
1523 	dib8000_write_word(state, 1288, reg_1288);
1524 }
1525 
1526 static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
1527 {
1528 	struct dib8000_state *state = fe->demodulator_priv;
1529 	u16 reg_1287;
1530 
1531 	switch (onoff) {
1532 	case 0: /* only use the internal way - not the diversity input */
1533 			dprintk("%s mode OFF : by default Enable Mpeg INPUT\n",
1534 					__func__);
1535 			/* outputRate = 8 */
1536 			dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
1537 
1538 			/* Do not divide the serial clock of MPEG MUX in
1539 			   SERIAL MODE in case input mode MPEG is used */
1540 			reg_1287 = dib8000_read_word(state, 1287);
1541 			/* enSerialClkDiv2 == 1 ? */
1542 			if ((reg_1287 & 0x1) == 1) {
1543 				/* force enSerialClkDiv2 = 0 */
1544 				reg_1287 &= ~0x1;
1545 				dib8000_write_word(state, 1287, reg_1287);
1546 			}
1547 			state->input_mode_mpeg = 1;
1548 			break;
1549 	case 1: /* both ways */
1550 	case 2: /* only the diversity input */
1551 			dprintk("%s ON : Enable diversity INPUT\n", __func__);
1552 			dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
1553 			state->input_mode_mpeg = 0;
1554 			break;
1555 	}
1556 
1557 	dib8000_set_diversity_in(state->fe[0], onoff);
1558 	return 0;
1559 }
1560 
1561 static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
1562 {
1563 	struct dib8000_state *state = fe->demodulator_priv;
1564 	u16 outreg, smo_mode, fifo_threshold;
1565 	u8 prefer_mpeg_mux_use = 1;
1566 	int ret = 0;
1567 
1568 	state->output_mode = mode;
1569 	dib8096p_host_bus_drive(state, 1);
1570 
1571 	fifo_threshold = 1792;
1572 	smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
1573 	outreg   = dib8000_read_word(state, 1286) &
1574 		~((1 << 10) | (0x7 << 6) | (1 << 1));
1575 
1576 	switch (mode) {
1577 	case OUTMODE_HIGH_Z:
1578 			outreg = 0;
1579 			break;
1580 
1581 	case OUTMODE_MPEG2_SERIAL:
1582 			if (prefer_mpeg_mux_use) {
1583 				dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux\n");
1584 				dib8096p_configMpegMux(state, 3, 1, 1);
1585 				dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1586 			} else {/* Use Smooth block */
1587 				dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc\n");
1588 				dib8096p_setHostBusMux(state,
1589 						DEMOUT_ON_HOSTBUS);
1590 				outreg |= (2 << 6) | (0 << 1);
1591 			}
1592 			break;
1593 
1594 	case OUTMODE_MPEG2_PAR_GATED_CLK:
1595 			if (prefer_mpeg_mux_use) {
1596 				dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux\n");
1597 				dib8096p_configMpegMux(state, 2, 0, 0);
1598 				dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1599 			} else { /* Use Smooth block */
1600 				dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block\n");
1601 				dib8096p_setHostBusMux(state,
1602 						DEMOUT_ON_HOSTBUS);
1603 				outreg |= (0 << 6);
1604 			}
1605 			break;
1606 
1607 	case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
1608 			dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block\n");
1609 			dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1610 			outreg |= (1 << 6);
1611 			break;
1612 
1613 	case OUTMODE_MPEG2_FIFO:
1614 			/* Using Smooth block because not supported
1615 			   by new Mpeg Mux bloc */
1616 			dprintk("dib8096P setting output mode TS_FIFO using Smooth block\n");
1617 			dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1618 			outreg |= (5 << 6);
1619 			smo_mode |= (3 << 1);
1620 			fifo_threshold = 512;
1621 			break;
1622 
1623 	case OUTMODE_DIVERSITY:
1624 			dprintk("dib8096P setting output mode MODE_DIVERSITY\n");
1625 			dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
1626 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1627 			break;
1628 
1629 	case OUTMODE_ANALOG_ADC:
1630 			dprintk("dib8096P setting output mode MODE_ANALOG_ADC\n");
1631 			dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
1632 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1633 			break;
1634 	}
1635 
1636 	if (mode != OUTMODE_HIGH_Z)
1637 		outreg |= (1<<10);
1638 
1639 	dprintk("output_mpeg2_in_188_bytes = %d\n",
1640 			state->cfg.output_mpeg2_in_188_bytes);
1641 	if (state->cfg.output_mpeg2_in_188_bytes)
1642 		smo_mode |= (1 << 5);
1643 
1644 	ret |= dib8000_write_word(state, 299, smo_mode);
1645 	/* synchronous fread */
1646 	ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
1647 	ret |= dib8000_write_word(state, 1286, outreg);
1648 
1649 	return ret;
1650 }
1651 
1652 static int map_addr_to_serpar_number(struct i2c_msg *msg)
1653 {
1654 	if (msg->buf[0] <= 15)
1655 		msg->buf[0] -= 1;
1656 	else if (msg->buf[0] == 17)
1657 		msg->buf[0] = 15;
1658 	else if (msg->buf[0] == 16)
1659 		msg->buf[0] = 17;
1660 	else if (msg->buf[0] == 19)
1661 		msg->buf[0] = 16;
1662 	else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1663 		msg->buf[0] -= 3;
1664 	else if (msg->buf[0] == 28)
1665 		msg->buf[0] = 23;
1666 	else if (msg->buf[0] == 99)
1667 		msg->buf[0] = 99;
1668 	else
1669 		return -EINVAL;
1670 	return 0;
1671 }
1672 
1673 static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
1674 		struct i2c_msg msg[], int num)
1675 {
1676 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1677 	u8 n_overflow = 1;
1678 	u16 i = 1000;
1679 	u16 serpar_num = msg[0].buf[0];
1680 
1681 	while (n_overflow == 1 && i) {
1682 		n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1683 		i--;
1684 		if (i == 0)
1685 			dprintk("Tuner ITF: write busy (overflow)\n");
1686 	}
1687 	dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1688 	dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1689 
1690 	return num;
1691 }
1692 
1693 static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
1694 		struct i2c_msg msg[], int num)
1695 {
1696 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1697 	u8 n_overflow = 1, n_empty = 1;
1698 	u16 i = 1000;
1699 	u16 serpar_num = msg[0].buf[0];
1700 	u16 read_word;
1701 
1702 	while (n_overflow == 1 && i) {
1703 		n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1704 		i--;
1705 		if (i == 0)
1706 			dprintk("TunerITF: read busy (overflow)\n");
1707 	}
1708 	dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
1709 
1710 	i = 1000;
1711 	while (n_empty == 1 && i) {
1712 		n_empty = dib8000_read_word(state, 1984)&0x1;
1713 		i--;
1714 		if (i == 0)
1715 			dprintk("TunerITF: read busy (empty)\n");
1716 	}
1717 
1718 	read_word = dib8000_read_word(state, 1987);
1719 	msg[1].buf[0] = (read_word >> 8) & 0xff;
1720 	msg[1].buf[1] = (read_word) & 0xff;
1721 
1722 	return num;
1723 }
1724 
1725 static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
1726 		struct i2c_msg msg[], int num)
1727 {
1728 	if (map_addr_to_serpar_number(&msg[0]) == 0) {
1729 		if (num == 1) /* write */
1730 			return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
1731 		else /* read */
1732 			return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
1733 	}
1734 	return num;
1735 }
1736 
1737 static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
1738 		struct i2c_msg msg[], int num, u16 apb_address)
1739 {
1740 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1741 	u16 word;
1742 
1743 	if (num == 1) {		/* write */
1744 		dib8000_write_word(state, apb_address,
1745 				((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1746 	} else {
1747 		word = dib8000_read_word(state, apb_address);
1748 		msg[1].buf[0] = (word >> 8) & 0xff;
1749 		msg[1].buf[1] = (word) & 0xff;
1750 	}
1751 	return num;
1752 }
1753 
1754 static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
1755 		struct i2c_msg msg[], int num)
1756 {
1757 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1758 	u16 apb_address = 0, word;
1759 	int i = 0;
1760 
1761 	switch (msg[0].buf[0]) {
1762 	case 0x12:
1763 			apb_address = 1920;
1764 			break;
1765 	case 0x14:
1766 			apb_address = 1921;
1767 			break;
1768 	case 0x24:
1769 			apb_address = 1922;
1770 			break;
1771 	case 0x1a:
1772 			apb_address = 1923;
1773 			break;
1774 	case 0x22:
1775 			apb_address = 1924;
1776 			break;
1777 	case 0x33:
1778 			apb_address = 1926;
1779 			break;
1780 	case 0x34:
1781 			apb_address = 1927;
1782 			break;
1783 	case 0x35:
1784 			apb_address = 1928;
1785 			break;
1786 	case 0x36:
1787 			apb_address = 1929;
1788 			break;
1789 	case 0x37:
1790 			apb_address = 1930;
1791 			break;
1792 	case 0x38:
1793 			apb_address = 1931;
1794 			break;
1795 	case 0x39:
1796 			apb_address = 1932;
1797 			break;
1798 	case 0x2a:
1799 			apb_address = 1935;
1800 			break;
1801 	case 0x2b:
1802 			apb_address = 1936;
1803 			break;
1804 	case 0x2c:
1805 			apb_address = 1937;
1806 			break;
1807 	case 0x2d:
1808 			apb_address = 1938;
1809 			break;
1810 	case 0x2e:
1811 			apb_address = 1939;
1812 			break;
1813 	case 0x2f:
1814 			apb_address = 1940;
1815 			break;
1816 	case 0x30:
1817 			apb_address = 1941;
1818 			break;
1819 	case 0x31:
1820 			apb_address = 1942;
1821 			break;
1822 	case 0x32:
1823 			apb_address = 1943;
1824 			break;
1825 	case 0x3e:
1826 			apb_address = 1944;
1827 			break;
1828 	case 0x3f:
1829 			apb_address = 1945;
1830 			break;
1831 	case 0x40:
1832 			apb_address = 1948;
1833 			break;
1834 	case 0x25:
1835 			apb_address = 936;
1836 			break;
1837 	case 0x26:
1838 			apb_address = 937;
1839 			break;
1840 	case 0x27:
1841 			apb_address = 938;
1842 			break;
1843 	case 0x28:
1844 			apb_address = 939;
1845 			break;
1846 	case 0x1d:
1847 			/* get sad sel request */
1848 			i = ((dib8000_read_word(state, 921) >> 12)&0x3);
1849 			word = dib8000_read_word(state, 924+i);
1850 			msg[1].buf[0] = (word >> 8) & 0xff;
1851 			msg[1].buf[1] = (word) & 0xff;
1852 			return num;
1853 	case 0x1f:
1854 			if (num == 1) {	/* write */
1855 				word = (u16) ((msg[0].buf[1] << 8) |
1856 						msg[0].buf[2]);
1857 				/* in the VGAMODE Sel are located on bit 0/1 */
1858 				word &= 0x3;
1859 				word = (dib8000_read_word(state, 921) &
1860 						~(3<<12)) | (word<<12);
1861 				/* Set the proper input */
1862 				dib8000_write_word(state, 921, word);
1863 				return num;
1864 			}
1865 	}
1866 
1867 	if (apb_address != 0) /* R/W access via APB */
1868 		return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
1869 	else  /* R/W access via SERPAR  */
1870 		return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
1871 
1872 	return 0;
1873 }
1874 
1875 static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
1876 {
1877 	return I2C_FUNC_I2C;
1878 }
1879 
1880 static const struct i2c_algorithm dib8096p_tuner_xfer_algo = {
1881 	.master_xfer = dib8096p_tuner_xfer,
1882 	.functionality = dib8096p_i2c_func,
1883 };
1884 
1885 static struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
1886 {
1887 	struct dib8000_state *st = fe->demodulator_priv;
1888 	return &st->dib8096p_tuner_adap;
1889 }
1890 
1891 static int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
1892 {
1893 	struct dib8000_state *state = fe->demodulator_priv;
1894 	u16 en_cur_state;
1895 
1896 	dprintk("sleep dib8096p: %d\n", onoff);
1897 
1898 	en_cur_state = dib8000_read_word(state, 1922);
1899 
1900 	/* LNAs and MIX are ON and therefore it is a valid configuration */
1901 	if (en_cur_state > 0xff)
1902 		state->tuner_enable = en_cur_state ;
1903 
1904 	if (onoff)
1905 		en_cur_state &= 0x00ff;
1906 	else {
1907 		if (state->tuner_enable != 0)
1908 			en_cur_state = state->tuner_enable;
1909 	}
1910 
1911 	dib8000_write_word(state, 1922, en_cur_state);
1912 
1913 	return 0;
1914 }
1915 
1916 static const s32 lut_1000ln_mant[] =
1917 {
1918 	908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
1919 };
1920 
1921 static s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
1922 {
1923 	struct dib8000_state *state = fe->demodulator_priv;
1924 	u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
1925 	s32 val;
1926 
1927 	val = dib8000_read32(state, 384);
1928 	if (mode) {
1929 		tmp_val = val;
1930 		while (tmp_val >>= 1)
1931 			exp++;
1932 		mant = (val * 1000 / (1<<exp));
1933 		ix = (u8)((mant-1000)/100); /* index of the LUT */
1934 		val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
1935 		val = (val*256)/1000;
1936 	}
1937 	return val;
1938 }
1939 
1940 static int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
1941 {
1942 	struct dib8000_state *state = fe->demodulator_priv;
1943 	int val = 0;
1944 
1945 	switch (IQ) {
1946 	case 1:
1947 			val = dib8000_read_word(state, 403);
1948 			break;
1949 	case 0:
1950 			val = dib8000_read_word(state, 404);
1951 			break;
1952 	}
1953 	if (val  & 0x200)
1954 		val -= 1024;
1955 
1956 	return val;
1957 }
1958 
1959 static void dib8000_update_timf(struct dib8000_state *state)
1960 {
1961 	u32 timf = state->timf = dib8000_read32(state, 435);
1962 
1963 	dib8000_write_word(state, 29, (u16) (timf >> 16));
1964 	dib8000_write_word(state, 30, (u16) (timf & 0xffff));
1965 	dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default);
1966 }
1967 
1968 static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
1969 {
1970 	struct dib8000_state *state = fe->demodulator_priv;
1971 
1972 	switch (op) {
1973 	case DEMOD_TIMF_SET:
1974 			state->timf = timf;
1975 			break;
1976 	case DEMOD_TIMF_UPDATE:
1977 			dib8000_update_timf(state);
1978 			break;
1979 	case DEMOD_TIMF_GET:
1980 			break;
1981 	}
1982 	dib8000_set_bandwidth(state->fe[0], 6000);
1983 
1984 	return state->timf;
1985 }
1986 
1987 static const u16 adc_target_16dB[11] = {
1988 	7250, 7238, 7264, 7309, 7338, 7382, 7427, 7456, 7500, 7544, 7574
1989 };
1990 
1991 static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
1992 
1993 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation)
1994 {
1995 	u8  cr, constellation, time_intlv;
1996 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
1997 
1998 	switch (c->layer[layer_index].modulation) {
1999 	case DQPSK:
2000 			constellation = 0;
2001 			break;
2002 	case  QPSK:
2003 			constellation = 1;
2004 			break;
2005 	case QAM_16:
2006 			constellation = 2;
2007 			break;
2008 	case QAM_64:
2009 	default:
2010 			constellation = 3;
2011 			break;
2012 	}
2013 
2014 	switch (c->layer[layer_index].fec) {
2015 	case FEC_1_2:
2016 			cr = 1;
2017 			break;
2018 	case FEC_2_3:
2019 			cr = 2;
2020 			break;
2021 	case FEC_3_4:
2022 			cr = 3;
2023 			break;
2024 	case FEC_5_6:
2025 			cr = 5;
2026 			break;
2027 	case FEC_7_8:
2028 	default:
2029 			cr = 7;
2030 			break;
2031 	}
2032 
2033 	time_intlv = fls(c->layer[layer_index].interleaving);
2034 	if (time_intlv > 3 && !(time_intlv == 4 && c->isdbt_sb_mode == 1))
2035 		time_intlv = 0;
2036 
2037 	dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv);
2038 	if (c->layer[layer_index].segment_count > 0) {
2039 		switch (max_constellation) {
2040 		case DQPSK:
2041 		case QPSK:
2042 				if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64)
2043 					max_constellation = c->layer[layer_index].modulation;
2044 				break;
2045 		case QAM_16:
2046 				if (c->layer[layer_index].modulation == QAM_64)
2047 					max_constellation = c->layer[layer_index].modulation;
2048 				break;
2049 		}
2050 	}
2051 
2052 	return  max_constellation;
2053 }
2054 
2055 static const u16 adp_Q64[4] = {0x0148, 0xfff0, 0x00a4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_noise_cnt -0.002, P_adp_regul_ext 0.02, P_adp_noise_ext -0.001 */
2056 static const u16 adp_Q16[4] = {0x023d, 0xffdf, 0x00a4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_noise_cnt -0.004, P_adp_regul_ext 0.02, P_adp_noise_ext -0.002 */
2057 static const u16 adp_Qdefault[4] = {0x099a, 0xffae, 0x0333, 0xfff8}; /* P_adp_regul_cnt 0.3,  P_adp_noise_cnt -0.01,  P_adp_regul_ext 0.1,  P_adp_noise_ext -0.002 */
2058 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation)
2059 {
2060 	u16 i, ana_gain = 0;
2061 	const u16 *adp;
2062 
2063 	/* channel estimation fine configuration */
2064 	switch (max_constellation) {
2065 	case QAM_64:
2066 			ana_gain = 0x7;
2067 			adp = &adp_Q64[0];
2068 			break;
2069 	case QAM_16:
2070 			ana_gain = 0x7;
2071 			adp = &adp_Q16[0];
2072 			break;
2073 	default:
2074 			ana_gain = 0;
2075 			adp = &adp_Qdefault[0];
2076 			break;
2077 	}
2078 
2079 	for (i = 0; i < 4; i++)
2080 		dib8000_write_word(state, 215 + i, adp[i]);
2081 
2082 	return ana_gain;
2083 }
2084 
2085 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain)
2086 {
2087 	u16 i;
2088 
2089 	dib8000_write_word(state, 116, ana_gain);
2090 
2091 	/* update ADC target depending on ana_gain */
2092 	if (ana_gain) { /* set -16dB ADC target for ana_gain=-1 */
2093 		for (i = 0; i < 10; i++)
2094 			dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
2095 	} else { /* set -22dB ADC target for ana_gain=0 */
2096 		for (i = 0; i < 10; i++)
2097 			dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
2098 	}
2099 }
2100 
2101 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe)
2102 {
2103 	u16 mode = 0;
2104 
2105 	if (state->isdbt_cfg_loaded == 0)
2106 		for (mode = 0; mode < 24; mode++)
2107 			dib8000_write_word(state, 117 + mode, ana_fe[mode]);
2108 }
2109 
2110 static const u16 lut_prbs_2k[13] = {
2111 	0x423, 0x009, 0x5C7,
2112 	0x7A6, 0x3D8, 0x527,
2113 	0x7FF, 0x79B, 0x3D6,
2114 	0x3A2, 0x53B, 0x2F4,
2115 	0x213
2116 };
2117 
2118 static const u16 lut_prbs_4k[13] = {
2119 	0x208, 0x0C3, 0x7B9,
2120 	0x423, 0x5C7, 0x3D8,
2121 	0x7FF, 0x3D6, 0x53B,
2122 	0x213, 0x029, 0x0D0,
2123 	0x48E
2124 };
2125 
2126 static const u16 lut_prbs_8k[13] = {
2127 	0x740, 0x069, 0x7DD,
2128 	0x208, 0x7B9, 0x5C7,
2129 	0x7FF, 0x53B, 0x029,
2130 	0x48E, 0x4C4, 0x367,
2131 	0x684
2132 };
2133 
2134 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel)
2135 {
2136 	int sub_channel_prbs_group = 0;
2137 	int prbs_group;
2138 
2139 	sub_channel_prbs_group = subchannel / 3;
2140 	if (sub_channel_prbs_group >= ARRAY_SIZE(lut_prbs_2k))
2141 		return 0;
2142 
2143 	switch (state->fe[0]->dtv_property_cache.transmission_mode) {
2144 	case TRANSMISSION_MODE_2K:
2145 		prbs_group = lut_prbs_2k[sub_channel_prbs_group];
2146 		break;
2147 	case TRANSMISSION_MODE_4K:
2148 		prbs_group =  lut_prbs_4k[sub_channel_prbs_group];
2149 		break;
2150 	default:
2151 	case TRANSMISSION_MODE_8K:
2152 		prbs_group = lut_prbs_8k[sub_channel_prbs_group];
2153 	}
2154 
2155 	dprintk("sub_channel_prbs_group = %d , subchannel =%d prbs = 0x%04x\n",
2156 		sub_channel_prbs_group, subchannel, prbs_group);
2157 
2158 	return prbs_group;
2159 }
2160 
2161 static void dib8000_set_13seg_channel(struct dib8000_state *state)
2162 {
2163 	u16 i;
2164 	u16 coff_pow = 0x2800;
2165 
2166 	state->seg_mask = 0x1fff; /* All 13 segments enabled */
2167 
2168 	/* ---- COFF ---- Carloff, the most robust --- */
2169 	if (state->isdbt_cfg_loaded == 0) {  /* if not Sound Broadcasting mode : put default values for 13 segments */
2170 		dib8000_write_word(state, 180, (16 << 6) | 9);
2171 		dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
2172 		coff_pow = 0x2800;
2173 		for (i = 0; i < 6; i++)
2174 			dib8000_write_word(state, 181+i, coff_pow);
2175 
2176 		/* P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1 */
2177 		/* P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1 */
2178 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
2179 
2180 		/* P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6 */
2181 		dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
2182 		/* P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1 */
2183 		dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
2184 
2185 		dib8000_write_word(state, 228, 0);  /* default value */
2186 		dib8000_write_word(state, 265, 31); /* default value */
2187 		dib8000_write_word(state, 205, 0x200f); /* init value */
2188 	}
2189 
2190 	/*
2191 	 * make the cpil_coff_lock more robust but slower p_coff_winlen
2192 	 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
2193 	 */
2194 
2195 	if (state->cfg.pll->ifreq == 0)
2196 		dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
2197 
2198 	dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);
2199 }
2200 
2201 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs)
2202 {
2203 	u16 reg_1;
2204 
2205 	reg_1 = dib8000_read_word(state, 1);
2206 	dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */
2207 }
2208 
2209 static void dib8000_small_fine_tune(struct dib8000_state *state)
2210 {
2211 	u16 i;
2212 	const s16 *ncoeff;
2213 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2214 
2215 	dib8000_write_word(state, 352, state->seg_diff_mask);
2216 	dib8000_write_word(state, 353, state->seg_mask);
2217 
2218 	/* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 */
2219 	dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);
2220 
2221 	if (c->isdbt_sb_mode) {
2222 		/* ---- SMALL ---- */
2223 		switch (c->transmission_mode) {
2224 		case TRANSMISSION_MODE_2K:
2225 				if (c->isdbt_partial_reception == 0) { /* 1-seg */
2226 					if (c->layer[0].modulation == DQPSK) /* DQPSK */
2227 						ncoeff = coeff_2k_sb_1seg_dqpsk;
2228 					else /* QPSK or QAM */
2229 						ncoeff = coeff_2k_sb_1seg;
2230 				} else { /* 3-segments */
2231 					if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2232 						if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2233 							ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
2234 						else /* QPSK or QAM on external segments */
2235 							ncoeff = coeff_2k_sb_3seg_0dqpsk;
2236 					} else { /* QPSK or QAM on central segment */
2237 						if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2238 							ncoeff = coeff_2k_sb_3seg_1dqpsk;
2239 						else /* QPSK or QAM on external segments */
2240 							ncoeff = coeff_2k_sb_3seg;
2241 					}
2242 				}
2243 				break;
2244 		case TRANSMISSION_MODE_4K:
2245 				if (c->isdbt_partial_reception == 0) { /* 1-seg */
2246 					if (c->layer[0].modulation == DQPSK) /* DQPSK */
2247 						ncoeff = coeff_4k_sb_1seg_dqpsk;
2248 					else /* QPSK or QAM */
2249 						ncoeff = coeff_4k_sb_1seg;
2250 				} else { /* 3-segments */
2251 					if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2252 						if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2253 							ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
2254 						else /* QPSK or QAM on external segments */
2255 							ncoeff = coeff_4k_sb_3seg_0dqpsk;
2256 					} else { /* QPSK or QAM on central segment */
2257 						if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2258 							ncoeff = coeff_4k_sb_3seg_1dqpsk;
2259 						else /* QPSK or QAM on external segments */
2260 							ncoeff = coeff_4k_sb_3seg;
2261 					}
2262 				}
2263 				break;
2264 		case TRANSMISSION_MODE_AUTO:
2265 		case TRANSMISSION_MODE_8K:
2266 		default:
2267 				if (c->isdbt_partial_reception == 0) { /* 1-seg */
2268 					if (c->layer[0].modulation == DQPSK) /* DQPSK */
2269 						ncoeff = coeff_8k_sb_1seg_dqpsk;
2270 					else /* QPSK or QAM */
2271 						ncoeff = coeff_8k_sb_1seg;
2272 				} else { /* 3-segments */
2273 					if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2274 						if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2275 							ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
2276 						else /* QPSK or QAM on external segments */
2277 							ncoeff = coeff_8k_sb_3seg_0dqpsk;
2278 					} else { /* QPSK or QAM on central segment */
2279 						if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2280 							ncoeff = coeff_8k_sb_3seg_1dqpsk;
2281 						else /* QPSK or QAM on external segments */
2282 							ncoeff = coeff_8k_sb_3seg;
2283 					}
2284 				}
2285 				break;
2286 		}
2287 
2288 		for (i = 0; i < 8; i++)
2289 			dib8000_write_word(state, 343 + i, ncoeff[i]);
2290 	}
2291 }
2292 
2293 static const u16 coff_thres_1seg[3] = {300, 150, 80};
2294 static const u16 coff_thres_3seg[3] = {350, 300, 250};
2295 static void dib8000_set_sb_channel(struct dib8000_state *state)
2296 {
2297 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2298 	const u16 *coff;
2299 	u16 i;
2300 
2301 	if (c->transmission_mode == TRANSMISSION_MODE_2K || c->transmission_mode == TRANSMISSION_MODE_4K) {
2302 		dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */
2303 		dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */
2304 	} else {
2305 		dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */
2306 		dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */
2307 	}
2308 
2309 	if (c->isdbt_partial_reception == 1) /* 3-segments */
2310 		state->seg_mask = 0x00E0;
2311 	else /* 1-segment */
2312 		state->seg_mask = 0x0040;
2313 
2314 	dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2315 
2316 	/* ---- COFF ---- Carloff, the most robust --- */
2317 	/* P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64, P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 */
2318 	dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3);
2319 
2320 	dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */
2321 	dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */
2322 
2323 	/* Sound Broadcasting mode 1 seg */
2324 	if (c->isdbt_partial_reception == 0) {
2325 		/* P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width = (P_mode == 3) , P_coff_one_seg_sym = (P_mode-1) */
2326 		if (state->mode == 3)
2327 			dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));
2328 		else
2329 			dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));
2330 
2331 		/* P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4 */
2332 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
2333 		coff = &coff_thres_1seg[0];
2334 	} else {   /* Sound Broadcasting mode 3 seg */
2335 		dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
2336 		/* P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4 */
2337 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
2338 		coff = &coff_thres_3seg[0];
2339 	}
2340 
2341 	dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */
2342 	dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */
2343 
2344 	if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K)
2345 		dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */
2346 
2347 	/* Write COFF thres */
2348 	for (i = 0 ; i < 3; i++) {
2349 		dib8000_write_word(state, 181+i, coff[i]);
2350 		dib8000_write_word(state, 184+i, coff[i]);
2351 	}
2352 
2353 	/*
2354 	 * make the cpil_coff_lock more robust but slower p_coff_winlen
2355 	 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
2356 	 */
2357 
2358 	dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */
2359 
2360 	if (c->isdbt_partial_reception == 0)
2361 		dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */
2362 	else
2363 		dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2364 }
2365 
2366 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
2367 {
2368 	u16 p_cfr_left_edge  = 0, p_cfr_right_edge = 0;
2369 	u16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ;
2370 	u16 max_constellation = DQPSK;
2371 	int init_prbs;
2372 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2373 
2374 	if (autosearching)
2375 		c->isdbt_partial_reception = 1;
2376 
2377 	/* P_mode */
2378 	dib8000_write_word(state, 10, (seq << 4));
2379 
2380 	/* init mode */
2381 	state->mode = fft_to_mode(state);
2382 
2383 	/* set guard */
2384 	tmp = dib8000_read_word(state, 1);
2385 	dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));
2386 
2387 	dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));
2388 
2389 	/* signal optimization parameter */
2390 	if (c->isdbt_partial_reception) {
2391 		state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];
2392 		for (i = 1; i < 3; i++)
2393 			nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2394 		for (i = 0; i < nbseg_diff; i++)
2395 			state->seg_diff_mask |= 1 << permu_seg[i+1];
2396 	} else {
2397 		for (i = 0; i < 3; i++)
2398 			nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2399 		for (i = 0; i < nbseg_diff; i++)
2400 			state->seg_diff_mask |= 1 << permu_seg[i];
2401 	}
2402 
2403 	if (state->seg_diff_mask)
2404 		dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2405 	else
2406 		dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */
2407 
2408 	for (i = 0; i < 3; i++)
2409 		max_constellation = dib8000_set_layer(state, i, max_constellation);
2410 	if (autosearching == 0) {
2411 		state->layer_b_nb_seg = c->layer[1].segment_count;
2412 		state->layer_c_nb_seg = c->layer[2].segment_count;
2413 	}
2414 
2415 	/* WRITE: Mode & Diff mask */
2416 	dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);
2417 
2418 	state->differential_constellation = (state->seg_diff_mask != 0);
2419 
2420 	/* channel estimation fine configuration */
2421 	ana_gain = dib8000_adp_fine_tune(state, max_constellation);
2422 
2423 	/* update ana_gain depending on max constellation */
2424 	dib8000_update_ana_gain(state, ana_gain);
2425 
2426 	/* ---- ANA_FE ---- */
2427 	if (c->isdbt_partial_reception) /* 3-segments */
2428 		dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);
2429 	else
2430 		dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */
2431 
2432 	/* TSB or ISDBT ? apply it now */
2433 	if (c->isdbt_sb_mode) {
2434 		dib8000_set_sb_channel(state);
2435 		init_prbs = dib8000_get_init_prbs(state,
2436 						  c->isdbt_sb_subchannel);
2437 	} else {
2438 		dib8000_set_13seg_channel(state);
2439 		init_prbs = 0xfff;
2440 	}
2441 
2442 	/* SMALL */
2443 	dib8000_small_fine_tune(state);
2444 
2445 	dib8000_set_subchannel_prbs(state, init_prbs);
2446 
2447 	/* ---- CHAN_BLK ---- */
2448 	for (i = 0; i < 13; i++) {
2449 		if ((((~state->seg_diff_mask) >> i) & 1) == 1) {
2450 			p_cfr_left_edge  += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0));
2451 			p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0));
2452 		}
2453 	}
2454 	dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */
2455 	dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */
2456 	/* "P_cspu_left_edge" & "P_cspu_right_edge" not used => do not care */
2457 
2458 	dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */
2459 	dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */
2460 	dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */
2461 
2462 	if (!autosearching)
2463 		dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
2464 	else
2465 		dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */
2466 
2467 	dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */
2468 	dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */
2469 
2470 	dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2471 
2472 	/* ---- TMCC ---- */
2473 	for (i = 0; i < 3; i++)
2474 		tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ;
2475 
2476 	/* Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); */
2477 	/* Threshold is set at 1/4 of max power. */
2478 	tmcc_pow *= (1 << (9-2));
2479 	dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */
2480 	dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */
2481 	dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */
2482 	/*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */
2483 
2484 	/* ---- PHA3 ---- */
2485 	if (state->isdbt_cfg_loaded == 0)
2486 		dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */
2487 
2488 	state->isdbt_cfg_loaded = 0;
2489 }
2490 
2491 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal,
2492 			     u32 wait0_ms, u32 wait1_ms, u32 wait2_ms)
2493 {
2494 	u32 value = 0;	/* P_search_end0 wait time */
2495 	u16 reg = 11;	/* P_search_end0 start addr */
2496 
2497 	for (reg = 11; reg < 16; reg += 2) {
2498 		if (reg == 11) {
2499 			if (state->revision == 0x8090)
2500 				value = internal * wait1_ms;
2501 			else
2502 				value = internal * wait0_ms;
2503 		} else if (reg == 13)
2504 			value = internal * wait1_ms;
2505 		else if (reg == 15)
2506 			value = internal * wait2_ms;
2507 		dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff));
2508 		dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff));
2509 	}
2510 	return value;
2511 }
2512 
2513 static int dib8000_autosearch_start(struct dvb_frontend *fe)
2514 {
2515 	struct dib8000_state *state = fe->demodulator_priv;
2516 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2517 	u8 slist = 0;
2518 	u32 value, internal = state->cfg.pll->internal;
2519 
2520 	if (state->revision == 0x8090)
2521 		internal = dib8000_read32(state, 23) / 1000;
2522 
2523 	if ((state->revision >= 0x8002) &&
2524 	    (state->autosearch_state == AS_SEARCHING_FFT)) {
2525 		dib8000_write_word(state,  37, 0x0065); /* P_ctrl_pha_off_max default values */
2526 		dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */
2527 
2528 		dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */
2529 		dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */
2530 		dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */
2531 		dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */
2532 		dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */
2533 		dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */
2534 
2535 		if (state->revision == 0x8090)
2536 			value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2537 		else
2538 			value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2539 
2540 		dib8000_write_word(state, 17, 0);
2541 		dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */
2542 		dib8000_write_word(state, 19, 0);
2543 		dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */
2544 		dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */
2545 		dib8000_write_word(state, 22, value & 0xffff);
2546 
2547 		if (state->revision == 0x8090)
2548 			dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */
2549 		else
2550 			dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */
2551 		dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */
2552 
2553 		/* P_search_param_select = (1 | 1<<4 | 1 << 8) */
2554 		dib8000_write_word(state, 356, 0);
2555 		dib8000_write_word(state, 357, 0x111);
2556 
2557 		dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */
2558 		dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */
2559 		dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */
2560 	} else if ((state->revision >= 0x8002) &&
2561 		   (state->autosearch_state == AS_SEARCHING_GUARD)) {
2562 		c->transmission_mode = TRANSMISSION_MODE_8K;
2563 		c->guard_interval = GUARD_INTERVAL_1_8;
2564 		c->inversion = 0;
2565 		c->layer[0].modulation = QAM_64;
2566 		c->layer[0].fec = FEC_2_3;
2567 		c->layer[0].interleaving = 0;
2568 		c->layer[0].segment_count = 13;
2569 
2570 		slist = 16;
2571 		c->transmission_mode = state->found_nfft;
2572 
2573 		dib8000_set_isdbt_common_channel(state, slist, 1);
2574 
2575 		/* set lock_mask values */
2576 		dib8000_write_word(state, 6, 0x4);
2577 		if (state->revision == 0x8090)
2578 			dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */
2579 		else
2580 			dib8000_write_word(state, 7, 0x8);
2581 		dib8000_write_word(state, 8, 0x1000);
2582 
2583 		/* set lock_mask wait time values */
2584 		if (state->revision == 0x8090)
2585 			dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2586 		else
2587 			dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2588 
2589 		dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */
2590 
2591 		/* P_search_param_select = 0xf; look for the 4 different guard intervals */
2592 		dib8000_write_word(state, 356, 0);
2593 		dib8000_write_word(state, 357, 0xf);
2594 
2595 		value = dib8000_read_word(state, 0);
2596 		dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2597 		dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */
2598 		dib8000_write_word(state, 0, (u16)value);
2599 	} else {
2600 		c->inversion = 0;
2601 		c->layer[0].modulation = QAM_64;
2602 		c->layer[0].fec = FEC_2_3;
2603 		c->layer[0].interleaving = 0;
2604 		c->layer[0].segment_count = 13;
2605 		if (!c->isdbt_sb_mode)
2606 			c->layer[0].segment_count = 13;
2607 
2608 		/* choose the right list, in sb, always do everything */
2609 		if (c->isdbt_sb_mode) {
2610 			slist = 7;
2611 			dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
2612 		} else {
2613 			if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2614 				if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2615 					c->transmission_mode = TRANSMISSION_MODE_8K;
2616 					c->guard_interval = GUARD_INTERVAL_1_8;
2617 					slist = 7;
2618 					dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 to have autosearch start ok with mode2 */
2619 				} else {
2620 					c->guard_interval = GUARD_INTERVAL_1_8;
2621 					slist = 3;
2622 				}
2623 			} else {
2624 				if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2625 					c->transmission_mode = TRANSMISSION_MODE_8K;
2626 					slist = 2;
2627 					dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 */
2628 				} else
2629 					slist = 0;
2630 			}
2631 		}
2632 		dprintk("Using list for autosearch : %d\n", slist);
2633 
2634 		dib8000_set_isdbt_common_channel(state, slist, 1);
2635 
2636 		/* set lock_mask values */
2637 		dib8000_write_word(state, 6, 0x4);
2638 		if (state->revision == 0x8090)
2639 			dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10));
2640 		else
2641 			dib8000_write_word(state, 7, 0x8);
2642 		dib8000_write_word(state, 8, 0x1000);
2643 
2644 		/* set lock_mask wait time values */
2645 		if (state->revision == 0x8090)
2646 			dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2647 		else
2648 			dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2649 
2650 		value = dib8000_read_word(state, 0);
2651 		dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2652 		dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */
2653 		dib8000_write_word(state, 0, (u16)value);
2654 	}
2655 	return 0;
2656 }
2657 
2658 static int dib8000_autosearch_irq(struct dvb_frontend *fe)
2659 {
2660 	struct dib8000_state *state = fe->demodulator_priv;
2661 	u16 irq_pending = dib8000_read_word(state, 1284);
2662 
2663 	if ((state->revision >= 0x8002) &&
2664 	    (state->autosearch_state == AS_SEARCHING_FFT)) {
2665 		if (irq_pending & 0x1) {
2666 			dprintk("dib8000_autosearch_irq: max correlation result available\n");
2667 			return 3;
2668 		}
2669 	} else {
2670 		if (irq_pending & 0x1) {	/* failed */
2671 			dprintk("dib8000_autosearch_irq failed\n");
2672 			return 1;
2673 		}
2674 
2675 		if (irq_pending & 0x2) {	/* succeeded */
2676 			dprintk("dib8000_autosearch_irq succeeded\n");
2677 			return 2;
2678 		}
2679 	}
2680 
2681 	return 0;		// still pending
2682 }
2683 
2684 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff)
2685 {
2686 	u16 tmp;
2687 
2688 	tmp = dib8000_read_word(state, 771);
2689 	if (onoff) /* start P_restart_chd : channel_decoder */
2690 		dib8000_write_word(state, 771, tmp & 0xfffd);
2691 	else /* stop P_restart_chd : channel_decoder */
2692 		dib8000_write_word(state, 771, tmp | (1<<1));
2693 }
2694 
2695 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz)
2696 {
2697 	s16 unit_khz_dds_val;
2698 	u32 abs_offset_khz = abs(offset_khz);
2699 	u32 dds = state->cfg.pll->ifreq & 0x1ffffff;
2700 	u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));
2701 	u8 ratio;
2702 
2703 	if (state->revision == 0x8090) {
2704 		ratio = 4;
2705 		unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000);
2706 		if (offset_khz < 0)
2707 			dds = (1 << 26) - (abs_offset_khz * unit_khz_dds_val);
2708 		else
2709 			dds = (abs_offset_khz * unit_khz_dds_val);
2710 
2711 		if (invert)
2712 			dds = (1<<26) - dds;
2713 	} else {
2714 		ratio = 2;
2715 		unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);
2716 
2717 		if (offset_khz < 0)
2718 			unit_khz_dds_val *= -1;
2719 
2720 		/* IF tuner */
2721 		if (invert)
2722 			dds -= abs_offset_khz * unit_khz_dds_val;
2723 		else
2724 			dds += abs_offset_khz * unit_khz_dds_val;
2725 	}
2726 
2727 	dprintk("setting a DDS frequency offset of %c%dkHz\n", invert ? '-' : ' ', dds / unit_khz_dds_val);
2728 
2729 	if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {
2730 		/* Max dds offset is the half of the demod freq */
2731 		dib8000_write_word(state, 26, invert);
2732 		dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff);
2733 		dib8000_write_word(state, 28, (u16)(dds & 0xffff));
2734 	}
2735 }
2736 
2737 static void dib8000_set_frequency_offset(struct dib8000_state *state)
2738 {
2739 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2740 	int i;
2741 	u32 current_rf;
2742 	int total_dds_offset_khz;
2743 
2744 	if (state->fe[0]->ops.tuner_ops.get_frequency)
2745 		state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], &current_rf);
2746 	else
2747 		current_rf = c->frequency;
2748 	current_rf /= 1000;
2749 	total_dds_offset_khz = (int)current_rf - (int)c->frequency / 1000;
2750 
2751 	if (c->isdbt_sb_mode) {
2752 		state->subchannel = c->isdbt_sb_subchannel;
2753 
2754 		i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */
2755 		dib8000_write_word(state, 26, c->inversion ^ i);
2756 
2757 		if (state->cfg.pll->ifreq == 0) { /* low if tuner */
2758 			if ((c->inversion ^ i) == 0)
2759 				dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
2760 		} else {
2761 			if ((c->inversion ^ i) == 0)
2762 				total_dds_offset_khz *= -1;
2763 		}
2764 	}
2765 
2766 	dprintk("%dkhz tuner offset (frequency = %dHz & current_rf = %dHz) total_dds_offset_hz = %d\n", c->frequency - current_rf, c->frequency, current_rf, total_dds_offset_khz);
2767 
2768 	/* apply dds offset now */
2769 	dib8000_set_dds(state, total_dds_offset_khz);
2770 }
2771 
2772 static u16 LUT_isdbt_symbol_duration[4] = { 26, 101, 63 };
2773 
2774 static u32 dib8000_get_symbol_duration(struct dib8000_state *state)
2775 {
2776 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2777 	u16 i;
2778 
2779 	switch (c->transmission_mode) {
2780 	case TRANSMISSION_MODE_2K:
2781 			i = 0;
2782 			break;
2783 	case TRANSMISSION_MODE_4K:
2784 			i = 2;
2785 			break;
2786 	default:
2787 	case TRANSMISSION_MODE_AUTO:
2788 	case TRANSMISSION_MODE_8K:
2789 			i = 1;
2790 			break;
2791 	}
2792 
2793 	return (LUT_isdbt_symbol_duration[i] / (c->bandwidth_hz / 1000)) + 1;
2794 }
2795 
2796 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_step)
2797 {
2798 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2799 	u16 reg_32 = 0, reg_37 = 0;
2800 
2801 	switch (loop_step) {
2802 	case LOOP_TUNE_1:
2803 			if (c->isdbt_sb_mode)  {
2804 				if (c->isdbt_partial_reception == 0) {
2805 					reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */
2806 					reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P_ctrl_sfreq_step = (10-P_mode)  */
2807 				} else { /* Sound Broadcasting mode 3 seg */
2808 					reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */
2809 					reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P_ctrl_sfreq_step = (9-P_mode)  */
2810 				}
2811 			} else { /* 13-seg start conf offset loop parameters */
2812 				reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
2813 				reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P_ctrl_sfreq_step = 9  */
2814 			}
2815 			break;
2816 	case LOOP_TUNE_2:
2817 			if (c->isdbt_sb_mode)  {
2818 				if (c->isdbt_partial_reception == 0) {  /* Sound Broadcasting mode 1 seg */
2819 					reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/
2820 					reg_37 = (12-state->mode) | ((5 + state->mode) << 5);
2821 				} else {  /* Sound Broadcasting mode 3 seg */
2822 					reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */
2823 					reg_37 = (11-state->mode) | ((5 + state->mode) << 5);
2824 				}
2825 			} else {  /* 13 seg */
2826 				reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */
2827 				reg_37 = ((5+state->mode) << 5) | (10 - state->mode);
2828 			}
2829 			break;
2830 	}
2831 	dib8000_write_word(state, 32, reg_32);
2832 	dib8000_write_word(state, 37, reg_37);
2833 }
2834 
2835 static void dib8000_demod_restart(struct dib8000_state *state)
2836 {
2837 	dib8000_write_word(state, 770, 0x4000);
2838 	dib8000_write_word(state, 770, 0x0000);
2839 	return;
2840 }
2841 
2842 static void dib8000_set_sync_wait(struct dib8000_state *state)
2843 {
2844 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2845 	u16 sync_wait = 64;
2846 
2847 	/* P_dvsy_sync_wait - reuse mode */
2848 	switch (c->transmission_mode) {
2849 	case TRANSMISSION_MODE_8K:
2850 			sync_wait = 256;
2851 			break;
2852 	case TRANSMISSION_MODE_4K:
2853 			sync_wait = 128;
2854 			break;
2855 	default:
2856 	case TRANSMISSION_MODE_2K:
2857 			sync_wait =  64;
2858 			break;
2859 	}
2860 
2861 	if (state->cfg.diversity_delay == 0)
2862 		sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + 48; /* add 50% SFN margin + compensate for one DVSY-fifo */
2863 	else
2864 		sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */
2865 
2866 	dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));
2867 }
2868 
2869 static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode)
2870 {
2871 	if (mode == SYMBOL_DEPENDENT_ON)
2872 		delay *= state->symbol_duration;
2873 
2874 	return jiffies + usecs_to_jiffies(delay * 100);
2875 }
2876 
2877 static s32 dib8000_get_status(struct dvb_frontend *fe)
2878 {
2879 	struct dib8000_state *state = fe->demodulator_priv;
2880 	return state->status;
2881 }
2882 
2883 static enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
2884 {
2885 	struct dib8000_state *state = fe->demodulator_priv;
2886 	return state->tune_state;
2887 }
2888 
2889 static int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
2890 {
2891 	struct dib8000_state *state = fe->demodulator_priv;
2892 
2893 	state->tune_state = tune_state;
2894 	return 0;
2895 }
2896 
2897 static int dib8000_tune_restart_from_demod(struct dvb_frontend *fe)
2898 {
2899 	struct dib8000_state *state = fe->demodulator_priv;
2900 
2901 	state->status = FE_STATUS_TUNE_PENDING;
2902 	state->tune_state = CT_DEMOD_START;
2903 	return 0;
2904 }
2905 
2906 static u16 dib8000_read_lock(struct dvb_frontend *fe)
2907 {
2908 	struct dib8000_state *state = fe->demodulator_priv;
2909 
2910 	if (state->revision == 0x8090)
2911 		return dib8000_read_word(state, 570);
2912 	return dib8000_read_word(state, 568);
2913 }
2914 
2915 static int dib8090p_init_sdram(struct dib8000_state *state)
2916 {
2917 	u16 reg = 0;
2918 	dprintk("init sdram\n");
2919 
2920 	reg = dib8000_read_word(state, 274) & 0xfff0;
2921 	dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */
2922 
2923 	dib8000_write_word(state, 1803, (7 << 2));
2924 
2925 	reg = dib8000_read_word(state, 1280);
2926 	dib8000_write_word(state, 1280,  reg | (1 << 2)); /* force restart P_restart_sdram */
2927 	dib8000_write_word(state, 1280,  reg); /* release restart P_restart_sdram */
2928 
2929 	return 0;
2930 }
2931 
2932 /**
2933  * is_manual_mode - Check if TMCC should be used for parameters settings
2934  * @c:	struct dvb_frontend_properties
2935  *
2936  * By default, TMCC table should be used for parameter settings on most
2937  * usercases. However, sometimes it is desirable to lock the demod to
2938  * use the manual parameters.
2939  *
2940  * On manual mode, the current dib8000_tune state machine is very restrict:
2941  * It requires that both per-layer and per-transponder parameters to be
2942  * properly specified, otherwise the device won't lock.
2943  *
2944  * Check if all those conditions are properly satisfied before allowing
2945  * the device to use the manual frequency lock mode.
2946  */
2947 static int is_manual_mode(struct dtv_frontend_properties *c)
2948 {
2949 	int i, n_segs = 0;
2950 
2951 	/* Use auto mode on DVB-T compat mode */
2952 	if (c->delivery_system != SYS_ISDBT)
2953 		return 0;
2954 
2955 	/*
2956 	 * Transmission mode is only detected on auto mode, currently
2957 	 */
2958 	if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2959 		dprintk("transmission mode auto\n");
2960 		return 0;
2961 	}
2962 
2963 	/*
2964 	 * Guard interval is only detected on auto mode, currently
2965 	 */
2966 	if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2967 		dprintk("guard interval auto\n");
2968 		return 0;
2969 	}
2970 
2971 	/*
2972 	 * If no layer is enabled, assume auto mode, as at least one
2973 	 * layer should be enabled
2974 	 */
2975 	if (!c->isdbt_layer_enabled) {
2976 		dprintk("no layer modulation specified\n");
2977 		return 0;
2978 	}
2979 
2980 	/*
2981 	 * Check if the per-layer parameters aren't auto and
2982 	 * disable a layer if segment count is 0 or invalid.
2983 	 */
2984 	for (i = 0; i < 3; i++) {
2985 		if (!(c->isdbt_layer_enabled & 1 << i))
2986 			continue;
2987 
2988 		if ((c->layer[i].segment_count > 13) ||
2989 		    (c->layer[i].segment_count == 0)) {
2990 			c->isdbt_layer_enabled &= ~(1 << i);
2991 			continue;
2992 		}
2993 
2994 		n_segs += c->layer[i].segment_count;
2995 
2996 		if ((c->layer[i].modulation == QAM_AUTO) ||
2997 		    (c->layer[i].fec == FEC_AUTO)) {
2998 			dprintk("layer %c has either modulation or FEC auto\n",
2999 				'A' + i);
3000 			return 0;
3001 		}
3002 	}
3003 
3004 	/*
3005 	 * Userspace specified a wrong number of segments.
3006 	 *	fallback to auto mode.
3007 	 */
3008 	if (n_segs == 0 || n_segs > 13) {
3009 		dprintk("number of segments is invalid\n");
3010 		return 0;
3011 	}
3012 
3013 	/* Everything looks ok for manual mode */
3014 	return 1;
3015 }
3016 
3017 static int dib8000_tune(struct dvb_frontend *fe)
3018 {
3019 	struct dib8000_state *state = fe->demodulator_priv;
3020 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3021 	enum frontend_tune_state *tune_state = &state->tune_state;
3022 
3023 	u16 locks, deeper_interleaver = 0, i;
3024 	int ret = 1; /* 1 symbol duration (in 100us unit) delay most of the time */
3025 
3026 	unsigned long *timeout = &state->timeout;
3027 	unsigned long now = jiffies;
3028 	u16 init_prbs;
3029 #ifdef DIB8000_AGC_FREEZE
3030 	u16 agc1, agc2;
3031 #endif
3032 
3033 	u32 corm[4] = {0, 0, 0, 0};
3034 	u8 find_index, max_value;
3035 
3036 #if 0
3037 	if (*tune_state < CT_DEMOD_STOP)
3038 		dprintk("IN: context status = %d, TUNE_STATE %d autosearch step = %u jiffies = %lu\n",
3039 			state->channel_parameters_set, *tune_state, state->autosearch_state, now);
3040 #endif
3041 
3042 	switch (*tune_state) {
3043 	case CT_DEMOD_START: /* 30 */
3044 		dib8000_reset_stats(fe);
3045 
3046 		if (state->revision == 0x8090)
3047 			dib8090p_init_sdram(state);
3048 		state->status = FE_STATUS_TUNE_PENDING;
3049 		state->channel_parameters_set = is_manual_mode(c);
3050 
3051 		dprintk("Tuning channel on %s search mode\n",
3052 			state->channel_parameters_set ? "manual" : "auto");
3053 
3054 		dib8000_viterbi_state(state, 0); /* force chan dec in restart */
3055 
3056 		/* Layer monitor */
3057 		dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
3058 
3059 		dib8000_set_frequency_offset(state);
3060 		dib8000_set_bandwidth(fe, c->bandwidth_hz / 1000);
3061 
3062 		if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */
3063 #ifdef DIB8000_AGC_FREEZE
3064 			if (state->revision != 0x8090) {
3065 				state->agc1_max = dib8000_read_word(state, 108);
3066 				state->agc1_min = dib8000_read_word(state, 109);
3067 				state->agc2_max = dib8000_read_word(state, 110);
3068 				state->agc2_min = dib8000_read_word(state, 111);
3069 				agc1 = dib8000_read_word(state, 388);
3070 				agc2 = dib8000_read_word(state, 389);
3071 				dib8000_write_word(state, 108, agc1);
3072 				dib8000_write_word(state, 109, agc1);
3073 				dib8000_write_word(state, 110, agc2);
3074 				dib8000_write_word(state, 111, agc2);
3075 			}
3076 #endif
3077 			state->autosearch_state = AS_SEARCHING_FFT;
3078 			state->found_nfft = TRANSMISSION_MODE_AUTO;
3079 			state->found_guard = GUARD_INTERVAL_AUTO;
3080 			*tune_state = CT_DEMOD_SEARCH_NEXT;
3081 		} else { /* we already know the channel struct so TUNE only ! */
3082 			state->autosearch_state = AS_DONE;
3083 			*tune_state = CT_DEMOD_STEP_3;
3084 		}
3085 		state->symbol_duration = dib8000_get_symbol_duration(state);
3086 		break;
3087 
3088 	case CT_DEMOD_SEARCH_NEXT: /* 51 */
3089 		dib8000_autosearch_start(fe);
3090 		if (state->revision == 0x8090)
3091 			ret = 50;
3092 		else
3093 			ret = 15;
3094 		*tune_state = CT_DEMOD_STEP_1;
3095 		break;
3096 
3097 	case CT_DEMOD_STEP_1: /* 31 */
3098 		switch (dib8000_autosearch_irq(fe)) {
3099 		case 1: /* fail */
3100 			state->status = FE_STATUS_TUNE_FAILED;
3101 			state->autosearch_state = AS_DONE;
3102 			*tune_state = CT_DEMOD_STOP; /* else we are done here */
3103 			break;
3104 		case 2: /* Success */
3105 			state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */
3106 			*tune_state = CT_DEMOD_STEP_3;
3107 			if (state->autosearch_state == AS_SEARCHING_GUARD)
3108 				*tune_state = CT_DEMOD_STEP_2;
3109 			else
3110 				state->autosearch_state = AS_DONE;
3111 			break;
3112 		case 3: /* Autosearch FFT max correlation endded */
3113 			*tune_state = CT_DEMOD_STEP_2;
3114 			break;
3115 		}
3116 		break;
3117 
3118 	case CT_DEMOD_STEP_2:
3119 		switch (state->autosearch_state) {
3120 		case AS_SEARCHING_FFT:
3121 			/* searching for the correct FFT */
3122 			if (state->revision == 0x8090) {
3123 				corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3124 				corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3125 				corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));
3126 			} else {
3127 				corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));
3128 				corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3129 				corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3130 			}
3131 			/* dprintk("corm fft: %u %u %u\n", corm[0], corm[1], corm[2]); */
3132 
3133 			max_value = 0;
3134 			for (find_index = 1 ; find_index < 3 ; find_index++) {
3135 				if (corm[max_value] < corm[find_index])
3136 					max_value = find_index ;
3137 			}
3138 
3139 			switch (max_value) {
3140 			case 0:
3141 				state->found_nfft = TRANSMISSION_MODE_2K;
3142 				break;
3143 			case 1:
3144 				state->found_nfft = TRANSMISSION_MODE_4K;
3145 				break;
3146 			case 2:
3147 			default:
3148 				state->found_nfft = TRANSMISSION_MODE_8K;
3149 				break;
3150 			}
3151 			/* dprintk("Autosearch FFT has found Mode %d\n", max_value + 1); */
3152 
3153 			*tune_state = CT_DEMOD_SEARCH_NEXT;
3154 			state->autosearch_state = AS_SEARCHING_GUARD;
3155 			if (state->revision == 0x8090)
3156 				ret = 50;
3157 			else
3158 				ret = 10;
3159 			break;
3160 		case AS_SEARCHING_GUARD:
3161 			/* searching for the correct guard interval */
3162 			if (state->revision == 0x8090)
3163 				state->found_guard = dib8000_read_word(state, 572) & 0x3;
3164 			else
3165 				state->found_guard = dib8000_read_word(state, 570) & 0x3;
3166 			/* dprintk("guard interval found=%i\n", state->found_guard); */
3167 
3168 			*tune_state = CT_DEMOD_STEP_3;
3169 			break;
3170 		default:
3171 			/* the demod should never be in this state */
3172 			state->status = FE_STATUS_TUNE_FAILED;
3173 			state->autosearch_state = AS_DONE;
3174 			*tune_state = CT_DEMOD_STOP; /* else we are done here */
3175 			break;
3176 		}
3177 		break;
3178 
3179 	case CT_DEMOD_STEP_3: /* 33 */
3180 		dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1);
3181 		dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */
3182 		*tune_state = CT_DEMOD_STEP_4;
3183 		break;
3184 
3185 	case CT_DEMOD_STEP_4: /* (34) */
3186 		dib8000_demod_restart(state);
3187 
3188 		dib8000_set_sync_wait(state);
3189 		dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
3190 
3191 		locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */
3192 		/* coff should lock over P_coff_winlen ofdm symbols : give 3 times this length to lock */
3193 		*timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);
3194 		*tune_state = CT_DEMOD_STEP_5;
3195 		break;
3196 
3197 	case CT_DEMOD_STEP_5: /* (35) */
3198 		locks = dib8000_read_lock(fe);
3199 		if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */
3200 			dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */
3201 			if (!state->differential_constellation) {
3202 				/* 2 times lmod4_win_len + 10 symbols (pipe delay after coff + nb to compute a 1st correlation) */
3203 				*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON);
3204 				*tune_state = CT_DEMOD_STEP_7;
3205 			} else {
3206 				*tune_state = CT_DEMOD_STEP_8;
3207 			}
3208 		} else if (time_after(now, *timeout)) {
3209 			*tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
3210 		}
3211 		break;
3212 
3213 	case CT_DEMOD_STEP_6: /* (36)  if there is an input (diversity) */
3214 		if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {
3215 			/* if there is a diversity fe in input and this fe is has not already failed : wait here until this this fe has succedeed or failed */
3216 			if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */
3217 				*tune_state = CT_DEMOD_STEP_8; /* go for mpeg */
3218 			else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failed also, break the current one */
3219 				*tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
3220 				dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3221 				dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3222 				state->status = FE_STATUS_TUNE_FAILED;
3223 			}
3224 		} else {
3225 			dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3226 			dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3227 			*tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
3228 			state->status = FE_STATUS_TUNE_FAILED;
3229 		}
3230 		break;
3231 
3232 	case CT_DEMOD_STEP_7: /* 37 */
3233 		locks = dib8000_read_lock(fe);
3234 		if (locks & (1<<10)) { /* lmod4_lock */
3235 			ret = 14; /* wait for 14 symbols */
3236 			*tune_state = CT_DEMOD_STEP_8;
3237 		} else if (time_after(now, *timeout))
3238 			*tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
3239 		break;
3240 
3241 	case CT_DEMOD_STEP_8: /* 38 */
3242 		dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3243 		dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3244 
3245 		/* mpeg will never lock on this condition because init_prbs is not set : search for it !*/
3246 		if (c->isdbt_sb_mode
3247 		    && c->isdbt_sb_subchannel < 14
3248 		    && !state->differential_constellation) {
3249 			state->subchannel = 0;
3250 			*tune_state = CT_DEMOD_STEP_11;
3251 		} else {
3252 			*tune_state = CT_DEMOD_STEP_9;
3253 			state->status = FE_STATUS_LOCKED;
3254 		}
3255 		break;
3256 
3257 	case CT_DEMOD_STEP_9: /* 39 */
3258 		if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
3259 			/* defines timeout for mpeg lock depending on interleaver length of longest layer */
3260 			for (i = 0; i < 3; i++) {
3261 				if (c->layer[i].interleaving >= deeper_interleaver) {
3262 					dprintk("layer%i: time interleaver = %d\n", i, c->layer[i].interleaving);
3263 					if (c->layer[i].segment_count > 0) { /* valid layer */
3264 						deeper_interleaver = c->layer[0].interleaving;
3265 						state->longest_intlv_layer = i;
3266 					}
3267 				}
3268 			}
3269 
3270 			if (deeper_interleaver == 0)
3271 				locks = 2; /* locks is the tmp local variable name */
3272 			else if (deeper_interleaver == 3)
3273 				locks = 8;
3274 			else
3275 				locks = 2 * deeper_interleaver;
3276 
3277 			if (state->diversity_onoff != 0) /* because of diversity sync */
3278 				locks *= 2;
3279 
3280 			*timeout = now + msecs_to_jiffies(200 * locks); /* give the mpeg lock 800ms if sram is present */
3281 			dprintk("Deeper interleaver mode = %d on layer %d : timeout mult factor = %d => will use timeout = %ld\n",
3282 				deeper_interleaver, state->longest_intlv_layer, locks, *timeout);
3283 
3284 			*tune_state = CT_DEMOD_STEP_10;
3285 		} else
3286 			*tune_state = CT_DEMOD_STOP;
3287 		break;
3288 
3289 	case CT_DEMOD_STEP_10: /* 40 */
3290 		locks = dib8000_read_lock(fe);
3291 		if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */
3292 			dprintk("ISDB-T layer locks: Layer A %s, Layer B %s, Layer C %s\n",
3293 				c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3294 				c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3295 				c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3296 			if (c->isdbt_sb_mode
3297 			    && c->isdbt_sb_subchannel < 14
3298 			    && !state->differential_constellation)
3299 				/* signal to the upper layer, that there was a channel found and the parameters can be read */
3300 				state->status = FE_STATUS_DEMOD_SUCCESS;
3301 			else
3302 				state->status = FE_STATUS_DATA_LOCKED;
3303 			*tune_state = CT_DEMOD_STOP;
3304 		} else if (time_after(now, *timeout)) {
3305 			if (c->isdbt_sb_mode
3306 			    && c->isdbt_sb_subchannel < 14
3307 			    && !state->differential_constellation) { /* continue to try init prbs autosearch */
3308 				state->subchannel += 3;
3309 				*tune_state = CT_DEMOD_STEP_11;
3310 			} else { /* we are done mpeg of the longest interleaver xas not locking but let's try if an other layer has locked in the same time */
3311 				if (locks & (0x7 << 5)) {
3312 					dprintk("Not all ISDB-T layers locked in %d ms: Layer A %s, Layer B %s, Layer C %s\n",
3313 						jiffies_to_msecs(now - *timeout),
3314 						c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3315 						c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3316 						c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3317 
3318 					state->status = FE_STATUS_DATA_LOCKED;
3319 				} else
3320 					state->status = FE_STATUS_TUNE_FAILED;
3321 				*tune_state = CT_DEMOD_STOP;
3322 			}
3323 		}
3324 		break;
3325 
3326 	case CT_DEMOD_STEP_11:  /* 41 : init prbs autosearch */
3327 		init_prbs = dib8000_get_init_prbs(state, state->subchannel);
3328 
3329 		if (init_prbs) {
3330 			dib8000_set_subchannel_prbs(state, init_prbs);
3331 			*tune_state = CT_DEMOD_STEP_9;
3332 		} else {
3333 			*tune_state = CT_DEMOD_STOP;
3334 			state->status = FE_STATUS_TUNE_FAILED;
3335 		}
3336 		break;
3337 
3338 	default:
3339 		break;
3340 	}
3341 
3342 	/* tuning is finished - cleanup the demod */
3343 	switch (*tune_state) {
3344 	case CT_DEMOD_STOP: /* (42) */
3345 #ifdef DIB8000_AGC_FREEZE
3346 		if ((state->revision != 0x8090) && (state->agc1_max != 0)) {
3347 			dib8000_write_word(state, 108, state->agc1_max);
3348 			dib8000_write_word(state, 109, state->agc1_min);
3349 			dib8000_write_word(state, 110, state->agc2_max);
3350 			dib8000_write_word(state, 111, state->agc2_min);
3351 			state->agc1_max = 0;
3352 			state->agc1_min = 0;
3353 			state->agc2_max = 0;
3354 			state->agc2_min = 0;
3355 		}
3356 #endif
3357 		ret = 0;
3358 		break;
3359 	default:
3360 		break;
3361 	}
3362 
3363 	if ((ret > 0) && (*tune_state > CT_DEMOD_STEP_3))
3364 		return ret * state->symbol_duration;
3365 	if ((ret > 0) && (ret < state->symbol_duration))
3366 		return state->symbol_duration; /* at least one symbol */
3367 	return ret;
3368 }
3369 
3370 static int dib8000_wakeup(struct dvb_frontend *fe)
3371 {
3372 	struct dib8000_state *state = fe->demodulator_priv;
3373 	u8 index_frontend;
3374 	int ret;
3375 
3376 	dib8000_set_power_mode(state, DIB8000_POWER_ALL);
3377 	dib8000_set_adc_state(state, DIBX000_ADC_ON);
3378 	if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
3379 		dprintk("could not start Slow ADC\n");
3380 
3381 	if (state->revision == 0x8090)
3382 		dib8000_sad_calib(state);
3383 
3384 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3385 		ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
3386 		if (ret < 0)
3387 			return ret;
3388 	}
3389 
3390 	return 0;
3391 }
3392 
3393 static int dib8000_sleep(struct dvb_frontend *fe)
3394 {
3395 	struct dib8000_state *state = fe->demodulator_priv;
3396 	u8 index_frontend;
3397 	int ret;
3398 
3399 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3400 		ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
3401 		if (ret < 0)
3402 			return ret;
3403 	}
3404 
3405 	if (state->revision != 0x8090)
3406 		dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
3407 	dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
3408 	return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
3409 }
3410 
3411 static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat);
3412 
3413 static int dib8000_get_frontend(struct dvb_frontend *fe,
3414 				struct dtv_frontend_properties *c)
3415 {
3416 	struct dib8000_state *state = fe->demodulator_priv;
3417 	u16 i, val = 0;
3418 	enum fe_status stat = 0;
3419 	u8 index_frontend, sub_index_frontend;
3420 
3421 	c->bandwidth_hz = 6000000;
3422 
3423 	/*
3424 	 * If called to early, get_frontend makes dib8000_tune to either
3425 	 * not lock or not sync. This causes dvbv5-scan/dvbv5-zap to fail.
3426 	 * So, let's just return if frontend 0 has not locked.
3427 	 */
3428 	dib8000_read_status(fe, &stat);
3429 	if (!(stat & FE_HAS_SYNC))
3430 		return 0;
3431 
3432 	dprintk("dib8000_get_frontend: TMCC lock\n");
3433 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3434 		state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
3435 		if (stat&FE_HAS_SYNC) {
3436 			dprintk("TMCC lock on the slave%i\n", index_frontend);
3437 			/* synchronize the cache with the other frontends */
3438 			state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c);
3439 			for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
3440 				if (sub_index_frontend != index_frontend) {
3441 					state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3442 					state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3443 					state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3444 					state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3445 					state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3446 					for (i = 0; i < 3; i++) {
3447 						state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3448 						state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3449 						state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3450 						state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3451 					}
3452 				}
3453 			}
3454 			return 0;
3455 		}
3456 	}
3457 
3458 	c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
3459 
3460 	if (state->revision == 0x8090)
3461 		val = dib8000_read_word(state, 572);
3462 	else
3463 		val = dib8000_read_word(state, 570);
3464 	c->inversion = (val & 0x40) >> 6;
3465 	switch ((val & 0x30) >> 4) {
3466 	case 1:
3467 		c->transmission_mode = TRANSMISSION_MODE_2K;
3468 		dprintk("dib8000_get_frontend: transmission mode 2K\n");
3469 		break;
3470 	case 2:
3471 		c->transmission_mode = TRANSMISSION_MODE_4K;
3472 		dprintk("dib8000_get_frontend: transmission mode 4K\n");
3473 		break;
3474 	case 3:
3475 	default:
3476 		c->transmission_mode = TRANSMISSION_MODE_8K;
3477 		dprintk("dib8000_get_frontend: transmission mode 8K\n");
3478 		break;
3479 	}
3480 
3481 	switch (val & 0x3) {
3482 	case 0:
3483 		c->guard_interval = GUARD_INTERVAL_1_32;
3484 		dprintk("dib8000_get_frontend: Guard Interval = 1/32\n");
3485 		break;
3486 	case 1:
3487 		c->guard_interval = GUARD_INTERVAL_1_16;
3488 		dprintk("dib8000_get_frontend: Guard Interval = 1/16\n");
3489 		break;
3490 	case 2:
3491 		dprintk("dib8000_get_frontend: Guard Interval = 1/8\n");
3492 		c->guard_interval = GUARD_INTERVAL_1_8;
3493 		break;
3494 	case 3:
3495 		dprintk("dib8000_get_frontend: Guard Interval = 1/4\n");
3496 		c->guard_interval = GUARD_INTERVAL_1_4;
3497 		break;
3498 	}
3499 
3500 	val = dib8000_read_word(state, 505);
3501 	c->isdbt_partial_reception = val & 1;
3502 	dprintk("dib8000_get_frontend: partial_reception = %d\n", c->isdbt_partial_reception);
3503 
3504 	for (i = 0; i < 3; i++) {
3505 		int show;
3506 
3507 		val = dib8000_read_word(state, 493 + i) & 0x0f;
3508 		c->layer[i].segment_count = val;
3509 
3510 		if (val == 0 || val > 13)
3511 			show = 0;
3512 		else
3513 			show = 1;
3514 
3515 		if (show)
3516 			dprintk("dib8000_get_frontend: Layer %d segments = %d\n",
3517 				i, c->layer[i].segment_count);
3518 
3519 		val = dib8000_read_word(state, 499 + i) & 0x3;
3520 		/* Interleaving can be 0, 1, 2 or 4 */
3521 		if (val == 3)
3522 			val = 4;
3523 		c->layer[i].interleaving = val;
3524 		if (show)
3525 			dprintk("dib8000_get_frontend: Layer %d time_intlv = %d\n",
3526 				i, c->layer[i].interleaving);
3527 
3528 		val = dib8000_read_word(state, 481 + i);
3529 		switch (val & 0x7) {
3530 		case 1:
3531 			c->layer[i].fec = FEC_1_2;
3532 			if (show)
3533 				dprintk("dib8000_get_frontend: Layer %d Code Rate = 1/2\n", i);
3534 			break;
3535 		case 2:
3536 			c->layer[i].fec = FEC_2_3;
3537 			if (show)
3538 				dprintk("dib8000_get_frontend: Layer %d Code Rate = 2/3\n", i);
3539 			break;
3540 		case 3:
3541 			c->layer[i].fec = FEC_3_4;
3542 			if (show)
3543 				dprintk("dib8000_get_frontend: Layer %d Code Rate = 3/4\n", i);
3544 			break;
3545 		case 5:
3546 			c->layer[i].fec = FEC_5_6;
3547 			if (show)
3548 				dprintk("dib8000_get_frontend: Layer %d Code Rate = 5/6\n", i);
3549 			break;
3550 		default:
3551 			c->layer[i].fec = FEC_7_8;
3552 			if (show)
3553 				dprintk("dib8000_get_frontend: Layer %d Code Rate = 7/8\n", i);
3554 			break;
3555 		}
3556 
3557 		val = dib8000_read_word(state, 487 + i);
3558 		switch (val & 0x3) {
3559 		case 0:
3560 			c->layer[i].modulation = DQPSK;
3561 			if (show)
3562 				dprintk("dib8000_get_frontend: Layer %d DQPSK\n", i);
3563 			break;
3564 		case 1:
3565 			c->layer[i].modulation = QPSK;
3566 			if (show)
3567 				dprintk("dib8000_get_frontend: Layer %d QPSK\n", i);
3568 			break;
3569 		case 2:
3570 			c->layer[i].modulation = QAM_16;
3571 			if (show)
3572 				dprintk("dib8000_get_frontend: Layer %d QAM16\n", i);
3573 			break;
3574 		case 3:
3575 		default:
3576 			c->layer[i].modulation = QAM_64;
3577 			if (show)
3578 				dprintk("dib8000_get_frontend: Layer %d QAM64\n", i);
3579 			break;
3580 		}
3581 	}
3582 
3583 	/* synchronize the cache with the other frontends */
3584 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3585 		state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode;
3586 		state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion;
3587 		state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode;
3588 		state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval;
3589 		state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception;
3590 		for (i = 0; i < 3; i++) {
3591 			state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count;
3592 			state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving;
3593 			state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec;
3594 			state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation;
3595 		}
3596 	}
3597 	return 0;
3598 }
3599 
3600 static int dib8000_set_frontend(struct dvb_frontend *fe)
3601 {
3602 	struct dib8000_state *state = fe->demodulator_priv;
3603 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3604 	int l, i, active, time, time_slave = 0;
3605 	u8 exit_condition, index_frontend;
3606 	unsigned long delay, callback_time;
3607 
3608 	if (c->frequency == 0) {
3609 		dprintk("dib8000: must at least specify frequency\n");
3610 		return 0;
3611 	}
3612 
3613 	if (c->bandwidth_hz == 0) {
3614 		dprintk("dib8000: no bandwidth specified, set to default\n");
3615 		c->bandwidth_hz = 6000000;
3616 	}
3617 
3618 	for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3619 		/* synchronization of the cache */
3620 		state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
3621 		memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
3622 
3623 		/* set output mode and diversity input */
3624 		if (state->revision != 0x8090) {
3625 			dib8000_set_diversity_in(state->fe[index_frontend], 1);
3626 			if (index_frontend != 0)
3627 				dib8000_set_output_mode(state->fe[index_frontend],
3628 						OUTMODE_DIVERSITY);
3629 			else
3630 				dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3631 		} else {
3632 			dib8096p_set_diversity_in(state->fe[index_frontend], 1);
3633 			if (index_frontend != 0)
3634 				dib8096p_set_output_mode(state->fe[index_frontend],
3635 						OUTMODE_DIVERSITY);
3636 			else
3637 				dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3638 		}
3639 
3640 		/* tune the tuner */
3641 		if (state->fe[index_frontend]->ops.tuner_ops.set_params)
3642 			state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
3643 
3644 		dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
3645 	}
3646 
3647 	/* turn off the diversity of the last chip */
3648 	if (state->revision != 0x8090)
3649 		dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);
3650 	else
3651 		dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);
3652 
3653 	/* start up the AGC */
3654 	do {
3655 		time = dib8000_agc_startup(state->fe[0]);
3656 		for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3657 			time_slave = dib8000_agc_startup(state->fe[index_frontend]);
3658 			if (time == 0)
3659 				time = time_slave;
3660 			else if ((time_slave != 0) && (time_slave > time))
3661 				time = time_slave;
3662 		}
3663 		if (time == 0)
3664 			break;
3665 
3666 		/*
3667 		 * Despite dib8000_agc_startup returns time at a 0.1 ms range,
3668 		 * the actual sleep time depends on CONFIG_HZ. The worse case
3669 		 * is when CONFIG_HZ=100. In such case, the minimum granularity
3670 		 * is 10ms. On some real field tests, the tuner sometimes don't
3671 		 * lock when this timer is lower than 10ms. So, enforce a 10ms
3672 		 * granularity.
3673 		 */
3674 		time = 10 * (time + 99)/100;
3675 		usleep_range(time * 1000, (time + 1) * 1000);
3676 		exit_condition = 1;
3677 		for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3678 			if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
3679 				exit_condition = 0;
3680 				break;
3681 			}
3682 		}
3683 	} while (exit_condition == 0);
3684 
3685 	for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3686 		dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
3687 
3688 	active = 1;
3689 	do {
3690 		callback_time = 0;
3691 		for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3692 			delay = dib8000_tune(state->fe[index_frontend]);
3693 			if (delay != 0) {
3694 				delay = jiffies + usecs_to_jiffies(100 * delay);
3695 				if (!callback_time || delay < callback_time)
3696 					callback_time = delay;
3697 			}
3698 
3699 			/* we are in autosearch */
3700 			if (state->channel_parameters_set == 0) { /* searching */
3701 				if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) {
3702 					dprintk("autosearch succeeded on fe%i\n", index_frontend);
3703 					dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the frontend which was successful */
3704 					state->channel_parameters_set = 1;
3705 
3706 					for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {
3707 						if (l != index_frontend) { /* and for all frontend except the successful one */
3708 							dprintk("Restarting frontend %d\n", l);
3709 							dib8000_tune_restart_from_demod(state->fe[l]);
3710 
3711 							state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3712 							state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3713 							state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3714 							state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3715 							state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3716 							for (i = 0; i < 3; i++) {
3717 								state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3718 								state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3719 								state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3720 								state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3721 							}
3722 
3723 						}
3724 					}
3725 				}
3726 			}
3727 		}
3728 		/* tuning is done when the master frontend is done (failed or success) */
3729 		if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||
3730 				dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||
3731 				dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {
3732 			active = 0;
3733 			/* we need to wait for all frontends to be finished */
3734 			for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3735 				if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)
3736 					active = 1;
3737 			}
3738 			if (active == 0)
3739 				dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0]));
3740 		}
3741 
3742 		if ((active == 1) && (callback_time == 0)) {
3743 			dprintk("strange callback time something went wrong\n");
3744 			active = 0;
3745 		}
3746 
3747 		while ((active == 1) && (time_before(jiffies, callback_time)))
3748 			msleep(100);
3749 	} while (active);
3750 
3751 	/* set output mode */
3752 	if (state->revision != 0x8090)
3753 		dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
3754 	else {
3755 		dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
3756 		if (state->cfg.enMpegOutput == 0) {
3757 			dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
3758 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
3759 		}
3760 	}
3761 
3762 	return 0;
3763 }
3764 
3765 static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat);
3766 
3767 static int dib8000_read_status(struct dvb_frontend *fe, enum fe_status *stat)
3768 {
3769 	struct dib8000_state *state = fe->demodulator_priv;
3770 	u16 lock_slave = 0, lock;
3771 	u8 index_frontend;
3772 
3773 	lock = dib8000_read_lock(fe);
3774 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3775 		lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
3776 
3777 	*stat = 0;
3778 
3779 	if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
3780 		*stat |= FE_HAS_SIGNAL;
3781 
3782 	if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
3783 		*stat |= FE_HAS_CARRIER;
3784 
3785 	if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
3786 		*stat |= FE_HAS_SYNC;
3787 
3788 	if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
3789 		*stat |= FE_HAS_LOCK;
3790 
3791 	if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
3792 		lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
3793 		if (lock & 0x01)
3794 			*stat |= FE_HAS_VITERBI;
3795 
3796 		lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
3797 		if (lock & 0x01)
3798 			*stat |= FE_HAS_VITERBI;
3799 
3800 		lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
3801 		if (lock & 0x01)
3802 			*stat |= FE_HAS_VITERBI;
3803 	}
3804 	dib8000_get_stats(fe, *stat);
3805 
3806 	return 0;
3807 }
3808 
3809 static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
3810 {
3811 	struct dib8000_state *state = fe->demodulator_priv;
3812 
3813 	/* 13 segments */
3814 	if (state->revision == 0x8090)
3815 		*ber = (dib8000_read_word(state, 562) << 16) |
3816 			dib8000_read_word(state, 563);
3817 	else
3818 		*ber = (dib8000_read_word(state, 560) << 16) |
3819 			dib8000_read_word(state, 561);
3820 	return 0;
3821 }
3822 
3823 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
3824 {
3825 	struct dib8000_state *state = fe->demodulator_priv;
3826 
3827 	/* packet error on 13 seg */
3828 	if (state->revision == 0x8090)
3829 		*unc = dib8000_read_word(state, 567);
3830 	else
3831 		*unc = dib8000_read_word(state, 565);
3832 	return 0;
3833 }
3834 
3835 static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
3836 {
3837 	struct dib8000_state *state = fe->demodulator_priv;
3838 	u8 index_frontend;
3839 	u16 val;
3840 
3841 	*strength = 0;
3842 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3843 		state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
3844 		if (val > 65535 - *strength)
3845 			*strength = 65535;
3846 		else
3847 			*strength += val;
3848 	}
3849 
3850 	val = 65535 - dib8000_read_word(state, 390);
3851 	if (val > 65535 - *strength)
3852 		*strength = 65535;
3853 	else
3854 		*strength += val;
3855 	return 0;
3856 }
3857 
3858 static u32 dib8000_get_snr(struct dvb_frontend *fe)
3859 {
3860 	struct dib8000_state *state = fe->demodulator_priv;
3861 	u32 n, s, exp;
3862 	u16 val;
3863 
3864 	if (state->revision != 0x8090)
3865 		val = dib8000_read_word(state, 542);
3866 	else
3867 		val = dib8000_read_word(state, 544);
3868 	n = (val >> 6) & 0xff;
3869 	exp = (val & 0x3f);
3870 	if ((exp & 0x20) != 0)
3871 		exp -= 0x40;
3872 	n <<= exp+16;
3873 
3874 	if (state->revision != 0x8090)
3875 		val = dib8000_read_word(state, 543);
3876 	else
3877 		val = dib8000_read_word(state, 545);
3878 	s = (val >> 6) & 0xff;
3879 	exp = (val & 0x3f);
3880 	if ((exp & 0x20) != 0)
3881 		exp -= 0x40;
3882 	s <<= exp+16;
3883 
3884 	if (n > 0) {
3885 		u32 t = (s/n) << 16;
3886 		return t + ((s << 16) - n*t) / n;
3887 	}
3888 	return 0xffffffff;
3889 }
3890 
3891 static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
3892 {
3893 	struct dib8000_state *state = fe->demodulator_priv;
3894 	u8 index_frontend;
3895 	u32 snr_master;
3896 
3897 	snr_master = dib8000_get_snr(fe);
3898 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3899 		snr_master += dib8000_get_snr(state->fe[index_frontend]);
3900 
3901 	if ((snr_master >> 16) != 0) {
3902 		snr_master = 10*intlog10(snr_master>>16);
3903 		*snr = snr_master / ((1 << 24) / 10);
3904 	}
3905 	else
3906 		*snr = 0;
3907 
3908 	return 0;
3909 }
3910 
3911 struct per_layer_regs {
3912 	u16 lock, ber, per;
3913 };
3914 
3915 static const struct per_layer_regs per_layer_regs[] = {
3916 	{ 554, 560, 562 },
3917 	{ 555, 576, 578 },
3918 	{ 556, 581, 583 },
3919 };
3920 
3921 struct linear_segments {
3922 	unsigned x;
3923 	signed y;
3924 };
3925 
3926 /*
3927  * Table to estimate signal strength in dBm.
3928  * This table was empirically determinated by measuring the signal
3929  * strength generated by a DTA-2111 RF generator directly connected into
3930  * a dib8076 device (a PixelView PV-D231U stick), using a good quality
3931  * 3 meters RC6 cable and good RC6 connectors.
3932  * The real value can actually be different on other devices, depending
3933  * on several factors, like if LNA is enabled or not, if diversity is
3934  * enabled, type of connectors, etc.
3935  * Yet, it is better to use this measure in dB than a random non-linear
3936  * percentage value, especially for antenna adjustments.
3937  * On my tests, the precision of the measure using this table is about
3938  * 0.5 dB, with sounds reasonable enough.
3939  */
3940 static struct linear_segments strength_to_db_table[] = {
3941 	{ 55953, 108500 },	/* -22.5 dBm */
3942 	{ 55394, 108000 },
3943 	{ 53834, 107000 },
3944 	{ 52863, 106000 },
3945 	{ 52239, 105000 },
3946 	{ 52012, 104000 },
3947 	{ 51803, 103000 },
3948 	{ 51566, 102000 },
3949 	{ 51356, 101000 },
3950 	{ 51112, 100000 },
3951 	{ 50869,  99000 },
3952 	{ 50600,  98000 },
3953 	{ 50363,  97000 },
3954 	{ 50117,  96000 },	/* -35 dBm */
3955 	{ 49889,  95000 },
3956 	{ 49680,  94000 },
3957 	{ 49493,  93000 },
3958 	{ 49302,  92000 },
3959 	{ 48929,  91000 },
3960 	{ 48416,  90000 },
3961 	{ 48035,  89000 },
3962 	{ 47593,  88000 },
3963 	{ 47282,  87000 },
3964 	{ 46953,  86000 },
3965 	{ 46698,  85000 },
3966 	{ 45617,  84000 },
3967 	{ 44773,  83000 },
3968 	{ 43845,  82000 },
3969 	{ 43020,  81000 },
3970 	{ 42010,  80000 },	/* -51 dBm */
3971 	{     0,      0 },
3972 };
3973 
3974 static u32 interpolate_value(u32 value, struct linear_segments *segments,
3975 			     unsigned len)
3976 {
3977 	u64 tmp64;
3978 	u32 dx;
3979 	s32 dy;
3980 	int i, ret;
3981 
3982 	if (value >= segments[0].x)
3983 		return segments[0].y;
3984 	if (value < segments[len-1].x)
3985 		return segments[len-1].y;
3986 
3987 	for (i = 1; i < len - 1; i++) {
3988 		/* If value is identical, no need to interpolate */
3989 		if (value == segments[i].x)
3990 			return segments[i].y;
3991 		if (value > segments[i].x)
3992 			break;
3993 	}
3994 
3995 	/* Linear interpolation between the two (x,y) points */
3996 	dy = segments[i - 1].y - segments[i].y;
3997 	dx = segments[i - 1].x - segments[i].x;
3998 
3999 	tmp64 = value - segments[i].x;
4000 	tmp64 *= dy;
4001 	do_div(tmp64, dx);
4002 	ret = segments[i].y + tmp64;
4003 
4004 	return ret;
4005 }
4006 
4007 static u32 dib8000_get_time_us(struct dvb_frontend *fe, int layer)
4008 {
4009 	struct dib8000_state *state = fe->demodulator_priv;
4010 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4011 	int ini_layer, end_layer, i;
4012 	u64 time_us, tmp64;
4013 	u32 tmp, denom;
4014 	int guard, rate_num, rate_denum = 1, bits_per_symbol, nsegs;
4015 	int interleaving = 0, fft_div;
4016 
4017 	if (layer >= 0) {
4018 		ini_layer = layer;
4019 		end_layer = layer + 1;
4020 	} else {
4021 		ini_layer = 0;
4022 		end_layer = 3;
4023 	}
4024 
4025 	switch (c->guard_interval) {
4026 	case GUARD_INTERVAL_1_4:
4027 		guard = 4;
4028 		break;
4029 	case GUARD_INTERVAL_1_8:
4030 		guard = 8;
4031 		break;
4032 	case GUARD_INTERVAL_1_16:
4033 		guard = 16;
4034 		break;
4035 	default:
4036 	case GUARD_INTERVAL_1_32:
4037 		guard = 32;
4038 		break;
4039 	}
4040 
4041 	switch (c->transmission_mode) {
4042 	case TRANSMISSION_MODE_2K:
4043 		fft_div = 4;
4044 		break;
4045 	case TRANSMISSION_MODE_4K:
4046 		fft_div = 2;
4047 		break;
4048 	default:
4049 	case TRANSMISSION_MODE_8K:
4050 		fft_div = 1;
4051 		break;
4052 	}
4053 
4054 	denom = 0;
4055 	for (i = ini_layer; i < end_layer; i++) {
4056 		nsegs = c->layer[i].segment_count;
4057 		if (nsegs == 0 || nsegs > 13)
4058 			continue;
4059 
4060 		switch (c->layer[i].modulation) {
4061 		case DQPSK:
4062 		case QPSK:
4063 			bits_per_symbol = 2;
4064 			break;
4065 		case QAM_16:
4066 			bits_per_symbol = 4;
4067 			break;
4068 		default:
4069 		case QAM_64:
4070 			bits_per_symbol = 6;
4071 			break;
4072 		}
4073 
4074 		switch (c->layer[i].fec) {
4075 		case FEC_1_2:
4076 			rate_num = 1;
4077 			rate_denum = 2;
4078 			break;
4079 		case FEC_2_3:
4080 			rate_num = 2;
4081 			rate_denum = 3;
4082 			break;
4083 		case FEC_3_4:
4084 			rate_num = 3;
4085 			rate_denum = 4;
4086 			break;
4087 		case FEC_5_6:
4088 			rate_num = 5;
4089 			rate_denum = 6;
4090 			break;
4091 		default:
4092 		case FEC_7_8:
4093 			rate_num = 7;
4094 			rate_denum = 8;
4095 			break;
4096 		}
4097 
4098 		interleaving = c->layer[i].interleaving;
4099 
4100 		denom += bits_per_symbol * rate_num * fft_div * nsegs * 384;
4101 	}
4102 
4103 	/* If all goes wrong, wait for 1s for the next stats */
4104 	if (!denom)
4105 		return 0;
4106 
4107 	/* Estimate the period for the total bit rate */
4108 	time_us = rate_denum * (1008 * 1562500L);
4109 	tmp64 = time_us;
4110 	do_div(tmp64, guard);
4111 	time_us = time_us + tmp64;
4112 	time_us += denom / 2;
4113 	do_div(time_us, denom);
4114 
4115 	tmp = 1008 * 96 * interleaving;
4116 	time_us += tmp + tmp / guard;
4117 
4118 	return time_us;
4119 }
4120 
4121 static int dib8000_get_stats(struct dvb_frontend *fe, enum fe_status stat)
4122 {
4123 	struct dib8000_state *state = fe->demodulator_priv;
4124 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4125 	int i;
4126 	int show_per_stats = 0;
4127 	u32 time_us = 0, snr, val;
4128 	u64 blocks;
4129 	s32 db;
4130 	u16 strength;
4131 
4132 	/* Get Signal strength */
4133 	dib8000_read_signal_strength(fe, &strength);
4134 	val = strength;
4135 	db = interpolate_value(val,
4136 			       strength_to_db_table,
4137 			       ARRAY_SIZE(strength_to_db_table)) - 131000;
4138 	c->strength.stat[0].svalue = db;
4139 
4140 	/* UCB/BER/CNR measures require lock */
4141 	if (!(stat & FE_HAS_LOCK)) {
4142 		c->cnr.len = 1;
4143 		c->block_count.len = 1;
4144 		c->block_error.len = 1;
4145 		c->post_bit_error.len = 1;
4146 		c->post_bit_count.len = 1;
4147 		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4148 		c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4149 		c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4150 		c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4151 		c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4152 		return 0;
4153 	}
4154 
4155 	/* Check if time for stats was elapsed */
4156 	if (time_after(jiffies, state->per_jiffies_stats)) {
4157 		state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
4158 
4159 		/* Get SNR */
4160 		snr = dib8000_get_snr(fe);
4161 		for (i = 1; i < MAX_NUMBER_OF_FRONTENDS; i++) {
4162 			if (state->fe[i])
4163 				snr += dib8000_get_snr(state->fe[i]);
4164 		}
4165 		snr = snr >> 16;
4166 
4167 		if (snr) {
4168 			snr = 10 * intlog10(snr);
4169 			snr = (1000L * snr) >> 24;
4170 		} else {
4171 			snr = 0;
4172 		}
4173 		c->cnr.stat[0].svalue = snr;
4174 		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
4175 
4176 		/* Get UCB measures */
4177 		dib8000_read_unc_blocks(fe, &val);
4178 		if (val < state->init_ucb)
4179 			state->init_ucb += 0x100000000LL;
4180 
4181 		c->block_error.stat[0].scale = FE_SCALE_COUNTER;
4182 		c->block_error.stat[0].uvalue = val + state->init_ucb;
4183 
4184 		/* Estimate the number of packets based on bitrate */
4185 		if (!time_us)
4186 			time_us = dib8000_get_time_us(fe, -1);
4187 
4188 		if (time_us) {
4189 			blocks = 1250000ULL * 1000000ULL;
4190 			do_div(blocks, time_us * 8 * 204);
4191 			c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4192 			c->block_count.stat[0].uvalue += blocks;
4193 		}
4194 
4195 		show_per_stats = 1;
4196 	}
4197 
4198 	/* Get post-BER measures */
4199 	if (time_after(jiffies, state->ber_jiffies_stats)) {
4200 		time_us = dib8000_get_time_us(fe, -1);
4201 		state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4202 
4203 		dprintk("Next all layers stats available in %u us.\n", time_us);
4204 
4205 		dib8000_read_ber(fe, &val);
4206 		c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
4207 		c->post_bit_error.stat[0].uvalue += val;
4208 
4209 		c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
4210 		c->post_bit_count.stat[0].uvalue += 100000000;
4211 	}
4212 
4213 	if (state->revision < 0x8002)
4214 		return 0;
4215 
4216 	c->block_error.len = 4;
4217 	c->post_bit_error.len = 4;
4218 	c->post_bit_count.len = 4;
4219 
4220 	for (i = 0; i < 3; i++) {
4221 		unsigned nsegs = c->layer[i].segment_count;
4222 
4223 		if (nsegs == 0 || nsegs > 13)
4224 			continue;
4225 
4226 		time_us = 0;
4227 
4228 		if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) {
4229 			time_us = dib8000_get_time_us(fe, i);
4230 
4231 			state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4232 			dprintk("Next layer %c  stats will be available in %u us\n",
4233 				'A' + i, time_us);
4234 
4235 			val = dib8000_read_word(state, per_layer_regs[i].ber);
4236 			c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4237 			c->post_bit_error.stat[1 + i].uvalue += val;
4238 
4239 			c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
4240 			c->post_bit_count.stat[1 + i].uvalue += 100000000;
4241 		}
4242 
4243 		if (show_per_stats) {
4244 			val = dib8000_read_word(state, per_layer_regs[i].per);
4245 
4246 			c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4247 			c->block_error.stat[1 + i].uvalue += val;
4248 
4249 			if (!time_us)
4250 				time_us = dib8000_get_time_us(fe, i);
4251 			if (time_us) {
4252 				blocks = 1250000ULL * 1000000ULL;
4253 				do_div(blocks, time_us * 8 * 204);
4254 				c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4255 				c->block_count.stat[0].uvalue += blocks;
4256 			}
4257 		}
4258 	}
4259 	return 0;
4260 }
4261 
4262 static int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
4263 {
4264 	struct dib8000_state *state = fe->demodulator_priv;
4265 	u8 index_frontend = 1;
4266 
4267 	while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
4268 		index_frontend++;
4269 	if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
4270 		dprintk("set slave fe %p to index %i\n", fe_slave, index_frontend);
4271 		state->fe[index_frontend] = fe_slave;
4272 		return 0;
4273 	}
4274 
4275 	dprintk("too many slave frontend\n");
4276 	return -ENOMEM;
4277 }
4278 
4279 static struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
4280 {
4281 	struct dib8000_state *state = fe->demodulator_priv;
4282 
4283 	if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
4284 		return NULL;
4285 	return state->fe[slave_index];
4286 }
4287 
4288 static int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
4289 		u8 default_addr, u8 first_addr, u8 is_dib8096p)
4290 {
4291 	int k = 0, ret = 0;
4292 	u8 new_addr = 0;
4293 	struct i2c_device client = {.adap = host };
4294 
4295 	client.i2c_write_buffer = kzalloc(4, GFP_KERNEL);
4296 	if (!client.i2c_write_buffer) {
4297 		dprintk("%s: not enough memory\n", __func__);
4298 		return -ENOMEM;
4299 	}
4300 	client.i2c_read_buffer = kzalloc(4, GFP_KERNEL);
4301 	if (!client.i2c_read_buffer) {
4302 		dprintk("%s: not enough memory\n", __func__);
4303 		ret = -ENOMEM;
4304 		goto error_memory_read;
4305 	}
4306 	client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
4307 	if (!client.i2c_buffer_lock) {
4308 		dprintk("%s: not enough memory\n", __func__);
4309 		ret = -ENOMEM;
4310 		goto error_memory_lock;
4311 	}
4312 	mutex_init(client.i2c_buffer_lock);
4313 
4314 	for (k = no_of_demods - 1; k >= 0; k--) {
4315 		/* designated i2c address */
4316 		new_addr = first_addr + (k << 1);
4317 
4318 		client.addr = new_addr;
4319 		if (!is_dib8096p)
4320 			dib8000_i2c_write16(&client, 1287, 0x0003);	/* sram lead in, rdy */
4321 		if (dib8000_identify(&client) == 0) {
4322 			/* sram lead in, rdy */
4323 			if (!is_dib8096p)
4324 				dib8000_i2c_write16(&client, 1287, 0x0003);
4325 			client.addr = default_addr;
4326 			if (dib8000_identify(&client) == 0) {
4327 				dprintk("#%d: not identified\n", k);
4328 				ret  = -EINVAL;
4329 				goto error;
4330 			}
4331 		}
4332 
4333 		/* start diversity to pull_down div_str - just for i2c-enumeration */
4334 		dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
4335 
4336 		/* set new i2c address and force divstart */
4337 		dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
4338 		client.addr = new_addr;
4339 		dib8000_identify(&client);
4340 
4341 		dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
4342 	}
4343 
4344 	for (k = 0; k < no_of_demods; k++) {
4345 		new_addr = first_addr | (k << 1);
4346 		client.addr = new_addr;
4347 
4348 		// unforce divstr
4349 		dib8000_i2c_write16(&client, 1285, new_addr << 2);
4350 
4351 		/* deactivate div - it was just for i2c-enumeration */
4352 		dib8000_i2c_write16(&client, 1286, 0);
4353 	}
4354 
4355 error:
4356 	kfree(client.i2c_buffer_lock);
4357 error_memory_lock:
4358 	kfree(client.i2c_read_buffer);
4359 error_memory_read:
4360 	kfree(client.i2c_write_buffer);
4361 
4362 	return ret;
4363 }
4364 
4365 static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
4366 {
4367 	tune->min_delay_ms = 1000;
4368 	tune->step_size = 0;
4369 	tune->max_drift = 0;
4370 	return 0;
4371 }
4372 
4373 static void dib8000_release(struct dvb_frontend *fe)
4374 {
4375 	struct dib8000_state *st = fe->demodulator_priv;
4376 	u8 index_frontend;
4377 
4378 	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
4379 		dvb_frontend_detach(st->fe[index_frontend]);
4380 
4381 	dibx000_exit_i2c_master(&st->i2c_master);
4382 	i2c_del_adapter(&st->dib8096p_tuner_adap);
4383 	kfree(st->fe[0]);
4384 	kfree(st);
4385 }
4386 
4387 static struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
4388 {
4389 	struct dib8000_state *st = fe->demodulator_priv;
4390 	return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
4391 }
4392 
4393 static int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
4394 {
4395 	struct dib8000_state *st = fe->demodulator_priv;
4396 	u16 val = dib8000_read_word(st, 299) & 0xffef;
4397 	val |= (onoff & 0x1) << 4;
4398 
4399 	dprintk("pid filter enabled %d\n", onoff);
4400 	return dib8000_write_word(st, 299, val);
4401 }
4402 
4403 static int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
4404 {
4405 	struct dib8000_state *st = fe->demodulator_priv;
4406 	dprintk("Index %x, PID %d, OnOff %d\n", id, pid, onoff);
4407 	return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
4408 }
4409 
4410 static const struct dvb_frontend_ops dib8000_ops = {
4411 	.delsys = { SYS_ISDBT },
4412 	.info = {
4413 		 .name = "DiBcom 8000 ISDB-T",
4414 		 .frequency_min_hz =  44250 * kHz,
4415 		 .frequency_max_hz = 867250 * kHz,
4416 		 .frequency_stepsize_hz = 62500,
4417 		 .caps = FE_CAN_INVERSION_AUTO |
4418 		 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
4419 		 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
4420 		 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
4421 		 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
4422 		 },
4423 
4424 	.release = dib8000_release,
4425 
4426 	.init = dib8000_wakeup,
4427 	.sleep = dib8000_sleep,
4428 
4429 	.set_frontend = dib8000_set_frontend,
4430 	.get_tune_settings = dib8000_fe_get_tune_settings,
4431 	.get_frontend = dib8000_get_frontend,
4432 
4433 	.read_status = dib8000_read_status,
4434 	.read_ber = dib8000_read_ber,
4435 	.read_signal_strength = dib8000_read_signal_strength,
4436 	.read_snr = dib8000_read_snr,
4437 	.read_ucblocks = dib8000_read_unc_blocks,
4438 };
4439 
4440 static struct dvb_frontend *dib8000_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
4441 {
4442 	struct dvb_frontend *fe;
4443 	struct dib8000_state *state;
4444 
4445 	dprintk("dib8000_init\n");
4446 
4447 	state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
4448 	if (state == NULL)
4449 		return NULL;
4450 	fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
4451 	if (fe == NULL)
4452 		goto error;
4453 
4454 	memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
4455 	state->i2c.adap = i2c_adap;
4456 	state->i2c.addr = i2c_addr;
4457 	state->i2c.i2c_write_buffer = state->i2c_write_buffer;
4458 	state->i2c.i2c_read_buffer = state->i2c_read_buffer;
4459 	mutex_init(&state->i2c_buffer_lock);
4460 	state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
4461 	state->gpio_val = cfg->gpio_val;
4462 	state->gpio_dir = cfg->gpio_dir;
4463 
4464 	/* Ensure the output mode remains at the previous default if it's
4465 	 * not specifically set by the caller.
4466 	 */
4467 	if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
4468 		state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
4469 
4470 	state->fe[0] = fe;
4471 	fe->demodulator_priv = state;
4472 	memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
4473 
4474 	state->timf_default = cfg->pll->timf;
4475 
4476 	if (dib8000_identify(&state->i2c) == 0)
4477 		goto error;
4478 
4479 	dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
4480 
4481 	/* init 8096p tuner adapter */
4482 	strscpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
4483 		sizeof(state->dib8096p_tuner_adap.name));
4484 	state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
4485 	state->dib8096p_tuner_adap.algo_data = NULL;
4486 	state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
4487 	i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
4488 	i2c_add_adapter(&state->dib8096p_tuner_adap);
4489 
4490 	dib8000_reset(fe);
4491 
4492 	dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));	/* ber_rs_len = 3 */
4493 	state->current_demod_bw = 6000;
4494 
4495 	return fe;
4496 
4497 error:
4498 	kfree(state);
4499 	return NULL;
4500 }
4501 
4502 void *dib8000_attach(struct dib8000_ops *ops)
4503 {
4504 	if (!ops)
4505 		return NULL;
4506 
4507 	ops->pwm_agc_reset = dib8000_pwm_agc_reset;
4508 	ops->get_dc_power = dib8090p_get_dc_power;
4509 	ops->set_gpio = dib8000_set_gpio;
4510 	ops->get_slave_frontend = dib8000_get_slave_frontend;
4511 	ops->set_tune_state = dib8000_set_tune_state;
4512 	ops->pid_filter_ctrl = dib8000_pid_filter_ctrl;
4513 	ops->get_adc_power = dib8000_get_adc_power;
4514 	ops->update_pll = dib8000_update_pll;
4515 	ops->tuner_sleep = dib8096p_tuner_sleep;
4516 	ops->get_tune_state = dib8000_get_tune_state;
4517 	ops->get_i2c_tuner = dib8096p_get_i2c_tuner;
4518 	ops->set_slave_frontend = dib8000_set_slave_frontend;
4519 	ops->pid_filter = dib8000_pid_filter;
4520 	ops->ctrl_timf = dib8000_ctrl_timf;
4521 	ops->init = dib8000_init;
4522 	ops->get_i2c_master = dib8000_get_i2c_master;
4523 	ops->i2c_enumeration = dib8000_i2c_enumeration;
4524 	ops->set_wbd_ref = dib8000_set_wbd_ref;
4525 
4526 	return ops;
4527 }
4528 EXPORT_SYMBOL(dib8000_attach);
4529 
4530 MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@parrot.com, Patrick Boettcher <patrick.boettcher@posteo.de>");
4531 MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
4532 MODULE_LICENSE("GPL");
4533