1 /* 2 * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC). 3 * 4 * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation, version 2. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/i2c.h> 16 #include <linux/mutex.h> 17 #include <asm/div64.h> 18 19 #include "dvb_math.h" 20 #include "dvb_frontend.h" 21 22 #include "dib7000p.h" 23 24 static int debug; 25 module_param(debug, int, 0644); 26 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); 27 28 static int buggy_sfn_workaround; 29 module_param(buggy_sfn_workaround, int, 0644); 30 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)"); 31 32 #define dprintk(fmt, arg...) do { \ 33 if (debug) \ 34 printk(KERN_DEBUG pr_fmt("%s: " fmt), \ 35 __func__, ##arg); \ 36 } while (0) 37 38 struct i2c_device { 39 struct i2c_adapter *i2c_adap; 40 u8 i2c_addr; 41 }; 42 43 struct dib7000p_state { 44 struct dvb_frontend demod; 45 struct dib7000p_config cfg; 46 47 u8 i2c_addr; 48 struct i2c_adapter *i2c_adap; 49 50 struct dibx000_i2c_master i2c_master; 51 52 u16 wbd_ref; 53 54 u8 current_band; 55 u32 current_bandwidth; 56 struct dibx000_agc_config *current_agc; 57 u32 timf; 58 59 u8 div_force_off:1; 60 u8 div_state:1; 61 u16 div_sync_wait; 62 63 u8 agc_state; 64 65 u16 gpio_dir; 66 u16 gpio_val; 67 68 u8 sfn_workaround_active:1; 69 70 #define SOC7090 0x7090 71 u16 version; 72 73 u16 tuner_enable; 74 struct i2c_adapter dib7090_tuner_adap; 75 76 /* for the I2C transfer */ 77 struct i2c_msg msg[2]; 78 u8 i2c_write_buffer[4]; 79 u8 i2c_read_buffer[2]; 80 struct mutex i2c_buffer_lock; 81 82 u8 input_mode_mpeg; 83 84 /* for DVBv5 stats */ 85 s64 old_ucb; 86 unsigned long per_jiffies_stats; 87 unsigned long ber_jiffies_stats; 88 unsigned long get_stats_time; 89 }; 90 91 enum dib7000p_power_mode { 92 DIB7000P_POWER_ALL = 0, 93 DIB7000P_POWER_ANALOG_ADC, 94 DIB7000P_POWER_INTERFACE_ONLY, 95 }; 96 97 /* dib7090 specific fonctions */ 98 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode); 99 static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff); 100 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode); 101 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode); 102 103 static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) 104 { 105 u16 ret; 106 107 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { 108 dprintk("could not acquire lock\n"); 109 return 0; 110 } 111 112 state->i2c_write_buffer[0] = reg >> 8; 113 state->i2c_write_buffer[1] = reg & 0xff; 114 115 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); 116 state->msg[0].addr = state->i2c_addr >> 1; 117 state->msg[0].flags = 0; 118 state->msg[0].buf = state->i2c_write_buffer; 119 state->msg[0].len = 2; 120 state->msg[1].addr = state->i2c_addr >> 1; 121 state->msg[1].flags = I2C_M_RD; 122 state->msg[1].buf = state->i2c_read_buffer; 123 state->msg[1].len = 2; 124 125 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2) 126 dprintk("i2c read error on %d\n", reg); 127 128 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; 129 mutex_unlock(&state->i2c_buffer_lock); 130 return ret; 131 } 132 133 static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val) 134 { 135 int ret; 136 137 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { 138 dprintk("could not acquire lock\n"); 139 return -EINVAL; 140 } 141 142 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; 143 state->i2c_write_buffer[1] = reg & 0xff; 144 state->i2c_write_buffer[2] = (val >> 8) & 0xff; 145 state->i2c_write_buffer[3] = val & 0xff; 146 147 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); 148 state->msg[0].addr = state->i2c_addr >> 1; 149 state->msg[0].flags = 0; 150 state->msg[0].buf = state->i2c_write_buffer; 151 state->msg[0].len = 4; 152 153 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? 154 -EREMOTEIO : 0); 155 mutex_unlock(&state->i2c_buffer_lock); 156 return ret; 157 } 158 159 static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf) 160 { 161 u16 l = 0, r, *n; 162 n = buf; 163 l = *n++; 164 while (l) { 165 r = *n++; 166 167 do { 168 dib7000p_write_word(state, r, *n++); 169 r++; 170 } while (--l); 171 l = *n++; 172 } 173 } 174 175 static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode) 176 { 177 int ret = 0; 178 u16 outreg, fifo_threshold, smo_mode; 179 180 outreg = 0; 181 fifo_threshold = 1792; 182 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); 183 184 dprintk("setting output mode for demod %p to %d\n", &state->demod, mode); 185 186 switch (mode) { 187 case OUTMODE_MPEG2_PAR_GATED_CLK: 188 outreg = (1 << 10); /* 0x0400 */ 189 break; 190 case OUTMODE_MPEG2_PAR_CONT_CLK: 191 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ 192 break; 193 case OUTMODE_MPEG2_SERIAL: 194 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */ 195 break; 196 case OUTMODE_DIVERSITY: 197 if (state->cfg.hostbus_diversity) 198 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ 199 else 200 outreg = (1 << 11); 201 break; 202 case OUTMODE_MPEG2_FIFO: 203 smo_mode |= (3 << 1); 204 fifo_threshold = 512; 205 outreg = (1 << 10) | (5 << 6); 206 break; 207 case OUTMODE_ANALOG_ADC: 208 outreg = (1 << 10) | (3 << 6); 209 break; 210 case OUTMODE_HIGH_Z: 211 outreg = 0; 212 break; 213 default: 214 dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod); 215 break; 216 } 217 218 if (state->cfg.output_mpeg2_in_188_bytes) 219 smo_mode |= (1 << 5); 220 221 ret |= dib7000p_write_word(state, 235, smo_mode); 222 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ 223 if (state->version != SOC7090) 224 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */ 225 226 return ret; 227 } 228 229 static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff) 230 { 231 struct dib7000p_state *state = demod->demodulator_priv; 232 233 if (state->div_force_off) { 234 dprintk("diversity combination deactivated - forced by COFDM parameters\n"); 235 onoff = 0; 236 dib7000p_write_word(state, 207, 0); 237 } else 238 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0)); 239 240 state->div_state = (u8) onoff; 241 242 if (onoff) { 243 dib7000p_write_word(state, 204, 6); 244 dib7000p_write_word(state, 205, 16); 245 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */ 246 } else { 247 dib7000p_write_word(state, 204, 1); 248 dib7000p_write_word(state, 205, 0); 249 } 250 251 return 0; 252 } 253 254 static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode) 255 { 256 /* by default everything is powered off */ 257 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff); 258 259 /* now, depending on the requested mode, we power on */ 260 switch (mode) { 261 /* power up everything in the demod */ 262 case DIB7000P_POWER_ALL: 263 reg_774 = 0x0000; 264 reg_775 = 0x0000; 265 reg_776 = 0x0; 266 reg_899 = 0x0; 267 if (state->version == SOC7090) 268 reg_1280 &= 0x001f; 269 else 270 reg_1280 &= 0x01ff; 271 break; 272 273 case DIB7000P_POWER_ANALOG_ADC: 274 /* dem, cfg, iqc, sad, agc */ 275 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9)); 276 /* nud */ 277 reg_776 &= ~((1 << 0)); 278 /* Dout */ 279 if (state->version != SOC7090) 280 reg_1280 &= ~((1 << 11)); 281 reg_1280 &= ~(1 << 6); 282 /* fall through wanted to enable the interfaces */ 283 284 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */ 285 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */ 286 if (state->version == SOC7090) 287 reg_1280 &= ~((1 << 7) | (1 << 5)); 288 else 289 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10)); 290 break; 291 292 /* TODO following stuff is just converted from the dib7000-driver - check when is used what */ 293 } 294 295 dib7000p_write_word(state, 774, reg_774); 296 dib7000p_write_word(state, 775, reg_775); 297 dib7000p_write_word(state, 776, reg_776); 298 dib7000p_write_word(state, 1280, reg_1280); 299 if (state->version != SOC7090) 300 dib7000p_write_word(state, 899, reg_899); 301 302 return 0; 303 } 304 305 static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no) 306 { 307 u16 reg_908 = 0, reg_909 = 0; 308 u16 reg; 309 310 if (state->version != SOC7090) { 311 reg_908 = dib7000p_read_word(state, 908); 312 reg_909 = dib7000p_read_word(state, 909); 313 } 314 315 switch (no) { 316 case DIBX000_SLOW_ADC_ON: 317 if (state->version == SOC7090) { 318 reg = dib7000p_read_word(state, 1925); 319 320 dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */ 321 322 reg = dib7000p_read_word(state, 1925); /* read acces to make it works... strange ... */ 323 msleep(200); 324 dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */ 325 326 reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12)); 327 dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */ 328 } else { 329 reg_909 |= (1 << 1) | (1 << 0); 330 dib7000p_write_word(state, 909, reg_909); 331 reg_909 &= ~(1 << 1); 332 } 333 break; 334 335 case DIBX000_SLOW_ADC_OFF: 336 if (state->version == SOC7090) { 337 reg = dib7000p_read_word(state, 1925); 338 dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */ 339 } else 340 reg_909 |= (1 << 1) | (1 << 0); 341 break; 342 343 case DIBX000_ADC_ON: 344 reg_908 &= 0x0fff; 345 reg_909 &= 0x0003; 346 break; 347 348 case DIBX000_ADC_OFF: 349 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12); 350 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2); 351 break; 352 353 case DIBX000_VBG_ENABLE: 354 reg_908 &= ~(1 << 15); 355 break; 356 357 case DIBX000_VBG_DISABLE: 358 reg_908 |= (1 << 15); 359 break; 360 361 default: 362 break; 363 } 364 365 // dprintk( "908: %x, 909: %x\n", reg_908, reg_909); 366 367 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4; 368 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7; 369 370 if (state->version != SOC7090) { 371 dib7000p_write_word(state, 908, reg_908); 372 dib7000p_write_word(state, 909, reg_909); 373 } 374 } 375 376 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw) 377 { 378 u32 timf; 379 380 // store the current bandwidth for later use 381 state->current_bandwidth = bw; 382 383 if (state->timf == 0) { 384 dprintk("using default timf\n"); 385 timf = state->cfg.bw->timf; 386 } else { 387 dprintk("using updated timf\n"); 388 timf = state->timf; 389 } 390 391 timf = timf * (bw / 50) / 160; 392 393 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); 394 dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff)); 395 396 return 0; 397 } 398 399 static int dib7000p_sad_calib(struct dib7000p_state *state) 400 { 401 /* internal */ 402 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0)); 403 404 if (state->version == SOC7090) 405 dib7000p_write_word(state, 74, 2048); 406 else 407 dib7000p_write_word(state, 74, 776); 408 409 /* do the calibration */ 410 dib7000p_write_word(state, 73, (1 << 0)); 411 dib7000p_write_word(state, 73, (0 << 0)); 412 413 msleep(1); 414 415 return 0; 416 } 417 418 static int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value) 419 { 420 struct dib7000p_state *state = demod->demodulator_priv; 421 if (value > 4095) 422 value = 4095; 423 state->wbd_ref = value; 424 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value); 425 } 426 427 static int dib7000p_get_agc_values(struct dvb_frontend *fe, 428 u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd) 429 { 430 struct dib7000p_state *state = fe->demodulator_priv; 431 432 if (agc_global != NULL) 433 *agc_global = dib7000p_read_word(state, 394); 434 if (agc1 != NULL) 435 *agc1 = dib7000p_read_word(state, 392); 436 if (agc2 != NULL) 437 *agc2 = dib7000p_read_word(state, 393); 438 if (wbd != NULL) 439 *wbd = dib7000p_read_word(state, 397); 440 441 return 0; 442 } 443 444 static int dib7000p_set_agc1_min(struct dvb_frontend *fe, u16 v) 445 { 446 struct dib7000p_state *state = fe->demodulator_priv; 447 return dib7000p_write_word(state, 108, v); 448 } 449 450 static void dib7000p_reset_pll(struct dib7000p_state *state) 451 { 452 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; 453 u16 clk_cfg0; 454 455 if (state->version == SOC7090) { 456 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv)); 457 458 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) 459 ; 460 461 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15)); 462 } else { 463 /* force PLL bypass */ 464 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | 465 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0); 466 467 dib7000p_write_word(state, 900, clk_cfg0); 468 469 /* P_pll_cfg */ 470 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset); 471 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff); 472 dib7000p_write_word(state, 900, clk_cfg0); 473 } 474 475 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff)); 476 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff)); 477 dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff)); 478 dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff)); 479 480 dib7000p_write_word(state, 72, bw->sad_cfg); 481 } 482 483 static u32 dib7000p_get_internal_freq(struct dib7000p_state *state) 484 { 485 u32 internal = (u32) dib7000p_read_word(state, 18) << 16; 486 internal |= (u32) dib7000p_read_word(state, 19); 487 internal /= 1000; 488 489 return internal; 490 } 491 492 static int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw) 493 { 494 struct dib7000p_state *state = fe->demodulator_priv; 495 u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856); 496 u8 loopdiv, prediv; 497 u32 internal, xtal; 498 499 /* get back old values */ 500 prediv = reg_1856 & 0x3f; 501 loopdiv = (reg_1856 >> 6) & 0x3f; 502 503 if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { 504 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio); 505 reg_1856 &= 0xf000; 506 reg_1857 = dib7000p_read_word(state, 1857); 507 dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15)); 508 509 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f)); 510 511 /* write new system clk into P_sec_len */ 512 internal = dib7000p_get_internal_freq(state); 513 xtal = (internal / loopdiv) * prediv; 514 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */ 515 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff)); 516 dib7000p_write_word(state, 19, (u16) (internal & 0xffff)); 517 518 dib7000p_write_word(state, 1857, reg_1857 | (1 << 15)); 519 520 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) 521 dprintk("Waiting for PLL to lock\n"); 522 523 return 0; 524 } 525 return -EIO; 526 } 527 528 static int dib7000p_reset_gpio(struct dib7000p_state *st) 529 { 530 /* reset the GPIOs */ 531 dprintk("gpio dir: %x: val: %x, pwm_pos: %x\n", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos); 532 533 dib7000p_write_word(st, 1029, st->gpio_dir); 534 dib7000p_write_word(st, 1030, st->gpio_val); 535 536 /* TODO 1031 is P_gpio_od */ 537 538 dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos); 539 540 dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div); 541 return 0; 542 } 543 544 static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val) 545 { 546 st->gpio_dir = dib7000p_read_word(st, 1029); 547 st->gpio_dir &= ~(1 << num); /* reset the direction bit */ 548 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */ 549 dib7000p_write_word(st, 1029, st->gpio_dir); 550 551 st->gpio_val = dib7000p_read_word(st, 1030); 552 st->gpio_val &= ~(1 << num); /* reset the direction bit */ 553 st->gpio_val |= (val & 0x01) << num; /* set the new value */ 554 dib7000p_write_word(st, 1030, st->gpio_val); 555 556 return 0; 557 } 558 559 static int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val) 560 { 561 struct dib7000p_state *state = demod->demodulator_priv; 562 return dib7000p_cfg_gpio(state, num, dir, val); 563 } 564 565 static u16 dib7000p_defaults[] = { 566 // auto search configuration 567 3, 2, 568 0x0004, 569 (1<<3)|(1<<11)|(1<<12)|(1<<13), 570 0x0814, /* Equal Lock */ 571 572 12, 6, 573 0x001b, 574 0x7740, 575 0x005b, 576 0x8d80, 577 0x01c9, 578 0xc380, 579 0x0000, 580 0x0080, 581 0x0000, 582 0x0090, 583 0x0001, 584 0xd4c0, 585 586 1, 26, 587 0x6680, 588 589 /* set ADC level to -16 */ 590 11, 79, 591 (1 << 13) - 825 - 117, 592 (1 << 13) - 837 - 117, 593 (1 << 13) - 811 - 117, 594 (1 << 13) - 766 - 117, 595 (1 << 13) - 737 - 117, 596 (1 << 13) - 693 - 117, 597 (1 << 13) - 648 - 117, 598 (1 << 13) - 619 - 117, 599 (1 << 13) - 575 - 117, 600 (1 << 13) - 531 - 117, 601 (1 << 13) - 501 - 117, 602 603 1, 142, 604 0x0410, 605 606 /* disable power smoothing */ 607 8, 145, 608 0, 609 0, 610 0, 611 0, 612 0, 613 0, 614 0, 615 0, 616 617 1, 154, 618 1 << 13, 619 620 1, 168, 621 0x0ccd, 622 623 1, 183, 624 0x200f, 625 626 1, 212, 627 0x169, 628 629 5, 187, 630 0x023d, 631 0x00a4, 632 0x00a4, 633 0x7ff0, 634 0x3ccc, 635 636 1, 198, 637 0x800, 638 639 1, 222, 640 0x0010, 641 642 1, 235, 643 0x0062, 644 645 0, 646 }; 647 648 static void dib7000p_reset_stats(struct dvb_frontend *fe); 649 650 static int dib7000p_demod_reset(struct dib7000p_state *state) 651 { 652 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 653 654 if (state->version == SOC7090) 655 dibx000_reset_i2c_master(&state->i2c_master); 656 657 dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE); 658 659 /* restart all parts */ 660 dib7000p_write_word(state, 770, 0xffff); 661 dib7000p_write_word(state, 771, 0xffff); 662 dib7000p_write_word(state, 772, 0x001f); 663 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3))); 664 665 dib7000p_write_word(state, 770, 0); 666 dib7000p_write_word(state, 771, 0); 667 dib7000p_write_word(state, 772, 0); 668 dib7000p_write_word(state, 1280, 0); 669 670 if (state->version != SOC7090) { 671 dib7000p_write_word(state, 898, 0x0003); 672 dib7000p_write_word(state, 898, 0); 673 } 674 675 /* default */ 676 dib7000p_reset_pll(state); 677 678 if (dib7000p_reset_gpio(state) != 0) 679 dprintk("GPIO reset was not successful.\n"); 680 681 if (state->version == SOC7090) { 682 dib7000p_write_word(state, 899, 0); 683 684 /* impulse noise */ 685 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */ 686 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */ 687 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */ 688 dib7000p_write_word(state, 273, (0<<6) | 30); 689 } 690 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0) 691 dprintk("OUTPUT_MODE could not be reset.\n"); 692 693 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); 694 dib7000p_sad_calib(state); 695 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF); 696 697 /* unforce divstr regardless whether i2c enumeration was done or not */ 698 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1)); 699 700 dib7000p_set_bandwidth(state, 8000); 701 702 if (state->version == SOC7090) { 703 dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */ 704 } else { 705 if (state->cfg.tuner_is_baseband) 706 dib7000p_write_word(state, 36, 0x0755); 707 else 708 dib7000p_write_word(state, 36, 0x1f55); 709 } 710 711 dib7000p_write_tab(state, dib7000p_defaults); 712 if (state->version != SOC7090) { 713 dib7000p_write_word(state, 901, 0x0006); 714 dib7000p_write_word(state, 902, (3 << 10) | (1 << 6)); 715 dib7000p_write_word(state, 905, 0x2c8e); 716 } 717 718 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 719 720 return 0; 721 } 722 723 static void dib7000p_pll_clk_cfg(struct dib7000p_state *state) 724 { 725 u16 tmp = 0; 726 tmp = dib7000p_read_word(state, 903); 727 dib7000p_write_word(state, 903, (tmp | 0x1)); 728 tmp = dib7000p_read_word(state, 900); 729 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); 730 } 731 732 static void dib7000p_restart_agc(struct dib7000p_state *state) 733 { 734 // P_restart_iqc & P_restart_agc 735 dib7000p_write_word(state, 770, (1 << 11) | (1 << 9)); 736 dib7000p_write_word(state, 770, 0x0000); 737 } 738 739 static int dib7000p_update_lna(struct dib7000p_state *state) 740 { 741 u16 dyn_gain; 742 743 if (state->cfg.update_lna) { 744 dyn_gain = dib7000p_read_word(state, 394); 745 if (state->cfg.update_lna(&state->demod, dyn_gain)) { 746 dib7000p_restart_agc(state); 747 return 1; 748 } 749 } 750 751 return 0; 752 } 753 754 static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band) 755 { 756 struct dibx000_agc_config *agc = NULL; 757 int i; 758 if (state->current_band == band && state->current_agc != NULL) 759 return 0; 760 state->current_band = band; 761 762 for (i = 0; i < state->cfg.agc_config_count; i++) 763 if (state->cfg.agc[i].band_caps & band) { 764 agc = &state->cfg.agc[i]; 765 break; 766 } 767 768 if (agc == NULL) { 769 dprintk("no valid AGC configuration found for band 0x%02x\n", band); 770 return -EINVAL; 771 } 772 773 state->current_agc = agc; 774 775 /* AGC */ 776 dib7000p_write_word(state, 75, agc->setup); 777 dib7000p_write_word(state, 76, agc->inv_gain); 778 dib7000p_write_word(state, 77, agc->time_stabiliz); 779 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock); 780 781 // Demod AGC loop configuration 782 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp); 783 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp); 784 785 /* AGC continued */ 786 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n", 787 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); 788 789 if (state->wbd_ref != 0) 790 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref); 791 else 792 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref); 793 794 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); 795 796 dib7000p_write_word(state, 107, agc->agc1_max); 797 dib7000p_write_word(state, 108, agc->agc1_min); 798 dib7000p_write_word(state, 109, agc->agc2_max); 799 dib7000p_write_word(state, 110, agc->agc2_min); 800 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2); 801 dib7000p_write_word(state, 112, agc->agc1_pt3); 802 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); 803 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); 804 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); 805 return 0; 806 } 807 808 static int dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz) 809 { 810 u32 internal = dib7000p_get_internal_freq(state); 811 s32 unit_khz_dds_val; 812 u32 abs_offset_khz = ABS(offset_khz); 813 u32 dds = state->cfg.bw->ifreq & 0x1ffffff; 814 u8 invert = !!(state->cfg.bw->ifreq & (1 << 25)); 815 if (internal == 0) { 816 pr_warn("DIB7000P: dib7000p_get_internal_freq returned 0\n"); 817 return -1; 818 } 819 /* 2**26 / Fsampling is the unit 1KHz offset */ 820 unit_khz_dds_val = 67108864 / (internal); 821 822 dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d\n", offset_khz, internal, invert); 823 824 if (offset_khz < 0) 825 unit_khz_dds_val *= -1; 826 827 /* IF tuner */ 828 if (invert) 829 dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */ 830 else 831 dds += (abs_offset_khz * unit_khz_dds_val); 832 833 if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */ 834 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9))); 835 dib7000p_write_word(state, 22, (u16) (dds & 0xffff)); 836 } 837 return 0; 838 } 839 840 static int dib7000p_agc_startup(struct dvb_frontend *demod) 841 { 842 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; 843 struct dib7000p_state *state = demod->demodulator_priv; 844 int ret = -1; 845 u8 *agc_state = &state->agc_state; 846 u8 agc_split; 847 u16 reg; 848 u32 upd_demod_gain_period = 0x1000; 849 s32 frequency_offset = 0; 850 851 switch (state->agc_state) { 852 case 0: 853 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 854 if (state->version == SOC7090) { 855 reg = dib7000p_read_word(state, 0x79b) & 0xff00; 856 dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */ 857 dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF)); 858 859 /* enable adc i & q */ 860 reg = dib7000p_read_word(state, 0x780); 861 dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7))); 862 } else { 863 dib7000p_set_adc_state(state, DIBX000_ADC_ON); 864 dib7000p_pll_clk_cfg(state); 865 } 866 867 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0) 868 return -1; 869 870 if (demod->ops.tuner_ops.get_frequency) { 871 u32 frequency_tuner; 872 873 demod->ops.tuner_ops.get_frequency(demod, &frequency_tuner); 874 frequency_offset = (s32)frequency_tuner / 1000 - ch->frequency / 1000; 875 } 876 877 if (dib7000p_set_dds(state, frequency_offset) < 0) 878 return -1; 879 880 ret = 7; 881 (*agc_state)++; 882 break; 883 884 case 1: 885 if (state->cfg.agc_control) 886 state->cfg.agc_control(&state->demod, 1); 887 888 dib7000p_write_word(state, 78, 32768); 889 if (!state->current_agc->perform_agc_softsplit) { 890 /* we are using the wbd - so slow AGC startup */ 891 /* force 0 split on WBD and restart AGC */ 892 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8)); 893 (*agc_state)++; 894 ret = 5; 895 } else { 896 /* default AGC startup */ 897 (*agc_state) = 4; 898 /* wait AGC rough lock time */ 899 ret = 7; 900 } 901 902 dib7000p_restart_agc(state); 903 break; 904 905 case 2: /* fast split search path after 5sec */ 906 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */ 907 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */ 908 (*agc_state)++; 909 ret = 14; 910 break; 911 912 case 3: /* split search ended */ 913 agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */ 914 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */ 915 916 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */ 917 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */ 918 919 dib7000p_restart_agc(state); 920 921 dprintk("SPLIT %p: %hd\n", demod, agc_split); 922 923 (*agc_state)++; 924 ret = 5; 925 break; 926 927 case 4: /* LNA startup */ 928 ret = 7; 929 930 if (dib7000p_update_lna(state)) 931 ret = 5; 932 else 933 (*agc_state)++; 934 break; 935 936 case 5: 937 if (state->cfg.agc_control) 938 state->cfg.agc_control(&state->demod, 0); 939 (*agc_state)++; 940 break; 941 default: 942 break; 943 } 944 return ret; 945 } 946 947 static void dib7000p_update_timf(struct dib7000p_state *state) 948 { 949 u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428); 950 state->timf = timf * 160 / (state->current_bandwidth / 50); 951 dib7000p_write_word(state, 23, (u16) (timf >> 16)); 952 dib7000p_write_word(state, 24, (u16) (timf & 0xffff)); 953 dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->cfg.bw->timf); 954 955 } 956 957 static u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf) 958 { 959 struct dib7000p_state *state = fe->demodulator_priv; 960 switch (op) { 961 case DEMOD_TIMF_SET: 962 state->timf = timf; 963 break; 964 case DEMOD_TIMF_UPDATE: 965 dib7000p_update_timf(state); 966 break; 967 case DEMOD_TIMF_GET: 968 break; 969 } 970 dib7000p_set_bandwidth(state, state->current_bandwidth); 971 return state->timf; 972 } 973 974 static void dib7000p_set_channel(struct dib7000p_state *state, 975 struct dtv_frontend_properties *ch, u8 seq) 976 { 977 u16 value, est[4]; 978 979 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); 980 981 /* nfft, guard, qam, alpha */ 982 value = 0; 983 switch (ch->transmission_mode) { 984 case TRANSMISSION_MODE_2K: 985 value |= (0 << 7); 986 break; 987 case TRANSMISSION_MODE_4K: 988 value |= (2 << 7); 989 break; 990 default: 991 case TRANSMISSION_MODE_8K: 992 value |= (1 << 7); 993 break; 994 } 995 switch (ch->guard_interval) { 996 case GUARD_INTERVAL_1_32: 997 value |= (0 << 5); 998 break; 999 case GUARD_INTERVAL_1_16: 1000 value |= (1 << 5); 1001 break; 1002 case GUARD_INTERVAL_1_4: 1003 value |= (3 << 5); 1004 break; 1005 default: 1006 case GUARD_INTERVAL_1_8: 1007 value |= (2 << 5); 1008 break; 1009 } 1010 switch (ch->modulation) { 1011 case QPSK: 1012 value |= (0 << 3); 1013 break; 1014 case QAM_16: 1015 value |= (1 << 3); 1016 break; 1017 default: 1018 case QAM_64: 1019 value |= (2 << 3); 1020 break; 1021 } 1022 switch (HIERARCHY_1) { 1023 case HIERARCHY_2: 1024 value |= 2; 1025 break; 1026 case HIERARCHY_4: 1027 value |= 4; 1028 break; 1029 default: 1030 case HIERARCHY_1: 1031 value |= 1; 1032 break; 1033 } 1034 dib7000p_write_word(state, 0, value); 1035 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */ 1036 1037 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */ 1038 value = 0; 1039 if (1 != 0) 1040 value |= (1 << 6); 1041 if (ch->hierarchy == 1) 1042 value |= (1 << 4); 1043 if (1 == 1) 1044 value |= 1; 1045 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) { 1046 case FEC_2_3: 1047 value |= (2 << 1); 1048 break; 1049 case FEC_3_4: 1050 value |= (3 << 1); 1051 break; 1052 case FEC_5_6: 1053 value |= (5 << 1); 1054 break; 1055 case FEC_7_8: 1056 value |= (7 << 1); 1057 break; 1058 default: 1059 case FEC_1_2: 1060 value |= (1 << 1); 1061 break; 1062 } 1063 dib7000p_write_word(state, 208, value); 1064 1065 /* offset loop parameters */ 1066 dib7000p_write_word(state, 26, 0x6680); 1067 dib7000p_write_word(state, 32, 0x0003); 1068 dib7000p_write_word(state, 29, 0x1273); 1069 dib7000p_write_word(state, 33, 0x0005); 1070 1071 /* P_dvsy_sync_wait */ 1072 switch (ch->transmission_mode) { 1073 case TRANSMISSION_MODE_8K: 1074 value = 256; 1075 break; 1076 case TRANSMISSION_MODE_4K: 1077 value = 128; 1078 break; 1079 case TRANSMISSION_MODE_2K: 1080 default: 1081 value = 64; 1082 break; 1083 } 1084 switch (ch->guard_interval) { 1085 case GUARD_INTERVAL_1_16: 1086 value *= 2; 1087 break; 1088 case GUARD_INTERVAL_1_8: 1089 value *= 4; 1090 break; 1091 case GUARD_INTERVAL_1_4: 1092 value *= 8; 1093 break; 1094 default: 1095 case GUARD_INTERVAL_1_32: 1096 value *= 1; 1097 break; 1098 } 1099 if (state->cfg.diversity_delay == 0) 1100 state->div_sync_wait = (value * 3) / 2 + 48; 1101 else 1102 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay; 1103 1104 /* deactive the possibility of diversity reception if extended interleaver */ 1105 state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K; 1106 dib7000p_set_diversity_in(&state->demod, state->div_state); 1107 1108 /* channel estimation fine configuration */ 1109 switch (ch->modulation) { 1110 case QAM_64: 1111 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 1112 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 1113 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 1114 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ 1115 break; 1116 case QAM_16: 1117 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ 1118 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ 1119 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 1120 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */ 1121 break; 1122 default: 1123 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */ 1124 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */ 1125 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */ 1126 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ 1127 break; 1128 } 1129 for (value = 0; value < 4; value++) 1130 dib7000p_write_word(state, 187 + value, est[value]); 1131 } 1132 1133 static int dib7000p_autosearch_start(struct dvb_frontend *demod) 1134 { 1135 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; 1136 struct dib7000p_state *state = demod->demodulator_priv; 1137 struct dtv_frontend_properties schan; 1138 u32 value, factor; 1139 u32 internal = dib7000p_get_internal_freq(state); 1140 1141 schan = *ch; 1142 schan.modulation = QAM_64; 1143 schan.guard_interval = GUARD_INTERVAL_1_32; 1144 schan.transmission_mode = TRANSMISSION_MODE_8K; 1145 schan.code_rate_HP = FEC_2_3; 1146 schan.code_rate_LP = FEC_3_4; 1147 schan.hierarchy = 0; 1148 1149 dib7000p_set_channel(state, &schan, 7); 1150 1151 factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz); 1152 if (factor >= 5000) { 1153 if (state->version == SOC7090) 1154 factor = 2; 1155 else 1156 factor = 1; 1157 } else 1158 factor = 6; 1159 1160 value = 30 * internal * factor; 1161 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); 1162 dib7000p_write_word(state, 7, (u16) (value & 0xffff)); 1163 value = 100 * internal * factor; 1164 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); 1165 dib7000p_write_word(state, 9, (u16) (value & 0xffff)); 1166 value = 500 * internal * factor; 1167 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); 1168 dib7000p_write_word(state, 11, (u16) (value & 0xffff)); 1169 1170 value = dib7000p_read_word(state, 0); 1171 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value)); 1172 dib7000p_read_word(state, 1284); 1173 dib7000p_write_word(state, 0, (u16) value); 1174 1175 return 0; 1176 } 1177 1178 static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod) 1179 { 1180 struct dib7000p_state *state = demod->demodulator_priv; 1181 u16 irq_pending = dib7000p_read_word(state, 1284); 1182 1183 if (irq_pending & 0x1) 1184 return 1; 1185 1186 if (irq_pending & 0x2) 1187 return 2; 1188 1189 return 0; 1190 } 1191 1192 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw) 1193 { 1194 static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 }; 1195 static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22, 1196 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51, 1197 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80, 1198 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105, 1199 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126, 1200 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146, 1201 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165, 1202 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182, 1203 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 1204 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212, 1205 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224, 1206 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235, 1207 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243, 1208 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249, 1209 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254, 1210 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1211 255, 255, 255, 255, 255, 255 1212 }; 1213 1214 u32 xtal = state->cfg.bw->xtal_hz / 1000; 1215 int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz; 1216 int k; 1217 int coef_re[8], coef_im[8]; 1218 int bw_khz = bw; 1219 u32 pha; 1220 1221 dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)\n", f_rel, rf_khz, xtal); 1222 1223 if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2) 1224 return; 1225 1226 bw_khz /= 100; 1227 1228 dib7000p_write_word(state, 142, 0x0610); 1229 1230 for (k = 0; k < 8; k++) { 1231 pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff; 1232 1233 if (pha == 0) { 1234 coef_re[k] = 256; 1235 coef_im[k] = 0; 1236 } else if (pha < 256) { 1237 coef_re[k] = sine[256 - (pha & 0xff)]; 1238 coef_im[k] = sine[pha & 0xff]; 1239 } else if (pha == 256) { 1240 coef_re[k] = 0; 1241 coef_im[k] = 256; 1242 } else if (pha < 512) { 1243 coef_re[k] = -sine[pha & 0xff]; 1244 coef_im[k] = sine[256 - (pha & 0xff)]; 1245 } else if (pha == 512) { 1246 coef_re[k] = -256; 1247 coef_im[k] = 0; 1248 } else if (pha < 768) { 1249 coef_re[k] = -sine[256 - (pha & 0xff)]; 1250 coef_im[k] = -sine[pha & 0xff]; 1251 } else if (pha == 768) { 1252 coef_re[k] = 0; 1253 coef_im[k] = -256; 1254 } else { 1255 coef_re[k] = sine[pha & 0xff]; 1256 coef_im[k] = -sine[256 - (pha & 0xff)]; 1257 } 1258 1259 coef_re[k] *= notch[k]; 1260 coef_re[k] += (1 << 14); 1261 if (coef_re[k] >= (1 << 24)) 1262 coef_re[k] = (1 << 24) - 1; 1263 coef_re[k] /= (1 << 15); 1264 1265 coef_im[k] *= notch[k]; 1266 coef_im[k] += (1 << 14); 1267 if (coef_im[k] >= (1 << 24)) 1268 coef_im[k] = (1 << 24) - 1; 1269 coef_im[k] /= (1 << 15); 1270 1271 dprintk("PALF COEF: %d re: %d im: %d\n", k, coef_re[k], coef_im[k]); 1272 1273 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); 1274 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff); 1275 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); 1276 } 1277 dib7000p_write_word(state, 143, 0); 1278 } 1279 1280 static int dib7000p_tune(struct dvb_frontend *demod) 1281 { 1282 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; 1283 struct dib7000p_state *state = demod->demodulator_priv; 1284 u16 tmp = 0; 1285 1286 if (ch != NULL) 1287 dib7000p_set_channel(state, ch, 0); 1288 else 1289 return -EINVAL; 1290 1291 // restart demod 1292 dib7000p_write_word(state, 770, 0x4000); 1293 dib7000p_write_word(state, 770, 0x0000); 1294 msleep(45); 1295 1296 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */ 1297 tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3); 1298 if (state->sfn_workaround_active) { 1299 dprintk("SFN workaround is active\n"); 1300 tmp |= (1 << 9); 1301 dib7000p_write_word(state, 166, 0x4000); 1302 } else { 1303 dib7000p_write_word(state, 166, 0x0000); 1304 } 1305 dib7000p_write_word(state, 29, tmp); 1306 1307 // never achieved a lock with that bandwidth so far - wait for osc-freq to update 1308 if (state->timf == 0) 1309 msleep(200); 1310 1311 /* offset loop parameters */ 1312 1313 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 1314 tmp = (6 << 8) | 0x80; 1315 switch (ch->transmission_mode) { 1316 case TRANSMISSION_MODE_2K: 1317 tmp |= (2 << 12); 1318 break; 1319 case TRANSMISSION_MODE_4K: 1320 tmp |= (3 << 12); 1321 break; 1322 default: 1323 case TRANSMISSION_MODE_8K: 1324 tmp |= (4 << 12); 1325 break; 1326 } 1327 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */ 1328 1329 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 1330 tmp = (0 << 4); 1331 switch (ch->transmission_mode) { 1332 case TRANSMISSION_MODE_2K: 1333 tmp |= 0x6; 1334 break; 1335 case TRANSMISSION_MODE_4K: 1336 tmp |= 0x7; 1337 break; 1338 default: 1339 case TRANSMISSION_MODE_8K: 1340 tmp |= 0x8; 1341 break; 1342 } 1343 dib7000p_write_word(state, 32, tmp); 1344 1345 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 1346 tmp = (0 << 4); 1347 switch (ch->transmission_mode) { 1348 case TRANSMISSION_MODE_2K: 1349 tmp |= 0x6; 1350 break; 1351 case TRANSMISSION_MODE_4K: 1352 tmp |= 0x7; 1353 break; 1354 default: 1355 case TRANSMISSION_MODE_8K: 1356 tmp |= 0x8; 1357 break; 1358 } 1359 dib7000p_write_word(state, 33, tmp); 1360 1361 tmp = dib7000p_read_word(state, 509); 1362 if (!((tmp >> 6) & 0x1)) { 1363 /* restart the fec */ 1364 tmp = dib7000p_read_word(state, 771); 1365 dib7000p_write_word(state, 771, tmp | (1 << 1)); 1366 dib7000p_write_word(state, 771, tmp); 1367 msleep(40); 1368 tmp = dib7000p_read_word(state, 509); 1369 } 1370 // we achieved a lock - it's time to update the osc freq 1371 if ((tmp >> 6) & 0x1) { 1372 dib7000p_update_timf(state); 1373 /* P_timf_alpha += 2 */ 1374 tmp = dib7000p_read_word(state, 26); 1375 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12)); 1376 } 1377 1378 if (state->cfg.spur_protect) 1379 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); 1380 1381 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); 1382 1383 dib7000p_reset_stats(demod); 1384 1385 return 0; 1386 } 1387 1388 static int dib7000p_wakeup(struct dvb_frontend *demod) 1389 { 1390 struct dib7000p_state *state = demod->demodulator_priv; 1391 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 1392 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); 1393 if (state->version == SOC7090) 1394 dib7000p_sad_calib(state); 1395 return 0; 1396 } 1397 1398 static int dib7000p_sleep(struct dvb_frontend *demod) 1399 { 1400 struct dib7000p_state *state = demod->demodulator_priv; 1401 if (state->version == SOC7090) 1402 return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1403 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1404 } 1405 1406 static int dib7000p_identify(struct dib7000p_state *st) 1407 { 1408 u16 value; 1409 dprintk("checking demod on I2C address: %d (%x)\n", st->i2c_addr, st->i2c_addr); 1410 1411 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) { 1412 dprintk("wrong Vendor ID (read=0x%x)\n", value); 1413 return -EREMOTEIO; 1414 } 1415 1416 if ((value = dib7000p_read_word(st, 769)) != 0x4000) { 1417 dprintk("wrong Device ID (%x)\n", value); 1418 return -EREMOTEIO; 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int dib7000p_get_frontend(struct dvb_frontend *fe, 1425 struct dtv_frontend_properties *fep) 1426 { 1427 struct dib7000p_state *state = fe->demodulator_priv; 1428 u16 tps = dib7000p_read_word(state, 463); 1429 1430 fep->inversion = INVERSION_AUTO; 1431 1432 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth); 1433 1434 switch ((tps >> 8) & 0x3) { 1435 case 0: 1436 fep->transmission_mode = TRANSMISSION_MODE_2K; 1437 break; 1438 case 1: 1439 fep->transmission_mode = TRANSMISSION_MODE_8K; 1440 break; 1441 /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */ 1442 } 1443 1444 switch (tps & 0x3) { 1445 case 0: 1446 fep->guard_interval = GUARD_INTERVAL_1_32; 1447 break; 1448 case 1: 1449 fep->guard_interval = GUARD_INTERVAL_1_16; 1450 break; 1451 case 2: 1452 fep->guard_interval = GUARD_INTERVAL_1_8; 1453 break; 1454 case 3: 1455 fep->guard_interval = GUARD_INTERVAL_1_4; 1456 break; 1457 } 1458 1459 switch ((tps >> 14) & 0x3) { 1460 case 0: 1461 fep->modulation = QPSK; 1462 break; 1463 case 1: 1464 fep->modulation = QAM_16; 1465 break; 1466 case 2: 1467 default: 1468 fep->modulation = QAM_64; 1469 break; 1470 } 1471 1472 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 1473 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */ 1474 1475 fep->hierarchy = HIERARCHY_NONE; 1476 switch ((tps >> 5) & 0x7) { 1477 case 1: 1478 fep->code_rate_HP = FEC_1_2; 1479 break; 1480 case 2: 1481 fep->code_rate_HP = FEC_2_3; 1482 break; 1483 case 3: 1484 fep->code_rate_HP = FEC_3_4; 1485 break; 1486 case 5: 1487 fep->code_rate_HP = FEC_5_6; 1488 break; 1489 case 7: 1490 default: 1491 fep->code_rate_HP = FEC_7_8; 1492 break; 1493 1494 } 1495 1496 switch ((tps >> 2) & 0x7) { 1497 case 1: 1498 fep->code_rate_LP = FEC_1_2; 1499 break; 1500 case 2: 1501 fep->code_rate_LP = FEC_2_3; 1502 break; 1503 case 3: 1504 fep->code_rate_LP = FEC_3_4; 1505 break; 1506 case 5: 1507 fep->code_rate_LP = FEC_5_6; 1508 break; 1509 case 7: 1510 default: 1511 fep->code_rate_LP = FEC_7_8; 1512 break; 1513 } 1514 1515 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */ 1516 1517 return 0; 1518 } 1519 1520 static int dib7000p_set_frontend(struct dvb_frontend *fe) 1521 { 1522 struct dtv_frontend_properties *fep = &fe->dtv_property_cache; 1523 struct dib7000p_state *state = fe->demodulator_priv; 1524 int time, ret; 1525 1526 if (state->version == SOC7090) 1527 dib7090_set_diversity_in(fe, 0); 1528 else 1529 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z); 1530 1531 /* maybe the parameter has been changed */ 1532 state->sfn_workaround_active = buggy_sfn_workaround; 1533 1534 if (fe->ops.tuner_ops.set_params) 1535 fe->ops.tuner_ops.set_params(fe); 1536 1537 /* start up the AGC */ 1538 state->agc_state = 0; 1539 do { 1540 time = dib7000p_agc_startup(fe); 1541 if (time != -1) 1542 msleep(time); 1543 } while (time != -1); 1544 1545 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO || 1546 fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) { 1547 int i = 800, found; 1548 1549 dib7000p_autosearch_start(fe); 1550 do { 1551 msleep(1); 1552 found = dib7000p_autosearch_is_irq(fe); 1553 } while (found == 0 && i--); 1554 1555 dprintk("autosearch returns: %d\n", found); 1556 if (found == 0 || found == 1) 1557 return 0; 1558 1559 dib7000p_get_frontend(fe, fep); 1560 } 1561 1562 ret = dib7000p_tune(fe); 1563 1564 /* make this a config parameter */ 1565 if (state->version == SOC7090) { 1566 dib7090_set_output_mode(fe, state->cfg.output_mode); 1567 if (state->cfg.enMpegOutput == 0) { 1568 dib7090_setDibTxMux(state, MPEG_ON_DIBTX); 1569 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS); 1570 } 1571 } else 1572 dib7000p_set_output_mode(state, state->cfg.output_mode); 1573 1574 return ret; 1575 } 1576 1577 static int dib7000p_get_stats(struct dvb_frontend *fe, enum fe_status stat); 1578 1579 static int dib7000p_read_status(struct dvb_frontend *fe, enum fe_status *stat) 1580 { 1581 struct dib7000p_state *state = fe->demodulator_priv; 1582 u16 lock = dib7000p_read_word(state, 509); 1583 1584 *stat = 0; 1585 1586 if (lock & 0x8000) 1587 *stat |= FE_HAS_SIGNAL; 1588 if (lock & 0x3000) 1589 *stat |= FE_HAS_CARRIER; 1590 if (lock & 0x0100) 1591 *stat |= FE_HAS_VITERBI; 1592 if (lock & 0x0010) 1593 *stat |= FE_HAS_SYNC; 1594 if ((lock & 0x0038) == 0x38) 1595 *stat |= FE_HAS_LOCK; 1596 1597 dib7000p_get_stats(fe, *stat); 1598 1599 return 0; 1600 } 1601 1602 static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber) 1603 { 1604 struct dib7000p_state *state = fe->demodulator_priv; 1605 *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501); 1606 return 0; 1607 } 1608 1609 static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) 1610 { 1611 struct dib7000p_state *state = fe->demodulator_priv; 1612 *unc = dib7000p_read_word(state, 506); 1613 return 0; 1614 } 1615 1616 static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength) 1617 { 1618 struct dib7000p_state *state = fe->demodulator_priv; 1619 u16 val = dib7000p_read_word(state, 394); 1620 *strength = 65535 - val; 1621 return 0; 1622 } 1623 1624 static u32 dib7000p_get_snr(struct dvb_frontend *fe) 1625 { 1626 struct dib7000p_state *state = fe->demodulator_priv; 1627 u16 val; 1628 s32 signal_mant, signal_exp, noise_mant, noise_exp; 1629 u32 result = 0; 1630 1631 val = dib7000p_read_word(state, 479); 1632 noise_mant = (val >> 4) & 0xff; 1633 noise_exp = ((val & 0xf) << 2); 1634 val = dib7000p_read_word(state, 480); 1635 noise_exp += ((val >> 14) & 0x3); 1636 if ((noise_exp & 0x20) != 0) 1637 noise_exp -= 0x40; 1638 1639 signal_mant = (val >> 6) & 0xFF; 1640 signal_exp = (val & 0x3F); 1641 if ((signal_exp & 0x20) != 0) 1642 signal_exp -= 0x40; 1643 1644 if (signal_mant != 0) 1645 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant); 1646 else 1647 result = intlog10(2) * 10 * signal_exp - 100; 1648 1649 if (noise_mant != 0) 1650 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant); 1651 else 1652 result -= intlog10(2) * 10 * noise_exp - 100; 1653 1654 return result; 1655 } 1656 1657 static int dib7000p_read_snr(struct dvb_frontend *fe, u16 *snr) 1658 { 1659 u32 result; 1660 1661 result = dib7000p_get_snr(fe); 1662 1663 *snr = result / ((1 << 24) / 10); 1664 return 0; 1665 } 1666 1667 static void dib7000p_reset_stats(struct dvb_frontend *demod) 1668 { 1669 struct dib7000p_state *state = demod->demodulator_priv; 1670 struct dtv_frontend_properties *c = &demod->dtv_property_cache; 1671 u32 ucb; 1672 1673 memset(&c->strength, 0, sizeof(c->strength)); 1674 memset(&c->cnr, 0, sizeof(c->cnr)); 1675 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); 1676 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); 1677 memset(&c->block_error, 0, sizeof(c->block_error)); 1678 1679 c->strength.len = 1; 1680 c->cnr.len = 1; 1681 c->block_error.len = 1; 1682 c->block_count.len = 1; 1683 c->post_bit_error.len = 1; 1684 c->post_bit_count.len = 1; 1685 1686 c->strength.stat[0].scale = FE_SCALE_DECIBEL; 1687 c->strength.stat[0].uvalue = 0; 1688 1689 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1690 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1691 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1692 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1693 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1694 1695 dib7000p_read_unc_blocks(demod, &ucb); 1696 1697 state->old_ucb = ucb; 1698 state->ber_jiffies_stats = 0; 1699 state->per_jiffies_stats = 0; 1700 } 1701 1702 struct linear_segments { 1703 unsigned x; 1704 signed y; 1705 }; 1706 1707 /* 1708 * Table to estimate signal strength in dBm. 1709 * This table should be empirically determinated by measuring the signal 1710 * strength generated by a RF generator directly connected into 1711 * a device. 1712 * This table was determinated by measuring the signal strength generated 1713 * by a DTA-2111 RF generator directly connected into a dib7000p device 1714 * (a Hauppauge Nova-TD stick), using a good quality 3 meters length 1715 * RC6 cable and good RC6 connectors, connected directly to antenna 1. 1716 * As the minimum output power of DTA-2111 is -31dBm, a 16 dBm attenuator 1717 * were used, for the lower power values. 1718 * The real value can actually be on other devices, or even at the 1719 * second antena input, depending on several factors, like if LNA 1720 * is enabled or not, if diversity is enabled, type of connectors, etc. 1721 * Yet, it is better to use this measure in dB than a random non-linear 1722 * percentage value, especially for antenna adjustments. 1723 * On my tests, the precision of the measure using this table is about 1724 * 0.5 dB, with sounds reasonable enough to adjust antennas. 1725 */ 1726 #define DB_OFFSET 131000 1727 1728 static struct linear_segments strength_to_db_table[] = { 1729 { 63630, DB_OFFSET - 20500}, 1730 { 62273, DB_OFFSET - 21000}, 1731 { 60162, DB_OFFSET - 22000}, 1732 { 58730, DB_OFFSET - 23000}, 1733 { 58294, DB_OFFSET - 24000}, 1734 { 57778, DB_OFFSET - 25000}, 1735 { 57320, DB_OFFSET - 26000}, 1736 { 56779, DB_OFFSET - 27000}, 1737 { 56293, DB_OFFSET - 28000}, 1738 { 55724, DB_OFFSET - 29000}, 1739 { 55145, DB_OFFSET - 30000}, 1740 { 54680, DB_OFFSET - 31000}, 1741 { 54293, DB_OFFSET - 32000}, 1742 { 53813, DB_OFFSET - 33000}, 1743 { 53427, DB_OFFSET - 34000}, 1744 { 52981, DB_OFFSET - 35000}, 1745 1746 { 52636, DB_OFFSET - 36000}, 1747 { 52014, DB_OFFSET - 37000}, 1748 { 51674, DB_OFFSET - 38000}, 1749 { 50692, DB_OFFSET - 39000}, 1750 { 49824, DB_OFFSET - 40000}, 1751 { 49052, DB_OFFSET - 41000}, 1752 { 48436, DB_OFFSET - 42000}, 1753 { 47836, DB_OFFSET - 43000}, 1754 { 47368, DB_OFFSET - 44000}, 1755 { 46468, DB_OFFSET - 45000}, 1756 { 45597, DB_OFFSET - 46000}, 1757 { 44586, DB_OFFSET - 47000}, 1758 { 43667, DB_OFFSET - 48000}, 1759 { 42673, DB_OFFSET - 49000}, 1760 { 41816, DB_OFFSET - 50000}, 1761 { 40876, DB_OFFSET - 51000}, 1762 { 0, 0}, 1763 }; 1764 1765 static u32 interpolate_value(u32 value, struct linear_segments *segments, 1766 unsigned len) 1767 { 1768 u64 tmp64; 1769 u32 dx; 1770 s32 dy; 1771 int i, ret; 1772 1773 if (value >= segments[0].x) 1774 return segments[0].y; 1775 if (value < segments[len-1].x) 1776 return segments[len-1].y; 1777 1778 for (i = 1; i < len - 1; i++) { 1779 /* If value is identical, no need to interpolate */ 1780 if (value == segments[i].x) 1781 return segments[i].y; 1782 if (value > segments[i].x) 1783 break; 1784 } 1785 1786 /* Linear interpolation between the two (x,y) points */ 1787 dy = segments[i - 1].y - segments[i].y; 1788 dx = segments[i - 1].x - segments[i].x; 1789 1790 tmp64 = value - segments[i].x; 1791 tmp64 *= dy; 1792 do_div(tmp64, dx); 1793 ret = segments[i].y + tmp64; 1794 1795 return ret; 1796 } 1797 1798 /* FIXME: may require changes - this one was borrowed from dib8000 */ 1799 static u32 dib7000p_get_time_us(struct dvb_frontend *demod) 1800 { 1801 struct dtv_frontend_properties *c = &demod->dtv_property_cache; 1802 u64 time_us, tmp64; 1803 u32 tmp, denom; 1804 int guard, rate_num, rate_denum = 1, bits_per_symbol; 1805 int interleaving = 0, fft_div; 1806 1807 switch (c->guard_interval) { 1808 case GUARD_INTERVAL_1_4: 1809 guard = 4; 1810 break; 1811 case GUARD_INTERVAL_1_8: 1812 guard = 8; 1813 break; 1814 case GUARD_INTERVAL_1_16: 1815 guard = 16; 1816 break; 1817 default: 1818 case GUARD_INTERVAL_1_32: 1819 guard = 32; 1820 break; 1821 } 1822 1823 switch (c->transmission_mode) { 1824 case TRANSMISSION_MODE_2K: 1825 fft_div = 4; 1826 break; 1827 case TRANSMISSION_MODE_4K: 1828 fft_div = 2; 1829 break; 1830 default: 1831 case TRANSMISSION_MODE_8K: 1832 fft_div = 1; 1833 break; 1834 } 1835 1836 switch (c->modulation) { 1837 case DQPSK: 1838 case QPSK: 1839 bits_per_symbol = 2; 1840 break; 1841 case QAM_16: 1842 bits_per_symbol = 4; 1843 break; 1844 default: 1845 case QAM_64: 1846 bits_per_symbol = 6; 1847 break; 1848 } 1849 1850 switch ((c->hierarchy == 0 || 1 == 1) ? c->code_rate_HP : c->code_rate_LP) { 1851 case FEC_1_2: 1852 rate_num = 1; 1853 rate_denum = 2; 1854 break; 1855 case FEC_2_3: 1856 rate_num = 2; 1857 rate_denum = 3; 1858 break; 1859 case FEC_3_4: 1860 rate_num = 3; 1861 rate_denum = 4; 1862 break; 1863 case FEC_5_6: 1864 rate_num = 5; 1865 rate_denum = 6; 1866 break; 1867 default: 1868 case FEC_7_8: 1869 rate_num = 7; 1870 rate_denum = 8; 1871 break; 1872 } 1873 1874 interleaving = interleaving; 1875 1876 denom = bits_per_symbol * rate_num * fft_div * 384; 1877 1878 /* If calculus gets wrong, wait for 1s for the next stats */ 1879 if (!denom) 1880 return 0; 1881 1882 /* Estimate the period for the total bit rate */ 1883 time_us = rate_denum * (1008 * 1562500L); 1884 tmp64 = time_us; 1885 do_div(tmp64, guard); 1886 time_us = time_us + tmp64; 1887 time_us += denom / 2; 1888 do_div(time_us, denom); 1889 1890 tmp = 1008 * 96 * interleaving; 1891 time_us += tmp + tmp / guard; 1892 1893 return time_us; 1894 } 1895 1896 static int dib7000p_get_stats(struct dvb_frontend *demod, enum fe_status stat) 1897 { 1898 struct dib7000p_state *state = demod->demodulator_priv; 1899 struct dtv_frontend_properties *c = &demod->dtv_property_cache; 1900 int show_per_stats = 0; 1901 u32 time_us = 0, val, snr; 1902 u64 blocks, ucb; 1903 s32 db; 1904 u16 strength; 1905 1906 /* Get Signal strength */ 1907 dib7000p_read_signal_strength(demod, &strength); 1908 val = strength; 1909 db = interpolate_value(val, 1910 strength_to_db_table, 1911 ARRAY_SIZE(strength_to_db_table)) - DB_OFFSET; 1912 c->strength.stat[0].svalue = db; 1913 1914 /* UCB/BER/CNR measures require lock */ 1915 if (!(stat & FE_HAS_LOCK)) { 1916 c->cnr.len = 1; 1917 c->block_count.len = 1; 1918 c->block_error.len = 1; 1919 c->post_bit_error.len = 1; 1920 c->post_bit_count.len = 1; 1921 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1922 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1923 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1924 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1925 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1926 return 0; 1927 } 1928 1929 /* Check if time for stats was elapsed */ 1930 if (time_after(jiffies, state->per_jiffies_stats)) { 1931 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000); 1932 1933 /* Get SNR */ 1934 snr = dib7000p_get_snr(demod); 1935 if (snr) 1936 snr = (1000L * snr) >> 24; 1937 else 1938 snr = 0; 1939 c->cnr.stat[0].svalue = snr; 1940 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 1941 1942 /* Get UCB measures */ 1943 dib7000p_read_unc_blocks(demod, &val); 1944 ucb = val - state->old_ucb; 1945 if (val < state->old_ucb) 1946 ucb += 0x100000000LL; 1947 1948 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1949 c->block_error.stat[0].uvalue = ucb; 1950 1951 /* Estimate the number of packets based on bitrate */ 1952 if (!time_us) 1953 time_us = dib7000p_get_time_us(demod); 1954 1955 if (time_us) { 1956 blocks = 1250000ULL * 1000000ULL; 1957 do_div(blocks, time_us * 8 * 204); 1958 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1959 c->block_count.stat[0].uvalue += blocks; 1960 } 1961 1962 show_per_stats = 1; 1963 } 1964 1965 /* Get post-BER measures */ 1966 if (time_after(jiffies, state->ber_jiffies_stats)) { 1967 time_us = dib7000p_get_time_us(demod); 1968 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000); 1969 1970 dprintk("Next all layers stats available in %u us.\n", time_us); 1971 1972 dib7000p_read_ber(demod, &val); 1973 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 1974 c->post_bit_error.stat[0].uvalue += val; 1975 1976 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 1977 c->post_bit_count.stat[0].uvalue += 100000000; 1978 } 1979 1980 /* Get PER measures */ 1981 if (show_per_stats) { 1982 dib7000p_read_unc_blocks(demod, &val); 1983 1984 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 1985 c->block_error.stat[0].uvalue += val; 1986 1987 time_us = dib7000p_get_time_us(demod); 1988 if (time_us) { 1989 blocks = 1250000ULL * 1000000ULL; 1990 do_div(blocks, time_us * 8 * 204); 1991 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 1992 c->block_count.stat[0].uvalue += blocks; 1993 } 1994 } 1995 return 0; 1996 } 1997 1998 static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune) 1999 { 2000 tune->min_delay_ms = 1000; 2001 return 0; 2002 } 2003 2004 static void dib7000p_release(struct dvb_frontend *demod) 2005 { 2006 struct dib7000p_state *st = demod->demodulator_priv; 2007 dibx000_exit_i2c_master(&st->i2c_master); 2008 i2c_del_adapter(&st->dib7090_tuner_adap); 2009 kfree(st); 2010 } 2011 2012 static int dib7000pc_detection(struct i2c_adapter *i2c_adap) 2013 { 2014 u8 *tx, *rx; 2015 struct i2c_msg msg[2] = { 2016 {.addr = 18 >> 1, .flags = 0, .len = 2}, 2017 {.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2}, 2018 }; 2019 int ret = 0; 2020 2021 tx = kzalloc(2*sizeof(u8), GFP_KERNEL); 2022 if (!tx) 2023 return -ENOMEM; 2024 rx = kzalloc(2*sizeof(u8), GFP_KERNEL); 2025 if (!rx) { 2026 ret = -ENOMEM; 2027 goto rx_memory_error; 2028 } 2029 2030 msg[0].buf = tx; 2031 msg[1].buf = rx; 2032 2033 tx[0] = 0x03; 2034 tx[1] = 0x00; 2035 2036 if (i2c_transfer(i2c_adap, msg, 2) == 2) 2037 if (rx[0] == 0x01 && rx[1] == 0xb3) { 2038 dprintk("-D- DiB7000PC detected\n"); 2039 return 1; 2040 } 2041 2042 msg[0].addr = msg[1].addr = 0x40; 2043 2044 if (i2c_transfer(i2c_adap, msg, 2) == 2) 2045 if (rx[0] == 0x01 && rx[1] == 0xb3) { 2046 dprintk("-D- DiB7000PC detected\n"); 2047 return 1; 2048 } 2049 2050 dprintk("-D- DiB7000PC not detected\n"); 2051 2052 kfree(rx); 2053 rx_memory_error: 2054 kfree(tx); 2055 return ret; 2056 } 2057 2058 static struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating) 2059 { 2060 struct dib7000p_state *st = demod->demodulator_priv; 2061 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); 2062 } 2063 2064 static int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff) 2065 { 2066 struct dib7000p_state *state = fe->demodulator_priv; 2067 u16 val = dib7000p_read_word(state, 235) & 0xffef; 2068 val |= (onoff & 0x1) << 4; 2069 dprintk("PID filter enabled %d\n", onoff); 2070 return dib7000p_write_word(state, 235, val); 2071 } 2072 2073 static int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff) 2074 { 2075 struct dib7000p_state *state = fe->demodulator_priv; 2076 dprintk("PID filter: index %x, PID %d, OnOff %d\n", id, pid, onoff); 2077 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0); 2078 } 2079 2080 static int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]) 2081 { 2082 struct dib7000p_state *dpst; 2083 int k = 0; 2084 u8 new_addr = 0; 2085 2086 dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL); 2087 if (!dpst) 2088 return -ENOMEM; 2089 2090 dpst->i2c_adap = i2c; 2091 mutex_init(&dpst->i2c_buffer_lock); 2092 2093 for (k = no_of_demods - 1; k >= 0; k--) { 2094 dpst->cfg = cfg[k]; 2095 2096 /* designated i2c address */ 2097 if (cfg[k].default_i2c_addr != 0) 2098 new_addr = cfg[k].default_i2c_addr + (k << 1); 2099 else 2100 new_addr = (0x40 + k) << 1; 2101 dpst->i2c_addr = new_addr; 2102 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ 2103 if (dib7000p_identify(dpst) != 0) { 2104 dpst->i2c_addr = default_addr; 2105 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ 2106 if (dib7000p_identify(dpst) != 0) { 2107 dprintk("DiB7000P #%d: not identified\n", k); 2108 kfree(dpst); 2109 return -EIO; 2110 } 2111 } 2112 2113 /* start diversity to pull_down div_str - just for i2c-enumeration */ 2114 dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY); 2115 2116 /* set new i2c address and force divstart */ 2117 dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2); 2118 2119 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); 2120 } 2121 2122 for (k = 0; k < no_of_demods; k++) { 2123 dpst->cfg = cfg[k]; 2124 if (cfg[k].default_i2c_addr != 0) 2125 dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1; 2126 else 2127 dpst->i2c_addr = (0x40 + k) << 1; 2128 2129 // unforce divstr 2130 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2); 2131 2132 /* deactivate div - it was just for i2c-enumeration */ 2133 dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z); 2134 } 2135 2136 kfree(dpst); 2137 return 0; 2138 } 2139 2140 static const s32 lut_1000ln_mant[] = { 2141 6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600 2142 }; 2143 2144 static s32 dib7000p_get_adc_power(struct dvb_frontend *fe) 2145 { 2146 struct dib7000p_state *state = fe->demodulator_priv; 2147 u32 tmp_val = 0, exp = 0, mant = 0; 2148 s32 pow_i; 2149 u16 buf[2]; 2150 u8 ix = 0; 2151 2152 buf[0] = dib7000p_read_word(state, 0x184); 2153 buf[1] = dib7000p_read_word(state, 0x185); 2154 pow_i = (buf[0] << 16) | buf[1]; 2155 dprintk("raw pow_i = %d\n", pow_i); 2156 2157 tmp_val = pow_i; 2158 while (tmp_val >>= 1) 2159 exp++; 2160 2161 mant = (pow_i * 1000 / (1 << exp)); 2162 dprintk(" mant = %d exp = %d\n", mant / 1000, exp); 2163 2164 ix = (u8) ((mant - 1000) / 100); /* index of the LUT */ 2165 dprintk(" ix = %d\n", ix); 2166 2167 pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908); 2168 pow_i = (pow_i << 8) / 1000; 2169 dprintk(" pow_i = %d\n", pow_i); 2170 2171 return pow_i; 2172 } 2173 2174 static int map_addr_to_serpar_number(struct i2c_msg *msg) 2175 { 2176 if ((msg->buf[0] <= 15)) 2177 msg->buf[0] -= 1; 2178 else if (msg->buf[0] == 17) 2179 msg->buf[0] = 15; 2180 else if (msg->buf[0] == 16) 2181 msg->buf[0] = 17; 2182 else if (msg->buf[0] == 19) 2183 msg->buf[0] = 16; 2184 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25) 2185 msg->buf[0] -= 3; 2186 else if (msg->buf[0] == 28) 2187 msg->buf[0] = 23; 2188 else 2189 return -EINVAL; 2190 return 0; 2191 } 2192 2193 static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) 2194 { 2195 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); 2196 u8 n_overflow = 1; 2197 u16 i = 1000; 2198 u16 serpar_num = msg[0].buf[0]; 2199 2200 while (n_overflow == 1 && i) { 2201 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1; 2202 i--; 2203 if (i == 0) 2204 dprintk("Tuner ITF: write busy (overflow)\n"); 2205 } 2206 dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); 2207 dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); 2208 2209 return num; 2210 } 2211 2212 static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) 2213 { 2214 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); 2215 u8 n_overflow = 1, n_empty = 1; 2216 u16 i = 1000; 2217 u16 serpar_num = msg[0].buf[0]; 2218 u16 read_word; 2219 2220 while (n_overflow == 1 && i) { 2221 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1; 2222 i--; 2223 if (i == 0) 2224 dprintk("TunerITF: read busy (overflow)\n"); 2225 } 2226 dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f)); 2227 2228 i = 1000; 2229 while (n_empty == 1 && i) { 2230 n_empty = dib7000p_read_word(state, 1984) & 0x1; 2231 i--; 2232 if (i == 0) 2233 dprintk("TunerITF: read busy (empty)\n"); 2234 } 2235 read_word = dib7000p_read_word(state, 1987); 2236 msg[1].buf[0] = (read_word >> 8) & 0xff; 2237 msg[1].buf[1] = (read_word) & 0xff; 2238 2239 return num; 2240 } 2241 2242 static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) 2243 { 2244 if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */ 2245 if (num == 1) { /* write */ 2246 return w7090p_tuner_write_serpar(i2c_adap, msg, 1); 2247 } else { /* read */ 2248 return w7090p_tuner_read_serpar(i2c_adap, msg, 2); 2249 } 2250 } 2251 return num; 2252 } 2253 2254 static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, 2255 struct i2c_msg msg[], int num, u16 apb_address) 2256 { 2257 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); 2258 u16 word; 2259 2260 if (num == 1) { /* write */ 2261 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2]))); 2262 } else { 2263 word = dib7000p_read_word(state, apb_address); 2264 msg[1].buf[0] = (word >> 8) & 0xff; 2265 msg[1].buf[1] = (word) & 0xff; 2266 } 2267 2268 return num; 2269 } 2270 2271 static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) 2272 { 2273 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); 2274 2275 u16 apb_address = 0, word; 2276 int i = 0; 2277 switch (msg[0].buf[0]) { 2278 case 0x12: 2279 apb_address = 1920; 2280 break; 2281 case 0x14: 2282 apb_address = 1921; 2283 break; 2284 case 0x24: 2285 apb_address = 1922; 2286 break; 2287 case 0x1a: 2288 apb_address = 1923; 2289 break; 2290 case 0x22: 2291 apb_address = 1924; 2292 break; 2293 case 0x33: 2294 apb_address = 1926; 2295 break; 2296 case 0x34: 2297 apb_address = 1927; 2298 break; 2299 case 0x35: 2300 apb_address = 1928; 2301 break; 2302 case 0x36: 2303 apb_address = 1929; 2304 break; 2305 case 0x37: 2306 apb_address = 1930; 2307 break; 2308 case 0x38: 2309 apb_address = 1931; 2310 break; 2311 case 0x39: 2312 apb_address = 1932; 2313 break; 2314 case 0x2a: 2315 apb_address = 1935; 2316 break; 2317 case 0x2b: 2318 apb_address = 1936; 2319 break; 2320 case 0x2c: 2321 apb_address = 1937; 2322 break; 2323 case 0x2d: 2324 apb_address = 1938; 2325 break; 2326 case 0x2e: 2327 apb_address = 1939; 2328 break; 2329 case 0x2f: 2330 apb_address = 1940; 2331 break; 2332 case 0x30: 2333 apb_address = 1941; 2334 break; 2335 case 0x31: 2336 apb_address = 1942; 2337 break; 2338 case 0x32: 2339 apb_address = 1943; 2340 break; 2341 case 0x3e: 2342 apb_address = 1944; 2343 break; 2344 case 0x3f: 2345 apb_address = 1945; 2346 break; 2347 case 0x40: 2348 apb_address = 1948; 2349 break; 2350 case 0x25: 2351 apb_address = 914; 2352 break; 2353 case 0x26: 2354 apb_address = 915; 2355 break; 2356 case 0x27: 2357 apb_address = 917; 2358 break; 2359 case 0x28: 2360 apb_address = 916; 2361 break; 2362 case 0x1d: 2363 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3); 2364 word = dib7000p_read_word(state, 384 + i); 2365 msg[1].buf[0] = (word >> 8) & 0xff; 2366 msg[1].buf[1] = (word) & 0xff; 2367 return num; 2368 case 0x1f: 2369 if (num == 1) { /* write */ 2370 word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]); 2371 word &= 0x3; 2372 word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12); 2373 dib7000p_write_word(state, 72, word); /* Set the proper input */ 2374 return num; 2375 } 2376 } 2377 2378 if (apb_address != 0) /* R/W acces via APB */ 2379 return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address); 2380 else /* R/W access via SERPAR */ 2381 return w7090p_tuner_rw_serpar(i2c_adap, msg, num); 2382 2383 return 0; 2384 } 2385 2386 static u32 dib7000p_i2c_func(struct i2c_adapter *adapter) 2387 { 2388 return I2C_FUNC_I2C; 2389 } 2390 2391 static struct i2c_algorithm dib7090_tuner_xfer_algo = { 2392 .master_xfer = dib7090_tuner_xfer, 2393 .functionality = dib7000p_i2c_func, 2394 }; 2395 2396 static struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe) 2397 { 2398 struct dib7000p_state *st = fe->demodulator_priv; 2399 return &st->dib7090_tuner_adap; 2400 } 2401 2402 static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive) 2403 { 2404 u16 reg; 2405 2406 /* drive host bus 2, 3, 4 */ 2407 reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); 2408 reg |= (drive << 12) | (drive << 6) | drive; 2409 dib7000p_write_word(state, 1798, reg); 2410 2411 /* drive host bus 5,6 */ 2412 reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); 2413 reg |= (drive << 8) | (drive << 2); 2414 dib7000p_write_word(state, 1799, reg); 2415 2416 /* drive host bus 7, 8, 9 */ 2417 reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); 2418 reg |= (drive << 12) | (drive << 6) | drive; 2419 dib7000p_write_word(state, 1800, reg); 2420 2421 /* drive host bus 10, 11 */ 2422 reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); 2423 reg |= (drive << 8) | (drive << 2); 2424 dib7000p_write_word(state, 1801, reg); 2425 2426 /* drive host bus 12, 13, 14 */ 2427 reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); 2428 reg |= (drive << 12) | (drive << 6) | drive; 2429 dib7000p_write_word(state, 1802, reg); 2430 2431 return 0; 2432 } 2433 2434 static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize) 2435 { 2436 u32 quantif = 3; 2437 u32 nom = (insertExtSynchro * P_Kin + syncSize); 2438 u32 denom = P_Kout; 2439 u32 syncFreq = ((nom << quantif) / denom); 2440 2441 if ((syncFreq & ((1 << quantif) - 1)) != 0) 2442 syncFreq = (syncFreq >> quantif) + 1; 2443 else 2444 syncFreq = (syncFreq >> quantif); 2445 2446 if (syncFreq != 0) 2447 syncFreq = syncFreq - 1; 2448 2449 return syncFreq; 2450 } 2451 2452 static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize) 2453 { 2454 dprintk("Configure DibStream Tx\n"); 2455 2456 dib7000p_write_word(state, 1615, 1); 2457 dib7000p_write_word(state, 1603, P_Kin); 2458 dib7000p_write_word(state, 1605, P_Kout); 2459 dib7000p_write_word(state, 1606, insertExtSynchro); 2460 dib7000p_write_word(state, 1608, synchroMode); 2461 dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff); 2462 dib7000p_write_word(state, 1610, syncWord & 0xffff); 2463 dib7000p_write_word(state, 1612, syncSize); 2464 dib7000p_write_word(state, 1615, 0); 2465 2466 return 0; 2467 } 2468 2469 static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize, 2470 u32 dataOutRate) 2471 { 2472 u32 syncFreq; 2473 2474 dprintk("Configure DibStream Rx\n"); 2475 if ((P_Kin != 0) && (P_Kout != 0)) { 2476 syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize); 2477 dib7000p_write_word(state, 1542, syncFreq); 2478 } 2479 dib7000p_write_word(state, 1554, 1); 2480 dib7000p_write_word(state, 1536, P_Kin); 2481 dib7000p_write_word(state, 1537, P_Kout); 2482 dib7000p_write_word(state, 1539, synchroMode); 2483 dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff); 2484 dib7000p_write_word(state, 1541, syncWord & 0xffff); 2485 dib7000p_write_word(state, 1543, syncSize); 2486 dib7000p_write_word(state, 1544, dataOutRate); 2487 dib7000p_write_word(state, 1554, 0); 2488 2489 return 0; 2490 } 2491 2492 static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff) 2493 { 2494 u16 reg_1287 = dib7000p_read_word(state, 1287); 2495 2496 switch (onoff) { 2497 case 1: 2498 reg_1287 &= ~(1<<7); 2499 break; 2500 case 0: 2501 reg_1287 |= (1<<7); 2502 break; 2503 } 2504 2505 dib7000p_write_word(state, 1287, reg_1287); 2506 } 2507 2508 static void dib7090_configMpegMux(struct dib7000p_state *state, 2509 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2) 2510 { 2511 dprintk("Enable Mpeg mux\n"); 2512 2513 dib7090_enMpegMux(state, 0); 2514 2515 /* If the input mode is MPEG do not divide the serial clock */ 2516 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1)) 2517 enSerialClkDiv2 = 0; 2518 2519 dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2) 2520 | ((enSerialMode & 0x1) << 1) 2521 | (enSerialClkDiv2 & 0x1)); 2522 2523 dib7090_enMpegMux(state, 1); 2524 } 2525 2526 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode) 2527 { 2528 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7); 2529 2530 switch (mode) { 2531 case MPEG_ON_DIBTX: 2532 dprintk("SET MPEG ON DIBSTREAM TX\n"); 2533 dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); 2534 reg_1288 |= (1<<9); 2535 break; 2536 case DIV_ON_DIBTX: 2537 dprintk("SET DIV_OUT ON DIBSTREAM TX\n"); 2538 dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); 2539 reg_1288 |= (1<<8); 2540 break; 2541 case ADC_ON_DIBTX: 2542 dprintk("SET ADC_OUT ON DIBSTREAM TX\n"); 2543 dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); 2544 reg_1288 |= (1<<7); 2545 break; 2546 default: 2547 break; 2548 } 2549 dib7000p_write_word(state, 1288, reg_1288); 2550 } 2551 2552 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode) 2553 { 2554 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4); 2555 2556 switch (mode) { 2557 case DEMOUT_ON_HOSTBUS: 2558 dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n"); 2559 dib7090_enMpegMux(state, 0); 2560 reg_1288 |= (1<<6); 2561 break; 2562 case DIBTX_ON_HOSTBUS: 2563 dprintk("SET DIBSTREAM TX ON HOST BUS\n"); 2564 dib7090_enMpegMux(state, 0); 2565 reg_1288 |= (1<<5); 2566 break; 2567 case MPEG_ON_HOSTBUS: 2568 dprintk("SET MPEG MUX ON HOST BUS\n"); 2569 reg_1288 |= (1<<4); 2570 break; 2571 default: 2572 break; 2573 } 2574 dib7000p_write_word(state, 1288, reg_1288); 2575 } 2576 2577 static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff) 2578 { 2579 struct dib7000p_state *state = fe->demodulator_priv; 2580 u16 reg_1287; 2581 2582 switch (onoff) { 2583 case 0: /* only use the internal way - not the diversity input */ 2584 dprintk("%s mode OFF : by default Enable Mpeg INPUT\n", __func__); 2585 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); 2586 2587 /* Do not divide the serial clock of MPEG MUX */ 2588 /* in SERIAL MODE in case input mode MPEG is used */ 2589 reg_1287 = dib7000p_read_word(state, 1287); 2590 /* enSerialClkDiv2 == 1 ? */ 2591 if ((reg_1287 & 0x1) == 1) { 2592 /* force enSerialClkDiv2 = 0 */ 2593 reg_1287 &= ~0x1; 2594 dib7000p_write_word(state, 1287, reg_1287); 2595 } 2596 state->input_mode_mpeg = 1; 2597 break; 2598 case 1: /* both ways */ 2599 case 2: /* only the diversity input */ 2600 dprintk("%s ON : Enable diversity INPUT\n", __func__); 2601 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); 2602 state->input_mode_mpeg = 0; 2603 break; 2604 } 2605 2606 dib7000p_set_diversity_in(&state->demod, onoff); 2607 return 0; 2608 } 2609 2610 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode) 2611 { 2612 struct dib7000p_state *state = fe->demodulator_priv; 2613 2614 u16 outreg, smo_mode, fifo_threshold; 2615 u8 prefer_mpeg_mux_use = 1; 2616 int ret = 0; 2617 2618 dib7090_host_bus_drive(state, 1); 2619 2620 fifo_threshold = 1792; 2621 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); 2622 outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1)); 2623 2624 switch (mode) { 2625 case OUTMODE_HIGH_Z: 2626 outreg = 0; 2627 break; 2628 2629 case OUTMODE_MPEG2_SERIAL: 2630 if (prefer_mpeg_mux_use) { 2631 dprintk("setting output mode TS_SERIAL using Mpeg Mux\n"); 2632 dib7090_configMpegMux(state, 3, 1, 1); 2633 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS); 2634 } else {/* Use Smooth block */ 2635 dprintk("setting output mode TS_SERIAL using Smooth bloc\n"); 2636 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); 2637 outreg |= (2<<6) | (0 << 1); 2638 } 2639 break; 2640 2641 case OUTMODE_MPEG2_PAR_GATED_CLK: 2642 if (prefer_mpeg_mux_use) { 2643 dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux\n"); 2644 dib7090_configMpegMux(state, 2, 0, 0); 2645 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS); 2646 } else { /* Use Smooth block */ 2647 dprintk("setting output mode TS_PARALLEL_GATED using Smooth block\n"); 2648 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); 2649 outreg |= (0<<6); 2650 } 2651 break; 2652 2653 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */ 2654 dprintk("setting output mode TS_PARALLEL_CONT using Smooth block\n"); 2655 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); 2656 outreg |= (1<<6); 2657 break; 2658 2659 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */ 2660 dprintk("setting output mode TS_FIFO using Smooth block\n"); 2661 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); 2662 outreg |= (5<<6); 2663 smo_mode |= (3 << 1); 2664 fifo_threshold = 512; 2665 break; 2666 2667 case OUTMODE_DIVERSITY: 2668 dprintk("setting output mode MODE_DIVERSITY\n"); 2669 dib7090_setDibTxMux(state, DIV_ON_DIBTX); 2670 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS); 2671 break; 2672 2673 case OUTMODE_ANALOG_ADC: 2674 dprintk("setting output mode MODE_ANALOG_ADC\n"); 2675 dib7090_setDibTxMux(state, ADC_ON_DIBTX); 2676 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS); 2677 break; 2678 } 2679 if (mode != OUTMODE_HIGH_Z) 2680 outreg |= (1 << 10); 2681 2682 if (state->cfg.output_mpeg2_in_188_bytes) 2683 smo_mode |= (1 << 5); 2684 2685 ret |= dib7000p_write_word(state, 235, smo_mode); 2686 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ 2687 ret |= dib7000p_write_word(state, 1286, outreg); 2688 2689 return ret; 2690 } 2691 2692 static int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff) 2693 { 2694 struct dib7000p_state *state = fe->demodulator_priv; 2695 u16 en_cur_state; 2696 2697 dprintk("sleep dib7090: %d\n", onoff); 2698 2699 en_cur_state = dib7000p_read_word(state, 1922); 2700 2701 if (en_cur_state > 0xff) 2702 state->tuner_enable = en_cur_state; 2703 2704 if (onoff) 2705 en_cur_state &= 0x00ff; 2706 else { 2707 if (state->tuner_enable != 0) 2708 en_cur_state = state->tuner_enable; 2709 } 2710 2711 dib7000p_write_word(state, 1922, en_cur_state); 2712 2713 return 0; 2714 } 2715 2716 static int dib7090_get_adc_power(struct dvb_frontend *fe) 2717 { 2718 return dib7000p_get_adc_power(fe); 2719 } 2720 2721 static int dib7090_slave_reset(struct dvb_frontend *fe) 2722 { 2723 struct dib7000p_state *state = fe->demodulator_priv; 2724 u16 reg; 2725 2726 reg = dib7000p_read_word(state, 1794); 2727 dib7000p_write_word(state, 1794, reg | (4 << 12)); 2728 2729 dib7000p_write_word(state, 1032, 0xffff); 2730 return 0; 2731 } 2732 2733 static const struct dvb_frontend_ops dib7000p_ops; 2734 static struct dvb_frontend *dib7000p_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg) 2735 { 2736 struct dvb_frontend *demod; 2737 struct dib7000p_state *st; 2738 st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL); 2739 if (st == NULL) 2740 return NULL; 2741 2742 memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config)); 2743 st->i2c_adap = i2c_adap; 2744 st->i2c_addr = i2c_addr; 2745 st->gpio_val = cfg->gpio_val; 2746 st->gpio_dir = cfg->gpio_dir; 2747 2748 /* Ensure the output mode remains at the previous default if it's 2749 * not specifically set by the caller. 2750 */ 2751 if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) 2752 st->cfg.output_mode = OUTMODE_MPEG2_FIFO; 2753 2754 demod = &st->demod; 2755 demod->demodulator_priv = st; 2756 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops)); 2757 mutex_init(&st->i2c_buffer_lock); 2758 2759 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */ 2760 2761 if (dib7000p_identify(st) != 0) 2762 goto error; 2763 2764 st->version = dib7000p_read_word(st, 897); 2765 2766 /* FIXME: make sure the dev.parent field is initialized, or else 2767 request_firmware() will hit an OOPS (this should be moved somewhere 2768 more common) */ 2769 st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent; 2770 2771 dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr); 2772 2773 /* init 7090 tuner adapter */ 2774 strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name)); 2775 st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo; 2776 st->dib7090_tuner_adap.algo_data = NULL; 2777 st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent; 2778 i2c_set_adapdata(&st->dib7090_tuner_adap, st); 2779 i2c_add_adapter(&st->dib7090_tuner_adap); 2780 2781 dib7000p_demod_reset(st); 2782 2783 dib7000p_reset_stats(demod); 2784 2785 if (st->version == SOC7090) { 2786 dib7090_set_output_mode(demod, st->cfg.output_mode); 2787 dib7090_set_diversity_in(demod, 0); 2788 } 2789 2790 return demod; 2791 2792 error: 2793 kfree(st); 2794 return NULL; 2795 } 2796 2797 void *dib7000p_attach(struct dib7000p_ops *ops) 2798 { 2799 if (!ops) 2800 return NULL; 2801 2802 ops->slave_reset = dib7090_slave_reset; 2803 ops->get_adc_power = dib7090_get_adc_power; 2804 ops->dib7000pc_detection = dib7000pc_detection; 2805 ops->get_i2c_tuner = dib7090_get_i2c_tuner; 2806 ops->tuner_sleep = dib7090_tuner_sleep; 2807 ops->init = dib7000p_init; 2808 ops->set_agc1_min = dib7000p_set_agc1_min; 2809 ops->set_gpio = dib7000p_set_gpio; 2810 ops->i2c_enumeration = dib7000p_i2c_enumeration; 2811 ops->pid_filter = dib7000p_pid_filter; 2812 ops->pid_filter_ctrl = dib7000p_pid_filter_ctrl; 2813 ops->get_i2c_master = dib7000p_get_i2c_master; 2814 ops->update_pll = dib7000p_update_pll; 2815 ops->ctrl_timf = dib7000p_ctrl_timf; 2816 ops->get_agc_values = dib7000p_get_agc_values; 2817 ops->set_wbd_ref = dib7000p_set_wbd_ref; 2818 2819 return ops; 2820 } 2821 EXPORT_SYMBOL(dib7000p_attach); 2822 2823 static const struct dvb_frontend_ops dib7000p_ops = { 2824 .delsys = { SYS_DVBT }, 2825 .info = { 2826 .name = "DiBcom 7000PC", 2827 .frequency_min = 44250000, 2828 .frequency_max = 867250000, 2829 .frequency_stepsize = 62500, 2830 .caps = FE_CAN_INVERSION_AUTO | 2831 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 2832 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 2833 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 2834 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO, 2835 }, 2836 2837 .release = dib7000p_release, 2838 2839 .init = dib7000p_wakeup, 2840 .sleep = dib7000p_sleep, 2841 2842 .set_frontend = dib7000p_set_frontend, 2843 .get_tune_settings = dib7000p_fe_get_tune_settings, 2844 .get_frontend = dib7000p_get_frontend, 2845 2846 .read_status = dib7000p_read_status, 2847 .read_ber = dib7000p_read_ber, 2848 .read_signal_strength = dib7000p_read_signal_strength, 2849 .read_snr = dib7000p_read_snr, 2850 .read_ucblocks = dib7000p_read_unc_blocks, 2851 }; 2852 2853 MODULE_AUTHOR("Olivier Grenie <olivie.grenie@parrot.com>"); 2854 MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>"); 2855 MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator"); 2856 MODULE_LICENSE("GPL"); 2857