1 /* 2 * Driver for DiBcom DiB3000MC/P-demodulator. 3 * 4 * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/) 5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de) 6 * 7 * This code is partially based on the previous dib3000mc.c . 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation, version 2. 12 */ 13 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/i2c.h> 19 20 #include "dvb_frontend.h" 21 22 #include "dib3000mc.h" 23 24 static int debug; 25 module_param(debug, int, 0644); 26 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); 27 28 static int buggy_sfn_workaround; 29 module_param(buggy_sfn_workaround, int, 0644); 30 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)"); 31 32 #define dprintk(fmt, arg...) do { \ 33 if (debug) \ 34 printk(KERN_DEBUG pr_fmt("%s: " fmt), \ 35 __func__, ##arg); \ 36 } while (0) 37 38 struct dib3000mc_state { 39 struct dvb_frontend demod; 40 struct dib3000mc_config *cfg; 41 42 u8 i2c_addr; 43 struct i2c_adapter *i2c_adap; 44 45 struct dibx000_i2c_master i2c_master; 46 47 u32 timf; 48 49 u32 current_bandwidth; 50 51 u16 dev_id; 52 53 u8 sfn_workaround_active :1; 54 }; 55 56 static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg) 57 { 58 u8 wb[2] = { (reg >> 8) | 0x80, reg & 0xff }; 59 u8 rb[2]; 60 struct i2c_msg msg[2] = { 61 { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 }, 62 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 }, 63 }; 64 65 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) 66 dprintk("i2c read error on %d\n",reg); 67 68 return (rb[0] << 8) | rb[1]; 69 } 70 71 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) 72 { 73 u8 b[4] = { 74 (reg >> 8) & 0xff, reg & 0xff, 75 (val >> 8) & 0xff, val & 0xff, 76 }; 77 struct i2c_msg msg = { 78 .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4 79 }; 80 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 81 } 82 83 static int dib3000mc_identify(struct dib3000mc_state *state) 84 { 85 u16 value; 86 if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) { 87 dprintk("-E- DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value); 88 return -EREMOTEIO; 89 } 90 91 value = dib3000mc_read_word(state, 1026); 92 if (value != 0x3001 && value != 0x3002) { 93 dprintk("-E- DiB3000MC/P: wrong Device ID (%x)\n",value); 94 return -EREMOTEIO; 95 } 96 state->dev_id = value; 97 98 dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id); 99 100 return 0; 101 } 102 103 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset) 104 { 105 u32 timf; 106 107 if (state->timf == 0) { 108 timf = 1384402; // default value for 8MHz 109 if (update_offset) 110 msleep(200); // first time we do an update 111 } else 112 timf = state->timf; 113 114 timf *= (bw / 1000); 115 116 if (update_offset) { 117 s16 tim_offs = dib3000mc_read_word(state, 416); 118 119 if (tim_offs & 0x2000) 120 tim_offs -= 0x4000; 121 122 if (nfft == TRANSMISSION_MODE_2K) 123 tim_offs *= 4; 124 125 timf += tim_offs; 126 state->timf = timf / (bw / 1000); 127 } 128 129 dprintk("timf: %d\n", timf); 130 131 dib3000mc_write_word(state, 23, (u16) (timf >> 16)); 132 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff); 133 134 return 0; 135 } 136 137 static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state) 138 { 139 u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb; 140 if (state->cfg->pwm3_inversion) { 141 reg_51 = (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0); 142 reg_52 |= (1 << 2); 143 } else { 144 reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0); 145 reg_52 |= (1 << 8); 146 } 147 dib3000mc_write_word(state, 51, reg_51); 148 dib3000mc_write_word(state, 52, reg_52); 149 150 if (state->cfg->use_pwm3) 151 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0)); 152 else 153 dib3000mc_write_word(state, 245, 0); 154 155 dib3000mc_write_word(state, 1040, 0x3); 156 return 0; 157 } 158 159 static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode) 160 { 161 int ret = 0; 162 u16 fifo_threshold = 1792; 163 u16 outreg = 0; 164 u16 outmode = 0; 165 u16 elecout = 1; 166 u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */ 167 168 dprintk("-I- Setting output mode for demod %p to %d\n", 169 &state->demod, mode); 170 171 switch (mode) { 172 case OUTMODE_HIGH_Z: // disable 173 elecout = 0; 174 break; 175 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock 176 outmode = 0; 177 break; 178 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock 179 outmode = 1; 180 break; 181 case OUTMODE_MPEG2_SERIAL: // STBs with serial input 182 outmode = 2; 183 break; 184 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding 185 elecout = 3; 186 /*ADDR @ 206 : 187 P_smo_error_discard [1;6:6] = 0 188 P_smo_rs_discard [1;5:5] = 0 189 P_smo_pid_parse [1;4:4] = 0 190 P_smo_fifo_flush [1;3:3] = 0 191 P_smo_mode [2;2:1] = 11 192 P_smo_ovf_prot [1;0:0] = 0 193 */ 194 smo_reg |= 3 << 1; 195 fifo_threshold = 512; 196 outmode = 5; 197 break; 198 case OUTMODE_DIVERSITY: 199 outmode = 4; 200 elecout = 1; 201 break; 202 default: 203 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod); 204 outmode = 0; 205 break; 206 } 207 208 if ((state->cfg->output_mpeg2_in_188_bytes)) 209 smo_reg |= (1 << 5); // P_smo_rs_discard [1;5:5] = 1 210 211 outreg = dib3000mc_read_word(state, 244) & 0x07FF; 212 outreg |= (outmode << 11); 213 ret |= dib3000mc_write_word(state, 244, outreg); 214 ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/ 215 ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */ 216 ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */ 217 return ret; 218 } 219 220 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw) 221 { 222 u16 bw_cfg[6] = { 0 }; 223 u16 imp_bw_cfg[3] = { 0 }; 224 u16 reg; 225 226 /* settings here are for 27.7MHz */ 227 switch (bw) { 228 case 8000: 229 bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20; 230 imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7; 231 break; 232 233 case 7000: 234 bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7; 235 imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0; 236 break; 237 238 case 6000: 239 bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5; 240 imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089; 241 break; 242 243 case 5000: 244 bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500; 245 imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072; 246 break; 247 248 default: return -EINVAL; 249 } 250 251 for (reg = 6; reg < 12; reg++) 252 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]); 253 dib3000mc_write_word(state, 12, 0x0000); 254 dib3000mc_write_word(state, 13, 0x03e8); 255 dib3000mc_write_word(state, 14, 0x0000); 256 dib3000mc_write_word(state, 15, 0x03f2); 257 dib3000mc_write_word(state, 16, 0x0001); 258 dib3000mc_write_word(state, 17, 0xb0d0); 259 // P_sec_len 260 dib3000mc_write_word(state, 18, 0x0393); 261 dib3000mc_write_word(state, 19, 0x8700); 262 263 for (reg = 55; reg < 58; reg++) 264 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]); 265 266 // Timing configuration 267 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0); 268 269 return 0; 270 } 271 272 static u16 impulse_noise_val[29] = 273 274 { 275 0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, 0x3ffe, 0x7f3, 276 0x2d94, 0x76, 0x53d, 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, 0x3feb, 0x7d2, 277 0x365e, 0x76, 0x48c, 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0000, 0xd 278 }; 279 280 static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft) 281 { 282 u16 i; 283 for (i = 58; i < 87; i++) 284 dib3000mc_write_word(state, i, impulse_noise_val[i-58]); 285 286 if (nfft == TRANSMISSION_MODE_8K) { 287 dib3000mc_write_word(state, 58, 0x3b); 288 dib3000mc_write_word(state, 84, 0x00); 289 dib3000mc_write_word(state, 85, 0x8200); 290 } 291 292 dib3000mc_write_word(state, 34, 0x1294); 293 dib3000mc_write_word(state, 35, 0x1ff8); 294 if (mode == 1) 295 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10)); 296 } 297 298 static int dib3000mc_init(struct dvb_frontend *demod) 299 { 300 struct dib3000mc_state *state = demod->demodulator_priv; 301 struct dibx000_agc_config *agc = state->cfg->agc; 302 303 // Restart Configuration 304 dib3000mc_write_word(state, 1027, 0x8000); 305 dib3000mc_write_word(state, 1027, 0x0000); 306 307 // power up the demod + mobility configuration 308 dib3000mc_write_word(state, 140, 0x0000); 309 dib3000mc_write_word(state, 1031, 0); 310 311 if (state->cfg->mobile_mode) { 312 dib3000mc_write_word(state, 139, 0x0000); 313 dib3000mc_write_word(state, 141, 0x0000); 314 dib3000mc_write_word(state, 175, 0x0002); 315 dib3000mc_write_word(state, 1032, 0x0000); 316 } else { 317 dib3000mc_write_word(state, 139, 0x0001); 318 dib3000mc_write_word(state, 141, 0x0000); 319 dib3000mc_write_word(state, 175, 0x0000); 320 dib3000mc_write_word(state, 1032, 0x012C); 321 } 322 dib3000mc_write_word(state, 1033, 0x0000); 323 324 // P_clk_cfg 325 dib3000mc_write_word(state, 1037, 0x3130); 326 327 // other configurations 328 329 // P_ctrl_sfreq 330 dib3000mc_write_word(state, 33, (5 << 0)); 331 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0)); 332 333 // Phase noise control 334 // P_fft_phacor_inh, P_fft_phacor_cpe, P_fft_powrange 335 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0)); 336 337 if (state->cfg->phase_noise_mode == 0) 338 dib3000mc_write_word(state, 111, 0x00); 339 else 340 dib3000mc_write_word(state, 111, 0x02); 341 342 // P_agc_global 343 dib3000mc_write_word(state, 50, 0x8000); 344 345 // agc setup misc 346 dib3000mc_setup_pwm_state(state); 347 348 // P_agc_counter_lock 349 dib3000mc_write_word(state, 53, 0x87); 350 // P_agc_counter_unlock 351 dib3000mc_write_word(state, 54, 0x87); 352 353 /* agc */ 354 dib3000mc_write_word(state, 36, state->cfg->max_time); 355 dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0)); 356 dib3000mc_write_word(state, 38, state->cfg->pwm3_value); 357 dib3000mc_write_word(state, 39, state->cfg->ln_adc_level); 358 359 // set_agc_loop_Bw 360 dib3000mc_write_word(state, 40, 0x0179); 361 dib3000mc_write_word(state, 41, 0x03f0); 362 363 dib3000mc_write_word(state, 42, agc->agc1_max); 364 dib3000mc_write_word(state, 43, agc->agc1_min); 365 dib3000mc_write_word(state, 44, agc->agc2_max); 366 dib3000mc_write_word(state, 45, agc->agc2_min); 367 dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2); 368 dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2); 369 dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2); 370 dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2); 371 372 // Begin: TimeOut registers 373 // P_pha3_thres 374 dib3000mc_write_word(state, 110, 3277); 375 // P_timf_alpha = 6, P_corm_alpha = 6, P_corm_thres = 0x80 376 dib3000mc_write_word(state, 26, 0x6680); 377 // lock_mask0 378 dib3000mc_write_word(state, 1, 4); 379 // lock_mask1 380 dib3000mc_write_word(state, 2, 4); 381 // lock_mask2 382 dib3000mc_write_word(state, 3, 0x1000); 383 // P_search_maxtrial=1 384 dib3000mc_write_word(state, 5, 1); 385 386 dib3000mc_set_bandwidth(state, 8000); 387 388 // div_lock_mask 389 dib3000mc_write_word(state, 4, 0x814); 390 391 dib3000mc_write_word(state, 21, (1 << 9) | 0x164); 392 dib3000mc_write_word(state, 22, 0x463d); 393 394 // Spurious rm cfg 395 // P_cspu_regul, P_cspu_win_cut 396 dib3000mc_write_word(state, 120, 0x200f); 397 // P_adp_selec_monit 398 dib3000mc_write_word(state, 134, 0); 399 400 // Fec cfg 401 dib3000mc_write_word(state, 195, 0x10); 402 403 // diversity register: P_dvsy_sync_wait.. 404 dib3000mc_write_word(state, 180, 0x2FF0); 405 406 // Impulse noise configuration 407 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K); 408 409 // output mode set-up 410 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); 411 412 /* close the i2c-gate */ 413 dib3000mc_write_word(state, 769, (1 << 7) ); 414 415 return 0; 416 } 417 418 static int dib3000mc_sleep(struct dvb_frontend *demod) 419 { 420 struct dib3000mc_state *state = demod->demodulator_priv; 421 422 dib3000mc_write_word(state, 1031, 0xFFFF); 423 dib3000mc_write_word(state, 1032, 0xFFFF); 424 dib3000mc_write_word(state, 1033, 0xFFF0); 425 426 return 0; 427 } 428 429 static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam) 430 { 431 u16 cfg[4] = { 0 },reg; 432 switch (qam) { 433 case QPSK: 434 cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0; 435 break; 436 case QAM_16: 437 cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0; 438 break; 439 case QAM_64: 440 cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8; 441 break; 442 } 443 for (reg = 129; reg < 133; reg++) 444 dib3000mc_write_word(state, reg, cfg[reg - 129]); 445 } 446 447 static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, 448 struct dtv_frontend_properties *ch, u16 seq) 449 { 450 u16 value; 451 u32 bw = BANDWIDTH_TO_KHZ(ch->bandwidth_hz); 452 453 dib3000mc_set_bandwidth(state, bw); 454 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0); 455 456 #if 1 457 dib3000mc_write_word(state, 100, (16 << 6) + 9); 458 #else 459 if (boost) 460 dib3000mc_write_word(state, 100, (11 << 6) + 6); 461 else 462 dib3000mc_write_word(state, 100, (16 << 6) + 9); 463 #endif 464 465 dib3000mc_write_word(state, 1027, 0x0800); 466 dib3000mc_write_word(state, 1027, 0x0000); 467 468 //Default cfg isi offset adp 469 dib3000mc_write_word(state, 26, 0x6680); 470 dib3000mc_write_word(state, 29, 0x1273); 471 dib3000mc_write_word(state, 33, 5); 472 dib3000mc_set_adp_cfg(state, QAM_16); 473 dib3000mc_write_word(state, 133, 15564); 474 475 dib3000mc_write_word(state, 12 , 0x0); 476 dib3000mc_write_word(state, 13 , 0x3e8); 477 dib3000mc_write_word(state, 14 , 0x0); 478 dib3000mc_write_word(state, 15 , 0x3f2); 479 480 dib3000mc_write_word(state, 93,0); 481 dib3000mc_write_word(state, 94,0); 482 dib3000mc_write_word(state, 95,0); 483 dib3000mc_write_word(state, 96,0); 484 dib3000mc_write_word(state, 97,0); 485 dib3000mc_write_word(state, 98,0); 486 487 dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode); 488 489 value = 0; 490 switch (ch->transmission_mode) { 491 case TRANSMISSION_MODE_2K: value |= (0 << 7); break; 492 default: 493 case TRANSMISSION_MODE_8K: value |= (1 << 7); break; 494 } 495 switch (ch->guard_interval) { 496 case GUARD_INTERVAL_1_32: value |= (0 << 5); break; 497 case GUARD_INTERVAL_1_16: value |= (1 << 5); break; 498 case GUARD_INTERVAL_1_4: value |= (3 << 5); break; 499 default: 500 case GUARD_INTERVAL_1_8: value |= (2 << 5); break; 501 } 502 switch (ch->modulation) { 503 case QPSK: value |= (0 << 3); break; 504 case QAM_16: value |= (1 << 3); break; 505 default: 506 case QAM_64: value |= (2 << 3); break; 507 } 508 switch (HIERARCHY_1) { 509 case HIERARCHY_2: value |= 2; break; 510 case HIERARCHY_4: value |= 4; break; 511 default: 512 case HIERARCHY_1: value |= 1; break; 513 } 514 dib3000mc_write_word(state, 0, value); 515 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); 516 517 value = 0; 518 if (ch->hierarchy == 1) 519 value |= (1 << 4); 520 if (1 == 1) 521 value |= 1; 522 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) { 523 case FEC_2_3: value |= (2 << 1); break; 524 case FEC_3_4: value |= (3 << 1); break; 525 case FEC_5_6: value |= (5 << 1); break; 526 case FEC_7_8: value |= (7 << 1); break; 527 default: 528 case FEC_1_2: value |= (1 << 1); break; 529 } 530 dib3000mc_write_word(state, 181, value); 531 532 // diversity synchro delay add 50% SFN margin 533 switch (ch->transmission_mode) { 534 case TRANSMISSION_MODE_8K: value = 256; break; 535 case TRANSMISSION_MODE_2K: 536 default: value = 64; break; 537 } 538 switch (ch->guard_interval) { 539 case GUARD_INTERVAL_1_16: value *= 2; break; 540 case GUARD_INTERVAL_1_8: value *= 4; break; 541 case GUARD_INTERVAL_1_4: value *= 8; break; 542 default: 543 case GUARD_INTERVAL_1_32: value *= 1; break; 544 } 545 value <<= 4; 546 value |= dib3000mc_read_word(state, 180) & 0x000f; 547 dib3000mc_write_word(state, 180, value); 548 549 // restart demod 550 value = dib3000mc_read_word(state, 0); 551 dib3000mc_write_word(state, 0, value | (1 << 9)); 552 dib3000mc_write_word(state, 0, value); 553 554 msleep(30); 555 556 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode); 557 } 558 559 static int dib3000mc_autosearch_start(struct dvb_frontend *demod) 560 { 561 struct dtv_frontend_properties *chan = &demod->dtv_property_cache; 562 struct dib3000mc_state *state = demod->demodulator_priv; 563 u16 reg; 564 // u32 val; 565 struct dtv_frontend_properties schan; 566 567 schan = *chan; 568 569 /* TODO what is that ? */ 570 571 /* a channel for autosearch */ 572 schan.transmission_mode = TRANSMISSION_MODE_8K; 573 schan.guard_interval = GUARD_INTERVAL_1_32; 574 schan.modulation = QAM_64; 575 schan.code_rate_HP = FEC_2_3; 576 schan.code_rate_LP = FEC_2_3; 577 schan.hierarchy = 0; 578 579 dib3000mc_set_channel_cfg(state, &schan, 11); 580 581 reg = dib3000mc_read_word(state, 0); 582 dib3000mc_write_word(state, 0, reg | (1 << 8)); 583 dib3000mc_read_word(state, 511); 584 dib3000mc_write_word(state, 0, reg); 585 586 return 0; 587 } 588 589 static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod) 590 { 591 struct dib3000mc_state *state = demod->demodulator_priv; 592 u16 irq_pending = dib3000mc_read_word(state, 511); 593 594 if (irq_pending & 0x1) // failed 595 return 1; 596 597 if (irq_pending & 0x2) // succeeded 598 return 2; 599 600 return 0; // still pending 601 } 602 603 static int dib3000mc_tune(struct dvb_frontend *demod) 604 { 605 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; 606 struct dib3000mc_state *state = demod->demodulator_priv; 607 608 // ** configure demod ** 609 dib3000mc_set_channel_cfg(state, ch, 0); 610 611 // activates isi 612 if (state->sfn_workaround_active) { 613 dprintk("SFN workaround is active\n"); 614 dib3000mc_write_word(state, 29, 0x1273); 615 dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift 616 } else { 617 dib3000mc_write_word(state, 29, 0x1073); 618 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift 619 } 620 621 dib3000mc_set_adp_cfg(state, (u8)ch->modulation); 622 if (ch->transmission_mode == TRANSMISSION_MODE_8K) { 623 dib3000mc_write_word(state, 26, 38528); 624 dib3000mc_write_word(state, 33, 8); 625 } else { 626 dib3000mc_write_word(state, 26, 30336); 627 dib3000mc_write_word(state, 33, 6); 628 } 629 630 if (dib3000mc_read_word(state, 509) & 0x80) 631 dib3000mc_set_timing(state, ch->transmission_mode, 632 BANDWIDTH_TO_KHZ(ch->bandwidth_hz), 1); 633 634 return 0; 635 } 636 637 struct i2c_adapter * dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod, int gating) 638 { 639 struct dib3000mc_state *st = demod->demodulator_priv; 640 return dibx000_get_i2c_adapter(&st->i2c_master, DIBX000_I2C_INTERFACE_TUNER, gating); 641 } 642 643 EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master); 644 645 static int dib3000mc_get_frontend(struct dvb_frontend* fe, 646 struct dtv_frontend_properties *fep) 647 { 648 struct dib3000mc_state *state = fe->demodulator_priv; 649 u16 tps = dib3000mc_read_word(state,458); 650 651 fep->inversion = INVERSION_AUTO; 652 653 fep->bandwidth_hz = state->current_bandwidth; 654 655 switch ((tps >> 8) & 0x1) { 656 case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break; 657 case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break; 658 } 659 660 switch (tps & 0x3) { 661 case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break; 662 case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break; 663 case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break; 664 case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break; 665 } 666 667 switch ((tps >> 13) & 0x3) { 668 case 0: fep->modulation = QPSK; break; 669 case 1: fep->modulation = QAM_16; break; 670 case 2: 671 default: fep->modulation = QAM_64; break; 672 } 673 674 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 675 /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */ 676 677 fep->hierarchy = HIERARCHY_NONE; 678 switch ((tps >> 5) & 0x7) { 679 case 1: fep->code_rate_HP = FEC_1_2; break; 680 case 2: fep->code_rate_HP = FEC_2_3; break; 681 case 3: fep->code_rate_HP = FEC_3_4; break; 682 case 5: fep->code_rate_HP = FEC_5_6; break; 683 case 7: 684 default: fep->code_rate_HP = FEC_7_8; break; 685 686 } 687 688 switch ((tps >> 2) & 0x7) { 689 case 1: fep->code_rate_LP = FEC_1_2; break; 690 case 2: fep->code_rate_LP = FEC_2_3; break; 691 case 3: fep->code_rate_LP = FEC_3_4; break; 692 case 5: fep->code_rate_LP = FEC_5_6; break; 693 case 7: 694 default: fep->code_rate_LP = FEC_7_8; break; 695 } 696 697 return 0; 698 } 699 700 static int dib3000mc_set_frontend(struct dvb_frontend *fe) 701 { 702 struct dtv_frontend_properties *fep = &fe->dtv_property_cache; 703 struct dib3000mc_state *state = fe->demodulator_priv; 704 int ret; 705 706 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); 707 708 state->current_bandwidth = fep->bandwidth_hz; 709 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz)); 710 711 /* maybe the parameter has been changed */ 712 state->sfn_workaround_active = buggy_sfn_workaround; 713 714 if (fe->ops.tuner_ops.set_params) { 715 fe->ops.tuner_ops.set_params(fe); 716 msleep(100); 717 } 718 719 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO || 720 fep->guard_interval == GUARD_INTERVAL_AUTO || 721 fep->modulation == QAM_AUTO || 722 fep->code_rate_HP == FEC_AUTO) { 723 int i = 1000, found; 724 725 dib3000mc_autosearch_start(fe); 726 do { 727 msleep(1); 728 found = dib3000mc_autosearch_is_irq(fe); 729 } while (found == 0 && i--); 730 731 dprintk("autosearch returns: %d\n",found); 732 if (found == 0 || found == 1) 733 return 0; // no channel found 734 735 dib3000mc_get_frontend(fe, fep); 736 } 737 738 ret = dib3000mc_tune(fe); 739 740 /* make this a config parameter */ 741 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO); 742 return ret; 743 } 744 745 static int dib3000mc_read_status(struct dvb_frontend *fe, enum fe_status *stat) 746 { 747 struct dib3000mc_state *state = fe->demodulator_priv; 748 u16 lock = dib3000mc_read_word(state, 509); 749 750 *stat = 0; 751 752 if (lock & 0x8000) 753 *stat |= FE_HAS_SIGNAL; 754 if (lock & 0x3000) 755 *stat |= FE_HAS_CARRIER; 756 if (lock & 0x0100) 757 *stat |= FE_HAS_VITERBI; 758 if (lock & 0x0010) 759 *stat |= FE_HAS_SYNC; 760 if (lock & 0x0008) 761 *stat |= FE_HAS_LOCK; 762 763 return 0; 764 } 765 766 static int dib3000mc_read_ber(struct dvb_frontend *fe, u32 *ber) 767 { 768 struct dib3000mc_state *state = fe->demodulator_priv; 769 *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501); 770 return 0; 771 } 772 773 static int dib3000mc_read_unc_blocks(struct dvb_frontend *fe, u32 *unc) 774 { 775 struct dib3000mc_state *state = fe->demodulator_priv; 776 *unc = dib3000mc_read_word(state, 508); 777 return 0; 778 } 779 780 static int dib3000mc_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 781 { 782 struct dib3000mc_state *state = fe->demodulator_priv; 783 u16 val = dib3000mc_read_word(state, 392); 784 *strength = 65535 - val; 785 return 0; 786 } 787 788 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr) 789 { 790 *snr = 0x0000; 791 return 0; 792 } 793 794 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune) 795 { 796 tune->min_delay_ms = 1000; 797 return 0; 798 } 799 800 static void dib3000mc_release(struct dvb_frontend *fe) 801 { 802 struct dib3000mc_state *state = fe->demodulator_priv; 803 dibx000_exit_i2c_master(&state->i2c_master); 804 kfree(state); 805 } 806 807 int dib3000mc_pid_control(struct dvb_frontend *fe, int index, int pid,int onoff) 808 { 809 struct dib3000mc_state *state = fe->demodulator_priv; 810 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0); 811 return 0; 812 } 813 EXPORT_SYMBOL(dib3000mc_pid_control); 814 815 int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff) 816 { 817 struct dib3000mc_state *state = fe->demodulator_priv; 818 u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4); 819 tmp |= (onoff << 4); 820 return dib3000mc_write_word(state, 206, tmp); 821 } 822 EXPORT_SYMBOL(dib3000mc_pid_parse); 823 824 void dib3000mc_set_config(struct dvb_frontend *fe, struct dib3000mc_config *cfg) 825 { 826 struct dib3000mc_state *state = fe->demodulator_priv; 827 state->cfg = cfg; 828 } 829 EXPORT_SYMBOL(dib3000mc_set_config); 830 831 int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib3000mc_config cfg[]) 832 { 833 struct dib3000mc_state *dmcst; 834 int k; 835 u8 new_addr; 836 837 static u8 DIB3000MC_I2C_ADDRESS[] = {20,22,24,26}; 838 839 dmcst = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL); 840 if (dmcst == NULL) 841 return -ENOMEM; 842 843 dmcst->i2c_adap = i2c; 844 845 for (k = no_of_demods-1; k >= 0; k--) { 846 dmcst->cfg = &cfg[k]; 847 848 /* designated i2c address */ 849 new_addr = DIB3000MC_I2C_ADDRESS[k]; 850 dmcst->i2c_addr = new_addr; 851 if (dib3000mc_identify(dmcst) != 0) { 852 dmcst->i2c_addr = default_addr; 853 if (dib3000mc_identify(dmcst) != 0) { 854 dprintk("-E- DiB3000P/MC #%d: not identified\n", k); 855 kfree(dmcst); 856 return -ENODEV; 857 } 858 } 859 860 dib3000mc_set_output_mode(dmcst, OUTMODE_MPEG2_PAR_CONT_CLK); 861 862 // set new i2c address and force divstr (Bit 1) to value 0 (Bit 0) 863 dib3000mc_write_word(dmcst, 1024, (new_addr << 3) | 0x1); 864 dmcst->i2c_addr = new_addr; 865 } 866 867 for (k = 0; k < no_of_demods; k++) { 868 dmcst->cfg = &cfg[k]; 869 dmcst->i2c_addr = DIB3000MC_I2C_ADDRESS[k]; 870 871 dib3000mc_write_word(dmcst, 1024, dmcst->i2c_addr << 3); 872 873 /* turn off data output */ 874 dib3000mc_set_output_mode(dmcst, OUTMODE_HIGH_Z); 875 } 876 877 kfree(dmcst); 878 return 0; 879 } 880 EXPORT_SYMBOL(dib3000mc_i2c_enumeration); 881 882 static const struct dvb_frontend_ops dib3000mc_ops; 883 884 struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib3000mc_config *cfg) 885 { 886 struct dvb_frontend *demod; 887 struct dib3000mc_state *st; 888 st = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL); 889 if (st == NULL) 890 return NULL; 891 892 st->cfg = cfg; 893 st->i2c_adap = i2c_adap; 894 st->i2c_addr = i2c_addr; 895 896 demod = &st->demod; 897 demod->demodulator_priv = st; 898 memcpy(&st->demod.ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops)); 899 900 if (dib3000mc_identify(st) != 0) 901 goto error; 902 903 dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr); 904 905 dib3000mc_write_word(st, 1037, 0x3130); 906 907 return demod; 908 909 error: 910 kfree(st); 911 return NULL; 912 } 913 EXPORT_SYMBOL(dib3000mc_attach); 914 915 static const struct dvb_frontend_ops dib3000mc_ops = { 916 .delsys = { SYS_DVBT }, 917 .info = { 918 .name = "DiBcom 3000MC/P", 919 .frequency_min = 44250000, 920 .frequency_max = 867250000, 921 .frequency_stepsize = 62500, 922 .caps = FE_CAN_INVERSION_AUTO | 923 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 924 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 925 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 926 FE_CAN_TRANSMISSION_MODE_AUTO | 927 FE_CAN_GUARD_INTERVAL_AUTO | 928 FE_CAN_RECOVER | 929 FE_CAN_HIERARCHY_AUTO, 930 }, 931 932 .release = dib3000mc_release, 933 934 .init = dib3000mc_init, 935 .sleep = dib3000mc_sleep, 936 937 .set_frontend = dib3000mc_set_frontend, 938 .get_tune_settings = dib3000mc_fe_get_tune_settings, 939 .get_frontend = dib3000mc_get_frontend, 940 941 .read_status = dib3000mc_read_status, 942 .read_ber = dib3000mc_read_ber, 943 .read_signal_strength = dib3000mc_read_signal_strength, 944 .read_snr = dib3000mc_read_snr, 945 .read_ucblocks = dib3000mc_read_unc_blocks, 946 }; 947 948 MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>"); 949 MODULE_DESCRIPTION("Driver for the DiBcom 3000MC/P COFDM demodulator"); 950 MODULE_LICENSE("GPL"); 951